ON ADP3212MNR2G, NCP3218GMNR2G, NCP3218MNR2G, NCP3218MNTWG Schematics

ADP3212, NCP3218,
NCP3218G

7-Bit, Programmable,
3-Phase, Mobile CPU
Synchronous Buck Controller

The APD3212/NCP3218/NCP3218G is a highly efficient,
multi−phase, synchronous buck switching regulator controller. With
its integrated drivers, the APD3212/NCP3218/NCP3218G is
optimized for converting the notebook battery voltage into the core
supply voltage required by high performance Intel processors. An
internal 7−bit DAC is used to read a VID code directly from the
processor and to set the CPU core voltage to a value within the range
of 0.3 V to 1.5 V. The APD3212/NCP3218/NCP3218G is
programmable for 1−, 2−, or 3−phase operation. The output signals
ensure interleaved 2− or 3−phase operation.

The APD3212/NCP3218/NCP3218G uses a multimode architecture
run at a programmable switching frequency and optimized for
efficiency depending on the output current requirement. The
APD3212/NCP3218/NCP3218G switches between single− and
multi−phase operation to maximize efficiency with all load conditions.
The chip includes a programmable load line slope function to adjust the
output voltage as a function of the load current so that the core voltage is
always optimally positioned for a load transient. The APD3212/
NCP3218/NCP3218G also provides accurate and reliable short−circuit
protection, adjustable current limiting, and a delayed power−good
output. The IC supports On−The−Fly (OTF) output voltage changes
requested by the CPU.

The APD3212/NCP3218/NCP3218G are specified over
the extended commercial temperature range of −40°C to
100°C. The ADP3212 is available in a 48−lead QFN 7x7mm

0.5mm pitch package. The NCP3218/NCP3218G is
available in a 48−lead QFN 6x6mm 0.4mm pitch package.
ADP3212/NCP3218 has 1.1 V Vboot Voltage, while
NCP3218G has 987.5 mV Vboot Voltage. Except for the
packages and Vboot Voltages, the APD3212/NCP3218/
NCP3218G are identical. APD3212/NCP3218/NCP3218G
are Halogen−Free, Pb−Free and RoHS compliant.

Features

• Single−Chip Solution

• Fully Compatible with the Intel

Specifications

®

IMVP−6.5t

• Selectable 1−, 2−, or 3−Phase Operation with Up to 1

MHz per Phase Switching Frequency

• Phase 1 and Phase 2 Integrated MOSFET Drivers

• Input Voltage Range of 3.3 V to 22 V

• Active Current Balancing Between Output Phases

• Independent Current Limit and Load Line Setting

Inputs for Additional Design Flexibility

• Built−In Power−Good Blanking Supports Voltage

Identification (VID) On−The−Fly (OTF) Transients

• 7−Bit, Digitally Programmable DAC with 0.3 V to

1.5 V Output

• Short−Circuit Protection with Programmable Latchoff

Delay

• Clock Enable Output Delays the CPU Clock Until the

Core Voltage is Stable

• Output Power or Current Monitor Options

• 48−Lead QFN 7x7mm (ADP3212), 48−Lead QFN

6x6mm (NCP3218/NCP3218G)

• Vboot = 1.1 V (ADP3212/NCP3218)

Vboot = 987.5 mV (NCP3218G)

• These are Pb−Free Devices

• Fully RoHS Compliant

• Guaranteed ±8 mV Worst−Case Differentially Sensed

Core Voltage Error Over Temperature

• Automatic Power−Saving Mode Maximizes Efficiency

with Light Load During Deeper Sleep Operation

Applications

• Notebook Power Supplies for Next−Generation Intel

Processors

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148

QFN48

CASE 485AJ

MARKING DIAGRAM

1

xxP321x

AWLYYWWG

See detailed ordering and shipping information in the package
dimensions section on page 33 of this data sheet.

xxx = Specific Device Code

(ADP3212 or NCP3218/G)
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package

ORDERING INFORMATION

481

QFN48

CASE 485BA

© Semiconductor Components Industries, LLC, 2012

August, 2012 − Rev. 4

1 Publication Order Number:

ADP3212/D

ADP3212, NCP3218, NCP3218G

PIN ASSIGNMENT

TRDET

COMP

FB

LLINE

SWFB1

SWFB2

SWFB3

PH0

PH1

PWRGD

CLKEN

FBRTN

PWRGD

IMON

CLKEN
FBRTN

COMP

TRDET

VARFREQ

VRTT

TTSNS

GND

TRDET

Generator

+

SS

REF

CSREF

+

SS

_

+

1.55 V

DAC + 200 mV

DAC − 300 mV

PWRGD

Open
Drain

CLKEN

Open
Drain

Precision

Precision

Reference

Reference

VID

DAC

EN

FB

VEA

−

+

CSREF

−

+

−

+

VID1

VID0

1

RPM

IREF

VCC

ENGND

UVLO

Shutdown

and Bias

+

−

Number of

Phases

PWRGD
Start Up

Delay

CLKEN

Start Up

Delay

VID6

VID5

VID4

VID3

VID2

ADP3212
NCP3218
(top view)

RT

LLINE

RAMP

CSREF

CSSUM

RPM RT RAMP

Oscillator

Current

Balancing

Circuit

OVP

OCP

Shutdown

Delay

Soft

Transient

Delay

Delay

Disable

DAC

DPRSLP

PH0

PH1

PSI

ILIM

OD3

PWM3

CSCOMP

Current

Limit

Circuit

REF

VCC

BST1
DRVH1
SW1
SWFB1
PVCC
DRVL1
PGND
DRVL2
SWFB2
SW2
DRVH2
BST2

SWFB3

VARFREQ

Driver

Logic

PSI and

DPRSLP

Logic

Current

Current
Monitor

Monitor

Thermal
Throttle

Control

Soft Start

PVCC

PGND

+

−

BST1

DRVH1

SW1

PVCC

DRVL1

PGND

BST2

DRVH2

SW2

DRVL2

OD3

PWM3

PSI

DPRSLP

IMON

CSREF

CSSUM

CSCOMP

ILIM

TTSENSE

VRTT

VID6

VID5

VID4

VID3

VID2

VID1

VID0

IREF

Figure 1. Functional Block Diagram

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2

ADP3212, NCP3218, NCP3218G

ABSOLUTE MAXIMUM RATINGS

Parameter Rating Unit

VCC, PV

FBRTN, PGND1, PGND2 −0.3 to +0.3 V

BST1, BST2, DRVH1, DRVH2

DC
t < 200 ns

BST1 to PVCC, BST2 to PV

DC
t < 200 ns

BST1 to SW1, BST2 to SW2 −0.3 to +6.0 V

SW1, SW2

DC
t < 200 ns

DRVH1 to SW1, DRVH2 to SW2 −0.3 to +6.0 V

DRVL1 to PGND1, DRVL2 to PGND2

DC
t < 200 ns

RAMP (in Shutdown) −0.3 to +22 V

All Other Inputs and Outputs −0.3 to +6.0 V

Storage Temperature Range −65 to +150 °C

Operating Ambient Temperature Range −40 to +100 °C

Operating Junction Temperature 125 °C

Thermal Impedance (qJA) 2−Layer Board

Lead Temperature

Soldering (10 sec)
Infrared (15 sec)

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.

CC1

, PV

CC2

CC

−0.3 to +6.0 V

V

−0.3 to +28

−0.3 to +33

V

−0.3 to +22

−0.3 to +28

V

−1.0 to +22

−6.0 to +28

V

−0.3 to +6.0

−5.0 to +6.0

30.5 °C/W

°C

300
260

PIN ASSIGNMENT

Pin No. Mnemonic Description

1 EN Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, pulls PWRGD and

2 PWRGD Power−Good Output. Open−drain output. A low logic state means that the output voltage is outside of the

3 IMON Current Monitor Output. This pin sources a current proportional to the output load current. A resistor to

4 CLKEN Clock Enable Output. Open−drain output. A low logic state enables the CPU internal PLL clock to lock to

5 FBRTN Feedback Return Input/Output. This pin remotely senses the CPU core voltage. It is also used as the

6 FB Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.

7 COMP Voltage Error Amplifier Output and Frequency Compensation Point.

8 TRDET Transient Detect Output. This pin is pulled low when a load release transient is detected. During repetitive

9 VARFREQ Variable Frequency Enable Input. A high logic state enables the PWM clock frequency to vary with VID code.

10 VRTT Voltage Regulator Thermal Throttling Output. Logic high state indicates that the voltage regulator

VRTT low, and pulls CLKEN

VID DAC defined range.

FBRTN sets the current monitor gain.

the external clock.

ground return for the VID DAC and the voltage error amplifier blocks.

load transients at high frequencies, this circuit optimally positions the maximum and minimum output
voltage into a specified loadline window.

temperature at the remote sensing point exceeded a set alarm threshold level.

high.

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3

ADP3212, NCP3218, NCP3218G

PIN ASSIGNMENT

Pin No. DescriptionMnemonic

11 TTSNS Thermal Throttling Sense and Crowbar Disable Input. A resistor divider where the upper resistor is connected

12 GND Analog and Digital Signal Ground.

13 IREF

14 RPM RPM Mode Timing Control Input. A resistor between this pin to ground sets the RPM mode turn−on

15 RT Multi−phase Frequency Setting Input. An external resistor connected between this pin and GND sets the

16 RAMP PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this pin sets

17 LLINE Output Load Line Programming Input. The center point of a resistor divider between CSREF and

18 CSREF Current Sense Reference Input. This pin must be connected to the common point of the output inductors.

19 CSSUM Current Sense Summing Input. External resistors from each switch node to this pin sum the inductor

20 CSCOMP Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the gain of

21 ILIM Current Limit Setpoint. An external resistor from this pin to CSCOMP sets the current limit threshold of the

22 OD3 Multi−phase Output Disable Logic Output. This pin is actively pulled low when the APD3212/NCP3218/

23 PWM3 Logic−Level PWM Output for phase 3. Connect to the input of an external MOSFET driver such as the

24 SWFB3 Current Balance Input for phase 3. Input for measuring the current level in phase 3. SWFB3 should be left

25 BST2 High−Side Bootstrap Supply for Phase 2. A capacitor from this pin to SW2 holds the bootstrapped voltage

26 DRVH2 High−Side Gate Drive Output for Phase 2.

27 SW2 Current Return for High−Side Gate Drive for phase 2.

28 SWFB2 Current Balance Input for phase 2. Input for measuring the current level in phase 2. SWFB2 should be left

29 DRVL2 Low−Side Gate Drive Output for Phase 2.

30 PGND Low−Side Driver Power Ground

31 DRVL1 Low−Side Gate Drive Output for Phase 1.

32 PVCC Power Supply Input/Output of Low−Side Gate Drivers.

33 SWFB1 Current Balance Input for phase 1. Input for measuring the current level in phase 1.

34 SW1 Current Return For High−Side Gate Drive for phase 1.

35 DRVH1 High−Side Gate Drive Output for Phase 1.

36 BST1 High−Side Bootstrap Supply for Phase 1. A capacitor from this pin to SW1 holds the bootstrapped voltage

37 VCC Power Supply Input/Output of the Controller.

38 PH1 Phase Number Configuration Input. Connect to VCC for 3 phase configuration.

39 PH0 Phase Number Configuration Input. Connect to GND for 1 phase configuration. Connect to VCC for

40 DPRSLP Deeper Sleep Control Input.

41 PSI Power State Indicator Input. Pulling this pin to GND forces the APD3212/NCP3218/NCP3218G to operate

42 to48VID6 to VID0 Voltage Identification DAC Inputs. When in normal operation mode, the DAC output programs the FB

to VCC, the lower resistor (NTC thermistor) is connected to GND, and the center point is connected to this
pin and acts as a temperature sensor half bridge. Connecting TTSNS to GND disables the thermal throttling
function and disables the crowbar, or Overvoltage Protection (OVP), feature of the chip.

This pin sets the internal bias currents. A 80 kW resistor is connected from this pin to ground.

threshold voltage.

oscillator frequency of the device when operating in multi−phase PWM mode threshold of the converter.

the slope of the internal PWM stabilizing ramp used for phase−current balancing.

CSCOMP is connected to this pin to set the load line slope.

The node is shorted to GND through an internal switch when the chip is disabled to provide soft stop
transient control of the converter output voltage.

currents to provide total current information.

the current−sense amplifier and the positioning loop response time.

converter.

NCP3218G enters single−phase mode or during shutdown. Connect this pin to the SD inputs of the
Phase−3 MOSFET drivers.

ADP3611.

open for 1 or 2 phase configuration.

while the high−side MOSFET is on.

open for 1 phase configuration.

while the high−side MOSFET is on.

multi−phase configuration.

in single−phase mode.

regulation voltage from 0.3 V to 1.5 V (see Table 3).

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4

ADP3212, NCP3218, NCP3218G

ELECTRICAL CHARACTERISTICS

VCC = PVCC = 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V,

= V

V

VID

VOLTAGE CONTROL
VOLTAGE ERROR AMPLIFIER (VEAMP)

FB, LLINE Voltage Range (Note 2) VFB, V

FB, LLINE Offset Voltage (Note 2) V

LLINE Bias Current I

FB Bias Current I

LLINE Positioning Accuracy VFB − V

COMP Voltage Range (Note 2) V

COMP Current I

COMP Slew Rate SR

Gain Bandwidth (Note 2) GBW Non−inverting unit gain configuration,

VID DAC VOLTAGE REFERENCE

VDAC Voltage Range (Note 2)

VDAC Accuracy VFB − V

VDAC Differential Non−linearity
(Note 2)

VDAC Line Regulation ΔV

VDAC Boot Voltage
(ADP3212, NCP3218)

VDAC Boot Voltage (NCP3218G) V

Soft−Start Delay (Note 2) t

Soft−Start Time t

Boot Delay t

VDAC Slew Rate (Note 2) Soft−Start

FBRTN Current I

VOLTAGE MONITORING and PROTECTION
POWER GOOD

CSREF Undervoltage Threshold

CSREF Overvoltage Threshold V

CSREF Crowbar Voltage
Threshold

1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2. Guaranteed by design or bench characterization, not production tested.

3. Based on bench characterization data.

4. Timing is referenced to the 90% and 10% points, unless otherwise noted.

= 1.2000 V, TA = −40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positive sign.

DAC

Parameter

Symbol Conditions Min Typ Max Units

LLINE

OSVEA

LLINE

FB

COMP

COMP

COMP

Relative to CSREF = VDAC −200 +200 mV

Relative to CSREF = VDAC −0.5 +0.5 mV

−100 +100 nA

−1.0 +1.0

Measured on FB relative to V

VID

LLINE forced 80 mV below CSREF

VID

,

−77.5 −80 −82.5 mV

0.85 4.0 V

COMP = 2.0 V, CSREF = VDAC
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF

C

= 10 pF, CSREF = VDAC,

COMP

Open loop configuration
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF

−0.75
6

15

−20

20 MHz

= 1 kW

R

FB

See VID table 0 1.5 V

Measured on FB (includes offset),

VID

relative to V
V

VID

T = −40°C to 100°C
V

VID

T = −40°C to 100°C

VID

= 1.2000 V to 1.5000 V,

= 0.3000 V to 1.1875 V,

−8.5

−7.5

−1.0 +1.0 LSB

VCC = 4.75 V to 5.25 V 0.02 %

Measured during boot delay period 1.100 V

Measured during boot delay period 987.5 mV

Measured from EN pos edge to

200

FB = 50 mV

Measured from FB = 50 mV to FB

1.4 ms

settles to 1.1 V within 5%

Measured from FB settling to 1.1 V
within 5% to CLKEN

neg edge

60

V

BOOTFB

BOOTFB

DSS

BOOT

FB

SS

0.0625

Non−LSB VID step, DPRSLP = H,

0.25

Slow C4 Entry/Exit
Non−LSB VID step, DPRSLP = L,

1.0

Fast C4 Exit

FBRTN

V

UVCSREF

OVCSREF

V

CBCSREF

LSB VID step, DVID transition

Relative to nominal VDAC voltage −240 −300 −360 mV

Relative to nominal VDAC voltage 150 200 250 mV

Relative to FBRTN, V
Relative to FBRTN, V

VID
VID

> 1.1 V
≤ 1.1 V

1.5

1.3

0.4

−90 −200

1.55

1.35

+8.5

+7.5

1.6

1.4

mA

mA

V/ms

mV

ms

ms

LSB/ms

mA

V

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5

ADP3212, NCP3218, NCP3218G

ELECTRICAL CHARACTERISTICS

VCC = PVCC = 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V,

= V

V

VID

VOLTAGE MONITORING and PROTECTION
POWER GOOD

CSREF Reverse Voltage
Threshold

PWRGD Low Voltage V

PWRGD High, Leakage Current I

PWRGD Startup Delay T

PWRGD Latchoff Delay T

PWRGD Propagation Delay
(Note 3)

Crowbar Latchoff Delay
(Note 2)

PWRGD Masking Time Triggered by any VID change or OCP

CSREF Soft−Stop Resistance EN = L or latchoff condition 70

CURRENT CONTROL
CURRENT−SENSE AMPLIFIER (CSAMP)

CSSUM, CSREF Common−Mode
Range (Note 2)

CSSUM, CSREF Offset Voltage V

CSSUM Bias Current I

CSREF Bias Current I

CSCOMP Voltage Range
(Note 2)

CSCOMP Current

CSCOMP Slew Rate (Note 2) C

Gain Bandwidth (Note 2) GBW

CURRENT MONITORING and PROTECTION
CURRENT REFERENCE

IREF Voltage

CURRENT LIMITER (OCP)

Current Limit (OCP) Threshold

Current Limit Latchoff Delay Measured from OCP event to PWRGD

1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2. Guaranteed by design or bench characterization, not production tested.

3. Based on bench characterization data.

4. Timing is referenced to the 90% and 10% points, unless otherwise noted.

= 1.2000 V, TA = −40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positive sign.

DAC

Parameter UnitsMaxTypMinConditionsSymbol

V

RVCSREF

PWRGD

PWRGD

SSPWRGD

LOFFPWRGD

T

PDPWRGD

T

LOFFCB

Relative to FBRTN, latchoff mode
CSREF is falling
CSREF is rising

I

PWRGD(SINK)

V

PWRDG

= 4 mA 85 250 mV

= 5.0 V 1.0

Measured from CLKEN neg edge to
PWRGD pos edge

Measured from Out−off−Good−Window
event to Latchoff (switching stops)

Measured from Out−off−Good−Window
event to PWRGD neg edge

Measured from Crowbar event to
latchoff (switching stops)

−370 −300

−75

8.0 ms

120

200 ns

200 ns

100

event

Voltage range of interest 0 2.0 V

OSCSA

BCSSUM

BCSREF

CSREF – CSSUM , TA = −40°C to 85°C −1.2 +1.2 mV

−20 +20 nA

−3.0 +3.0

Voltage range of interest 0.05 2.0 V

I

CSCOMPsource

I

CSCOMPsink

CSA

V

REF

V

LIMTH

CSCOMP = 2.0 V, CSSUM forced

−750

200 mV below CSREF

CSSUM forced 200 mV above CSREF 1.0 mA

= 10 pF, CSREF = VDAC,

CSCOMP

Open loop configuration
CSSUM forced 200 mV below CSREF
CSSUM forced 200 mV above CSREF

Non−inverting unit gain configuration

= 1 kW

R

FB

R

= 80 kW to set I

REF

REF

= 20 mA

1.55 1.6 1.65 V

20

−20

20 MHz

Measured from CSCOMP to CSREF,

= 1.5 kW,

R

LIM

3−ph configuration, PSI = H
3−ph configuration, PSI = L
2−ph configuration, PSI
2−ph configuration, PSI

= H
= L

1−ph configuration

−75

−22

−75

−36

−75

−90

−30

−90

−45

−90

120

de−assertion

mV

−10

mA

ms

ms

W

mA

mA

V/ms

mV

−106

−38

−106

−54

−106

ms

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6

ADP3212, NCP3218, NCP3218G

ELECTRICAL CHARACTERISTICS

VCC = PVCC = 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V,

= V

V

VID

CURRENT MONITOR

Current Gain Accuracy

IMON Clamp Voltage V

PULSE WIDTH MODULATOR
CLOCK OSCILLATOR

RT Voltage V

PWM Clock Frequency Range
(Note 2)

PWM Clock Frequency f

RAMP GENERATOR

RAMP Voltage

RAMP Current Range (Note 2) I

PWM COMPARATOR

PWM Comparator Offset (Note 2)

RPM COMPARATOR

RPM Current

RPM Comparator Offset (Note 2) V

EPWM CLOCK SYNC

Trigger Threshold (Note 2)

TRDET

Trigger Threshold (Note 2) Relative to COMP sampled T

TRDET Low Voltage (Note 2) V

TRDET Leakage Current I

SWITCH AMPLIFIER

SW Common Mode Range
(Note 2)

SWFB Input Resistance R

ZERO CURRENT SWITCHING COMPARATOR

SW ZCS Threshold

1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2. Guaranteed by design or bench characterization, not production tested.

3. Based on bench characterization data.

4. Timing is referenced to the 90% and 10% points, unless otherwise noted.

= 1.2000 V, TA = −40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positive sign.

DAC

Parameter UnitsMaxTypMinConditionsSymbol

I

MON/ILIM

MAXMON

RT

f

CLK

CLK

V

RAMP

RAMP

V

OSRPM

I

RPM

OSRPM

LTRDET

HTRDET

V

SW(X)CM

SW(X)

V

DCM(SW1)

Measured from ILIM to IMON

= −20 mA

I

LIM

= −10 mA

I

LIM

= −5 mA

I

LIM

Relative to FBRTN, ILIMP = −30 mA

3.7

3.6

3.5

1.0 1.15 V

4.0

4.0

4.0

VARFREQ = high, RT = 125 kW,
V

= 1.5000 V

VID

VARFREQ = low
See also VRT(V

VID

1.125

0.9

) formula

1.25

1.0

Operation of interest 0.3 3.0 MHz

TA = +25°C, V

= 72 kW

R

T

= 120 kW

R

T

= 180 kW

R

T

EN = high, I
EN = low

EN = high
EN = low, RAMP = 19 V

V

− V

RAMP

V

= 1.2 V, RT = 215 kW

VID

See also I

V

− (1 + V

COMP

Relative to COMP sampled T
earlier
3−phase configuration
2−phase configuration
1−phase configuration

earlier
3−phase configuration
2−phase configuration
1−phase configuration

Logic low, I

Logic high, V

VID

RAMP

COMP

RPM(RT

RPMTH

TRDETsink

TRDET

= 1.2000 V

= 60 mA

1100

700
500

0.9 1.0

1257

800
550

V

IN

1.0

−1.0

±3.0 mV

−9.0

) formula

) ±3.0 mV

time

CLK

350
400
450

time

CLK

−450

−500

−600

= 4 mA 30 300 mV

= VCC 5.0

Operation of interest for current sensing −600 +200 mV

SWX = 0 V, SWFB = 0 V 20 35 50

DCM mode, DPRSLP = 3.3 V −6.0 mV

4.3

4.4

4.5

1.375

1.1

1400

900
600

1.1 V

100

+1.0

−

V

kHz

mA

mA

mV

mV

mA

kW

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7

ADP3212, NCP3218, NCP3218G

ELECTRICAL CHARACTERISTICS

VCC = PVCC = 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V,

= V

V

VID

ZERO CURRENT SWITCHING COMPARATOR

Masked Off−Time t

SYSTEM I/O BUFFERS
VID[6:0], DPRSLP, PSI INPUTS

Input Voltage

Input Current V = 0.2 V, VID[6:0], DPRSLP

VID Delay Time (Note 2) Any VID edge to FB change 10% 200 ns

VARFREQ

Input Voltage

Input Current 1.0

EN INPUT

Input Voltage

Input Current EN = L or EN = H (static)

PH1, PH0 INPUTS

Input Voltage

Input Current 1.0

CLKEN OUTPUT

Output Low Voltage

Output High, Leakage Current Logic high, V

PWM3, OD3 OUTPUTS

Output Voltage

THERMAL MONITORING and PROTECTION

TTSNS Voltage Range (Note 2) 0 5.0 V

TTSNS Threshold VCC = 5.0 V, TTSNS is falling 2.45 2.5 2.55 V

TTSNS Hysteresis 95 mV

TTSNS Bias Current TTSNS = 2.6 V −2.0 2.0

VRTT Output Voltage V

SUPPLY

Supply Voltage Range

Supply Current EN = high

VCC OK Threshold V

VCC UVLO Threshold V

1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2. Guaranteed by design or bench characterization, not production tested.

3. Based on bench characterization data.

4. Timing is referenced to the 90% and 10% points, unless otherwise noted.

= 1.2000 V, TA = −40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positive sign.

DAC

Parameter UnitsMaxTypMinConditionsSymbol

OFFMSKD

Measured from DRVH1 neg edge to
DRVH1 pos edge at operation max

600 ns

frequency

Refers to driving signal level
Logic low

0.3

Logic high 0.7

(active pulldown to GND)
PSI

(active pullup to VCC)

−1.0

1.0

Refers to driving signal level
Logic low
Logic high

4.0

0.7

Refers to driving signal level
Logic low
Logic high

1.9

0.4

10

0.8 V < EN < 1.6 V (during transition)

−70

Refers to driving signal level

VRTT

V

CC

CCOK

CCUVLO

Logic low
Logic high

Logic low, I

Logic low, I
Logic high, I

Logic low, I
Logic high, I

= 4 mA 60 200 mV

sink

= VCC 1.0

CLKEN

= 400 mA

SINK

VRTT(SINK)

= −400 mA

SOURCE

= 400 mA

VRTT(SOURCE)

= −400 mA

4.0

4.0

4.5

10

5.0

10

5.0

4.5 5.5 V

7

EN = 0 V

10

VCC is rising 4.4 4.5 V

VCC is falling 4.0 4.15 V

0.5

100 mV

100 mV

10

150

V

mA

V

mA

V

nA
mA

V

mA

mA

V

mA

V

mA

mA

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8

ADP3212, NCP3218, NCP3218G

ELECTRICAL CHARACTERISTICS

VCC = PVCC = 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V,

= V

V

VID

SUPPLY

VCC Hysteresis (Note 2) 150 mV

HIGH−SIDE MOSFET DRIVER

Pullup Resistance, Sourcing
Current (Note 3)

Pulldown Resistance, Sinking
Current (Note 3)

Transition Times tr

Dead Delay Times tpdh

BST Quiescent Current EN = L (Shutdown)

LOW−SIDE MOSFET DRIVER

Pullup Resistance, Sourcing
Current (Note 3)

Pulldown Resistance, Sinking
Current (Note 3)

Transition Times tr

Propagation Delay Times tpdh

SW Transition Timeout t

SW Off Threshold V

PVCC Quiescent Current EN = L (Shutdown)

BOOTSTRAP RECTIFIER SWITCH

On Resistance (Note 3)

1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2. Guaranteed by design or bench characterization, not production tested.

3. Based on bench characterization data.

4. Timing is referenced to the 90% and 10% points, unless otherwise noted.

= 1.2000 V, TA = −40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positive sign.

DAC

Parameter UnitsMaxTypMinConditionsSymbol

BST = PVCC 1.8 3.3

BST = PVCC 1.0 2.0

DRVH

tf

DRVH

DRVH

BST = PVCC, CL = 3 nF, Figure 2
BST = PVCC, C

= 3 nF, Figure 2

L

BST = PVCC, Figure 2 15 30 40 ns

EN = H, no switching

15
13

1.0

200

30
25

10

1.7 2.8

0.8 1.7

DRVL

tf

DRVL

DRVL

TOSW

OFFSW

CL = 3 nF, Figure 2
C

= 3 nF, Figure 2

L

CL = 3 nF, Figure 2 11 30 ns

DRVH = L, SW = 2.5 V 100 250 350 ns

EN = H, no switching

15
14

35
35

2.5 V

1.0

10

170

EN = L or EN = H and DRVL = H 4.0 6.0 8.0

W

W

ns

mA

W

W

ns

mA

W

DRVL

DRVH

(WITH RESPECT TO SW)

SW

tpdh

tf

DRVL

tr

DRVH

DRVH

V

TH

Figure 2. Timing Diagram (Note 4)

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9

V

TH

1.0 V

tf

tpdh

tr

DRVL

DRVH

DRVL

3.3 V

ADP3212, NCP3218, NCP3218G

TEST CIRCUITS

7−BIT CODE

48

1

EN

PWRGD

1 kW

GND

80 kW

VID1

VID2

VID0

IMON
CLKEN

FBRTN
FB
COMP

TRDET
VARFREQ
VRTT
TTSNS

IREF

RPMRTRAMP

VID3

VID6

VID5

VID4

ADP3212

LLINE

CSREF

CSSUM

PSI

PH1

PH2

DPRSLP

SWFB1

PVCC

DRVL1

PGND

DRVL2

SWFB2

CSCOMP

ILIM

OD3

20 kW

100 nF

VCC

SW1

SW2

PWM3

SWFB3

5 V

BST1
DRVH1

DRVH2
BST2

39 kW

1 kW

1.0 V

5.0 V

100 nF

37

20

19

18

12

VCC

CSCOMP

CSSUM

CSREF

GND

Figure 3. Closed−Loop Output Voltage Accuracy

5.0 V

ADP3212

−

+

CSCOMP * 1.0 V

V

+

OS

40 V

10 kW

DV

1.0 V

VCC

37

COMP

7

FB

6

LLINE

17

CSREF

18

GND

12

DVFB+ FBDV+ DV * FB

ADP3212

−

+

VID DAC

DV+0mV

Figure 4. Current Sense Amplifier, V

OS

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Figure 5. Positioning Accuracy

10

ADP3212, NCP3218, NCP3218G

TYPICAL PERFORMANCE CHARACTERISTICS

V

= 1.5 V, TA = 20°C to 100°C, unless otherwise noted.

VID

400

350

300

250

200

150

FREQUENCY (kHz)

100

PER PHASE SWITCHING

50

0

VARFREQ = 0 V

VARFREQ = 5 V

VID OUTPUT VOLTAGE (V)

Figure 6. Switching Frequency vs. VID Output

Voltage in PWM Mode

Output Voltage

1

RT = 187 kW

2 Phase Mode

1000

VID = 0.8125 V

SWITCHING FREQUENCY (kHz)

100

1.501.251.000.750.500.25

Figure 7. Per Phase Switching Frequency vs.

1

VID = 1.4125 V

VID = 1.2125 V

VID = 1.1 V

VID = 0.6125 V

100010010

Rt RESISTANCE (kW)

RT Resistance

Output Voltage

PWRGD

2

3

4

1: 0.5 V/div
2: 2 V/div

3: 5 V/div
4: 5 V/div

PWRGD

CLKEN

1 ms/div

EN

GPU Mode

2

3

4

1: 0.5 V/div
2: 2 V/div

3: 5 V/div
4: 5 V/div

EN

4 ms/div

CLKEN

CPU Mode

Figure 8. Startup in GPU Mode Figure 9. Startup in CPU Mode

Output Voltage

1

2

3

4

1: 0.5 V/div
2: 2 V/div

PWRGD

EN

3: 2 V/div
4: 2 V/div

CLKEN

200 ms/div

1 A Load

Figure 10. Shutdown

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11