ON ADP3211, ADP3211A Schematics

ADP3211, ADP3211A

7-Bit, Programmable, Single-Phase, Synchronous Buck Controller

The ADP3211 is a highly efficient, single−phase, synchronous buck switching regulator controller. With its integrated driver, the ADP3211 is optimized for converting the notebook battery voltage to the supply voltage required by high performance Intel chipsets. An internal 7−bit DAC is used to read a VID code directly from the chip−set or the CPU and to set the GMCH render voltage or the CPU core voltage to a value within the range of 0 V to 1.5 V.

The ADP3211 uses a multi−mode architecture. It provides programmable switching frequency that can be optimized for efficiency depending on the output current requirement. In addition, the ADP3211 includes a programmable load line slope function to adjust the output voltage as a function of the load current so that the core voltage is always optimally positioned for a load transient. The ADP3211 also provides accurate and reliable current overload protection and a delayed power−good output. The IC supports On−The−Fly (OTF) output voltage changes requested by the chip−set.

The ADP3211 has a boot voltage of 1.1 V for IMVP−6.5 applications in CPU mode. The ADP3211A has a boot voltage of

1.2 V in CPU mode.

The ADP3211 is specified over the extended commercial temperature range of −40°C to 100°C and is available in a 32−lead QFN.

Features

• Single−Chip Solution

♦ Fully Compatible with the Intel

Chipset Voltage Regulator Specifications Integrated MOSFET Drivers

• Input Voltage Range of 3.3 V to 22 V

• ±7 mV Worst−Case Differentially Sensed Core Voltage Error

Overtemperature

• Automatic Power−Saving Modes Maximize Efficiency During

Light Load Operation

• Soft Transient Control Reduces Inrush Current and Audio Noise

• Independent Current Limit and Load Line Setting Inputs for

Additional Design Flexibility

• Built−in Power−Good Masking Supports Voltage Identification

(VID) OTF Transients

• 7−Bit, Digitally Programmable DAC with 0 V to 1.5 V Output

• Short−Circuit Protection

• Current Monitor Output Signal

• This is a Pb−Free Device

• Fully RoHS Compliant

• 32−Lead QFN

Applications

• Notebook Power Supplies for Next Generation Intel Chipsets

• Intel Netbook Atom Processors

IMVP−6.5t CPU and GMCH

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QFN32

MN SUFFIX

MARKING DIAGRAM

ADP3211(A)

AWLYYWWG

(A) = ADP3211A Device Only A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

PIN ASSIGNMENT

VID0

PWRGD

IMON

CLKEN

FBRTN

COMP

GPU

ILIM

See detailed ordering and shipping information in the package dimensions section on page 31 of this data sheet.

IREF

RPM

ORDERING INFORMATION

CASE 488AM

VID1

VID2

VID3

ADP3211

ADP3211A

(top view)

LLINE

RAMP

VID4

VID5

CSFB

CSREF

VID6

VCC

BST

DRVH

PVCC

DRVL

PGND

GND

CSCOMP

November, 2009 − Rev. 2

1 Publication Order Number:

ADP3211/D

ADP3211, ADP3211A

COMP

LLINE

PWRGD

CLKEN

FBRTN

UVLO Shutdown

PWRGD

Open Drain

CLKEN

Open Drain

Precision

Reference

REF

DAC + 200mV

CSREF

DAC − 300 mV

VCCGND

and Bias

CSREF

−

VID

DAC

VEA

−

1.55V

PWRGD

Startup

Delay

CLKEN

Start Up

Delay

OVP

−

RPM RT

Oscillator

Soft

Transient

Delay

Delay Disable

Current

Limit

Circuit

RAMP

PVCC

MOSFET

Driver

OCP

Shutdown

Delay

Current Monitor

Soft Start

and Soft

Transient

Control

BST

DRVH

DRVL

PGND

IMON

−

CSREF

CSFB

CSCOMP

ILIM

GPU

VID6

VID5

VID4

VID3

VID2

VID1

VID0

IREF

Figure 1. Functional Block Diagram

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DAC

REF

ADP3211, ADP3211A

ABSOLUTE MAXIMUM RATINGS

Parameter Rating Unit

FBRTN, PGND −0.3 to +0.3 V

BST, DRVH

DC t < 200 ns

BST to PV

BST to SW −0.3 to +6.0 V

DRVH to SW −0.3 to +6.0 V

DRVL to PGND

RAMP (in Shutdown)

All Other Inputs and Outputs −0.3 to +6.0 V

Storage Temperature Range −65 to +150 °C

Operating Ambient Temperature Range −40 to 100 °C

Operating Junction Temperature 125 °C

Thermal Impedance (qJA) 2−Layer Board 32.6 °C/W

Lead Temperature

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.

DC t < 200 ns

Soldering (10 sec) Infrared (15 sec)

−0.3 to +6.0 V

−0.3 to +28

−0.3 to +33

−0.3 to +22

−0.3 to +28

−1.0 to +22

−6.0 to +28

−0.3 to +6.0

−5.0 to +6.0

−0.3 to +22

−0.3 to +26

°C 300 260

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ADP3211, ADP3211A

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 PWRGD Power−Good Output. Open−drain output. A low logic state means that the output voltage is outside of the

2 IMON Current Monitor Output. This pin sources current proportional to the output load current. A resistor connected

3 CLKEN Clock Enable Output. Open drain output. The pull−high voltage on this pin cannot be higher than VCC.

4 FBRTN Feedback Return Input/Output. This pin remotely senses the GMCH voltage. It is also used as the ground

5 FB Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.

6 COMP Voltage Error Amplifier Output and Frequency Compensation Point.

7 GPU GMCH/CPU select pin. Connect to ground when powering the CPU. Connect to 5.0 V when powering the

8 ILIM Current Limit Set pin. Connect a resistor between ILIM and CSCOMP to the current limit threshold.

9 IREF This pin sets the internal bias currents. A 80 kW is connected from IREF to ground.

10 RPM RPM Mode Timing Control Input. A resistor is connected from RPM to ground sets the RPM mode turn−on

11 RT PWM Oscillator Frequency Setting Input. An external resistor from this pin to GND sets the PWM oscillator

12 RAMP PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this pin sets

13 LLINE Load Line Programming Input. The center point of a resistor divider connected between CSREF and

14 CSREF Current Sense Reference Input. This pin must be connected to the opposite side of the output inductor.

15 CSFB Non−inverting Input of the Current Sense Amplifier. The combination of a resistor from the switch node to this

16 CSCOMP Current Sense Amplifier Output and Frequency Compensation Point.

17 GND Analog and Digital Signal Ground.

18 PGND Low−Side Driver Power Ground. This pin should be connected close to the source of the lower MOSFET(s).

19 DRVL Low−Side Gate Drive Output.

20 PVCC Power Supply Input/Output of Low−Side Gate Driver.

21 SW Current Return For High−Side Gate Drive.

22 DRVH High−Side Gate Drive Output.

23 BST High−Side Bootstrap Supply. A capacitor from this pin to SW holds the bootstrapped voltage while the

24 VCC Power Supply Input/Output of the Controller.

25 to 31 VID6 to VID0 Voltage Identification DAC Inputs. A 7−bit word (the VID Code) programs the DAC output voltage, the

32 EN Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, and pulls PWRGD low.

VID DAC defined range.

to FBRTN sets the current monitor gain.

return for the VID DAC and the voltage error amplifier blocks.

GMCH. When GPU is connected to ground, the boot voltage is 1.1 V for the ADP3211 and 1.2 V for the ADP3211A. When GPU is connected to 5.0 V, there is no boot voltage.

threshold voltage.

frequency.

the slope of the internal PWM stabilizing ramp.

CSCOMP tied to this pin sets the load line slope.

pin and the feedback network from this pin to the CSCOMP pin sets the gain of the current sense amplifier.

high−side MOSFET is on.

reference voltage of the voltage error amplifier without a load (see the VID Code Table, Table NO TAG). In normal operation mode, the VID DAC output programs the output voltage to a value within the 0 V to 1.5 V range. The input is actively pulled down.

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ADP3211, ADP3211A

ELECTRICAL CHARACTERISTICS (V

= PVCC = 5.0 V, FBRTN = GND = PGND = 0 V, H = 5.0 V, L = 0 V, V

VID

= V

TA = −40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sunk by the device) has a positive sign.

Parameter Symbol Conditions Min Typ Max Units

VOLTAGE CONTROL − Voltage Error Amplifier (VEAMP)

FB, LLINE Voltage Range (Note 2)

FB, LLINE Offset Voltage (Note 2)

FB Bias Current I

LLINE Bias Current I

LLINE Positioning Accuracy VFB − V

COMP Voltage Range V

COMP Current I

COMP Slew Rate SR

Gain Bandwidth (Note 2) GBW Non−inverting unit gain configuration,

VFB, V

OSVEA

COMP

LLINE

COMP

DAC

Relative to CSREF = V

DAC

−200 +200 mV

−0.5 +0.5 mV

−1.0 +1.0 mA

−50 +50 nA

Measured on FB relative to nominal V LLINE forced 80 mV below CSREF

−10°C to 100°C

−40°C to 100°C

DAC

−78

−77

−80

Voltage range of interest 0.85 4.0 V

COMP = 2.0 V, CSREF = V FB forced 200 mV below CSREF FB forced 200 mV above CSREF

= 10 pF, CSREF = V

COMP

Open loop configuration FB forced 200 mV below CSREF FB forced 200 mV above CSREF

DAC

−650

2.0

−10

20 MHz

RFB = 1 kW

VID DAC VOLTAGE REFERENCE

Voltage Range (Note 2) See VID Code Table 0 1.5 V

DAC

Accuracy VFB − V

DAC

Differential Non−linearity (Note 2) −1.0 +1.0 LSB

DAC

Line Regulation ΔV

DAC

Boot Voltage V

DAC

Soft−Start Delay (Note 2) t

Soft−Start Time t

Boot Delay t

Slew Rate Soft−Start

DAC

FBRTN Current I

DAC

BOOTFB

DSS

BOOT

FBRTN

Measured on FB (includes offset), relative to nominal V V V V

DAC

= 0.3000 V to 1.2000 V, −10°C to 100°C

DAC

= 0.3000 V to 1.2000 V, −40°C to 100°C

DAC

= 1.2125 V to 1.5000 V, −40°C to 100°C

DAC

−7.0

−9.0

VCC = 4.75 V to 5.25 V 0.05 %

Measured during boot delay period, GPU = 0 V ADP3211 ADP3211A

1.100

1.200

Measured from EN pos edge to FB = 50 mV 200 ms

Measured from EN pos edge to FB settles to V

= 1.1 V within −5%

boot

Measured from FB settling to Vboot = 1.1 V

1.4 ms

100 ms

within −5% to CLKEN neg edge

0.0625

Arbitrary VID step

1.0

70 200 mA

VOLTAGE MONITORING and PROTECTION − Power Good

CSREF Undervoltage Threshold

CSREF Overvoltage Threshold

CSREF Crowbar Voltage Threshold

CSREF Reverse Voltage Threshold

UVCSREF

DAC

OVCSREF

DAC

CBCSREF

RVCSREF

−

Relative to nominal V

−

Relative to nominal V

Voltage −360 −300 −240 mV

DAC

Voltage 150 200 250 mV

DAC

Relative to FBRTN 1.5 1.55 1.6 V

Relative to FBRTN, Latchoff Mode CSREF is falling CSREF is rising

−350 −300

−75 −5.0

DAC

−82

−83

+7.0 +9.0 +9.0

= 1.2 V,

V/ms

LSB/ms

1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2. Guaranteed by design or bench characterization, not production tested.

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ADP3211, ADP3211A

ELECTRICAL CHARACTERISTICS (V

= PVCC = 5.0 V, FBRTN = GND = PGND = 0 V, H = 5.0 V, L = 0 V, V

VID

= V

DAC

= 1.2 V,

TA = −40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sunk by the device) has a positive sign.

Parameter UnitsMaxTypMinConditionsSymbol

VOLTAGE MONITORING and PROTECTION − Power Good

PWRGD Low Voltage V

PWRGD High Leakage Current

PWRGD Startup Delay T

PWRGD Latchoff Delay T

PWRGD Propagation Delay

(Note 2)

Crowbar Latchoff Delay (Note 2)

PWRGD Masking Time T

PWRGD

SSPWRGD

LOFFPWRGD

PDPWRGD

LOFFCB

MSkPWRGD

PWRGD(SINK)

PWRDG

Measured from CLKEN neg edge to PWRGD

= 4 mA 75 200 mV

= 5.0 V 1.0 mA

8.0 ms

pos edge

Measured from Out−off−Good−Window event

8.0 ms

to Latchoff (switching stops)

Measured from Out−off−Good−Window event

200 ns

to PWRGD neg edge

Measured from Crowbar event to Latchoff

200 ns

(switching stops)

Triggered by any VID change 100 ms

CSREF Soft−Stop Resistance EN = L or Latchoff condition 60 W

CURRENT CONTROL − Current Sense Amplifier (CSAMP)

CSFB, CSREF Common−Mode Range

Voltage range of interest 0 2.0 V

(Note 2)

CSFB, CSREF Offset Voltage V

CSFB Bias Current I

CSREF Bias Current I

CSCOMP Voltage Range

OSCSA

BCSFB

BCSREF

CSREF – CSSUM, TA = −40°C to 85°C TA = 25°C

−1.5

−0.4

+1.5 +0.4

−50 +50 nA

−2.0 2.0 mA

Voltage range of interest 0.05 2.0 V

(Note 2)

CSCOMP Current

CSCOMPsource

CSCOMPsink

CSCOMP Slew Rate (Note 2) C

Gain Bandwidth (Note 2) GBW

CSA

CSCOMP = 2.0 V CSFB forced 200 mV below CSREF CSFB forced 200 mV above CSREF

= 10 pF, CSREF = V

CSCOMP

Open loop configuration

DAC

CSFB forced 200 mV below CSREF CSFB forced 200 mV above CSREF

Non−inverting unit gain configuration RFB = 1 kW

−650

1.0

−10

20 MHz

CURRENT MONITORING AND PROTECTION − Current Reference

Voltage V

REF

= 80 kW to set I

REF

= 20 mA 1.55 1.6 1.65 V

REF

CURRENT LIMITER (OCP)

Current Limit (OCP) Threshold

Current Limit Latchoff Delay Measured from OCP event to PWRGD

LIMTH

Measured from CSCOMP to CSREF R

= 4.5 kW

LIM

−11 5 −90 −70 mV

8.0 ms

de−assertion

CURRENT MONITOR

Current Gain Accuracy I

Clamp Voltage V

MON

MON/ILIM

MAXMON

Measured from I I

= −20 mA

LIM

= −10 mA

LIM

= −5 mA

LIM

Relative to FBRTN, I R

= 8 kW

IMON

to I

LIM

MON

= −30 mA

9.5

9.4

9.0

10 10 10

10.6

10.8 11

1.0 1.15 V

1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2. Guaranteed by design or bench characterization, not production tested.

V/ms

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ADP3211, ADP3211A

ELECTRICAL CHARACTERISTICS (V

= PVCC = 5.0 V, FBRTN = GND = PGND = 0 V, H = 5.0 V, L = 0 V, V

VID

= V

DAC

= 1.2 V,

TA = −40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sunk by the device) has a positive sign.

Parameter UnitsMaxTypMinConditionsSymbol

PULSE WIDTH MODULATOR − Clock Oscillator

RT Voltage V

PWM Clock Frequency Range (Note 2)

CLK

RT = 243 kW, V See also VRT(V

VID

= 1.2 V

) formula

1.08 1.2 1.35 V

Operation of interest 0.3 3.0 MHz

RAMP GENERATOR

RAMP Voltage V

RAMP Current Range (Note 2) I

RAMP

EN = H, I EN = L

RAMP

= 60 mA

EN = H EN = L, RAMP = 19 V

0.9 1.0

1.0

−0.5

100

+0.5

1.1 V

PWM COMPARATOR

PWM Comparator Offset (Note 2)

OSRPM

−3.0 +3.0 mV

RPM COMPARATOR

RPM Current I

RPM Comparator Offset

(Note 2)

RPM

OSRPM

= 1.2 V, RT = 243 kW

VID

See also I

COMP

RPM(RT

− (1 + V

) formula

−6.0 mA

) −3.0 +3.0 mV

RPM

SWITCH AMPLIFIER

SW Input Resistance R

Measured from SW to PGND 1.3 kW

ZERO CURRENT SWITCHING COMPARATOR

SW ZCS Threshold V

Masked Off−Time t

ZCSSW

OFFMSKD

DCM mode, DPRSLP = 3.3 V −4.0 mV

Measured from DRVH neg edge to DRVH

700 ns

pos edge at max frequency of operation

SYSTEM I/O BUFFERS − EN and VID[6:0] INPUTS

Input Voltage V

Input Current I

EN,VID[6:0]

Refers to driving signal level Logic low, I Logic high, I

EN,VID[6:0]

0.2 V < V

= 1 mA

sink

= −5 mA 0.7

source

= 0 V

EN,VID[6:0]

≤ V

0.3

1.0

VID Delay Time (Note 2) Any VID edge to 10% of FB change 200 ns

GPU INPUT

Input Voltage V

Input Current I

GPU

Refers to driving signal level Logic low, I Logic high, I

= 1 mA

sink

= −5 mA 4.0

source

GPU = L or GPU = H (static)

0.8 V < EN < 1.6 V (during transition)

0.3

10 70

CLKEN OUTPUT

Output Low Voltage V

Output High, Leakage Current I

CLKEN

Logic low, I

Logic high, V

= 4 mA 30 300 mV

CLKEN

= V

CLKEN

3.0 mA

SUPPLY

Supply Voltage Range V

Supply Current EN = H

EN = L

VCC OK Threshold V

VCC UVLO Threshold V

CCOK

CCUVLO

VCC is rising 4.4 4.5 V

VCC is falling 4.0 4.15 V

4.5 5.5 V

6.0 60

200

VCC Hysteresis (Note 2) 150 mV

1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2. Guaranteed by design or bench characterization, not production tested.

nA mA

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ADP3211, ADP3211A

ELECTRICAL CHARACTERISTICS (V

= PVCC = 5.0 V, FBRTN = GND = PGND = 0 V, H = 5.0 V, L = 0 V, V

VID

= V

DAC

= 1.2 V,

TA = −40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sunk by the device) has a positive sign.

Parameter UnitsMaxTypMinConditionsSymbol

HIGH−SIDE MOSFET DRIVER

Pullup Resistance, Sourcing Current Pulldown Resistance, Sinking Current

Transition Times tr

Dead Delay Times tpdh

DRVH,

DRVH

BST Quiescent Current EN = L (Shutdown)

BST = PV

BST = PVCC, CL = 3 nF, Figure 2 15

2.0

1.0

3.3

2.8

35 31

BST = PVCC, Figure 2 10 45 ns

EN = H, No Switching

5.0

200

15 mA

LOW−SIDE MOSFET DRIVER

Pullup Resistance, Sourcing Current Pulldown Resistance, Sinking Current

Transition Times tr

Propagation Delay Times tpdh

SW Transition Timeout t

SW Off Threshold V

DRVL,

DRVL

SWTO

OFFSW

CL = 3 nF, Figure 2 15

CL = 3 nF, Figure 2 15 30 ns

DRVH = L, SW = 2.5 V 150 250 450 ns

PVCC Quiescent Current EN = L (Shutdown)

EN = H, No Switching

1.8

0.9

3.0

2.7

2.2 V

50 mA

200

BOOTSTRAP RECTIFIER SWITCH

On−Resistance EN = L or EN = H and DRVL = H 4 7 11 W

1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2. Guaranteed by design or bench characterization, not production tested.

3. Timing is referenced to the 90% and 10% points, unless otherwise noted.

DRVL

DRVH

(with respect to SW)

tpdh

DRVL

DRVH

Figure 2. Timing Diagram

DRVH

1.0 V

tpdh

DRVL

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ADP3211, ADP3211A

TYPICAL PERFORMANCE CHARACTERISTICS

= 1.5 V, TA = 20°C to 100°C, unless otherwise noted.

VID

1: 200mV/div 2: 2V/div

Switch

Node

: 10V/div

Input = 12V, 1A Load VID Step 0.7V to 1.2V

Figure 3. VID Change Soft Transient

300

250

200

150

100

SWITCHING FREQUENCY (kHz)

SWITCHING

FREQUENCY

OUTPUT RIPPLE

LOAD CURRENT (A) LOAD CURRENT (A)

Output Voltage

VID5

20 ms/div

151050

1.2

1.0

OUTPUT RIPPLE (mV)

0.8

(V)

0.6

MON

0.4

0.2

Output Voltage

VID5

Switch Node

1: 200mV/div 2: 2V/div

3: 10V/div

Input = 12V, 1A Load VID Step 1.2V to 0.7V

20 ms/div

Figure 4. VID Change Soft Transient

2520151050

1.35

1.30

1.25

VID VOLTAGE (V)

1.20

1.15

Figure 5. Switching Frequency vs. Load

Current in RPM Mode

Measured Load Line

Specified Load Line

LOAD CURRENT (A) VCC VOLTAGE (V)

Figure 7. Load Line Accuracy Figure 8. VCC Current vs. VCC Voltage with

+2%

−2%

151050

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Figure 6. I

CURRENT (mA)

Voltage vs. Load Current

MON

6543210

Enable Low

ADP3211, ADP3211A

TYPICAL PERFORMANCE CHARACTERISTICS

Output Voltage

1: 0.5V/div 2: 5V/div

3: 5V/div 4: 5V/div

2ms/div

GPU = 0V

Figure 9. Startup Waveforms CPU Mode

Output Voltage

Switch Node

PWRGD

CLKEN

Inductor

Current

Output Voltage

1: 0.5V/div 2: 5V/div

3: 5V/div 4: 5V/div

4ms/div

PWRGD

CLKEN

GPU = 5V

Figure 10. Startup Waveforms GPU Mode

Output Voltage

Switch Node

Inductor

Current

3 4

1 : 100mV/div 2 : 10V/div

Low Side Gate Drive

3: 5A/div 4 : 5V/div

4 ms/div

Figure 11. DCM Waveforms, 1 A Load Current

Output Voltage

Switch Node

1: 50mV/div 2: 10V/div

40 ms/div

Input = 12V Output = 1.2V 3A to 15A Step

Figure 13. Load Transient Figure 14. Load Transient

1 : 100mV/div 2 : 10V/div

3 : 5A/div 4 : 5V/div

Low Side Gate Drive

2 ms/div

Figure 12. CCM Waveforms, 10 A Load Current

Output Voltage

Switch Node

1: 50mV/div 2: 10V/div

40 ms/div

Input = 12V Output = 1.2V 3A to 15A Step

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ADP3211, ADP3211A

TYPICAL PERFORMANCE CHARACTERISTICS

1: 50mV/div 2: 10V/div

1: 100mV/div 2: 10V/div

Switch Node

40 ms/div

Figure 15. Load Transient

Switch Node

200 ms/div

Output Voltage

Input = 12V Output = 1.2V 15A to 3A Step

Output Voltage

Input = 12V 10A Load DVID = 250mV

1 : 500mV/div 2 : 10V/div

Switch Node

1: 100mV/div 2: 10V/div

Figure 16. VID on the Fly

CLKEN

200 ms/div

3 : 5V/div 4 : 2V/div

Output Voltage

Input = 12V No Load DVID = 250mV

Output Voltage

Switch

Node

PWRGD

2ms/div

Figure 17. VID on the Fly

Figure 18. Over Current Protection

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ADP3211, ADP3211A

Theory of Operation

The ADP3211 is a Ramp Pulse Modulated (RPM) controller for synchronous buck Intel GMCH and CPU core power supply. The internal 7−bit VID DAC conforms to the Intel IMVP−6.5 specifications. The ADP3211 is a stable, high performance architecture that includes

• High speed response at the lowest possible switching

frequency and minimal count of output decoupling capacitors

• Minimized thermal switching losses due to lower

frequency operation

• High accuracy load line regulation

• High power conversion efficiency with a light load by

automatically switching to DCM operation

IR = AR X I

RAMP

1.0 V

VRMP

400ns

FLIP−FLOP

Operation Modes

The ADP3211 runs in RPM mode for the purpose of fast transient response and high light load efficiency. During the following transients, the ADP3211 runs in PWM mode:

• Soft−Start

• Soft transient: the period of 110 ms following any VID

change

• Current overload

5.0 V

BST

GATE DRIVER

BST

DRVH

DCM

DRVL

DRVH

DRVL

VCC

LOAD

30mV

COMP FB FBRTN

1.0 V

VDC

R1R2

Figure 19. RPM Mode Operation

LLINE

–

+ CSCOMP

CSREF

CSFB

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ADP3211, ADP3211A

5.0 V

VCC

IR = AR X I

RAMP

CLOCK

OSCILLATOR

0.2 V

COMP

FLIP−FLOP

VDC

FB FBRTN

Figure 20. PWM Mode Operation

DRIVER

–

+ LLINE

GATE

BST

DRVH

DRVL

DRVH

DRVL

CSREF

CSFB

BST

VCC

CSSUM

LOAD

Setting Switch Frequency

Master Clock Frequency in PWM Mode

When the ADP3211 runs in PWM, the clock frequency is set by an external resistor connected from the RT pin to GND. The frequency varies with the VID voltage: the lower the VID voltage, the lower the clock frequency. The variation of clock frequency with VID voltage maintains constant V

ripple and improves power conversion

CCGFX

efficiency at lower VID voltages.

Switching Frequency in RPM Mode

When the ADP3211 operates in RPM mode, its switching frequency is controlled by the ripple voltage on the COMP pin. Each time the COMP pin voltage exceeds the RPM pin voltage threshold level determined by the VID voltage and the external resistor connected between RPM and ground, an internal ramp signal is started and DRVH is driven high. The slew rate of the internal ramp is programmed by the current entering the RAMP pin. One−third of the RAMP current charges an internal ramp capacitor (5 pF typical) and creates a ramp. When the internal ramp signal intercepts the COMP voltage, the DRVH pin is reset low.

In continuous current mode, the switching frequency of RPM operation is almost constant. While in discontinuous current conduction mode, the switching frequency is reduced as a function of the load current.

Differential Sensing of Output Voltage

The ADP3211 combines differential sensing with a high accuracy VID DAC, referenced by a precision band gap source and a low offset error amplifier, to meet the rigorous accuracy requirement of the Intel IMVP−6.5 specification. In steady−state mode, the combination of the VID DAC and error amplifier maintain the output voltage for a worst−case scenario within ±7 mV of the full operating output voltage and temperature range.

The V

output voltage is sensed between the FB

CCGFX

and FBRTN pins. FB should be connected through a resistor to the positive regulation point, the VCC remote sensing pin of the GMCH or CPU. FBRTN should be connected directly to the negative remote sensing point, the VSS sensing point of the GMCH or CPU. The internal VID DAC and precision voltage reference are referenced to FBRTN and have a typical current of 70 mA for guaranteed accurate remote sensing.

Output Current Sensing

The ADP3211 includes a dedicated current sense amplifier (CSA) to monitor the total output current of the converter for proper voltage positioning vs. load current and for overcurrent detection. Sensing the current delivered to the load is an inherently more accurate method than detecting peak current or sampling the current across

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ADP3211, ADP3211A

a sense element, such as the low−side MOSFET. The current sense amplifier can be configured several ways, depending on system optimization objectives, and the current information can be obtained by:

• Output inductor ESR sensing without the use of a

thermistor for the lowest cost

• Output inductor ESR sensing with the use of a

thermistor that tracks inductor temperature to improve accuracy

• Discrete resistor sensing for the highest accuracy

At the positive input of the CSA, the CSREF pin is connected to the output voltage. At the negative input (that is, the CSFB pin of the CSA), signals from the sensing element (in the case of inductor DCR sensing, signals from the switch node side of the output inductors) are connected with a resistor. The feedback resistor between the CSCOMP and CSFB pins sets the gain of the current sense amplifier, and a filter capacitor is placed in parallel with this resistor. The current information is then given as the voltage difference between the CSCOMP and CSREF pins. This signal is used internally as a differential input for the current limit comparator.

An additional resistor divider connected between the CSCOMP and CSREF pins with the midpoint connected to the LLINE pin can be used to set the load line required by the GMCH specification. The current information to set the load line is then given as the voltage difference between the LLINE and CSREF pins. This configuration allows the load line slope to be set independent from the current limit threshold. If the current limit threshold and load line do not have to be set independently, the resistor divider between the CSCOMP and CSREF pins can be omitted and the CSCOMP pin can be connected directly to LLINE. To disable voltage positioning entirely (that is, to set no load line), LLINE should be tied to CSREF.

To provide the best accuracy for current sensing, the CSA has a low offset input voltage and the sensing gain is set by an external resistor ratio.

Active Impedance Control Mode

To control the dynamic output voltage droop as a function of the output current, the signal that is proportional to the total output current, converted from the voltage difference between LLINE and CSREF, can be scaled to be equal to the required droop voltage. This droop voltage is calculated by multiplying the droop impedance of the regulator by the output current. This value is used as the control voltage of the PWM regulator. The droop voltage is subtracted from the DAC reference output voltage, and the resulting voltage is used as the voltage positioning set−point. The arrangement results in an enhanced feed−forward response.

Voltage Control Mode

A high−gain bandwidth error amplifier is used for the voltage mode control loop. The non−inverting input voltage is set via the 7−bit VID DAC. The VID codes are

listed in Table NO TAG. The non−inverting input voltage is offset by the droop voltage as a function of current, commonly known as active voltage positioning. The output of the error amplifier is the COMP pin, which sets the termination voltage of the internal PWM ramps.

At the negative input, the FB pin is tied to the output sense location using RFB, a resistor for sensing and controlling the output voltage at the remote sensing point. The main loop compensation is incorporated in the feedback network connected between the FB and COMP pins.

Power−Good Monitoring

The power−good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open−drain output that can be pulled up through an external resistor to a voltage rail, not necessarily the same V

voltage rail that is running the controller. A logic high level indicates that the output voltage is within the voltage limits defined by a range around the VID voltage setting. PWRGD goes low when the output voltage is outside of this range.

Following the GMCH and CPU specification, the PWRGD range is defined to be 300 mV less than and 200 mV greater than the actual VID DAC output voltage. To prevent a false alarm, the power−good circuit is masked during any VID change and during soft−start. The duration of the PWRGD mask is set to approximately 130 ms by an internal timer. In addition, for a VID change from high to low, there is an additional period of PWRGD masking before the internal DAC voltage drops within 200 mV of the new lower VID DAC output voltage, as shown in Figure 21.

VID SIGNAL

CHANGE

INTERNAL

DAC VOLTAGE

PWRGD MASK

Figure 21. PWRGD Masking for VID Change

Powerup Sequence and Soft−Start

100 ms

The power−on ramp−up time of the output voltage is set internally. With GPU pulled to ground, the ADP3211 steps sequentially through each VID code until it reaches the boot voltage. With GPU pulled to 5.0 V, the ADP3211 steps sequentially through each VID code until it reaches the set VID code voltage. The powerup sequence is illustrated in Figure 22 for GPU connected to ground and Figure 23 for GPU connected to 5.0 V.

When GPU is connected to ground, the ADP3211 has a boot voltage of 1.1 V for IMVP−6.5 CPU applications. When GPU is connected to ground, the ADP3211A has a boot voltage of 1.2 V. The boot voltage is the only difference between the ADP3211 and ADP3211A.

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ADP3211, ADP3211A

VCC = 5.0 V

= 1.1 V

BOOT

DAC and V

BOOT

CLKEN

CPU_PWRGD

GPU = 0 V

Figure 22. ADP3211 Powerup Sequence for CPU

CORE

PWRGD

V5_S

CCGFX

PWRGD

GPU = 5.0 V

Figure 23. Powerup Sequence for GPU

VID Change and Soft Transient

PGDELAY

With GPU connected to 5.0 V for GPU operation, when a VID input changes, the ADP3211 detects the change but ignores new code for a minimum of 400 ns. This delay is required to prevent the device from reacting to digital signal skew while the 7−bit VID input code is in transition. Additionally, the VID change triggers a PWRGD masking timer to prevent a PWRGD failure. Each VID change resets and re−triggers the internal PWRGD masking timer.

The ADP3211 provides a soft transient function to reduce inrush current during VID transitions. Reducing the inrush current helps decrease the acoustic noise generated by the MLCC input capacitors and inductors.

The soft transient feature is implemented internally. When a new VID code is detected, the ADP3211 steps sequentially through each VID voltage to the final VID voltage.

Current Limit, Short−Circuit, and Latchoff Protection

The ADP3211 has an adjustable current limit set by the

resistor. The ADP3211 compares a programmable

CLIM

current limit set point to the voltage from the output of the current sense amplifier. The level of current limit is set with the resistor from the ILIM pin to CSCOMP. During operation, the voltage on ILIM is equal to the voltage on CSREF. The current through the external resistor connected between I

and CSCOMP is then compared to

LIM

the internal current limit current Icl. If the current generated through this resistor into the ILIM pin (Ilim) exceeds the internal current limit threshold current (Icl), the internal current limit amplifier controls the internal COMP voltage to maintain the average output current at the limit.

Normally, the ADP3211 operates in RPM mode. During

a current overload, the ADP3211 switches to PWM mode.

With low impedance loads, the ADP3211 operates in a constant current mode to ensure that the external MOSFETs and inductor function properly and to protect the GPU or CPU. With a low constant impedance load, the output voltage decreases to supply only the set current limit. If the output voltage drops below the power−good limit, the PWRGD signal transitions. After the PWRGD single transitions, internal waits 8 ms before latching off the ADP3211.

Figure 24 shows how the ADP3211 reacts to a current overload.

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ADP3211, ADP3211A

Output Voltage 0.5 V/div

SWITCH NODE 10 V/div

PWRGD 5.0 V/div

CLKEN

CURRENT LIMIT

The latchoff function can be reset either by removing and

reapplying VCC or by briefly pulling the EN pin low.

During startup, when the output voltage is below 200 mV, a secondary current limit is active. This is necessary because the voltage swing of CSCOMP cannot extend below ground. This secondary current limit clamp controls the minimum internal COMP voltage to the PWM comparators to 1.5 V. This limits the voltage drop across the low−side MOSFETs through the current balance circuitry.

Light Load RPM DCM Operation

The ADP3211 operates in RPM mode. With higher loads, the ADP3211 operates in continuous conduction mode (CCM), and the upper and lower MOSFETs run synchronously and in complementary phase. See Figure 25 for the typical waveforms of the ADP3211 running in CCM with a 10 A load current.

2.0 V/div

2 ms/div

APPLIED

Figure 24. Current Overload

LOW SIDE GATE 5.0 V/div

LATCHED

OFF

In DCM with a light load, the ADP3211 monitors the switch node voltage to determine when to turn off the low−side FET. Figure 31 shows a typical waveform in DCM with a 1 A load current. Between t1 and t2, the inductor current ramps down. The current flows through the source drain of the low−side FET and creates a voltage drop across the FET with a slightly negative switch node. As the inductor current ramps down to 0 A, the switch voltage approaches 0 V, as seen just before t2. When the switch voltage is approximately −4 mV, the low−side FET is turned off.

Figure 30 shows a small, dampened ringing at t2. This is caused by the LC created from capacitance on the switch node, including the CDS of the FETs and the output inductor. This ringing is normal.

The ADP3211 automatically goes into DCM with a light load. Figure 31 shows the typical DCM waveform of the ADP3211 with a 1 A load current. As the load increases, the ADP3211 enters into CCM. In DCM, frequency decreases with load current, and switching frequency is a function of the inductor, load current, input voltage, and output voltage.

INPUT

VOLTAGE

DRVH

DRVL

Figure 26. Buck Topology

SWITCH

NODE

OUTPUT

VOLTAGE

LOAD

SWITCH NODE

5.0 V/div

CSREF to CSCOMP 50mV/div

2 ms/div

Figure 25. Single−Phase Waveforms in CCM

With lighter loads, the ADP3211 enters discontinuous conduction mode (DCM). Figure 26 shows a typical single−phase buck with one upper FET, one lower FET, an output inductor, an output capacitor, and a load resistor. Figure 27 shows the path of the inductor current with the upper FET on and the lower FET off. In Figure 28 the high−side FET is off and the low−side FET is on. In CCM, if one FET is on, its complementary FET must be off; however, in DCM, both high− and low−side FETs are off and no current flows into the inductor (see Figure 29). Figure 30 shows the inductor current and switch node voltage in DCM.

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OFF

Figure 27. Buck Topology Inductor Current During t

and t

OFF

Figure 28. Buck Topology Inductor Current During

and t

OFF

Figure 29. Buck Topology Inductor Current During

and t

LOAD

ADP3211, ADP3211A

Inductor

Current

Switch

Node

Voltage

t0t

Figure 30. Inductor Current and Switch Node in DCM

SWITCH NODE

5.0 V/div

CSREF to CSCOMP 50mV/div

LOW SIDE GATE 5V/div

t3t

Reverse Voltage Protection

Very large reverse current in inductors can cause

negative V

voltage, which is harmful to the chip−set

CCGFX

and other output components. The ADP3211 provides a reverse voltage protection (RVP) function without additional system cost. The V

voltage is monitored

CCGFX

through the CSREF pin. When the CSREF pin voltage drops to less than −300 mV, the ADP3211 triggers the RVP function by setting both DRVH and DRVL low, thus turning off all MOSFETs. The reverse inductor currents can be quickly reset to 0 by discharging the built−up energy in the inductor into the input dc voltage source via the forward−biased body diode of the high−side MOSFETs. The RVP function is terminated when the CSREF pin voltage returns to greater than −100 mV.

Sometimes the crowbar feature inadvertently results in

negative V

voltage because turning on the low−side

CCGFX

MOSFETs results in a very large reverse inductor current. To prevent damage to the chip−set caused from negative voltage, the ADP3211 maintains its RVP monitoring function even after OVP latchoff. During OVP latchoff, if the CSREF pin voltage drops to less than −300 mV, the low−side MOSFETs is turned off by setting DRVL low. DRVL will be set high again when the CSREF voltage recovers to greater than −100 mV.

Figure 32 shows the reverse voltage protection function of the ADP3211. The CSREF pin is disconnected from the output voltage and pulled negative. As the CSREF pin drops to less than −300 mV, the low−side and high−side FETs turn off.

4 ms/div

Figure 31. Single−Phase Waveforms in DCM with 1 A

Load Current

Output Crowbar

To protect the load and output components of the supply, the DRVL output is driven high (turning the low−side MOSFETs on) and DRVH is driven low (turning the high−side MOSFETs off) when the output voltage exceeds the CPU or GMCH OVP threshold.

Turning on the low−side MOSFETs forces the output capacitor to discharge and the current to reverse due to current build up in the inductors. If the output overvoltage is due to a drain−source short of the high−side MOSFET, turning on the low−side MOSFET results in a crowbar across the input voltage rail. The crowbar action blows the fuse of the input rail, breaking the circuit and thus protecting the CPU or GMCH chip−set from destruction.

When the OVP feature is triggered, the ADP3211 is latched off. The latchoff function can be reset by removing and reapplying VCC to the ADP3211 or by briefly pulling the EN pin low.

SWITCH NODE

10 V/div

LOW SIDE GATE

5.0 V/div

PWRGD

5.0 V/div

OVP RVP

Figure 32. ADP3211 RVP Function

Output Enable and UVLO

OUTPUT VOLTAGE

0.5 V/div

20 ms/div

For the ADP3211 to begin switching, the VCC supply voltage to the controller must be greater than the V threshold and the EN pin must be driven high. If the V voltage is less than the V

CCUVLO

threshold or the EN pin

CCOK

is logic low, the ADP3211 shuts off. In shutdown mode, the controller holds DRVH and DRVL low and drives PWRGD to low.

The user must adhere to proper power−supply sequencing during startup and shutdown of the ADP3211. All input pins must be at ground prior to removing or applying VCC, and all output pins should be left in high impedance state while VCC is off.

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Overlay Protection Circuit

The overlap protection circuit prevents both main power switches, the high side MOSFET Q1 and the low side MOSFET Q2, from being on at the same time. This is done to prevent shoot−through currents from flowing through both power switches and the associated losses that can occur during their on−off transitions. The overlap protection circuit accomplishes this by adaptively controlling the delay from Q1’s turn−off to Q2’s turn−on, and the delay from Q2’s turn−off to Q1’s turn−on.

supply voltage, gate charge, and drive current. There is, however, a timeout circuit that overrides the waiting period for the SW and DRVH pins to reach 2.2 V. After the timeout period has expired, DRVL is asserted high regardless of the SW and DRVH voltages. The timeout period is approximately 250 ns. In the opposite case, when the internal PWM signal goes high, Q2 begins to turn off after a propagation delay. The overlap protection circuit waits for the voltage at DRVL to fall below 2.2 V, after which DRVH is asserted high and Q1 turns on.

To prevent the overlap of the gate drives during Q1’s turn−off and Q2’s turn−on, the overlap circuit monitors the voltage at the SW pin and DRVH pin. When the internal PWM signal goes low, Q1 begins to turn off. The overlap protection circuit waits for the voltage at the SW and DRVH pins to both fall below 2.2 V. Once both of these conditions are met, Q2 begins to turn on. Using this method, the overlap protection circuit ensures that Q1 is off before Q2 turns on, regardless of variations in temperature,

Table 1. VID Code Table

VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output (V)

0 0 0 0 0 0 0 1.5000

0 0 0 0 0 0 1 1.4875

0 0 0 0 0 1 0 1.4750

0 0 0 0 0 1 1 1.4625

0 0 0 0 1 0 0 1.4500

0 0 0 0 1 0 1 1.4375

0 0 0 0 1 1 0 1.4250

0 0 0 0 1 1 1 1.4125

0 0 0 1 0 0 0 1.4000

0 0 0 1 0 0 1 1.3875

0 0 0 1 0 1 0 1.3750

0 0 0 1 0 1 1 1.3625

0 0 0 1 1 0 0 1.3500

0 0 0 1 1 0 1 1.3375

0 0 0 1 1 1 0 1.3250

0 0 0 1 1 1 1 1.3125

0 0 1 0 0 0 0 1.3000

0 0 1 0 0 0 1 1.2875

0 0 1 0 0 1 0 1.2750

0 0 1 0 0 1 1 1.2625

0 0 1 0 1 0 0 1.2500

0 0 1 0 1 0 1 1.2375

0 0 1 0 1 1 0 1.2250

0 0 1 0 1 1 1 1.2125

0 0 1 1 0 0 0 1.2000

0 0 1 1 0 0 1 1.1875

0 0 1 1 0 1 0 1.1750

0 0 1 1 0 1 1 1.1625

0 0 1 1 1 0 0 1.1500

0 0 1 1 1 0 1 1.1375

0 0 1 1 1 1 0 1.1250

0 0 1 1 1 1 1 1.1125

Output Current Monitor

The ADP3211 includes an output current monitor

function. The I

pin outputs an accurate current that is

MON

directly proportional to the output current. This current is then run through a parallel RC connected from the I to the FBRTN pin to generate an accurately scaled and filtered voltage. The maximum voltage on I internally clamped by the ADP3211 at 1.15.V.

MON

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Table 1. VID Code Table

VID6 Output (V)VID0VID1VID2VID3VID4VID5

0 1 0 0 0 0 0 1.1000

0 1 0 0 0 0 1 1.0875

0 1 0 0 0 1 0 1.0750

0 1 0 0 0 1 1 1.0625

0 1 0 0 1 0 0 1.0500

0 1 0 0 1 0 1 1.0375

0 1 0 0 1 1 0 1.0250

0 1 0 0 1 1 1 1.0125

0 1 0 1 0 0 0 1.0000

0 1 0 1 0 0 1 0.9875

0 1 0 1 0 1 0 0.9750

0 1 0 1 0 1 1 0.9625

0 1 0 1 1 0 0 0.9500

0 1 0 1 1 0 1 0.9375

0 1 0 1 1 1 0 0.9250

0 1 0 1 1 1 1 0.9125

0 1 1 0 0 0 0 0.9000

0 1 1 0 0 0 1 0.8875

0 1 1 0 0 1 0 0.8750

0 1 1 0 0 1 1 0.8625

0 1 1 0 1 0 0 0.8500

0 1 1 0 1 0 1 0.8375

0 1 1 0 1 1 0 0.8250

0 1 1 0 1 1 1 0.8125

0 1 1 1 0 0 0 0.8000

0 1 1 1 0 0 1 0.7875

0 1 1 1 0 1 0 0.7750

0 1 1 1 0 1 1 0.7625

0 1 1 1 1 0 0 0.7500

0 1 1 1 1 0 1 0.7375

0 1 1 1 1 1 0 0.7250

0 1 1 1 1 1 1 0.7125

1 0 0 0 0 0 0 0.7000

1 0 0 0 0 0 1 0.6875

1 0 0 0 0 1 0 0.6750

1 0 0 0 0 1 1 0.6625

1 0 0 0 1 0 0 0.6500

1 0 0 0 1 0 1 0.6375

1 0 0 0 1 1 0 0.6250

1 0 0 0 1 1 1 0.6125

1 0 0 1 0 0 0 0.6000

1 0 0 1 0 0 1 0.5875

1 0 0 1 0 1 0 0.5750

1 0 0 1 0 1 1 0.5625

1 0 0 1 1 0 0 0.5500

1 0 0 1 1 0 1 0.5375

1 0 0 1 1 1 0 0.5250

1 0 0 1 1 1 1 0.5125

1 0 1 0 0 0 0 0.5000

1 0 1 0 0 0 1 0.4875

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Table 1. VID Code Table

VID6 Output (V)VID0VID1VID2VID3VID4VID5

1 0 1 0 0 1 0 0.4750

1 0 1 0 0 1 1 0.4625

1 0 1 0 1 0 0 0.4500

1 0 1 0 1 0 1 0.4375

1 0 1 0 1 1 0 0.4250

1 0 1 0 1 1 1 0.4125

1 0 1 1 0 0 0 0.4000

1 0 1 1 0 0 1 0.3875

1 0 1 1 0 1 0 0.3750

1 0 1 1 0 1 1 0.3625

1 0 1 1 1 0 0 0.3500

1 0 1 1 1 0 1 0.3375

1 0 1 1 1 1 0 0.3250

1 0 1 1 1 1 1 0.3125

1 1 0 0 0 0 0 0.3000

1 1 0 0 0 0 1 0.2875

1 1 0 0 0 1 0 0.2750

1 1 0 0 0 1 1 0.2625

1 1 0 0 1 0 0 0.2500

1 1 0 0 1 0 1 0.2375

1 1 0 0 1 1 0 0.2250

1 1 0 0 1 1 1 0.2125

1 1 0 1 0 0 0 0.2000

1 1 0 1 0 0 1 0.1875

1 1 0 1 0 1 0 0.1750

1 1 0 1 0 1 1 0.1625

1 1 0 1 1 0 0 0.1500

1 1 0 1 1 0 1 0.1375

1 1 0 1 1 1 0 0.1250

1 1 0 1 1 1 1 0.1125

1 1 1 0 0 0 0 0.1000

1 1 1 0 0 0 1 0.0875

1 1 1 0 0 1 0 0.0750

1 1 1 0 0 1 1 0.0625

1 1 1 0 1 0 0 0.0500

1 1 1 0 1 0 1 0.0375

1 1 1 0 1 1 0 0.0250

1 1 1 0 1 1 1 0.0125

1 1 1 1 0 0 0 0.0000

1 1 1 1 0 0 1 0.0000

1 1 1 1 0 1 0 0.0000

1 1 1 1 0 1 1 0.0000

1 1 1 1 1 0 0 0.0000

1 1 1 1 1 0 1 0.0000

1 1 1 1 1 1 0 0.0000

1 1 1 1 1 1 1 0.0000

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ADP3211, ADP3211A

C18, 0.1 mF

CLKEN

CB1

220 pF

CFB1

22 pF

COMP

DRVL

PVCC

ADP3211

FBRTN

R18

4.53 kΩ

CLKEN

DRVH

IMON

BST

10 kΩ

R16

PWRGD

R17

0 Ω

V3.3V

PWRGD

VID0

VID1

VID2

VID3

VID4

VID5

VID6 VCC

V3.3V

VR_ON

VID0

VID1

VID2

VID3

VID4

VID5

VID6

V5S

10 Ω

C28

1 nF

VSSSENSE

VCCSENSE

CA1

470 pF

100Ω

R14 200 kΩ

R13

VGFX_CORE

R23

0 Ω

R25

7.68 kΩ

DNP

R20

IREF

RPM

RAMP

LLINE

CSREF

CSFB

CSCOMP

0 Ω

ILIM

AGND

C21, 0.33 mF

20 kΩ

R21

RA1

GPU

PGND

100 Ω

R53

VGFX_CORE_RTN

R15 340 kΩ

1nF

C27

100 pF

VDC

R24 DNP

4.7 mF

TP8

L1, 560nH/

1.3mΩ

VGFX_CORE

NTMFS4821N

DRVH

GND

TP11

GND

10mF

25V

10mF

25V

10mF

25V

VDC

RPH1

53.6

kΩ

RTH1, 220kΩ

8% NTC

22mF

6.3V

22mF

6.3V

0.22mF

0.1mF

VGFX_CORE_RTN

0.1mF

1nF

NTMS4846N

NTMFS4846N

C10

C11

C12

C13

C14

RPH2

DNP

TP12

DRVL

R55

0 Ω

R54

DNP

C22

220mF

2.5V

C23

220mF

2.5V

C30

DNP

C31

DNP

C15

DNP

Figure 33. Typical Application Circuit

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Application Information

The ADP3211 application circuit should be fine−tuned in the final design. The equations in the Application Information section are used as a starting point for a new design.

The design parameters for a typical IMVP−6.5− compliant GPU core VR application are as follows:

• Maximum input voltage (V

• Minimum input voltage (V

• Output voltage by VID setting (V

• Maximum output current (I

• Droop resistance (R

) = 8 mW

• Nominal output voltage at 10 A load (V

INMAX

INMIN

) = 10 A

) = 19 V

) = 8.0 V

) = 1.1 V

VID

) = 1.02 V

OFL

• Static output voltage drop from no load to full load

(DV) = V

• Maximum output current step (DI

• Switching frequency (f

• Duty cycle at maximum input voltage (D

• Duty cycle at minimum input voltage (D

Setting the Clock Frequency for PWM

The ADP3211 operates in fixed frequency PWM mode during startup, for 100 ms after a VID change, and in current limit. In PWM operation, the ADP3211 uses a fixed−frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency determines the switching frequency, which relates directly to the switching losses and the sizes of the inductors and input and output capacitors. For example, a clock frequency of 400 kHz sets the switching frequency to 400 kHz. This selection represents the trade−off between the switching losses and the minimum sizes of the output filter components. To achieve a 400 kHz oscillator frequency at a VID voltage of 1.1 V, R must be 274 kW. Alternatively, the value for RT can be calculated by using the following equation:

RT+

where: 9 pF and 16 kW are internal IC component values. V

is the VID voltage in volts.

VID

fSW is the switching frequency in hertz.

For good initial accuracy and frequency stability, it is recommended to use a 1% resistor.

Ramp Resistor Selection

The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. Use this equation to determine a starting value:

RR+

3 A

RR+

3 5 5.2 mW 5pF

− V

ONL

VID

2 fSW 9pF

0.5 560 nH

OFL

) 1.0 V

AR L

RDS C

= 1.1 V − 1.02 V = 80 mV

) = 8 A

) = 400 kHz

) = 0.14

MAX

) = 0.054

MIN

* 16 kW

+ 718 kW

(eq. 1)

(eq. 2)

where: AR is the internal ramp amplifier gain. AD is the current balancing amplifier gain. RDS is the total low−side MOSFET on−resistance, CR is the internal ramp capacitor value.

Setting the Switching Frequency for RPM Operation

During the RPM operation, the ADP3211 runs in pseudo−constant frequency if the load current is high enough for continuous current mode. While in DCM, the switching frequency is reduced with the load current in a linear manner. To save power with light loads, lower switching frequency is usually preferred during RPM operation. However, the V

ripple specification of

CCGFX

IMVP−6.5 sets a limitation for the lowest switching frequency. Therefore, depending on the inductor and output capacitors, the switching frequency in RPM can be equal to, greater than, or less than its counterpart in PWM.

A resistor from RPM to GND sets the pseudo constant frequency as following:

RPM

2 R

VID

) 1.0 V

AR (1 * D) V

RR CR f

where: AR is the internal ramp amplifier gain. CR is the internal ramp capacitor value. R

is an external resistor on the RAMPADJ pin to set the

internal ramp magnitude.

Because R

= 718 kW, the following resistance sets up

400 kHz switching frequency in RPM operation.

RPM

2 274 kW

1.1 V ) 1.0 V

Inductor Selection

0.5 (1 * 0.054) 1.1 V

718 kW 5pF 400 kHz

* 500 W + 93.1 kW

The choice of inductance determines the ripple current of the inductor. Less inductance results in more ripple current, which increases the output ripple voltage and the conduction losses in the MOSFETs. However, this allows the use of smaller−size inductors, and for a specified peak−to−peak transient deviation, it allows less total output capacitance. Conversely, a higher inductance results in lower ripple current and reduced conduction losses, but it requires larger−size inductors and more output capacitance for the same peak−to−peak transient deviation. For a buck converter, the practical value for peak−to−peak inductor ripple current is less than 50% of the maximum dc current of that inductor. Equation 5 shows the relationship between the inductance, oscillator frequency, and peak−to−peak ripple current. Equation 6 can be used to determine the minimum inductance based on a given output ripple voltage.

VID

* 0.5 kW

(eq. 3)

(eq. 4)

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ADP3211, ADP3211A

IR+

L w

(1 * D

VID

RO (1 * D

VID

MIN

RIPPLE

)

MIN

(eq. 5)

(eq. 6)

In this example, RO is assumed to be the ESR of the output capacitance, which results in an optimal transient response. Solving Equation 6 for a 16 mV peak−to−peak output ripple voltage yields:

1.1 V 8mW (1 * 0.054)

L w

400 kHz 16 mV

+ 1.4 mH

(eq. 7)

If the resultant ripple voltage is less than the initially selected value, the inductor can be changed to a smaller value until the ripple value is met. This iteration allows optimal transient response and minimum output decoupling. In this example, the iteration showed that a 560 nH inductor was sufficient to achieve a good ripple.

The smallest possible inductor should be used to minimize the number of output capacitors. Choosing a 560 nH inductor is a good choice for a starting point, and it provides a calculated ripple current of 6.6 A. The inductor should not saturate at the peak current of 18.3 A, and it should be able to handle the sum of the power dissipation caused by the winding’s average current (10 A) plus the ac core loss.

Another important factor in the inductor design is the DCR, which is used for measuring the inductor current. Too large of a DCR causes excessive power losses, whereas too small of a value leads to increased measurement error. For this example, an inductor with a DCR of 1.3 mW is used.

Selecting a Standard Inductor

After the inductance and DCR are known, select a standard inductor that best meets the overall design goals. It is also important to specify the inductance and DCR tolerance to maintain the accuracy of the system. Using 10% tolerance for the inductance and 7% for the DCR at room temperature are reasonable values that most manufacturers can meet.

Power Inductor Manufacturers

The following companies provide surface−mount power inductors optimized for high power applications upon request.

Vishay Dale Electronics, Inc. (605) 665−9301 Panasonic (714) 373−7334 Sumida Electric Company (847) 545−6700 NEC Tokin Corporation (510) 324−4110

Output Droop Resistance

The design requires that the regulator output voltage measured at the chip−set pins decreases when the output current increases. The specified voltage drop corresponds to the droop resistance (RO).

The output current is measured by low−pass filtering the voltage across the inductor or current sense resistor. The filter is implemented by the CS amplifier that is configured with RPH, RCS, and CCS. The output resistance of the regulator is set by the following equations:

RO+

CCS+

where R

SENSE

is the DCR of the output inductors.

SENSE

(eq. 8)

(eq. 9)

Either RCS or RPH can be chosen for added flexibility. Due to the current drive ability of the CSCOMP pin, the RCS resistance should be greater than 100 kW. For example, initially select RCS to be equal to 200 kW, and then use Equation 9 to solve for CCS:

CCS+

560 nH

1.3 mW 200 kW

+ 2.2 nF

(eq. 10)

If CCS is not a standard capacitance, RCS can be tuned. In this case, the required CCS is a standard value and no tuning is required. For best accuracy, CCS should be a 5% NPO capacitor.

Next, solve for RPH by rearranging Equation 8 as follows:

RPHw

1.3 mW 8mW

200 kW + 32.5 kW

(eq. 11)

The standard 1% resistor for RPH is 32.4 kW.

Inductor DCR Temperature Correction

If the DCR of the inductor is used as a sense element and copper wire is the source of the DCR, the temperature changes associated with the inductor’s winding must be compensated for. Fortunately, copper has a well−known temperature coefficient (TC) of 0.39%/°C.

If RCS is designed to have an opposite but equal percentage of change in resistance, it cancels the temperature variation of the inductor’s DCR. Due to the nonlinear nature of NTC thermistors, series resistors R and R

(see Figure 34) are needed to linearize the NTC

CS2

CS1

and produce the desired temperature coefficient tracking.

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ADP3211, ADP3211A

Place as close as possible

to nearest inductor

ADP3211

CS1

−

CSCOMP

CSFB

CSREF

Figure 34. Temperature−Compensation Circuit Values

The following procedure and expressions yield values

for R

CS1

, R

, and RTH (the thermistor value at 25°C) for

CS2

a given RCS value.

1. Select an NTC to be used based on its type and value. Because the value needed is not yet determined, start with a thermistor with a value close to RCS and an NTC with an initial tolerance of better than 5%.

2. Find the relative resistance value of the NTC at two temperatures. The appropriate temperatures will depend on the type of NTC, but 50°C and 90°C have been shown to work well for most types of NTCs. The resistance values are called A (A is RTH(50°C)/RTH(25°C)) and B (B is RTH(90°C)/RTH(25°C)). Note that the relative value of the NTC is always 1 at 25°C.

3. Find the relative value of RCS required for each of the two temperatures. The relative value of RCS is based on the percentage of change needed, which is initially assumed to be 0.39%/°C in this example. The relative values are called r1 (r1 is 1/(1+ TC × (T1 − 25))) and r2 (r2 is 1/(1 + TC × (T2 − 25))), where TC is 0.0039, T1 is 50°C, and T2 is 90°C.

4. Compute the relative values for r

CS1

, r

CS2

, and

rTH by using the following equations:

(A * B) r1 r2* A (1 * B) r2) B (1 * A) r

CS2

A (1 * B) r1* B (1 * A) r2* (A * B)

1*r

CS2

(1 * A)

r1*r

CS1

CS2

CS1

rTH+

(eq. 12)

5. Calculate RTH = rTH × RCS, and then select a thermistor of the closest value available. In addition, compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one:

k +

TH(CALCULATED)

TH(ACTUAL)

(eq. 13)

CS1

To V

Sense

To Switch Node

CS2

Keep This Path As Short As Possible And Well Away From Switch Node Lines

6. Calculate values for R

OUT

CS1

and R

CS2

following equations:

+ RCS k r

CS1

+ RCS ǒ(1 * k) ) (k r

CS2

CS1

CS2

)

For example, if a thermistor value of 100 kW is selected

in Step 1, an available 0603−size thermistor with a value close to RCS is the Vishay NTHS0603N04 NTC thermistor, which has resistance values of A = 0.3359 and B = 0.0771. Using the equations in Step 4, r

is 0.359, r

CS1

and rTH is 1.094. Solving for rTH yields 219 kW, so a thermistor of 220 kW would be a reasonable selection, making k equal to 1.005. Finally, R

CS1

and R

to be 72.2 kW and 146 kW. Choosing the closest 1% resistor values yields a choice of 71.5 kW and 147 kW.

Selection

out

The required output decoupling for processors and platforms is typically recommended by Intel. For systems containing both bulk and ceramic capacitors, however, the following guidelines can be a helpful supplement.

Select the number of ceramics and determine the total ceramic capacitance (CZ). This is based on the number and type of capacitors used. Keep in mind that the best location to place ceramic capacitors is inside the socket; however, the physical limit is twenty 0805−size pieces inside the socket. Additional ceramic capacitors can be placed along the outer edge of the socket. A combined ceramic capacitor value of 40 mF to 50 mF is recommended and is usually composed of multiple 10 mF or 22 mF capacitors.

Ensure that the total amount of bulk capacitance (CX) is within its limits. The upper limit is dependent on the VID OTF output voltage stepping (voltage step, VV, in time, tV, with error of V

); the lower limit is based on meeting the

ERR

critical capacitance for load release at a given maximum load step, DIO. The current version of the IMVP−6.5 specification allows a maximum V (V

) of 10 mV more than the VID voltage for a

OSMAX

CCGFX

step−off load current.

by using the

(eq. 14)

is 0.729,

CS2

are found

CS2

overshoot

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ADP3211, ADP3211A

RO)

+ 256 m

ȧ Ȥ

−44 mF

ȧ Ȥ

(eq. 18)

L DI

To meet the conditions of these expressions and the transient response, the ESR of the bulk capacitor bank (RX) should be less than two times the droop resistance, RO. If the C meet the VID OTF specifications and may require less inductance. In addition, the switching frequency may have to be increased to maintain the output ripple.

For example, if two pieces of 22 mF, 0805−size MLC capacitors (CZ = 44 mF) are used during a VID voltage change, the V setting error of 10 mV. If k = 3.1, solving for the bulk capacitance yields:

is greater than C

X(MIN)

X(MAX)

change is 220 mV in 22 ms with a

CCGFX

X(MIN)

X(MAX)

where k + −1n

, the system does not

ȡ ȧ

X(MIN)

X(MAX)

3.1

22 ms 1.174 V 3.1 5.1 mW

+ 992 mF (eq. 17)

Using two 220 mF Panasonic SP capacitors with a typical ESR of 7 mW each yields CX = 440 mF and RX = 3.5 mW.

Ensure that the ESL of the bulk capacitors (LX) is low enough to limit the high frequency ringing during a load change. This is tested using:

LXv CZ R

LXv 44 mF (5.1 mW)2 2 + 2.3 nH

where: Q is limited to the square root of 2 to ensure a critically damped system. LX is about 450 pH for the two SP capacitors, which is low enough to avoid ringing during a load change. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capacitors may need to be increased to prevent excessive ringing.

560 nH 8A

10 mV

5.1 mW)

560 nH 220 mV

(5.1 mW)2 1.174 V

220 mV 560 nH

1.174 V

−44 mF

−1

OSMAX

VID

ERR

* C

VID

ȧ Ȣ

For this multi−mode control technique, an all ceramic capacitor design can be used if the conditions of Equations 15, 16, and 18 are satisfied.

Power MOSFETs

For typical 15 A applications, the N−channel power MOSFETs are selected for one high−side switch and two low−side switch. The main selection parameters for the power MOSFETs are V R

DS(ON)

logic−level threshold MOSFETs must be used.

The maximum output current, IO, determines the R

DS(ON)

MOSFETs. With conduction losses being dominant, the following expression shows the total power that is dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and the average total output current (IO):

PSF+ (1 * D)

where: D is the duty cycle and is approximately the output voltage divided by the input voltage. IR is the inductor peak−to−peak ripple current and is approximately:

Knowing the maximum output current and the maximum allowed power dissipation, the user can calculate the required R 8−lead SOIC−compatible MOSFET, the junction to ambient (PCB) thermal impedance is 50°C/W. In the worst case, the PCB temperature is 70°C to 80°C during heavy load operation of the notebook, and a safe limit for PSF is about 0.8 W to 1.0 W at 120°C junction temperature. Therefore, for this example (15 A maximum), the R per MOSFET is less than 18.8 mW for the low−side MOSFET. This R

1 )ǒt

. Because the voltage of the gate driver is 5.0 V,

requirement for the low−side (synchronous)

DS(ON)

k R

VID

GS(TH)

(1 * D) V

IR+

for the MOSFET. For an 8−lead SOIC or

DS(SF)

L f

is also at a junction temperature of

)

* 1

ȧ Ȥ

, QG, C

OUT

* C

, C

ISS

(eq. 15)

(eq. 16)

, and

RSS

(eq. 19)

DS(SF)

(eq. 20)

DS(SF)

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ADP3211, ADP3211A

about 120°C; therefore, the R be less than 13.3 mW at room temperature, or 18.8 mW at high temperature.

Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of the feedback to input must be small (less than 10% is recommended) to prevent accidentally turning on the synchronous MOSFETs when the switch node goes high.

The high−side (main) MOSFET must be able to handle two main power dissipation components: conduction losses and switching losses. Switching loss is related to the time for the main MOSFET to turn on and off and to the current and voltage that are being switched. Basing the switching speed on the rise and fall times of the gate driver impedance and MOSFET input capacitance, the following expression provides an approximate value for the switching loss per main MOSFET:

S(MF)

+ 2 fSW

where: nMF is the total number of main MOSFETs. RG is the total gate resistance. C

is the input capacitance of the main MOSFET.

ISS

The most effective way to reduce switching loss is to use lower gate capacitance devices.

The conduction loss of the main MOSFET is given by the following equation:

C(MF)

where R

+ D

DS(MF)

is the on resistance of the MOSFET.

)

Typically, a user wants the highest speed (low C device for a main MOSFET, but such a device usually has higher on resistance. Therefore, the user must select a device that meets the total power dissipation (about 0.8 W to 1.0 W for an 8−lead SOIC) when combining the switching and conduction losses.

For example, an NTMFS4821N device can be selected as the main MOSFET (one in total; that is, nMF = 1), with approximately C

= 1400 pF (maximum) and R

ISS

8.6 mW (maximum at TJ = 120°C), and an NTMFS4846N device can be selected as the synchronous MOSFET (two in total; that is, nSF = 2), with R at TJ = 120°C). Solving for the power dissipation per MOSFET at IO = 15 A and IR = 5.0 A yields 178 mW for each synchronous MOSFET and 446 mW for each main MOSFET. A third synchronous MOSFET is an option to further increase the conversion efficiency and reduce thermal stress.

Finally, consider the power dissipation in the driver. This is best described in terms of the QG for the MOSFETs and is given by the following equation:

per MOSFET should

DS(SF)

RG nMF C

DS(SF)

= 3.8 mW (maximum

ISS

(eq. 21)

DS(MF)

(eq. 22)

DS(MF)

ISS

DRV

(nMF Q

where Q

is the total gate charge for each main

GMF

MOSFET, and Q

) nSF Q

GMF

is the total gate charge for each

GSF

) ) I

synchronous MOSFET.

The previous equation also shows the standby dissipation

(ICC times the VCC) of the driver.

Current Limit Set−Point

To select the current limit set point, we need to find the resistor value for R ADP3211 is set when the current in R

. The current limit threshold for the

LIM

is equal to the

LIM

internal reference current of 20 mA. The current in R equal to the inductor current times RO. R

LIM

using the following equation:

LIM

20 mA

where: R

is the current limit resistor. R

LIM

the I

pin to the CSCOMP pin.

LIM

is connected from

LIM

RO is the output load line resistance. I

is the current limit set point. This is the peak inductor

LIM

current that will trip current limit.

In this example, if choosing 20 A for I

6.9 kW, which is close to a standard 1% resistance of

6.98 kW.

The per phase current limit described earlier has its limit determined by the following:

PHLIM

)

For the ADP3211, the maximum COMP voltage (V

COMP(MAX)

) is 3.3 V, the COMP pin bias voltage (V

AD R

* VR* V

DS(MAX)

BIAS

)

is 1.0 V, and the current balancing amplifier gain (AD) is 5. Using a VR of 0.55 V, and a R

DS(MAX)

of 3.8 mW (low−side

on−resistance at 150°C) results in a per phase limit of 85 A. Although this number seems high, this current level can only be reached with a absolute short at the output and the current limit latchoff function shutting down the regulator before overheating occurs.

This limit can be adjusted by changing the ramp voltage VR. However, users should not set the per phase limit lower than the average per phase current (I

LIM

/n).

There is also a per phase initial duty−cycle limit at maximum input voltage:

LIM

RC Snubber

+ D

MIN

COMP(MAX)

* V

BIAS

It is important in any buck topology to use a resistor−capacitor snubber across the low side power MOSFET. The RC snubber dampens ringing on the switch

VCC

(eq. 23)

LIM

can be found

(eq. 24)

, R

LIM

(eq. 25)

(eq. 26)

BIAS

)

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ADP3211, ADP3211A

node when the high side MOSFET turns on. The switch node ringing could cause EMI system failures and increased stress on the power components and controller. The RC snubber should be placed as close as possible to the low side MOSFET. Typical values for the resistor range from 1 W to 10 W. Typical values for the capacitor range from 330 pF to 4.7 nF. The exact value of the RC snubber depends on the PCB layout and MOSFET selection. Some fine tuning must be done to find the best values. The equation below is used to find the starting values for the RC snubber.

Ringing

Input

Snubber

OSS

Switching

(eq. 27)

(eq. 28)

(eq. 29)

Where R C

Snubber

Ringing

Snubber

is the snubber capacitor.

2 p f

p f

+ C

Snubber

is the snubber resistor.

Snubber

is the frequency of the ringing on the switch node when the high side MOSFET turns on. C

is the low side MOSFET output capacitance at V

OSS

Input

This is taken from the low side MOSFET data sheet. V

is the input voltage.

input

Switching

is the switching frequency.

is the power dissipated in R

Snubber

Current Monitor

The ADP3211 has an output current monitor. The I

MON

pin sources a current proportional to the total inductor current. A resistor, R

MON

, from I

to FBRTN sets the

MON

gain of the output current monitor. A 0.1 mF is placed in parallel with R high frequency load transients. Since the I

to filter the inductor current ripple and

MON

pin is connected directly to the CPU, it is clamped to prevent it from going above 1.15 V.

The I

gain of 10. R

pin current is equal to the R

MON

can be found using the following

MON

times a fixed

LIM

equation:

MON

1.15 V R

10 RO I

LIM

(eq. 30)

where: R

is the current monitor resistor. R

MON

from I R

LIM

pin to FBRTN.

MON

is the current limit resistor.

is connected

MON

RO is the output load line resistance. IFS is the output current when the voltage on I

MON

is at full

scale.

Feedback Loop Compensation Design

Optimized compensation of the ADP3211 allows the best possible response of the regulator’s output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible

frequency range, including dc, and that is equal to the droop resistance (RO). With the resistive output impedance, the output voltage droops in proportion with the load current at any load current slew rate, ensuring the optimal position and allowing the minimization of the output decoupling.

With the multi−mode feedback structure of the ADP3211, it is necessary to set the feedback compensation so that the converter’s output impedance works in parallel with the output decoupling. In addition, it is necessary to compensate for the several poles and zeros created by the output inductor and decoupling capacitors (output filter).

A Type III compensator on the voltage feedback is adequate for proper compensation of the output filter. Figure 35 shows the Type III amplifier used in the ADP3211. Figure 36 shows the locations of the two poles and two zeros created by this amplifier.

VOLTAGE ERROR

AMPLIFIER

COMP

REFERENCE

VOLTAGE

ADP3211

Figure 35. Voltage Error Amplifier

GAIN

–20dB/DEC

0dB

fZ2fZ1f

Figure 36. Poles and Zeros of Voltage Error Amplifier

–20dB/DEC

The following equations give the locations of the poles and zeros shown in Figure 36:

fZ1+

fZ2+

fP1+

fP2+

2p C

) CFB) R

2p(C

CA) C

2p RA CFB C

OUTPUT

VOLTAGE

FREQUENCY

(eq. 31)

(eq. 32)

(eq. 33)

(eq. 34)

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The expressions that follow compute the time constants for the poles and zeros in the system and are intended to yield an optimal starting point for the design; some adjustments may be necessary to account for PCB and component parasitic effects (see the Tuning Procedure for ADP3211 section):

RE+ RO) AD RDS)

2 L (1 * D) V

CX RO V

VID

TA+ CX (RO* RȀ) )

TB+ (RX) RȀ*RO) C

ǒL *

TC+

TD+

CX (RO* RȀ) ) CZ R

2 f

VID

CZ R

D RDS

DCR

VID

* RȀ

)

(eq. 35)

(eq. 36)

(eq. 37)

(eq. 38)

(eq. 39)

where: R’ is the PCB resistance from the bulk capacitors to the ceramics and is approximately 0.4 mW (assuming an 8−layer motherboard). RDS is the total low−side MOSFET for on resistance. AD is 5. VRT is 1.25 V. LX is the ESL of the bulk capacitors (450 pH for the two Panasonic SP capacitors).

The compensation values can be calculated as follows:

CA+

RA+

CFB+

CB+

RE R

T C

T R

(eq. 40)

(eq. 41)

(eq. 42)

(eq. 43)

The standard values for these components are subject to the tuning procedure described in the Tuning Procedure for ADP3211 section.

CIN Selection and Input Current DI/DT Reduction

In continuous inductor−current mode, the source current of the high−side MOSFET is approximately a square wave with a duty ratio equal to V

OUT/VIN

. To prevent large voltage transients, use a low ESR input capacitor sized for the maximum RMS current.

The maximum RMS capacitor current occurs at the lowest input voltage and is given by:

+ D IO

CRMS

+ 0.15 15 A

CRMS

* 1

* 1Ǹ+ 5.36 A

0.15

(eq. 44)

where IO is the output current.

In a typical notebook system, the battery rail decoupling is achieved by using MLC capacitors or a mixture of MLC capacitors and bulk capacitors. In this example, the input capacitor bank is formed by four pieces of 10 mF, 25 V MLC capacitors, with a ripple current rating of about 1.5 A each.

Tuning Procedure for ADP3211

Set Up and Test the Circuit

1. Build a circuit based on the compensation values computed from the design spreadsheet.

2. Connect a dc load to the circuit.

3. Turn on the ADP3211 and verify that it operates properly.

4. Check for jitter with no load and full load conditions.

Set the DC Load Line

1. Measure the output voltage with no load (VNL) and verify that this voltage is within the specified tolerance range.

2. Measure the output voltage with a full load when the device is cold (V

FLCOLD

). Allow the board to run for ~10 minutes with a full load and then measure the output when the device is hot (V

). If the difference between the two

FLHOT

measured voltages is more than a few millivolts, adjust R

CS2(NEW)

3. Repeat Step 2 until no adjustment of R

using Equation 45.

CS2

+ R

CS2(OLD)

* V

VNL* V

FLCOLD

FLHOT

CS2

(eq. 45)

needed.

4. Compare the output voltage with no load to that with a full load using 5 A steps. Compute the load line slope for each change and then find the average to determine the overall load line slope (R

5. If the difference between R

OMEAS

and RO is more

OMEAS

than 0.05 mW, use the following equation to adjust the RPH values:

PH(NEW)

+ R

PH(OLD)

6. Repeat Steps 4 and 5 until no adjustment of R

OMEAS

(eq. 46)

is needed. Once this is achieved, do not change RPH, R

CS1

, R

, or RTH for the rest of the

CS2

procedure.

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7. Measure the output ripple with no load and with a full load with scope, making sure both are within the specifications.

Set the AC Load Line

1. Remove the dc load from the circuit and connect a dynamic load.

2. Connect the scope to the output voltage and set it to dc coupling mode with a time scale of 100 ms/div.

3. Set the dynamic load for a transient step of about 40 A at 1 kHz with 50% duty cycle.

4. Measure the output waveform (note that use of a dc offset on the scope may be necessary to see the waveform). Try to use a vertical scale of 100 mV/div or finer.

5. The resulting waveform will be similar to that shown in Figure 37. Use the horizontal cursors to measure V

ACDRP

and V

DCDRP

, as shown in Figure 37. Do not measure the undershoot or overshoot that occurs immediately after the step.

9. Ensure that the load step slew rate and the

powerup slew rate are set to ~150 A/ms to 250 A/ms (for example, a load step of 10 A should take 50 ns to 100 ns) with no overshoot. Some dynamic loads have an excessive overshoot at powerup if a minimum current is incorrectly set (this is an issue if a VTT tool is in use).

Set the Initial Transient

1. With the dynamic load set at its maximum step

size, expand the scope time scale to 2 ms/div to 5 ms/div. This results in a waveform that may have two overshoots and one minor undershoot before achieving the final desired value after V

(see Figure 38).

DROOP

Figure 37. AC Load Line Waveform

6. If the difference between V

ACDRP

and V

DCDRP

more than a couple of millivolts, use Equation 47 to adjust CCS. It may be necessary to try several parallel values to obtain an adequate one because there are limited standard capacitor values available (it is a good idea to have locations for two capacitors in the layout for this reason).

CS(NEW)

+ C

CS(OLD)

ACDRP

DCDRP

(eq. 47)

7. Repeat Steps 5 and 6 until no adjustment of C is needed. Once this is achieved, do not change CCS for the rest of the procedure.

8. Set the dynamic load step to its maximum step size (but do not use a step size that is larger than needed) and verify that the output waveform is square, meaning V

ACDRP

and V

DCDRP

are equal.

TRAN1

Figure 38. Transient Setting Waveform, Load Step

TRAN2

2. If both overshoots are larger than desired, try the following adjustments in the order shown.

a. Increase the resistance of the ramp resistor

b. For V

) by 25%.

RAMP

, increase CB or increase the

TRAN1

switching frequency.

c. For V

, increase RA by 25% and decrease

TRAN2

CA by 25%. If these adjustments do not change the response, it is because the system is limited by the output decoupling. Check the output response and the switching nodes each time a change is made to ensure that the output decoupling is stable.

3. For load release (see Figure 39), if V

TRANREL

larger than the value specified by IMVP−6.5, a greater percentage of output capacitance is needed. Either increase the capacitance directly or decrease the inductor values. (If inductors are changed, however, it will be necessary to redesign the circuit using the information from the spreadsheet and to repeat all tuning guide procedures).

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TRANREL

DROOP

Figure 39. Transient Setting Waveform, Load Release

receives the power (for example, a microprocessor core). If the load is distributed, the capacitors should also be distributed and generally placed in greater proportion where the load is more dynamic.

7. Avoid crossing signal lines over the switching power path loop, as described in the Power Circuitry section.

8. Connect a 1 mF decoupling ceramic capacitor from VCC to AGND. Place this capacitor as close as possible to the controller. Connect a 4.7 mF decoupling ceramic capacitor from PVCC to PGND. Place this capacitor as close as possible to the controller.

Layout and Component Placement

The following guidelines are recommended for optimal

performance of a switching regulator in a PC system.

General Recommendations

1. For best results, use a PCB of four or more layers. This should provide the needed versatility for control circuitry interconnections with optimal placement; power planes for ground, input, and output; and wide interconnection traces in the rest of the power delivery current paths. Keep in mind that each square unit of 1 oz copper trace has a resistance of ~0.53 mW at room temperature.

2. When high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded.

3. If critical signal lines (including the output voltage sense lines of the ADP3211) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of increasing signal ground noise.

4. An analog ground plane should be used around and under the ADP3211 for referencing the components associated with the controller. This plane should be tied to the nearest ground of the output decoupling capacitor, but should not be tied to any other power circuitry to prevent power currents from flowing into the plane.

5. The components around the ADP3211 should be located close to the controller with short traces. The most important traces to keep short and away from other traces are those to the FB and CSFB pins. Refer to Figure 34 for more details on the layout for the CSFB node.

6. The output capacitors should be connected as close as possible to the load (or connector) that

Power Circuitry

1. The switching power path on the PCB should be routed to encompass the shortest possible length to minimize radiated switching noise energy (that is, EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system as well as noise−related operational problems in the power−converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. The use of short, wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss.

2. When a power−dissipating component (for example, a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are improved current rating through the vias and improved thermal performance from vias extended to the opposite side of the PCB, where a plane can more readily transfer heat to the surrounding air. To achieve optimal thermal dissipation, mirror the pad configurations used to heat sink the MOSFETs on the opposite side of the PCB. In addition, improvements in thermal performance can be obtained using the largest possible pad area.

3. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load.

4. For best EMI containment, a solid power ground plane should be used as one of the inner layers and extended under all power components.

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ADP3211, ADP3211A

Signal Circuitry

1. The output voltage is sensed and regulated between the FB and FBRTN pins, and the traces of these pins should be connected to the signal ground of the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be as small as possible. Therefore, the FB and FBRTN traces should be routed adjacent to each other, atop the power ground plane, and back to the controller.

ORDERING INFORMATION

Device Number* Temperature Range Package Package Option Shipping

ADP3211MNR2G −40°C to 100°C 32−Lead QFN IMVP−6.5 1.1 V

ADP3211AMNR2G −40°C to 100°C 32−Lead QFN 1.2 V Boot Voltage 5000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

*The “G’’ suffix indicates Pb−Free package.

2. The feedback traces from the switch nodes should be connected as close as possible to the inductor. The CSREF signal should be Kelvin connected to the center point of the copper bar, which is the V

common node for the inductor.

CCGFX

3. On the back of the ADP3211 package, there is a metal pad that can be used to heat sink the device. Therefore, running vias under the ADP3211 is not recommended because the metal pad may cause shorting between vias.

†

Boot Voltage

5000 / Tape & Reel

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2 X

32 X

2 X

PIN ONE

LOCATION

0.15 C

0.10 C

0.08 C

32 X

ADP3211, ADP3211A

PACKAGE DIMENSIONS

QFN32 5*5*1 0.5 P

CASE 488AM−01

ISSUE O

TOP VIEW

(A3)

SEATING

SIDE VIEW

PLANE

EXPOSED PAD

32 X

NOTES:

1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30 MM TERMINAL

4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

MILLIMETERS

DIM MIN NOM MAX

A 0.800 0.900 1.000 A1 0.000 0.025 0.050 A3 0.200 REF

b 0.180 0.250 0.300

D 5.00 BSC D2 2.950 3.100 3.250

E 5.00 BSC E2

2.950 3.100 3.250

e 0.500 BSC

K 0.200 −−− −−−

L 0.300 0.400 0.500

SOLDERING FOOTPRINT*

5.30

32 X

0.63

3.20

A0.10 BC

0.05 C

3.20

BOTTOM VIEW

32 X

0.28

28 X

0.50 PITCH

5.30

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

All brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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For additional information, please contact your loc Sales Representative

ADP3211/D

ON ADP3211, ADP3211A Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual