ON ADP3211, ADP3211A Schematics

ADP3211, ADP3211A

7-Bit, Programmable, Single-Phase, Synchronous Buck Controller

The ADP3211 is a highly efficient, single−phase, synchronous buck switching regulator controller. With its integrated driver, the ADP3211 is optimized for converting the notebook battery voltage to the supply voltage required by high performance Intel chipsets. An internal 7−bit DAC is used to read a VID code directly from the chip−set or the CPU and to set the GMCH render voltage or the CPU core voltage to a value within the range of 0 V to 1.5 V.

The ADP3211 uses a multi−mode architecture. It provides programmable switching frequency that can be optimized for efficiency depending on the output current requirement. In addition, the ADP3211 includes a programmable load line slope function to adjust the output voltage as a function of the load current so that the core voltage is always optimally positioned for a load transient. The ADP3211 also provides accurate and reliable current overload protection and a delayed power−good output. The IC supports On−The−Fly (OTF) output voltage changes requested by the chip−set.

The ADP3211 has a boot voltage of 1.1 V for IMVP−6.5 applications in CPU mode. The ADP3211A has a boot voltage of

1.2 V in CPU mode.

The ADP3211 is specified over the extended commercial temperature range of −40°C to 100°C and is available in a 32−lead QFN.

Features

• Single−Chip Solution

♦ Fully Compatible with the Intel

Chipset Voltage Regulator Specifications Integrated MOSFET Drivers

• Input Voltage Range of 3.3 V to 22 V

• ±7 mV Worst−Case Differentially Sensed Core Voltage Error

Overtemperature

• Automatic Power−Saving Modes Maximize Efficiency During

Light Load Operation

• Soft Transient Control Reduces Inrush Current and Audio Noise

• Independent Current Limit and Load Line Setting Inputs for

Additional Design Flexibility

• Built−in Power−Good Masking Supports Voltage Identification

(VID) OTF Transients

• 7−Bit, Digitally Programmable DAC with 0 V to 1.5 V Output

• Short−Circuit Protection

• Current Monitor Output Signal

• This is a Pb−Free Device

• Fully RoHS Compliant

• 32−Lead QFN

Applications

• Notebook Power Supplies for Next Generation Intel Chipsets

• Intel Netbook Atom Processors

IMVP−6.5t CPU and GMCH

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QFN32

MN SUFFIX

MARKING DIAGRAM

ADP3211(A)

AWLYYWWG

(A) = ADP3211A Device Only A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

PIN ASSIGNMENT

VID0

PWRGD

IMON

CLKEN

FBRTN

COMP

GPU

ILIM

See detailed ordering and shipping information in the package dimensions section on page 31 of this data sheet.

IREF

RPM

ORDERING INFORMATION

CASE 488AM

VID1

VID2

VID3

ADP3211

ADP3211A

(top view)

LLINE

RAMP

VID4

VID5

CSFB

CSREF

VID6

VCC

BST

DRVH

PVCC

DRVL

PGND

GND

CSCOMP

November, 2009 − Rev. 2

1 Publication Order Number:

ADP3211/D

ADP3211, ADP3211A

COMP

LLINE

PWRGD

CLKEN

FBRTN

UVLO Shutdown

PWRGD

Open Drain

CLKEN

Open Drain

Precision

Reference

REF

DAC + 200mV

CSREF

DAC − 300 mV

VCCGND

and Bias

CSREF

−

VID

DAC

VEA

−

1.55V

PWRGD

Startup

Delay

CLKEN

Start Up

Delay

OVP

−

RPM RT

Oscillator

Soft

Transient

Delay

Delay Disable

Current

Limit

Circuit

RAMP

PVCC

MOSFET

Driver

OCP

Shutdown

Delay

Current Monitor

Soft Start

and Soft

Transient

Control

BST

DRVH

DRVL

PGND

IMON

−

CSREF

CSFB

CSCOMP

ILIM

GPU

VID6

VID5

VID4

VID3

VID2

VID1

VID0

IREF

Figure 1. Functional Block Diagram

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DAC

REF

ADP3211, ADP3211A

ABSOLUTE MAXIMUM RATINGS

Parameter Rating Unit

FBRTN, PGND −0.3 to +0.3 V

BST, DRVH

DC t < 200 ns

BST to PV

BST to SW −0.3 to +6.0 V

DRVH to SW −0.3 to +6.0 V

DRVL to PGND

RAMP (in Shutdown)

All Other Inputs and Outputs −0.3 to +6.0 V

Storage Temperature Range −65 to +150 °C

Operating Ambient Temperature Range −40 to 100 °C

Operating Junction Temperature 125 °C

Thermal Impedance (qJA) 2−Layer Board 32.6 °C/W

Lead Temperature

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.

DC t < 200 ns

Soldering (10 sec) Infrared (15 sec)

−0.3 to +6.0 V

−0.3 to +28

−0.3 to +33

−0.3 to +22

−0.3 to +28

−1.0 to +22

−6.0 to +28

−0.3 to +6.0

−5.0 to +6.0

−0.3 to +22

−0.3 to +26

°C 300 260

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ADP3211, ADP3211A

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 PWRGD Power−Good Output. Open−drain output. A low logic state means that the output voltage is outside of the

2 IMON Current Monitor Output. This pin sources current proportional to the output load current. A resistor connected

3 CLKEN Clock Enable Output. Open drain output. The pull−high voltage on this pin cannot be higher than VCC.

4 FBRTN Feedback Return Input/Output. This pin remotely senses the GMCH voltage. It is also used as the ground

5 FB Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.

6 COMP Voltage Error Amplifier Output and Frequency Compensation Point.

7 GPU GMCH/CPU select pin. Connect to ground when powering the CPU. Connect to 5.0 V when powering the

8 ILIM Current Limit Set pin. Connect a resistor between ILIM and CSCOMP to the current limit threshold.

9 IREF This pin sets the internal bias currents. A 80 kW is connected from IREF to ground.

10 RPM RPM Mode Timing Control Input. A resistor is connected from RPM to ground sets the RPM mode turn−on

11 RT PWM Oscillator Frequency Setting Input. An external resistor from this pin to GND sets the PWM oscillator

12 RAMP PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this pin sets

13 LLINE Load Line Programming Input. The center point of a resistor divider connected between CSREF and

14 CSREF Current Sense Reference Input. This pin must be connected to the opposite side of the output inductor.

15 CSFB Non−inverting Input of the Current Sense Amplifier. The combination of a resistor from the switch node to this

16 CSCOMP Current Sense Amplifier Output and Frequency Compensation Point.

17 GND Analog and Digital Signal Ground.

18 PGND Low−Side Driver Power Ground. This pin should be connected close to the source of the lower MOSFET(s).

19 DRVL Low−Side Gate Drive Output.

20 PVCC Power Supply Input/Output of Low−Side Gate Driver.

21 SW Current Return For High−Side Gate Drive.

22 DRVH High−Side Gate Drive Output.

23 BST High−Side Bootstrap Supply. A capacitor from this pin to SW holds the bootstrapped voltage while the

24 VCC Power Supply Input/Output of the Controller.

25 to 31 VID6 to VID0 Voltage Identification DAC Inputs. A 7−bit word (the VID Code) programs the DAC output voltage, the

32 EN Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, and pulls PWRGD low.

VID DAC defined range.

to FBRTN sets the current monitor gain.

return for the VID DAC and the voltage error amplifier blocks.

GMCH. When GPU is connected to ground, the boot voltage is 1.1 V for the ADP3211 and 1.2 V for the ADP3211A. When GPU is connected to 5.0 V, there is no boot voltage.

threshold voltage.

frequency.

the slope of the internal PWM stabilizing ramp.

CSCOMP tied to this pin sets the load line slope.

pin and the feedback network from this pin to the CSCOMP pin sets the gain of the current sense amplifier.

high−side MOSFET is on.

reference voltage of the voltage error amplifier without a load (see the VID Code Table, Table NO TAG). In normal operation mode, the VID DAC output programs the output voltage to a value within the 0 V to 1.5 V range. The input is actively pulled down.

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ADP3211, ADP3211A

ELECTRICAL CHARACTERISTICS (V

= PVCC = 5.0 V, FBRTN = GND = PGND = 0 V, H = 5.0 V, L = 0 V, V

VID

= V

TA = −40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sunk by the device) has a positive sign.

Parameter Symbol Conditions Min Typ Max Units

VOLTAGE CONTROL − Voltage Error Amplifier (VEAMP)

FB, LLINE Voltage Range (Note 2)

FB, LLINE Offset Voltage (Note 2)

FB Bias Current I

LLINE Bias Current I

LLINE Positioning Accuracy VFB − V

COMP Voltage Range V

COMP Current I

COMP Slew Rate SR

Gain Bandwidth (Note 2) GBW Non−inverting unit gain configuration,

VFB, V

OSVEA

COMP

LLINE

COMP

DAC

Relative to CSREF = V

DAC

−200 +200 mV

−0.5 +0.5 mV

−1.0 +1.0 mA

−50 +50 nA

Measured on FB relative to nominal V LLINE forced 80 mV below CSREF

−10°C to 100°C

−40°C to 100°C

DAC

−78

−77

−80

Voltage range of interest 0.85 4.0 V

COMP = 2.0 V, CSREF = V FB forced 200 mV below CSREF FB forced 200 mV above CSREF

= 10 pF, CSREF = V

COMP

Open loop configuration FB forced 200 mV below CSREF FB forced 200 mV above CSREF

DAC

−650

2.0

−10

20 MHz

RFB = 1 kW

VID DAC VOLTAGE REFERENCE

Voltage Range (Note 2) See VID Code Table 0 1.5 V

DAC

Accuracy VFB − V

DAC

Differential Non−linearity (Note 2) −1.0 +1.0 LSB

DAC

Line Regulation ΔV

DAC

Boot Voltage V

DAC

Soft−Start Delay (Note 2) t

Soft−Start Time t

Boot Delay t

Slew Rate Soft−Start

DAC

FBRTN Current I

DAC

BOOTFB

DSS

BOOT

FBRTN

Measured on FB (includes offset), relative to nominal V V V V

DAC

= 0.3000 V to 1.2000 V, −10°C to 100°C

DAC

= 0.3000 V to 1.2000 V, −40°C to 100°C

DAC

= 1.2125 V to 1.5000 V, −40°C to 100°C

DAC

−7.0

−9.0

VCC = 4.75 V to 5.25 V 0.05 %

Measured during boot delay period, GPU = 0 V ADP3211 ADP3211A

1.100

1.200

Measured from EN pos edge to FB = 50 mV 200 ms

Measured from EN pos edge to FB settles to V

= 1.1 V within −5%

boot

Measured from FB settling to Vboot = 1.1 V

1.4 ms

100 ms

within −5% to CLKEN neg edge

0.0625

Arbitrary VID step

1.0

70 200 mA

VOLTAGE MONITORING and PROTECTION − Power Good

CSREF Undervoltage Threshold

CSREF Overvoltage Threshold

CSREF Crowbar Voltage Threshold

CSREF Reverse Voltage Threshold

UVCSREF

DAC

OVCSREF

DAC

CBCSREF

RVCSREF

−

Relative to nominal V

−

Relative to nominal V

Voltage −360 −300 −240 mV

DAC

Voltage 150 200 250 mV

DAC

Relative to FBRTN 1.5 1.55 1.6 V

Relative to FBRTN, Latchoff Mode CSREF is falling CSREF is rising

−350 −300

−75 −5.0

DAC

−82

−83

+7.0 +9.0 +9.0

= 1.2 V,

V/ms

LSB/ms

1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2. Guaranteed by design or bench characterization, not production tested.

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ADP3211, ADP3211A

ELECTRICAL CHARACTERISTICS (V

= PVCC = 5.0 V, FBRTN = GND = PGND = 0 V, H = 5.0 V, L = 0 V, V

VID

= V

DAC

= 1.2 V,

TA = −40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sunk by the device) has a positive sign.

Parameter UnitsMaxTypMinConditionsSymbol

VOLTAGE MONITORING and PROTECTION − Power Good

PWRGD Low Voltage V

PWRGD High Leakage Current

PWRGD Startup Delay T

PWRGD Latchoff Delay T

PWRGD Propagation Delay

(Note 2)

Crowbar Latchoff Delay (Note 2)

PWRGD Masking Time T

PWRGD

SSPWRGD

LOFFPWRGD

PDPWRGD

LOFFCB

MSkPWRGD

PWRGD(SINK)

PWRDG

Measured from CLKEN neg edge to PWRGD

= 4 mA 75 200 mV

= 5.0 V 1.0 mA

8.0 ms

pos edge

Measured from Out−off−Good−Window event

8.0 ms

to Latchoff (switching stops)

Measured from Out−off−Good−Window event

200 ns

to PWRGD neg edge

Measured from Crowbar event to Latchoff

200 ns

(switching stops)

Triggered by any VID change 100 ms

CSREF Soft−Stop Resistance EN = L or Latchoff condition 60 W

CURRENT CONTROL − Current Sense Amplifier (CSAMP)

CSFB, CSREF Common−Mode Range

Voltage range of interest 0 2.0 V

(Note 2)

CSFB, CSREF Offset Voltage V

CSFB Bias Current I

CSREF Bias Current I

CSCOMP Voltage Range

OSCSA

BCSFB

BCSREF

CSREF – CSSUM, TA = −40°C to 85°C TA = 25°C

−1.5

−0.4

+1.5 +0.4

−50 +50 nA

−2.0 2.0 mA

Voltage range of interest 0.05 2.0 V

(Note 2)

CSCOMP Current

CSCOMPsource

CSCOMPsink

CSCOMP Slew Rate (Note 2) C

Gain Bandwidth (Note 2) GBW

CSA

CSCOMP = 2.0 V CSFB forced 200 mV below CSREF CSFB forced 200 mV above CSREF

= 10 pF, CSREF = V

CSCOMP

Open loop configuration

DAC

CSFB forced 200 mV below CSREF CSFB forced 200 mV above CSREF

Non−inverting unit gain configuration RFB = 1 kW

−650

1.0

−10

20 MHz

CURRENT MONITORING AND PROTECTION − Current Reference

Voltage V

REF

= 80 kW to set I

REF

= 20 mA 1.55 1.6 1.65 V

REF

CURRENT LIMITER (OCP)

Current Limit (OCP) Threshold

Current Limit Latchoff Delay Measured from OCP event to PWRGD

LIMTH

Measured from CSCOMP to CSREF R

= 4.5 kW

LIM

−11 5 −90 −70 mV

8.0 ms

de−assertion

CURRENT MONITOR

Current Gain Accuracy I

Clamp Voltage V

MON

MON/ILIM

MAXMON

Measured from I I

= −20 mA

LIM

= −10 mA

LIM

= −5 mA

LIM

Relative to FBRTN, I R

= 8 kW

IMON

to I

LIM

MON

= −30 mA

9.5

9.4

9.0

10 10 10

10.6

10.8 11

1.0 1.15 V

1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2. Guaranteed by design or bench characterization, not production tested.

V/ms

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ADP3211, ADP3211A

ELECTRICAL CHARACTERISTICS (V

= PVCC = 5.0 V, FBRTN = GND = PGND = 0 V, H = 5.0 V, L = 0 V, V

VID

= V

DAC

= 1.2 V,

TA = −40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sunk by the device) has a positive sign.

Parameter UnitsMaxTypMinConditionsSymbol

PULSE WIDTH MODULATOR − Clock Oscillator

RT Voltage V

PWM Clock Frequency Range (Note 2)

CLK

RT = 243 kW, V See also VRT(V

VID

= 1.2 V

) formula

1.08 1.2 1.35 V

Operation of interest 0.3 3.0 MHz

RAMP GENERATOR

RAMP Voltage V

RAMP Current Range (Note 2) I

RAMP

EN = H, I EN = L

RAMP

= 60 mA

EN = H EN = L, RAMP = 19 V

0.9 1.0

1.0

−0.5

100

+0.5

1.1 V

PWM COMPARATOR

PWM Comparator Offset (Note 2)

OSRPM

−3.0 +3.0 mV

RPM COMPARATOR

RPM Current I

RPM Comparator Offset

(Note 2)

RPM

OSRPM

= 1.2 V, RT = 243 kW

VID

See also I

COMP

RPM(RT

− (1 + V

) formula

−6.0 mA

) −3.0 +3.0 mV

RPM

SWITCH AMPLIFIER

SW Input Resistance R

Measured from SW to PGND 1.3 kW

ZERO CURRENT SWITCHING COMPARATOR

SW ZCS Threshold V

Masked Off−Time t

ZCSSW

OFFMSKD

DCM mode, DPRSLP = 3.3 V −4.0 mV

Measured from DRVH neg edge to DRVH

700 ns

pos edge at max frequency of operation

SYSTEM I/O BUFFERS − EN and VID[6:0] INPUTS

Input Voltage V

Input Current I

EN,VID[6:0]

Refers to driving signal level Logic low, I Logic high, I

EN,VID[6:0]

0.2 V < V

= 1 mA

sink

= −5 mA 0.7

source

= 0 V

EN,VID[6:0]

≤ V

0.3

1.0

VID Delay Time (Note 2) Any VID edge to 10% of FB change 200 ns

GPU INPUT

Input Voltage V

Input Current I

GPU

Refers to driving signal level Logic low, I Logic high, I

= 1 mA

sink

= −5 mA 4.0

source

GPU = L or GPU = H (static)

0.8 V < EN < 1.6 V (during transition)

0.3

10 70

CLKEN OUTPUT

Output Low Voltage V

Output High, Leakage Current I

CLKEN

Logic low, I

Logic high, V

= 4 mA 30 300 mV

CLKEN

= V

CLKEN

3.0 mA

SUPPLY

Supply Voltage Range V

Supply Current EN = H

EN = L

VCC OK Threshold V

VCC UVLO Threshold V

CCOK

CCUVLO

VCC is rising 4.4 4.5 V

VCC is falling 4.0 4.15 V

4.5 5.5 V

6.0 60

200

VCC Hysteresis (Note 2) 150 mV

1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2. Guaranteed by design or bench characterization, not production tested.

nA mA

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ADP3211, ADP3211A

ELECTRICAL CHARACTERISTICS (V

= PVCC = 5.0 V, FBRTN = GND = PGND = 0 V, H = 5.0 V, L = 0 V, V

VID

= V

DAC

= 1.2 V,

TA = −40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sunk by the device) has a positive sign.

Parameter UnitsMaxTypMinConditionsSymbol

HIGH−SIDE MOSFET DRIVER

Pullup Resistance, Sourcing Current Pulldown Resistance, Sinking Current

Transition Times tr

Dead Delay Times tpdh

DRVH,

DRVH

BST Quiescent Current EN = L (Shutdown)

BST = PV

BST = PVCC, CL = 3 nF, Figure 2 15

2.0

1.0

3.3

2.8

35 31

BST = PVCC, Figure 2 10 45 ns

EN = H, No Switching

5.0

200

15 mA

LOW−SIDE MOSFET DRIVER

Pullup Resistance, Sourcing Current Pulldown Resistance, Sinking Current

Transition Times tr

Propagation Delay Times tpdh

SW Transition Timeout t

SW Off Threshold V

DRVL,

DRVL

SWTO

OFFSW

CL = 3 nF, Figure 2 15

CL = 3 nF, Figure 2 15 30 ns

DRVH = L, SW = 2.5 V 150 250 450 ns

PVCC Quiescent Current EN = L (Shutdown)

EN = H, No Switching

1.8

0.9

3.0

2.7

2.2 V

50 mA

200

BOOTSTRAP RECTIFIER SWITCH

On−Resistance EN = L or EN = H and DRVL = H 4 7 11 W

1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2. Guaranteed by design or bench characterization, not production tested.

3. Timing is referenced to the 90% and 10% points, unless otherwise noted.

DRVL

DRVH

(with respect to SW)

tpdh

DRVL

DRVH

Figure 2. Timing Diagram

DRVH

1.0 V

tpdh

DRVL

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ADP3211, ADP3211A

TYPICAL PERFORMANCE CHARACTERISTICS

= 1.5 V, TA = 20°C to 100°C, unless otherwise noted.

VID

1: 200mV/div 2: 2V/div

Switch

Node

: 10V/div

Input = 12V, 1A Load VID Step 0.7V to 1.2V

Figure 3. VID Change Soft Transient

300

250

200

150

100

SWITCHING FREQUENCY (kHz)

SWITCHING

FREQUENCY

OUTPUT RIPPLE

LOAD CURRENT (A) LOAD CURRENT (A)

Output Voltage

VID5

20 ms/div

151050

1.2

1.0

OUTPUT RIPPLE (mV)

0.8

(V)

0.6

MON

0.4

0.2

Output Voltage

VID5

Switch Node

1: 200mV/div 2: 2V/div

3: 10V/div

Input = 12V, 1A Load VID Step 1.2V to 0.7V

20 ms/div

Figure 4. VID Change Soft Transient

2520151050

1.35

1.30

1.25

VID VOLTAGE (V)

1.20

1.15

Figure 5. Switching Frequency vs. Load

Current in RPM Mode

Measured Load Line

Specified Load Line

LOAD CURRENT (A) VCC VOLTAGE (V)

Figure 7. Load Line Accuracy Figure 8. VCC Current vs. VCC Voltage with

+2%

−2%

151050

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Figure 6. I

CURRENT (mA)

Voltage vs. Load Current

MON

6543210

Enable Low

ADP3211, ADP3211A

TYPICAL PERFORMANCE CHARACTERISTICS

Output Voltage

1: 0.5V/div 2: 5V/div

3: 5V/div 4: 5V/div

2ms/div

GPU = 0V

Figure 9. Startup Waveforms CPU Mode

Output Voltage

Switch Node

PWRGD

CLKEN

Inductor

Current

Output Voltage

1: 0.5V/div 2: 5V/div

3: 5V/div 4: 5V/div

4ms/div

PWRGD

CLKEN

GPU = 5V

Figure 10. Startup Waveforms GPU Mode

Output Voltage

Switch Node

Inductor

Current

3 4

1 : 100mV/div 2 : 10V/div

Low Side Gate Drive

3: 5A/div 4 : 5V/div

4 ms/div

Figure 11. DCM Waveforms, 1 A Load Current

Output Voltage

Switch Node

1: 50mV/div 2: 10V/div

40 ms/div

Input = 12V Output = 1.2V 3A to 15A Step

Figure 13. Load Transient Figure 14. Load Transient

1 : 100mV/div 2 : 10V/div

3 : 5A/div 4 : 5V/div

Low Side Gate Drive

2 ms/div

Figure 12. CCM Waveforms, 10 A Load Current

Output Voltage

Switch Node

1: 50mV/div 2: 10V/div

40 ms/div

Input = 12V Output = 1.2V 3A to 15A Step

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