ON ADP3208JCPZ Schematics

7-Bit, Programmable, Dual-Phase, Mobile,

VRPMRPM

FEATURES

Single-chip solution

Fully compatible with the Intel® IMVP-6+™ specifications
Integrated MOSFET drivers

Selectable 1- or 2-phase operation with up to 1 MHz per

phase switching frequency

Guaranteed ±8 mV worst-case differentially sensed core

voltage error over temperature

Automatic power-saving mode maximizes efficiency with

light load during deeper sleep operation
Soft transient control reduces inrush current and audio noise
Active current balancing between output phases
Independent current limit and load line setting inputs for

additional design flexibility
Built-in power-good blanking supports

voltage identification (VID) on-the-fly transients
7-bit, digitally programmable DAC with 0.3 V to 1.5 V output
Short-circuit protection with programmable latch-off delay
Clock enable output delays the CPU clock until the core

voltage is stable
Output power or current monitor options
48-lead LFCSP

APPLICATIONS

Notebook power supplies for next-generation Intel processors

CPU, Synchronous Buck Controller

ADP3208

GENERAL DESCRIPTION

The ADP3208 is a highly efficient, multiphase, synchronous
buck switching regulator controller. With its integrated drivers,
the ADP3208 is optimized for converting the notebook battery
voltage into the core supply voltage required by high performance
Intel processors. An internal 7-bit DAC is used to read a VID code
directly from the processor and to set the CPU core voltage to a
value within the range of 0.3 V to 1.5 V. The phase relationship
of the output signals ensures interleaved 2-phase operation.

The ADP3208 uses a multimode architecture run at a program­mable switching frequency and optimized for efficiency depending
on the output current requirement. The ADP3208 switches
between single- and dual-phase operation to maximize efficiency
with all load conditions. The chip includes a programmable load
line slope function to adjust the output voltage as a function of the
load current so that the core voltage is always optimally positioned
for a load transient. The ADP3208 also provides accurate and
reliable short-circuit protection, adjustable current limiting, and
a delayed power-good output. The IC supports on-the-fly output
voltage changes requested by the CPU.

The ADP3208 is specified over the extended commercial tempera­ture range of 0°C to 100°C and is available in a 48-lead LFCSP.

SP

PSI

VID6, VID5,

VID4, VID3,
VID2, VID1,

VID0

ST

VARFREQ

DPRSTP
DPRSLP

SS

PWRGD

PGDELAY

CLKEN

EN

VCC

GND

FUNCTIONAL BLOCK DIAGRAM

RAMP

RAMP

GENER-

ATOR

VREF

REFER-

VDAC

VID

DAC

FBRTN

PSI

UVLO REF

VDAC

HOUSE-

KEEPING

REFTH

ENCE

SELECT

SPSEL

VREF

ADP3208

RT

OSCILLATOR

PWM

CMPS

SWITCH

CLREF
CLTHSEL

PWM
LATCH
PHASE

CONTROL

AMPS

OVTH
UVTH

BIAS

BIAS

PMON

PWM

PMON PMONFS

Figure 1.

ERR AMP

CSAMP

CLIM
CMP

–

+

CSAVG

DRV2

IN

OD2

DRV1

IN

OD1B
OD1A

–

+

BST2
DRVH2
SW2

PVCC2
DRVL2

PGND2
BST1

DRVH1
SW1

PVCC1
DRVL1

VCC

PGND1

COMP
FB

LLINE
CSCOMP
CSSUM
CSREF

CLIM

VRTT
TTSNS

FBRTN

06374-001

+

+

–

–

–
+

SS

+
–

–
+

–+
–

+

+

–

©2007 SCILLC. All rights reserved. Publication Order Number:
December 2007 – Rev. 1 ADP3208/D

ADP3208

TABLE OF CONTENTS

Features...............................................................................................1

Applications .......................................................................................1

General Description..........................................................................1

Functional Block Diagram...............................................................1

Revision History................................................................................2

Specifications ..................................................................................... 3

Timing Diagram................................................................................ 7

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions .............................9

Test Circuits .....................................................................................11

Typical Performance Characteristics............................................12

Theory of Operation.......................................................................15

Number of Phases.......................................................................15

Operation Modes ........................................................................15

Differential Sensing of Output Voltage ....................................18

Output Current Sensing.............................................................18

Active Impedance Control Mode .............................................18

Current Control Mode and Thermal Balance.........................19

Voltage Control Mode................................................................19

Power-Good Monitoring ...........................................................19

Power-Up Sequence and Soft Start...........................................19

Soft Transient...............................................................................20

Current Limit, Short-Circuit, and Latch-Off Protection.......21

Changing VID on the Fly...........................................................21

Output Crowbar..........................................................................23

REVISION HISTORY

Reverse Voltage Protection........................................................23

Output Enable and UVLO.........................................................23

Thermal Throttling Control......................................................23

Power Monitor Function ...........................................................24

Application Information ................................................................ 27

Setting the Clock Frequency for PWM....................................27

Setting the Switching Frequency for

RPM Operation of Phase 1 ........................................................27

Soft Start and Current Limit Latch-Off Delay Times ............ 27

PWRGD Delay Timer ................................................................ 28

Inductor Selection.......................................................................28

C

Selection..............................................................................30

OUT

Power MOSFETs.........................................................................31

Ramp Resistor Selection ............................................................32

COMP Pin Ramp........................................................................32

Current Limit Setpoint...............................................................32

Power Monitor ............................................................................33

Feedback Loop Compensation Design .................................... 33

CIN Selection and Input Current di/dt Reduction ..................34

Soft Transient Setting .................................................................34

Selecting Thermal Monitor Components................................34

Tuning Procedure for ADP3208 ...............................................35

Layout and Component Placement.......................................... 36

Outline Dimension ......................................................................... 38

Ordering Guide...........................................................................38

12/07- Rev 1: Conversion to ON Semiconductor

9/07—Rev. Sp0 to Rev. SpA

Changes to Absolute Maximum Ratings........................................8

Change to Table 3..............................................................................9

Change to Power Monitor Function Section...............................24

Changes to Ordering Guide...........................................................38

10/06—Revision Sp0: Initial Version

Rev. 1 | Page 2 of 38 | www.onsemi.com

ADP3208

SPECIFICATIONS

VCC = PVCC1 = PVCC2 = BST1 = BST2 = high = 5 V, FBRTN = GND = SW1 = SW2 = PGND1 = PGND2 = low = 0 V, EN = VARFREQ =
high, DPRSLP = 0 V,

PSI

= 1.05 V,

(sunk by the device) has a positive sign.

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

VOLTAGE ERROR AMPLIFIER

Output Voltage Range V
DC Accuracy VFB Relative to nominal V

V
V
Boot Voltage V
LLINE Positioning Accuracy
LLINE − CSREF = −200 mV 180 200 220 mV
LLINE Input Bias Current I
Differential Nonlinearity

2

Line Regulation
Input Bias Current IFB −1 +1 μA
FBRTN Current I
Output Current I
FB forced to V
Gain Bandwidth Product2 GBW COMP = FB 20 MHz
Slew Rate

2

VID DAC INPUTS

Input Low Voltage VIL VID(x) 0.52 0.3 V
Input High Voltage VIH VID(x) 0.7 0.52 V
Input Current I
VID Transition Delay Time2 VID code change to FB change 400 ns

PWM OSCILLATOR

Frequency Range2

Frequency f

T

RT Voltage VRT RT = 250 kΩ to GND, V

VRPM Reference Voltage V
I
RPM Output Current I
RPM Comparator Offset V

RAMP Input Voltage V
RAMP Input Current Range I
RAMP Input Current in Shutdown EN = low or UVLO, RAMP = 19 V 1 μA

CURRENT SENSE AMPLIFIER

Offset Voltage V
Input Bias Current I
Input Common-Mode Range
Output Voltage Range V
Output Current I

2

DPRSTP

= 0 V, V

0.8 3.6 V

COMP

= 1.2000 V, TA = 0°C to 100°C, unless otherwise noted.1 Current entering a pin

VID

VID

,

LLINE = CSREF

= 0.5000 V to 1.5000 V −8 +8 mV

VID

= 0.3000 V to 0.4875 V −10 +10 mV

VID

BOOT(FB)

ΔV

FB

−80 +80 nA

LLINE

Startup 1.192 1.200 1.208 V
LLINE − CSREF = −80 mV 78 80 82 mV

−1 +1 LSB

ΔV

FB

60 400 μA

FBRTN

COMP

C

Sink current 1 μA

IN(VID)

T

OSC

VCC = 4.75 V to 5.25 V 0.005 %

FB forced to V

= 10 pF 25 V/μs

COMP

=

PSI

DPRSTP

= 25°C, RT = 250 kΩ, PWM mode,

A

VARFREQ = high, V

= 25°C, RT = 125 kΩ, PWM mode,

A

VARFREQ = high, V

− 3% −4 mA

VID

+ 3% 900 μA

VID

= 1.05 V, DPRSLP = 0 V 0.3 3 MHz

400 kHz

= 1.5000 V

VID

750 kHz

= 1.5000 V

VID

= 1.5000 V,

VID

1.08 1.25 1.32 V

VARFREQ = low
I

VRPM

V

RPM

|V

OS(RPM)

0.9 1.0 1.1 V

RAMP

EN = high 1 50 μA

RAMP

CSSUM − CSREF −2.0 +2.0 mV

OS(CSA)

−65 +65 nA

CSSUM

= 0 μA 0.95 1 1.05 V

VRPM

= 120 μA 0.95 1 1.16 V

VRPM

= 1.5000 V, RT = 250 kΩ −5 μA

VID

− V

|,

= 0 V −20 −1 +15 mV

RPM

PSI

COMP

CSSUM and CSREF 0 3.5 V

0.05 2.7 V

CSCOMP

Sink current 1 mA

CSCOMP

Rev. 1 | Page 3 of 38 | www.onsemi.com

ADP3208

Parameter Symbol Conditions Min Typ Max Unit

Source current −15 mA

Gain Bandwidth Product

Slew Rate

2

2

GBW

10 MHz

CSA

C

= 10 pF 10 V/μs

CSCOMP

CURRENT BALANCE AMPLIFIER

Common-Mode Voltage Range2 V

Input Resistance R

Input Current I

Input Current Matching

Zero Current Switching Threshold

SW(x)

SW(x)

SW(x)

ΔI

SW(x)

V

ZCS(SW1)

−600 +200 mV
30 50 60 kΩ
SW(x) = 0 V −3.5 μA
SW(x) = 0 V −5 +5 %
DPRSLP = 3.3 V, DCM −6 mV

Voltage

DCM Minimum Off Time Masking

t

OFFMASK

DPRSLP = 3.3 V, SW1 falling 450 ns

CURRENT LIMIT COMPARATOR

Output Current I

Current Limit Threshold Voltage V

CLIM

V

CLTH

V

V

R

= 125 kΩ 10 μA

CLIM

− V

CSREF

SP = low (2-phase),

− V

CSREF

(2-phase),

− V

CSREF

, R

CSCOMP

CSCOMP

PSI

CSCOMP

= 125 kΩ,

CLIM

= 1.05 V

PSI

, R

= 125 kΩ, SP = low

CLIM

= 0 V or DPRSLP = low

, R

= 125 kΩ,

CLIM

111 125 139 mV

54 62.5 74 mV

111 125 139 mV

SP = high (1-phase)

Current Limit Setting Ratio VCL/V

V

ILIM

CL/VILIM

,

= 1.05 V 0.1

PSI

,

= low, SP = low 0.05

PSI

SOFT START/LATCH-OFF TIMER

Output Current ISS V

V

V

Termination Threshold Voltage V

TH(SS)

Normal Mode Operating Voltage

Current Limit Latch-Off Voltage V

Current limit or PWRGD failure, SS falling 1.55 1.65 1.8 V

LOFF(SS)

< 1.7 V, startup −10 −8 −6 μA

SS

> 1.7 V, normal mode −48 μA

SS

> 1.7 V, current limit −2.5 −2 −1.5 μA

SS

Startup, SS rising 1.6 1.7 1.8 V

= low 2.9 V

CLKEN

SOFT TRANSIENT CONTROL

ST Sourcing Current I

Slow exit from deeper sleep mode,

ST Sinking Current I

ST Offset Voltage V

Fast exit from deeper sleep mode,

SOURCE(ST)

DPRSLP = 0 V, ST = V

DPRSLP = 3.3 V,
ST = V

DAC

Slow entry to deeper sleep,

SINK(ST)

DPRSTP

− 0.3 V

DPRSLP = 3.3 V, ST = V

|ST − V

OS(ST)

| at the end of PWRGD

VID

− 0.3 V

DAC

DAC

−9 μA

−2.5 μA

= 0,

2.5 μA

+ 0.3 V

−25 +25 mV

masking
Minimum Capacitance2 C
Extended PWRGD Masking

ST

V

|ST − V

TH(ST)

100 pF

|, DPRSLP = 3.3 V, ST falling 170 mV

VID

Comparator Voltage Thre shold

DIGITAL CONTROL INPUTS

Input Low Voltage VIL

PSI, DPRSTP

0.3 V

VARFREQ, SP 0.7 V
DPRSLP, EN 1.0 V
Input High Voltage VIH

PSI, DPRSTP

0.7 V

VARFREQ, SP 4 V
DPRSLP, EN 2.3 V
Input Current IIN

, VARFREQ, DPRSLP, SP

DPRSTP

20 nA

EN = low or EN = high 20 nA
EN = V

Rev. 1 | Page 4 of 38 | www.onsemi.com

, high-to-low or low-to-high 60 μA

TH(EN)

ADP3208

Parameter Symbol Conditions Min Typ Max Unit

transition

THERMAL THROTTLING/CROWBAR

= high,

DPRSTP

= low −100 nA

PSI

= high 1 μA

PSI

DISABLE CONTROL
TTSNS Voltage Range2 Temperature sensing 0.4 5 V
Crowbar disable threshold disable 0 50 mV
TTSNS VRTT Threshold Voltage V

VCC = 5 V, TTSNS falling 2.45 2.5 2.55 V

VRTT(TTSNS)

TTSNS VRTT Threshold Hysteresis 50 95 mV
TTSNS Crowbar Disable Threshold

V

CBDIS(TTSNS)

50 mV

Voltage
TTSNS Input Current TTSNS > 1.0 V, temperature sensing −1 +1 μA
TTSNS = 0 V, disabling overvoltage

−3 μA

protection
VRTT Output Low Voltage V
VRTT Output High Voltage V

OL(VRTT)

OH(VRTT)

I

SINK(VRTT)

I

SOURCE(VRTT)

= 400 μA 50 100 mV

= −400 μA 4 5 V

POWER GOOD

CSREF Undervoltage Threshold V
Relative to V
CSREF Overvoltage Threshold V
CSREF Crowbar (Overvoltage

Relative to V

UV(CSREF)

Relative to V

OV(CSREF)

V

Relative to FBRTN 1.65 1.7 1.75 V

CB(CSREF)

= 0.5 V to 1.5 V −300 mV

VID

= 0.3125 V to 0.4875 V −160 mV

VID

= 0.5 V to 1.5 V 150 200 250 mV

VID

Protection) Threshold

CSREF Reverse Voltage Detection

V

RVP(CSREF)

Relative to FBRTN

Threshold
CSREF falling −400 −300 mV
CSREF rising −60 −5 mV
PWRGD Output Low Voltage V
PWRGD Output Leakage Current V

OL(PWRGD)

I

SINK(PWRGD)

PWRDG

= 4 mA 70 200 mV

= 5 V 0.03 3 μA

Power-Good Delay Timer

PGDELAY Voltage Detection

V

TH(PGDELAY)

2.9 V

Threshold
PGDELAY Charge Current I
PGDELAY Discharge Resistance R

V

PGDELAY

V

PGDELAY

= 2.0 V −3 μA

PGDELAY

= 0.2 V 600 Ω

PGDELAY

PWRGD Masking Time 130 μs

CLOCK ENABLE

Output Low Voltage I
Output Leakage Current

= 4 mA 100 400 mV

SINK

= 5 V, VSS = GND 1 μA

CLKEN

POWER MONITOR

PMON Output Resistance I

= 2 mA 16 Ω

SINK

PMON Leakage Current PMON = 5 V 1 μA
PMON Oscillator Frequency PMONFS = 2 V 320 kHz
PMONFS Voltage Range2 1.5 4 V
PMONFS Output Current PMONFS = 2.5 V −10 μA

HIGH-SIDE MOSFET DRIVERS

DRVH Output Resistance, Sourcing

BST − SW = 4.6 V 1.9 3.3 Ω

Current

DRVH Output Resistance, Sinking

BST − SW = 4.6 V 1.5 3 Ω

Current
Transition Times t r
tf

DRVH,

DRVH

Propagation Delay Time tpdh

BST − SW = 4.6 V, CL = 3 nF, see Figure 2 8 25 ns

DRVH

BST − SW = 4.6 V, CL = 3 nF, see Figure 2 10 30 ns

BST − SW = 4.6 V, see Figure 2 16 70 ns

Rev. 1 | Page 5 of 38 | www.onsemi.com

ADP3208

Parameter Symbol Conditions Min Typ Max Unit

BST Quiescent Current EN = low, shutdown 5 μA
EN = high, no switching 120 μA

LOW-SIDE MOSFET DRIVERS

Output Resistance, Sourcing

1.8 3.3 Ω

Current
Output Resistance, Sinking Current
Transition Times t r
tf

DRVL

DRVL

Propagation Delay Time tpdl
SW Transition Timeout t
Zero Voltage Switching Detection

TO(SW )

V

ZVS(SW)

C

DRVL

1.4 2.5 Ω
CL = 3 nF, see Figure 2 11 30 ns

= 3 nF, see Figure 2 9 25 ns

L

CL = 3 nF, see Figure 2 13 30 ns
BST − SW = 4.6 V 80 130 300 ns

2.2 V

Threshold
PVCC Quiescent Current EN = low, shutdown 13 μA
EN = high, no switching 180 μA

SUPPLY

Supply Voltage Range2 V

CC

4.5 5.5 V
Supply Current EN = high, normal mode 5.5 10 mA
EN = low, shutdown 32 150 μA
VCC OK Threshold Voltage V
VCC UVLO Threshold Voltage V

CCOK

CCUVLO

VCC rising 4.4 4.5 V

VCC falling 4.0 4.2 V

UVLO Hysteresis2 150 mV

1

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2

Guaranteed by design or characterization, not production tested.

Rev. 1 | Page 6 of 38 | www.onsemi.com

TIMING DIAGRAM

Timing is referenced to the 90% and 10% points, unless otherwise noted.

IN

DRVL

tf

DRVL

tpdh

DRVHtrDRVH

tpdl

DRVL

tpdl

DRVH

tf

DRVH

tr

ADP3208

DRVL

(WITH RESPECT

DRVH

TO SW)

SW

V

TH

Figure 2. Timing Diagram

V

TH

tpdh

DRVL

1V

06374-006

Rev. 1 | Page 7 of 38 | www.onsemi.com

ADP3208

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VCC, PVCC1, PVCC2 −0.3 V to +6 V
FBRTN, PGND1, PGND2 −0.3 V to +0.3 V
BST1, BST2

DC −0.3 V to +25 V
t < 200 ns −0.3 V to +30 V

BST1 to SW1, BST2 to SW2 −0.3 V to +6 V
DRVH1, DRVH2, SW1, SW2

DC −5 V to +20 V
t < 200 ns −10 V to +25 V

DRVH1 to SW1, DRVH2 to SW2, −0.3 V to +6 V
DRVL1 to PGND1, DRVL2 to PGND2

DC −0.3 V to +6 V
t < 200 ns −5 V to +6 V

RAMP (in Shutdown)

DC −0.3 V to +20 V
t < 200 ns −0.3 V to +25 V

All Other Inputs and Outputs −0.3 V to +6 V
Storage Temperature −65°C to +150°C
Operating Ambient Temperature Range 0°C to 100°C
Operating Junction Temperature 125°C
Thermal Impedance (θJA) 2-Layer Board
Lead Temperature

Soldering (10 sec) 300°C
Infrared (15 sec) 260°C

40°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 1 | Page 8 of 38 | www.onsemi.com

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DPRSLP

DPRSTP

PSI

VID0

VID1

VID2

VID3

VID4

VID5

4847464544434241403938

VID6SPVCC

ADP3208

37

EN

PWRGD

PGDELAY

CLKEN
FBRTN

FB

COMP

SS

ST

VARFREQ

VRTT

TTSNS

1
2

3
4
5
6
7
8

9
10
11
12

PIN 1
INDICAT OR

ADP3208

TOP VIEW

(Not to Scale)

13141516171819

CLIM

LLINE

PMON

PMONFS

CSREF

CSCOMP

2021222324

VRPM

RAMP

CSSUM

RPMRTGND

35
34
33

32
31
30
29
28
27
26
25

BST136

DRVH1
SW1
PVCC1

DRVL1
PGND1
PGND2
DRVL2
PVCC2
SW2
DRVH2
BST2

06374-002

Figure 3. LFCSP Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 EN Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, pulls PWRGD

and VRTT low, and pulls

CLKEN

high.

2 PWRGD Power-Good Output. Open-drain output. A low logic state means that the output voltage is outside

of the VID DAC defined range.

3 PGDELAY Power-Good Delay Setting Input/Output. A capacitor connected from this pin to GND sets the

power-good delay time.

4

CLKEN

Clock Enable Output. Open-drain output. A low logic state enables the CPU internal PLL clock to
lock to the external clock.

5 FBRTN Feedback Return Input/Output. This pin remotely senses the CPU core voltage. It is also used as the

ground return for the VID DAC and the voltage error amplifier blocks.
6 FB Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.
7 COMP Voltage Error Amplifier Output and Frequency Compensation Point.
8 SS Soft Start and Latch-Off Delay Setting Input/Output. An external capacitor from this pin to GND sets

the soft start ramp-up time and the current limit latch-off delay ramp-down time.
9 ST Soft Transient Slew Rate Timing Input/Output. A capacitor from this pin to GND sets the slew rate of

the output voltage when it transitions from one VID setting to another, including boot-to-active

VID, VID on the fly, and deeper sleep entry and exit transients.
10 VARFREQ Variable Frequency Enable Input. A high logic state enables the PWM clock frequency to vary with

VID code.
11 VRTT Voltage Regulator Thermal Throttling Output. Logic high state indicates that the voltage regulator

temperature at the remote sensing point exceeded a set alarm threshold level.
12 TTSNS Thermal Throttling Sense and Crowbar Disable Input. A resistor divider where the upper resistor is

connected to VCC, the lower resistor (NTC thermistor) is connected to GND, and the center point is

connected to this pin and acts as a temperature sensor half bridge. Connecting TTSNS to GND disables

the thermal throttling function and disables the crowbar, or overvoltage protection (OVP), feature

of the chip.
13 PMON Power Monitor Output. Open-drain output. A pull-up resistor from PMON to CSREF provides a duty

cycle–modulated power output signal. An external RC network can be used to convert the digital

signal stream to an averaged power analog output voltage.
14 PMONFS Power Monitor Full-Scale Setting Input/Output. A resistor from this pin to GND sets the full-scale

value of the PMON output signal.

Rev. 1 | Page 9 of 38 | www.onsemi.com

ADP3208

Pin No. Mnemonic Description

15 CLIM Current Limit Setting Input/Output. An external resistor from this pin to GND sets the current limit

threshold of the converter.

16 LLINE Load Line Programming Input. The center point of a resistor divider connected between CSREF and

CSCOMP can be tied to this pin to set the load line slope.
17 CSCOMP Current Sense Amplifier Output and Frequency Compensation Point.
18 CSREF Current Sense Reference Input. This pin must be connected to the common point of the output

inductors. The node is shorted to GND through an internal switch when the chip is disabled to

provide soft stop transient control of the converter output voltage.
19 CSSUM Current Sense Summing Input. External resistors from each switch node to this pin sum the

inductor currents to provide total current information.
20 RAMP PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this

pin sets the slope of the internal PWM stabilizing ramp used for phase-current balancing.
21 VRPM RPM Mode Reference Voltage Output.
22 RPM Ramp Pulse Modulation Current Source Output. A resistor between this pin and VRPM sets the RPM

comparator upper threshold.
23 RT PWM Oscillator Frequency Setting Input. An external resistor from this pin to GND sets the PWM

oscillator frequency.
24 GND Analog and Digital Signal Ground.
25 BST2 High-Side Bootstrap Supply for Phase 2. A capacitor from this pin to SW2 holds the bootstrapped

voltage while the high-side MOSFET is on.
26 DRVH2 High-Side Gate Drive Output for Phase 2.
27 SW2 Current Balance Input for Phase 2 and Current Return for High-Side Gate Drive.
28 PVCC2 Power Supply Input/Output of Low-Side Gate Driver for Phase 2.
29 DRVL2 Low-Side Gate Drive Output for Phase 2.
30 PGND2 Low-Side Driver Power Ground for Phase 2.
31 PGND1 Low-Side Driver Power Ground for Phase 1.
32 DRVL1 Low-Side Gate Drive Output for Phase 1.
33 PVCC1 Power Supply Input/Output of Low-Side Gate Driver for Phase 1.
34 SW1 Current Balance Input for Phase 1 and Current Return For High-Side Gate Drive.
35 DRVH1 High-Side Gate Drive Output for Phase 1.
36 BST1 High-Side Bootstrap Supply for Phase 1. A capacitor from this pin to SW1 holds the bootstrapped

voltage while the high-side MOSFET is on.
37 VCC Power Supply Input/Output of the Controller.
38 SP Single-Phase Select Input. Logic high state sets single-phase configuration.
39 to 45 VID6 to VID0 Voltage Identification DAC Inputs. A 7-bit word (the VID code) programs the DAC output voltage,

the reference voltage of the voltage error amplifier without a load (see the VID code table, Table 6).
46

47

48 DPRSLP Deeper Sleep Control Input.

PSI

DPRSTP

Power State Indicator Input. Driving this pin low forces the controller to operate in single-phase mode.

Deeper Stop Control Input. The logic state of this pin is usually complementary to the state of the

DPRSLP pin; however, during slow deeper sleep exit, both pins are logic low.

Rev. 1 | Page 10 of 38 | www.onsemi.com

3

TEST CIRCUITS

ADP3208

7-BIT CO DE

48

1.05V

1kΩ

10nF

PWRGD

TTSNS

1

EN

PGDELAY
CLKEN
FBRTN
FB
COMP
SS
ST
VARFREQ
VRTT

DPRSLP

PMON

250kΩ

PSI

DPRSTP

PMONFS

CLIM

VID0

VID1

VID2

ADP3208

LLINE

CSCOMP

CSREF

100nF

Figure 4. Closed-Loop Output Voltage Accuracy

ADP3208

VID3

CSSUM

20kΩ

100nF

5V

ADP3208

VCC

5V

10kΩ

ΔV

1V

06374-003

37

COMP

7

FB

6

LLINE

16

CSREF

18

GND

24

ΔVFB = FB

–

+

ΔV = 80mV

– FB

ΔV= 0mV

VID

DAC

06374-005

1μF

SP

VID5

VRPM

VID6

PVCC1

DRVL1
PGND1
PGND2

DRVL2

PVCC2

DRVH2

RPMRTGND

VCC

BST1

SW1

SW2

BST2

VID4

RAMP

Figure 6. Positioning Accuracy

VCC

100nF

37

CSCOMP

17

CSSUM

19

CSREF

18

GND

24

VOS =

CSCOMP – 1V

40

OS

06374-004

5V

9kΩ

1kΩ

1V

Figure 5. Current Sense Amplifier, V

Rev. 1 | Page 11 of 38 | www.onsemi.com

ADP3208

TYPICAL PERFORMANCE CHARACTERISTICS

V

= 1.5 V, TA = 20°C to 100°C, unless otherwise noted.

VID

95

90

85

80

75

70

EFFICIENCY (%)

65

60

55

50

0 10203040

Figure 7. PWM Mode Efficiency vs. Load Current

VIN = 8V

= 12V

V

IN

LOAD CURRENT (A)

V

= 19V

IN

f

= 318kHz

SW

06374-007

90

88

86

84

82

80

78

EFFICIENCY (%)

76

74

72

70

0

RPM AUTOMATI C CCM/DCM

RPM CCM ONLY

10 20 30 40

LOAD CURRENT (A)

Figure 10. Efficiency vs. Load Current in All Modes

PWM

VIN = 12V

06374-010

95

90

85

V

80

75

EFFICIENCY (%)

70

65

60

030

IN

VIN = 8V

V

= 19V

= 12V

IN

10 20

LOAD CURRENT (A)

06374-008

Figure 8. RPM Mode Efficiency vs. Load Current in CCM Only

91

= 8V

V

89

87

85

83

81

EFFICIENCY (%)

79

77

75

IN

VIN = 12V

VIN = 19V

CCM/DCM
TRANSITION

030

10 20

LOAD CURRENT (A)

06374-009

Figure 9. RPM Mode Efficiency vs. Load Current Automatic in CCM/DCM

400

350

300

250

200

150

100

SWITCHING FREQUENCY (kHz)

50

0

030

Figure 11. Switching Frequency vs. Load Current in RPM Mode

500

400

300

200

SWITCHING FREQUENCY (kHz)

100

0

01.50

Figure 12. Switching Frequency vs. VID Output Voltage in PWM Mode

CCM ONLY

AUTOMAT IC CCM/ DCM

5 10152025

LOAD CURRENT (A)

VARFREQ = 0V

VARFREQ = 5V

RT = 237kΩ

0.25 0.50 0.75 1.00 1.25

VID OUTPUT VOLT AGE (V)

06374-011

06374-012

Rev. 1 | Page 12 of 38 | www.onsemi.com