Omega Products DAQP-12 Installation Manual

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DAQP-12/12H/16

PCMCIA

Data Acquisition System

For Machines with Standard PCMCIA Interface

Users Manual

INTERFACE CARDS FOR PERSONAL COMPUTERS

OMEGA ENGINEERING, INC. Tel: [phone]
One Omega Drive Fax: [phone]
P.O. Box 4047 Toll free: 1-800-826-6342
Stamford, CT 06907-4047 E-mail: [e-mail]

http://www.dasieee.com

WARRANTY/DISCLAIMER

OMEGA ENGINEERING, INC., warrants this unit to be free of defects in materials and workmanship fo r a period of 13

DAQP-12/12H/16 Users Manual 2

months from the date of purchase. OMEGA warranty adds an additional one (1) month grace period to the normal one (1)
year product warranty

coverage on each product. If the unit should malfunction, it must be returned to the factory for evaluation. OMEGA’s
Customer Service Department will issue an Authorized Return (AR) number im mediately upon phone or written request.
Upon examination by OMEGA, if the unit is found to be defective it will be repaired or replaced at no charge. OMEGA’s
warranty does not apply to defects resulting from any action of the purchaser, including but not limited to mishandling,
improper interfacing, operation o utside design limits, impr oper repair or unauthorized modif ication. This WARRANTY is
VOID if the unit shows evidence of having been tampered with or shows evidence of being damaged as a result of excessive
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under 10 CFR 21 (NRC), used in or with any nuclear installation or activity, medical application or used on humans.
Should any Product(s) be used in or with any nuclear installation or activity, medical application, used on humans or
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to cover shipping and handling time. This ensures that OMEGA’s customers receive maximum

RETURN REQUESTS/INQUIRIES

Direct all warranty and repair requests/inquiries to the OMEGA Customer Service Department. BEFORE RETURNING
ANY PRODUCT(S) TO OMEGA, PURCHASER MUST OBTAIN AN AUTHORIZED RETURN (AR) NUMBER FROM
OMEGA’S CUSTOMER SERVICE DEPARTMENT (IN ORDER TO AVOID PROCESSING DELAYS). THE ASSIGNED
NUMBER SHOULD THEN BE MARKED ON THE OUTSIDE OF THE RETURN PACKAGE AND ON ANY
CORRESPONDEN CE. THE PURCHASER IS RESPONSIBLE FOR SHIPPING C HARGES, FREIGHT, IN SURANCE AND
PROPER PACKAGING TO PREVENT BREAKAGE IN TRANSIT.

FOR WARRANTY
(1) P.O. Number under which the product was purchased,
(2) Model and serial number of the product under warranty, and
(3) Repair instructions and/or specific problems relative to the product.

FOR NON-WARRANTY
BEFORE contacting OMEGA:
(1) P.O. Number to cover the cost of the repair,
(2) Model and serial number of the product, and
(3) Repair instructions relative to the product.

OMEGA’s policy is to make running changes, not model changes, whenever an improvem ent is possible. This af fords our
customers the latest in technology and engineering.

OMEGA is a registered trademark of OMEGA ENGINEERING, INC. © Copyright 1999 OMEGA ENGIN EERING, IN C. A ll
rights reserved. This document may not be copied, photocopied, reproduced, translated or reduced to any electronic
medium or machine readable form, in whole or in part, without prior written consent of OMEGA ENGINEERING, INC.

RETURNS, please have the following information available BEFORE contacting OMEGA:

REPAIRS, consult OMEGA fo r current repair charges. Have the fo llowing information available

Declaration of Conformity

Manufacturer's Name:

Manufacturer’s Address:

Application of Council Directive:

Standards to which
Conformity is Declared:

(EN55022, EN60555-2, EN60555-3)

Type of Equipment:

Equipment Class:

Information Technology Equipment

Commercial, Residential and Light Industrial

89/336/EEC

Omega Engineering, Inc.

One Omega Drive
P.O. Box 4047
Stamford, CT 06907-0047

* EN50081-1

* EN50082-1
(IEC 801-2, IEC 801-3, & IEC 801-4)

Product Name:

Model Number :

DAQP-12/12H/16 Users Manual 3

PCMCIA Card

DAQP-12/12H/16

OMEGAnet On-line Service: Internet e-mail:

DAQP-12/12H/16 Users Manual 4

http://www.omega.com

Servicing North America

: One Omega Drive, Box 4047 E-mail: [e-mail]

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Stamford, CT 06907-0047
Tel: [phone] FAX: [phone]

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Tel: [phone] FAX: [phone]

[e-mail]

:

For immediate technical or application assistance

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: Sales Service: 1-800-826-6342 / 1-800-TC-OMEGA

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:

United Kingdom: One Omega Drive, River Bend Technology Drive

DAQP-12/12H/16 Users Manual 5

ISO 9002 Certified

It is the policy of OMEGA to comply with all worldwide safety and EMC/EMI regulations that app ly.
OMEGA is constantly pursuing certification of it’s products to the European New Approach
Directives. OMEGA will add the CE mark to every appropriate device upon certification.

The information contained in this document is believed to be correct but OMEGA Engineering, Inc.
accepts no liability for any errors it contains, and reserves the right to alter specifications without
notice. WARNING: These products are not designed for use in, and should not be used for, p atient
connected applications.

Northbank, Irlam, Manchester
M44 5EX, England
Tel: [phone]
FAX: [phone]
Toll Free in England: 0800-488-488
E-mail: [e-mail]

Table of Contents

5.9 A/D State Machine

5.8 Digital I/O

5.7 Interrupt and Status

5.6 A/D Converter and Data FIFO

5.5 Trigger Circuit

5.4 Scan List Register

5.3 Programmable Gain Control Amplifier

5.2 Analog Input Multiplexer

5.1 DC/DC Power Supply

5. Theory of Operation

4.4 After Completing Configuration

20

4.3.3 Card and Socket Services Software

20

4.3.2 Socket Numbers

20

4.3.1 Memory Range Exclusion

4.3 Common Problems

4.2 Enabler Examples

4.1 Enabler Command Line Options

4. Using the Enabler

3.5 After Completing Configuration

16

3.4.3 Older Versions of Card and Socket Services

16

3.4.2 Multiple Configuration Attempts

16

3.4.1 Available Resources

15

3.4.1 Generic Client Drivers

3.4 Common Problems

3.3 Client Driver Installation Examples

3.2 Client Driver Command Line Options

3.1 Installing the Client Driver

2.3 Software Setup (Windows 3.xx and MS-DOS®)

11

2.2.3 Changing the Configuration of the DAQP Card

10

2.2.2 Viewing the DAQP Series Card Status

10

2.2.1 Installing the DAQP Series Card

2.2 Software Setup (Windows 95/98®)

2.1 Hardware Setup

1. Introduction

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DAQP-12/12H/16 Users Manual 6

9

2. Installation

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3. Using the Client Driver

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10. Specifications

9.2 CP-DAQP Cable Assembly

9.1 UIO-37 Screw Terminal Block

8. I/O Connections

40

7.7.6 Scan Rate Selection

39

7.7.5 Data FIFO Program/Access Control

39

7.7.4 A/D Stop Command

38

7.7.3 Flush Data FIFO Command

38

7.7.2 Flush Scan List Queue Command

38

7.7.1 Trigger/Arm Command

7.7 Auxiliary Control Register (base + 7)

7.6 Pacer Clock (base + 4, + 5, + 6)

36

7.5.2 Digital Input

36

7.5.1 Digital Output

7.5 Digital I/O Register

7.4 Status Register (base + 2, read)

35

7.3.5 Trigger Edge

35

7.3.4 Trigger Mode/Source

34

7.3.3 Interrupt Enable

34

7.3.2 Expansion Mode

34

7.3.1 Clock Source

7.3 Control Register (base + 2, write)

33

7.2.3 Analog Input Offset Correction

33

7.2.2 Channel Configuration

32

7.2.1 Scan List Queue Programming

7.2 Scan List Queue Register (base + 1)

31

7.1.3 FIFO Flags

31

7.1.2 Mode Setting

30

7.1.1 Data FIFO Operation Modes

7.1 Data FIFO Register (base + 0)

7. I/O Registers

6.2 Card Configuration and Status Register (CCSR)

6.1 Configuration and Option Register (COR)

6. PCMCIA Interface

DAQP-12/12H/16 Users Manual 7

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9. Optional Accessories

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42
42
43

46

List of Figures and Tables

45

Table 9-1. DAQP Series Card Cable Mapping

39

Table 7-14. Data FIFO Threshold Setting

38

Table 7-13. Auxiliary Control Register Bit Definition

36

Table 7-12. Digital Input Register Bit Definition

36

Table 7-11. Digital Output Register Bit Definition

35

Table 7-10. Status Register Bit Definition

34

Table 7-9. Control Register Bit Definition

33

Table 7-8. Scan List Queue Programming Example 2

33

Table 7-7. Scan List Queue Programming Example 1

32

Table 7-6. Scan List Queue Entry Bit Definition

31

Table 7-5. Data FIFO Flag Status

30

Table 7-4. Data FIFO Threshold Setting

30

Table 7-3. Data FIFO Operation Mode

30

Table 7-2. Data FIFO Register Bit Allocation

29

Table 7-1. DAQP Series Card Address Map

28

Table 6-3. CCSR Bit Definition

28

Table 6-2. COR Bit Definition

27

Table 6-1. PCMCIA Configuration Registers

12

Table 2-1. Comparison Between Client Driver and Enabler

44

Figure 9-3. CP-DAQP/UIO-37 D-37 Pin Diagram

43

Figure 9-1. DAQP Series Card Accessory Connection

41

Figure 8-1. DAQP Series Card Hirose-32 Output Connector

37

Figure 7-1. Pacer Clock Block Diagram

26

Figure 5-3. Transition Diagram of A/D Conversion Process

21

Figure 5-1. DAQP Data Acquisition System Block Diagram

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DAQP-12/12H/16 Users Manual 8

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1. Introduction

DAQP-12/12H/16 Users Manual 9

DAQP CARD FEATURES:



Sampling rate up to 100 kHz with 12 or 16 bit resolution



8 differential or 16 single-ended analog input channels, expandable to 256 channels



Bipolar input range up to ±10 volts



Software programmable gain selection: 1, 2, 4 or 8 for the DAQP-12/16 and

1, 10, 100 or 1000 for the DAQP-12H



2048 sample Data and Scan FIFOs



24-bit pacer clock with variable pre-scalers and internal or external clock source



Digital input/output channels



Flexible trigger mode (internal/external, one-shot/continuous, rising/falling edge)



Omega’s “DaqSuite” data acquisition software included in addition to drivers for
MS-DOS®, Windows 3.xx and Windows 95/98®

The DAQP series card is a PCMCIA type II data acquisition system with 8 differential or 16
single-ended analog input channels. The number of input channels can be expanded to 256
with an i nput e x pansi on card. DAQP series pr od ucts include the DAQP-12, the DAQP-16 and
the high gain DAQP-12H. The programmable gain settings of the DAQP-12 and DAQP-16
span bipolar input ranges of ±1.25 V (gain = 8), ±2. 5 V (gain = 4), ±5 V (gain = 2) and ± 10V
(gain = 1), w hile the DAQP-12H offers a bipol ar input range of ±0.01 V (gain = 1000), ±0.1 V
(gain = 100), ±1 V (gain = 10) and ± 10V (gain = 1).

The DAQP card supports sampling rates up to 100 kHz with either 12 or 16-bit resolution.
Equipped with a data FIFO of 2048 samples, the DAQP card can achieve high speed data
acquisition under various operating platforms including MS-DOS®, Windows 3.xx and
Windows 95®. Also equipped with a scan FIFO of the same size, the DAQP supports full
speed, random order channel scanning and gain selection for all input channels including
expansion channels. The DAQP card uses a 24-bit pacer clock and a programmable
divide-by-2, by-10 or by-100 pre-scaler. The pacer clock can also be used with either an
internal or external cl ock source. With the 10 MH z internal clock source, the pacer clock can
generate accurate sampling rates from 0.006 Hz to 100 kHz. The DAQP card has 4 digital
input and output channels, all TTL compatible, which may be used for process control or
monitoring in addition to analog data acquisition.

Software drivers are provided that support various programming languages like Microsoft
C/C++, Borland C/C++, Delphi, QuickBasic, Visual Basic for DOS and Turbo Pascal. Also
included is a Dynamic Link Library (DLL) that supports programming languages under
Microsoft Windows as well as the Visual Basic Controls (VBX). Omega includes it’s user
friendly data acquisition software: DaqEZ®, as well as turnkey software support for LabTech
NoteBook®, SnapMaster®, LabVIEW® and TestPoint®.

2. Installation

DAQP-12/12H/16 Users Manual 10

2.1 Hardware Setup

Insert the DAQP card into any type II PCMCIA socket. All other configuration options are
determined by the operating system.

2.2 Software Setup (Windows 95/98®)

An “.INF” file (DAQPCARD.INF) is provided on the root directory of the DAQSUITE
CD-ROM for easy installati on of the DAQP series car d under Wind ows 95/98. The operating
system uses the “.INF” file to determine what system resources are required by the card,
searches for available resources to fill the requirements, configures the DAQP card hardware
and then updates the hardware registry with an entry that allocates these resources.

2.2.1 Installing the DAQP Series Card

1. Insert the DAQP card in any available PCMCIA socket.

2. The first time a new PCMCIA type card is installed the “New Hardware Found”
window opens. Windows 95/98 will automatically detect and configure the card. If
the “New Hardware Found” window does not open, skip to the next section:
“Viewing the PCMCIA Card Status”.

3. Windows will ask for the CD-ROM that came with the device. Insert the CD, click
“Next” to continue and then click “Finish”.

4. W indows automatically b rowses the root dir ectory on the CD for the IN F file that
defines configurations for the new hardware type found. The file name is not
required. After searching the root directory, Windows will choose the correct file.

5. Your new PCMCIA card should now be configured. In the future, Windows will
automatically recognize and configure this specific PCMCIA card type.

2.2.2 Viewing the DAQP Series Card Status

1. Double click the “My Computer” icon located on the Windows 95/98 desktop. This
opens a folder showing the various drives, printers, etc. (This can also be done by
clicking “Start”, “Settings” and then “Control Panel”).

2. Doub le click the “Control Pane l” icon. This opens another fol der with dif ferent system
configuration utilities.

3. Double click the “PC card (PCMCIA)” icon. This opens the “PC Card (PCMCIA)
Properties” window.

4. The “PC Card (PCMCIA) Properties” window shows the status of your computers
PCMCIA sockets. The DAQP card should be listed in one of these sockets. To change
the DAQP card configuration see the next section.

IMPORTANT:

DAQP-12/12H/16 Users Manual 11

If you are using Wi ndows 95/98 to configure the DAQP card then ignore section 2.3 of
this chapter. The Windows 95/98 operating system completely installs and configures the
DAQP series ca rd. Do NOT attempt to use the D AQP series Client Dri ver or Enabler to
configure any DAQP series card under Windows 95/98.

2.2.3 Changing the Configuration of the DAQP Card

1.

Double cli ck the “My Computer” i con located on the Wind ows 95 desktop. Inside the
“My Computer” folder, double click the “Control Panel” icon. This can also be done by
clicking “Start”, “Settings” and then “Control Panel”.

2.

Inside the “Control Panel” fold er, double cli ck the “System” icon so that the “System
Properties” window opens. Select the “Device Manager” tab. Find the entry titled
“Data_Acquisition” on the device list. Expand the entry by clicking the leading “+”
sign or by double clicking the name.

3.

From the expa nded sub-list, choose the DAQP card to reconfigure (ther e may be only
one entry) by double clicking it.

4.

Select the “Resources” tab from the pop-up window. Click the resource type (either
“Input/Output range” or “Interrupt Request”) from the “Resource Setting” table and
then click the “Change Settings ...” button. This opens the “Edit Input/Output Range”
or “ Edit Interrupt Request” window.

5.

Change the value by clicking on the slider controls by the “value” list and then click
OK to confirm the change, or CANCEL to discard it. Watch for possible conflicts
shown in the “Conflict Information” box.

The only conf iguration parameters that can be changed for the DAQP car d under Windows
95/98 are “Input/Output Ranges” and “Interrupt Request”.

2.3 Software Setup (Windows 3.xx and MS-DOS®)

Does not require PCMCIA Card and

Requires PCMCIA Card and Socket

Does not support automatic

Allows automatic configuration of

Interfaces directly to Intel 82365SL and

Interfaces to PCMCIA Card and

DAQP_EN.EXE

DAQP_CL.SYS

DAQP-12/12H/16 Users Manual 12

Two software configuration programs are provided with the DAQP card: a Client Driver
named DAQP_CL.SYS and a card Enabler named DAQP_EN.EXE. Either one of these
programs may be used to configure the card
below highlights the differences between the Client Driver and the Enabler programs.
(Detailed instructions for using the Client Driver and Enabler are discussed in Chapters 3 and
4 respectively).

but only one may be used at a time

EnablerClient Driver

. The table

Socket Services software (PCMCIA
host adapter independent)

DAQP card upon insertion (Hot
Swapping)

Services software

Table 2-1. Comparison Between Client Driver and Enabler

On systems with Card and Socket Services installed, the Client Driver is the preferred method
of installation. To determine if Card and Socket Services software is installed, install the
DAQP series Client Driver as discussed in Chapter 3. When loaded, the Client Driver will
display an error message if Card and Socket Services software is not detected.

other PCIC compatible PCMCIA host
adapters

configuration of DAQP card upon
insertion (Hot Swapping)

Socket Services software

3. Using the Client Driver

DAQP-12/12H/16 Users Manual 13

3.1

For systems using MS-DOS and PCMCIA Card and Socket Services software, a Client Driver
named “DAQP_CL.SYS” i s provided to confi gure the DAQP series card s. PCMCIA Card and
Socket Services software is not provided and must be purchased independently.

Some versions of Card and Socket Services dated b efore 1993 do not support general purpose
I/O cards. After careful installation of the Client Driver, if the DAQP card still does not
configure or operate properly, an updated version of Card and Socket Services software may
be required. The following procedures are used to install the DAQP series Client Driver:

Installing the Client Driver

1. Copy the file DAQP_CL.SYS located in the PCMCIA\DOS\CLIENTS directory of the
“DAQSUITE” CD-ROM onto the root directory of the system hard drive.

2. Using an ASCII text editor, open the system CONFIG.SYS file located in the root
directory of the boot drive.

3. Locate the line in the CONFIG.SYS file where the Card and Socket Services software is
installed.

4. AFTER the line installing the Card and Socket Services software, add the following line
to the CONFIG.SYS file:

DEVICE = drive:\path\DAQP_CL.SYS options
where options ar e the DAQP series Cl ient Driver command line options discussed on

the following pages. (Path is only required if the user copies the Client Driver into a
directory other than the root directory).

5. Save the CONFIG.SYS file and exit the text editor.

6. Insert the DAQP card into one of the system PCMCIA slots.

NOTE: Since the DAQP series Client Driver supports "Hot Swapping", it is not
necessary to have the DAQP card installed when booting the system. However, by
inserting the card before booting, the Client Driver will report the card configuration
during the boot process and thereby verify changes made to the CONFIG.SYS file.

7. Reb oot the system and note the message d isplay ed when the Cli ent Dri ver is loade d. If
the Client Driver reports an “invalid command line option”, correct the entry in the
CONFIG.SYS f ile and reb oot the system. If the Client D river r eports “Card and Sock et
Services not found”, then either Card and Socket Services software must be installed on
the system or the DAQP series Enabler program must be used to configure the card,
(see Chapter 4 ). If the Client Driver reports the desired card configuration, the
installation process is complete and the DAQP card may be removed and inserted from
the system as desir ed. On each insertion into the PCMCIA socket, the DAQP card wil l
automatically be reconfigured to the specified settings.

3.2

DAQP-12/12H/16 Users Manual 14

The DAQP series Client Dri ver accepts up to eight command l ine arguments from the user to
determine the configuration of the DAQP card. If any arguments are provided, the Client
Driver will attempt to configure any DAQP card with the options specified in the order they
are entered on the command line. Each argument must be enclosed i n parenthesi s and must be
separated from other arguments by a space in the command line. Inside an argument, a
comma (no space) should b e used to separate the para meters f rom each other if there are two
or more parameters. Within each argument, any or all of the following parameters may be
specified:

(b address) Specifies the base I/O address of the DAQP card in hexadecimal.

(i irq) Specifies the interrupt level (IRQ) of the DAQP card in hexadecimal.

Client Driver Command Line Options

“Address” must be in the range 100H - 3F8H and must reside on an even 8-byte
boundary (“address” must end in 0 or 8). If this option is omitted, a base address
will be assigned by Card and Socket Services software.

“Irq” must be one of the following values: 3, 4, 5, 7, 9, 10, 11, 12, 14, 15 or 0 if no
IRQ is desired. If this option is omitted, an interrupt level will be assigned by
Card and Socket Services software.

(s socket) Specifies the PCMCIA socket number to configure.

“Socket” must be in the range 0 - 15. If this option is omitted, the configuration
argument will be applied to any DAQP card inserted into any socket(s) in the
system.

3.3 Client Driver Installation Examples

With the Client Driver, the user may specify a list of selections (in the form of command line
arguments) for the configuration of the DAQP series cards. The Client Driver scans this list
from left to right until it finds a selection that is currently available in the system. If none of
the preferred selections are available, the Client Driver requests a configuration from Card
and Socket Services software.

Example 1: DEVICE = C:\DAQP_CL.SYS
In example 1, no command line arguments are specified. The Client Driver will configure the

DAQP card into ANY socket with a base ad dress and IRQ level assigned by Card and Socket
Services.

Example 2: DEVICE = C:\DAQP_CL.SYS (b300)
In this example, a single command line argument is provided. The Client Driver will attempt

to configure a DAQP card inserted into ANY socket with a base address of 300H and an IRQ
level assigned by Card and Socket Services. If the base address 300H is not available, the
DAQP card will NOT be configured.

Example 3: DEVICE = C:\DAQP_CL.SYS (s0,b300,i5)

Example 3 is also a single command line argument. The Client Driver will attempt to

DAQP-12/12H/16 Users Manual 15

configure the DAQP card inserted in socket 0 at base address 300H and IRQ level 5. If either
address 300H or IRQ 5 are unavailable, the card will NOT be configured. In addition, the
Client Driver will NOT configure any DAQP card unless inserted into socket 0.

Example 4: DEVICE = C:\DAQP_CL.SYS (b300,i5) (i10) ( )
Three command line arguments are provided in this example. The Client Driver will first

attempt to configure a DAQP card inserted into any socket wi th a base address 300H and IRQ
level 5. If either address 300H or IRQ 5 are unavailable, the Client Driver will proceed to the
second command line argument and attempt to configure the card with a base address
assigned by the Card and Socket Services and IRQ level 10. If IRQ 10 is also unavailable, the
Client Driver will then go to the third command line argument and attempt to configure it
with a base address and an IRQ level assigned by Card and Socket Services.

Example 5: DEVICE = C:\DAQP_CL.SYS (b300,i5) ( ) (i10)
The difference between examples 5 and 4 is the order of the second and third command line

arguments. The Client Driver will first attempt to configure a DAQP card inserted into any
socket with a base address 300H and IRQ level 5. If either address 300H or IRQ 5 are
unavailable, the Client Driver will proceed to the second command line argument and attempt
to configure the card with a base address and IRQ level assigned by Card and Socket Services.
Since the second command line argument includes all available address and IRQ resources,
the third command line argument will never be reached. The user must ensure the command
line arguments are placed in a logical order.

Example 6: DEVICE = C:\DAQP_CL.SYS (s0,b300,i5) (s1,b310,i10)
There are two command line arguments in example 6, which is desirable in systems where

two or more DAQP cards are to be installed. The Client Driver will attempt to configure the
DAQP card in socket 0 with base addr ess 300H and IRQ level 5. If there is a DAQP card i n
socket 1, it will be configured with base address 310H and IRQ 10. This allows the user to
force the card addresses and I RQ settings to be socket speci f i c as required by software or cable
connections. If the requested resources are not available, the DAQP cards will not be

configured.

3.4 Common Problems

3.4.1 Generic Client Drivers

Many Card and Socket Services packages include a generic client driver (or SuperClient)
which configures standard I/O devices. If one of these generic client drivers is installed, it
may configure the DAQP card and cause the DAQP series Client Driver to fail installation. If
this is the case, the operation of the generic client driver can be modified so that it will not
configure the DAQP card. Place the DAQP series Client Driver command line before the
generic client driver command line in the CONFIG.SYS file. Consult the Card and Socket
Services documentation for availability and details of this feature.

3.4.1 Available Resources

DAQP-12/12H/16 Users Manual 16

One function of Card and Socket Services software is to track which system resources
(memory addresses, I/O addresses, IRQ levels, etc.) are available for assignment to inserted
PCMCIA cards. Sometimes, however, the Card and Socket Services assumes or incorrectly
determines that a particular resource is unavailable when it actually is available. Most Card
and Socket Services generate a resource table, typically in the form of an “.INI” file, which the
user can modify to ad j ust the avai l a b l e system resources. Consul t the Card and Socket Services
documentation for the availability and details of this feature.

3.4.2 Multiple Configuration Attempts

Some Card an d Socket Services have a setting whi ch aborts the confi guration process after a
single configuration failure (such as a configuration request for an unavailable resource). The
user should change this setting to allow f or mul ti ple configurati on attempts. Consult the Car d
and Socket Services documentation for the availability and details of this feature.

3.4.3 Older Versions of Card and Socket Services

Some versions of Card and Socket Services dated b efore 1993 do not support general purpose
I/O cards like the DAQP series card s. If after careful installati on of the DAQP Client Dri ver,
the DAQP card still can not be configured or operated properly, an updated version of Card

and Socket Services may be required.

3.5 After Completing Configuration

The DAQP card is now configured and ready for use. Depending on the type of application
software to be used, the user may wish to review one or more of the following:

1. Chapter 5 of this document provides basic theory of operation for users that wish to
learn technical details about the operation of the DAQP card.

2. For users that want to program direct I/O transfers to the DAQP card’s register set,
Chapter 7 provides an address map and a detailed description of each register.

3. User s that wish to write custom application software w ithout programming the DAQP
card di rectl y should consult the D AQDRI VE® softwar e ref ere nce manual . DA QDRIVE
provides a library of data acquisition subroutines for various data acquisition cards and
is included free of charge with the DAQP card.

4. For turnkey data acquisition software such as LabTech NoteBook®, SnapMaster®,
LabVIEW® and TestPoint®, consult the documentation provided by the software
manufacturer.

4. Using the Enabler

For systems that are not operating PCMCIA Card and Socket Services software, the DAQP

DAQP-12/12H/16 Users Manual 17

series card includes an Enabler program to enable and configure the DAQP series card. This
Enabler, DAQP_EN.EXE, will operate in any DOS system using an Intel 82365SL or PCIC
compatible PCMCIA host adapter including the Cirrus Logic CL-PD6710/6720, the VLSI
VL82C146 and the Vadem VG-365.

In order to use the DAQP seri es Enabler for DOS, the system must NOT be confi gured with
Card and Socket Services software. If Card and Socket Services software is installed, the
Enabler may interfere with its operation and the devices it controls. Therefore use either the
DAQP series Client Driver or Enabler exclusively.

The DAQP se ries Enabler d oes not support automatic configurati on of PCMCIA cards upon
insertion, more commonly referred to as “Hot Swapping”. This means the card must be
installed in one of the system's PCMCIA sockets before executing DAQP_EN.EXE. If more
than one adapter is installed in a system, the Enabler must be executed separately for each
card. Furthermore, DAQP_EN.EXE should be executed to release the resources used by the
card bef ore it is removed from the PCMCIA socket. Si nce PCMCIA cards do not retain their
configurati on af ter r e moval , any card r e moved from the syste m must b e reconfigur ed with the
Enabler after being reinserted into it’s PCMCIA socket.

The Enabler requires a region of high DOS memory when configuring the DAQP card. This
region is 1000H (4096) bytes long and by default begins at address D0000H (this may be
changed by the “W” option as will be described later). If a memory manager such EMM386,
QEMM or 386MAX is installed on the system, this region of DOS memory must be excluded
from the memory manager’s control (normally by using the “x” switch). Consult the
documentation provided with the memory manager software for instructions on how to
exclude this memory region.

The following procedures are used to install the DAQP series Enabler:

1. Copy the file DAQP_EN.EXE located in the PCMCIA\DOS\ENABLERS directory of
the “DAQSUITE” CD-ROM onto the root directory of the system hard drive.

2. Using an ASCII text editor, open the system's CONFIG.SYS file located in the root
directory of the boot drive.

3. Add the following line to the CONFIG.SYS file:

DEVICE = drive:\DAQP_EN.EXE (options)

where (options) are the DAQPA series Ena bler command line opti ons discussed on the
following pages.

4. Save the CONFIG.SYS file and exit the text editor.

5. Insert the DAQP card into one of the system PCMCIA slots.

DAQP-12/12H/16 Users Manual 18

NOTE: Since the DAQP series Enabler does not support "Hot Swapping",
it is necessary to have the DAQP card installed when booting the system.

6. Reboot the system and note the message displayed when the Enabler is loaded.
If the Enabler reports the desired card configuration, the installation process
is complete.

4.1 Enabler Command Line Options

To configure a DAQP series card in the system, the Enabler requires one command line
argument from the user to determine the configuration. This argument must be enclosed in
parenthesis. Within the argument, a comma (no space) must be used to separate the
parameters from each other if there are two or more parameters. The following parameters
may be specified in the command line argument:

(s socket) Specifies the PCMCIA socket number to configure.

“Socket” must be in the range 0 - 15. This option is always required.

(b address) Specifies the base I/O address of the DAQP card in hexadecimal.

“Address” must reside on an even 8-byte boundary (“address” must end in 0 or 8).
This option is required if the “r” option is not used.

(i irq) Specifies the interrupt level (IRQ) of the DAQP card in hexadecimal.

“Irq” must be one of the following values: 3, 4, 5, 7, 9, 10, 11, 12, 14, 15, or 0 i f no
IRQ is desired. This option is required if the “r” option is not used.

(w address) Specifies the base address of the memory window required to configure the

DAQP card. Set “address” = D0 for a memory window at D0000, = D8 for a
memory window at D8000, etc. Valid settings for address are C8, CC, D0, D4,
D8, and DC. If omitted, “address” = D0 is assumed.

(r) Instructs the Enabl er to release the resources previousl y allocated to the DAQP

card. When this option is used, (b address) and (i irq) options will be ignored.
Therefore, do NOT use this option when initially configuring the DAQP card.

4.2 Enabler Examples

DAQP-12/12H/16 Users Manual 19

Example 1

No command line argument is specified. The Enabler will report an error and display the
proper usage of the Enabler.

Example 2: DEVICE=C:\DAQP_EN.EXE (s0,b300,i5)
In this example, the Enabler will configure the DAQP card in socket 0 with a base address

300H and IRQ level 5 using a configuration memory window at D0000H.

Example 3: DEVICE=C:\DAQP_EN.EXE (i10,b310,s1)
In example 3, the Enabler will configure the DAQP card in socket 1 with a base address at

310H and IRQ level 10 using a configuration memory window at D0000H. Note the parameter
order is not significant.

Example 4: DEVICE=C:\DAQP_EN.EXE (s0,b300,i5,wCC)
Here the Enabler will configure the DAQP card in socket 0 with a base address at 300H and

IRQ level 5 using a configuration memory window at CC000H.

:

DEVICE=C:\DAQP_EN.EXE

Example 5: DEVICE=C:\DAQP_EN.EXE (s0,r)

DEVICE=C:\DAQP_EN.EXE (s0,r,b300,i5)

These two command line arguments are equivalent because of the “r” option. The Enabler
will release the configuration used by the DAQP card in socket 0 using a configuration
memory window at D0000H.

Example 6: DEVICE=C:\DAQP_EN.EXE (s0,r,wC8)
Here the Enabler will release the configuration used by the DAQP card in socket 1, using a

configuration memory window at C8000H.

4.3 Common Problems

4.3.1 Memory Range Exclusion

DAQP-12/12H/16 Users Manual 20

The Enabler requires a region of high DOS memory when configuring a DAQP card. This
region is 1000H (4096) bytes long and by default begins at address D0000H (this default
address can be changed by usi ng the “W” option). If a memory manager such as EMM386,
QEMM or 386MAX is installed on the system, this region of DOS memory must be excluded
from the memory manager’s control (normally by using the “x” switch). Consult the
documentation provided with the memory manager software for instructions on how to
exclude this memory r egion. Furthermor e, some systems use the high memory area for ROM
shadowing to i mprove overall system per formance. For the E nabler to properl y operate, any
ROM shadowing must be disabled in the address range specified for the configuration
window. This can usually be completed by using the system’s CMOS setup utility.

4.3.2 Socket Numbers

The Enabler requi res that the socket number be specifi ed for the DAQP card to be configured .
The DAQP card must be inserted into the socket before executing the Enabler. For the DAQP
series Enabler, the lowest socket number is always designated as socket 0 and the highest
socket number as N-1, (assuming there are N sockets avail able). Some vendors number their
sockets from 1 to N. In that case, the vendor socket number minus 1 should be used in the “s”
option for the DAQP series Enabler.

4.3.3 Card and Socket Services Software

In order to use DAQP seri es Enab ler for DOS, the system must NOT be configure d with Card
and Socket Services software. If Card and Socket Services software is installed, the Enabler
may interfere with its operation and the devices it controls.

4.4 After Completing Configuration

The DAQP card is now configured and ready for use. Depending on the type of application
software to be used, the user may wish to review one or more of the following:

1. Chapter 5 of this document provides basic theory of operation for users that wish to
learn technical details about the operation of the DAQP series card.

2. For users that want to program direct I/O transfers to the DAQP card’s register set,
Chapter 7 provides an address map and a detailed description of each register.

3. User s that wish to write custom application software w ithout programming the DAQP
card di rectl y should consult the D AQDRI VE® softwar e ref ere nce manual . DA QDRIVE
provides a library of data acquisition subroutines for various data acquisition cards and
is included free of charge with the DAQP card.

4. For turnkey data acquisition software such as LabTech NoteBook®, SnapMaster®,
LabVIEW® and TestPoint®, consult the documentation provided by the software
manufacturer.

5. Theory of Operation

The DAQP card consists of 8 differential or 16 single-ended analog input channels. The A/D

DAQP-12/12H/16 Users Manual 21

converter, either 12 -bit or 16-bit, can be operated at a top speed of 100,000 samples per
second, (10 ms per sample). The A/D converter uses l eft-j ustifi ed 2's complement cod ing. For
the 16-bit version, the output ranges f rom -32768 to 32767. The 12-bit version i s structured so
that it’s contents occupy the most significant 12 bits, padding the least significant 4 bits with
all zeros to make a 16-bit output word for each converted input sample.

8 Differential

or

16 Single Ended

Analog Input

Multiplexer

Programmable
24-bit
Pacer Cl o c k

Programmable

Gain Amp

x1, 2, 4, 8

512 or 2048
step
Scan List

A/D

Converter

512 or 2048
word
Data FIFO

Clock

Selection

Trigger
Control

Digital I/O

Sampling

Control

PCMCIA

BUS

Interface

Card Info

Memory

Figure 5-1. DAQP Data Acquisition System Block Diagram

The DAQP card can be operated as an I/O de vice, occupying eight consecutive bytes in the
I/O address space . It can also be config ured to operate via memory mapped I/O. The DAQP
fully compli es with PCMCIA standard 2.10 as a type II card. The card has no jumpers or DIP
switches. All the configurable features are software programmable.

Functionally, the DAQP card consists of the following components: the DC/DC power

DAQP-12/12H/16 Users Manual 22

supply, analog input multiplexer, programmable gain control amplifier, A/D converter, data
FIFO, scan list FIFO, trigger control circuit, pacer clock, interrupt & status registers, digital
I/O register and associated control circuits.

5.1 DC/DC Power Supply

The DAQP card uses a standard +5 volt digital input power supply from the PCMCIA
connector to generate the ±15 volt power supplies for the analog front end and the +5 volt
power supply for the A/D converter. The DC/DC converter uses 140 mA, 78% of the 180 mA
total load current, from the digital input power supply to generate the necessary voltages.

According to the PCMCIA standard, any card that draws more than 100 mA must not be
automatically turned on upon insertion until it is intentionally accessed by writing to the card
configuration and option register (or its allocated I/O space). The DAQP card supports this
specification by providing a unique power down mode control. When the card is first
powered up or af te r a r e se t, the D C/D C conver te r is turned of f, so that only the d igital portion
of the DAQP card is up and running. This requires only 40 mA from the digital input +5 volt
power supply. The user has the option of reading the card information memory, where the
maximum power consumption is listed for reference, and then decide whether or not to
“wake up” the card. If required, the card can be set to full power mode immediately when it’s
PCMCIA configuration and option register (COR) is written by the software.

After the card is set for full power mode for the first time by writing the PCMCIA
configuration and option register, it can then be set to power down mode by writing a ‘1’ into
bit 2 (the power down bit) of the PCMCIA auxiliary control register. Refer to Chapter 6 for
more information about the COR.

5.2 Analog Input Multiplexer

Differential or single-ended configuration is determined by bit 6 of the high byte in the scan
list register. ‘1’ selects differential input, while a ‘0’ selects single-ended input. Expansion
cards will only support single-ended channels. It is strongly recommended that single-ended
or differential selection be uniform for all internal channels (e.g., all 8 channels as differential
or all 16 channels as single-ended). Although it is possible to have some channels configured
as single-ended and others as differential, doing so may cause confusion and unexpected
signal errors.

With differential configuration, there are 8 channels. However, if the user specifies channels 8
to 15 in a differential configuration, it will short the inputs to ground for system offset
measurement. The readings taken under such a circumstance can be used for offset
correction.

The input multiple xers have built-i n protection against over-vol tage when the board i s at full
power AND when it is powered down. The protection mechanism will isolate the input from
the rest of the board, as long as the input voltage is within the protection range of ± 30 volts.

5.3 Programmable Gain Control Amplifier

DAQP-12/12H/16 Users Manual 23

The DAQP-12 and DAQP-16 cards have an internal gain of 1, 2, 4 or 8; and the DAQP-12H has
an internal gain of 1, 10, 100 or 1000. The gai n can be changed “on the fly” when scanning
from channel to channel by changing the configuration of the programmable gain
instrumentation amplifiers. The internal gain selection is specified by the scan list entry, bits 4
and 5 of the high byte. The contents of these two bits will determine the gain of the analog
front end.

The settling time of the analog front end meets speed re quirements, however, if the amplifi er
is saturated i t may need more time to recover. T his can cause di stortion at the input sig nal to
the A/D converter. It is recommended that amplifier saturation be avoided by using a low
gain and attenuating the input signal whenever possible.

5.4 Scan List Register

One entry to the scan list register contains a 16-bit word or two 8-bit bytes. It specifies the
internal channel and gain selection in the high byte or MSB, and the external channel and gain
selection in the low byte or LSB, in addition to other control and configuration settings. The
external selections are used for expansion card channels (up to 256), while the internal
selections are for channels on board the DAQP card. Expansion cards are not included as part
of the DAQP seri es data acquisiti on system, however, they can be purchased se parately from
your vendor.

The number of entries in the scan list ranges from 1 to 2048. There are no dependencies
implied among the entries of the scan list. The user may choose any valid gain combination
for any channel, internal or external. Channels can be scanned in any order required, repeated
or not, with the same or different gain for each entry.

The scan list has to be f lushed before programming to g uarantee the integrity of each entry .
There must be an even number of bytes programmed into the scan list, with the low byte
sitting at an even offset followed by the high byte, otherwise the channel scan result will be
unpredictable.

It is strongly recommended that the differential/single-ended control bit (bit 14, MSB) be
programmed the same for all the entries in the scan list. Single-ended configuration should be
selected if there are expansion cards connected to the DAQP card. The synchronous sample
hold bit (bit 6, LSB) is reserved for expansion cards.

The fir st channel flag ( bit 7, LSB ) has to be set for the first (and ONLY the first) entry of the
scan list. Th e DAQP card hard ware relies on thi s bit to tell the end (or the start) of the scan.
During normal operations, the DA QP card starts one scan when tri ggered, (software or TTL
trigger i n one- shot mode or sampling pulse tr i g g er s f r om the pace r clock in conti nuous mod e ) .
During the scan, each entry in the scan list will be processed until it finds the entry that has
the first channel flag set to ‘1’. The hardware then stops scanning and waits for the next
trigger. The scan will continue indefinitely if none of the list entries has the flag set to ‘1’. On
the other hand, if more than one entry has the flag set to ‘1’, the scan list will then be chopped

into pieces. Each piece will require a trigger to be scanned. Should the flag be set to ‘1’ on an

entry other than the first, a “starting offset” will be introduced to the scan list. Channel

DAQP-12/12H/16 Users Manual 24

scanning will start from the entry with the flag set to ‘1’, run through the list, turn around and
end at the one before it. Although this may be useful for diagnosis or special applications, it is
the abnormal way of setting the first channel flag and should be avoided unless absolutely
necessary.

5.5 Trigger Circuit

The DAQP card can be trigger ed by software, an external T TL signal or the pacer clock. F or
the external TTL trigger, an active trigger edge can be selected for either the low-to-high or
high-to-low transition.

In one-shot trigger mode, one trigger, either internal or external, will start one and only one
scan of all channels specified in the scan list. (The pacer clock has no effect in this mode
although it is good practice to program the pacer clock with a divisor greater than 2).
Multiple scans can be initiated by issuing multiple triggers.

In continuous trigger mode, the software or TTL trigger initiates a series of scans. The first
scan begins immediately on receiving a trigger, while the rest are carried out each time the
pacer clock fires. The process will continue until an A/D stop command is received.

If the internal trigger (or software trigger) is selected, the trig/arm command will serve as a
trigger w hen received by the DAQP card . For the external tri gger source, the same command
will be taken as an arm command, which arms the DAQP card so that the first proper trigger
edge following the arm command will serve as the trigger. Unexpected edge transitions
during the trigger source configuration are totally ignored if the DAQP card is not armed.

5.6 A/D Converter and Data FIFO

The DAQP ca rd alw ays assumes a bipol ar input range of ±10V if the gain i s one. The output
data format will always be in 2's complement (and left justified for 12-bit versions). The data
acquisition time of the A/D converter is 2µs while it’s conversion time is no more than 8µs.
The output of the A/D converter is fed into a data FIFO providing data buffering of up to
2048 samples. The A/D converter, once triggered, will complete conversion for every analog
input channel in the scan list at the specified scan speed and then feed the results into the data
FIFO. In between scans, the DAQP card waits until another trigger is received (one-shot
mode) or the pacer clock fires (continuous mode).

The data FIFO has two progr ammable thr esholds, one for almost full and the other for almost
empty. The DAQP card uses the almost full threshold and ignores the other one. The data
FIFO should always be flushed prior to using the arm/trig command to start data acquisition.
When the FIFO is flushed or emptied by the host reading its content, the FIFO empty flag will
be set. As long as there are samples left in the data FIFO, the empty flag will be cleared.
When the number of data sa mples in the FIFO b ecomes greater than the progr ammed almost
full threshold, the almost full flag is set. When the number becomes less than or equal to the
specified almost full threshold, the flag will be cleared. On power up or reset, the threshold is

defaulted at 7 bytes to full (3.5 samples). Correct setting of the threshold will help achieve

optimal performance of the card.

DAQP-12/12H/16 Users Manual 25

When the FIFO is full, the full flag will be set, and no more samples can be written into the
FIFO. At the end of each scan, the DAQP card will set the data lost flag if the data FIFO is
already full. Thi s flag is not set b efore or duri ng the scan, but a t the end of it. Once the data
lost flag is set, it will not clear until the status register is read.

5.7 Interrupt and Status

The DAQP card has two interrupt sources, the end-of-scan (EOS) interrupt and the FIFO
threshold interrupt. The control register (base + 2, write only) has two bits to enable or
disable either one of the interrupts independently. However, it is strongly recommended that
the two interrupts be used exclusively.

When the EOS interrupt is enab led, an interrupt is sent to the host at the end of each scan of
the channel list. If there is only one channel in the scan list, the EOS interrupt is reduced to an
EOC (end-of-conversion) interrupt. The FIFO threshold interrupt, when enabled, is sent to the
host when the almost ful l fl ag i s set. The host then uses the “str ing input” instr uction to move
a block of samples from the FIFO. The EOS and FIFO threshold event bits in the status
register (base + 2, read only) and will be set whenever the corresponding event happens.
These bits can be used for indica ting the source of the interr upt. Once set, the event bits wil l
not be cleared until the host reads the status register.

5.8 Digital I/O

The DAQP ca rd has one dig ital in put port (ba se + 3, read onl y) of four b its (bi ts 0-3) and one
digital output port (base + 3, write only) of four bits (bits 0-3). The output port is latched,
while the input port is not. Four input lines are connected to the digital input port, each
representi ng one bit in the port. When read ing the di gital i nput port, the CURRENT sta tus of
the digital input lines are returned to the host.

All four input lines are shared with other functions. Bit 0 is shared as the external trigger
input, while bit 2 is shared as the external clock input. Bits 1 and 3 are taken over as the
external gain selection lines if there is an expansion card(s) connected and the expansion bit in
the control regi ster is set to ‘1’. In this case, the digi tal output lin es are drive n by the exte rnal
channel selection bits of the current scan list entry. Otherwise, they will be connected to the
latched bits 0-3 of the digital output port. The current status of the digital input lines will
always be returned when the host reads the digital input port regardless of whether the lines
are shared or not.

5.9 A/D State Machine

The DAQP card has an internal state machi ne that controls A/D oper ation. The state machine

DAQP-12/12H/16 Users Manual 26

defaults to S0 afte r power up or rese t. The normal sta te flow w ould be fi rst S0 to S3, ini tiated
by a scan list (queue) flush command (RSTQ). Then the queue must be programmed by
writing into the queue (base + 1). With the queue being programmed, the next step is moving
the state machine from S3 back to S0. This is done by issuing a flush data FIFO command
(RSTF), which sets up the gain and channel selections for the first channel in the scan list and
then waits f or a tri gger to start the sca n. When the trigger (ADCLK) comes, the state machine
moves from S0 to S1 and then A/D conversion is started. The state machine will wait at S2
until the conversion is completed. It then moves to S4, where the A/D conversion result is
written into the data FIFO. The scan ra te is determine d by the time the state machine moves
from S1 to S4, which can be programmed as either 10, 20 or 40 µs. If there are more channels
left in the scan list, the state machine will skip to S1 for another conversion loop. Otherwise it
will return to S0, waiting for another trigger (or a sampling pulse from the pacer clock if in
continuous trigger mode). Any time during data acquisition, an A/D stop command will stop
the data acquisition by moving the state machine back to S0.

ADCLK (trigger)

RSTF
data
FIFO
flush

S0

RSTQ

<

>

scan
list flush

S1

<

S3

Figure 5-3. Transition Diagram of A/D Conversion Process

It is important that the sequence of S0-S3-S0 be followed as described above. The user must
issue two commands to the DAQP card: the flush scan list command (RSTQ) and the flush
data FIFO command (RST F). This guarantees that the scan list and the data FIFO are flushed
properly for the expected data acquisition. Once the flush data FIFO command is issued, the
DAQP card will prepare the first channel in the scan list and then return to state S0 waiting for
the first trigger. Anytime the data FIFO is flushed, the default threshold setting will be
restored (7 bytes to full) by the hardware. The data FIFO threshold should always be
programmed after flushing if the required threshold is different from the default threshold.

Wait (A/D conve r si on)

S2

Channels
remaining

S4

< Scan list comple ted

6. PCMCIA Interface

Card Configuration and Status Register

R/W

0x8002

Configuration Option Register

R/W

0x8000

Description

Access

Offset

DAQP-12/12H/16 Users Manual 27

The information in this section is provided for those who need low level PCMCIA interface
details for the DAQP card. The client driver or enabler that comes with the DAQP card will
be sufficient for most applications.

The DAQP card performs data acquisition for all host computers equipped with a version 2.10
compliant PCMCIA i nterface. The D AQP card has a form f actor of type II (5 mm thick). The
card is highly flexible with respect to addressing and interrupt level use. It can be configured
either as a memor y only i nterf ace or a s an I/O inter face a nd can b e power ed up or d own wi th
the help of PCMCIA card and socket services. T he D AQP car d pr ovi des a single inter r upt that
can be routed to any system interrupt via the PCMCIA socket controller.

There are two sets of reg isters on the D AQP card : the prog ram reg ister s and the confi gura tion
registers.

Program regi sters f all under progra m control and bel ong to the DAQP card . T he I/O l ocation
of these regi sters is control led by the PCMCI A socket config uration and b y the contents of the
PCMCIA configuration registers.

The configuration registers are as those defined in the PCMCIA 2.10 specification and are
located in the DAQP card’s confi guration space at offset 8000H. T he configuration space al so
contains the Card Information Structure (CIS) which is located at offset 0000H. The CIS
memory contains information about the DAQP card as defined by the PCMCIA 2.10
specification. It is recommended that configuration and power up/down control of the DAQP
card be car ried out through the standard card and socket servi ces although an enabl er can be
used to complete these tasks.

Two PCMCIA configuration registers are supported by the DAQP card, (see Table 6-1): the
Configuration Option Register and the Card Configuration and Status Register.

Table 6-1. PCMCIA Configuration Registers

6.1 Configuration and Option Register (COR)

Bits 7 and 6 of the Configura tion Option Regi ster are d efined by the PCMCIA stand ard as the

000000 = Memory mode

Index Bits

5-0

1 = Level mode interrupt

LevlReq

6

1 = Put the card into reset state

SRESET

7

Description

Name

Bit

Reserved as ‘0’

Reserved

0

1 = Interrupt pending

Intr11 = Power down mode

PwrDwn

2
Reserved, all ‘0’ when writing and reading

Not Used

7--3

Description

Name

Bit

DAQP-12/12H/16 Users Manual 28

SRESET and the LevlREQ Bits. A ‘1’ written into the SRESET bit puts the card in reset state,
while a ‘0’ moves i t out of r eset state. I n reset state, it be haves as i f a har d w ar e r eset is received
from the host. The LevlREQ bi t controls the type of interrupt sign al generated by the DAQP
card. Setting the Configuration Index bits to ‘0’ makes the DAQP card a memory only card
(accessed only by memory read /write operations), while setting it to ‘1’ enable s the card for
standard I/O. Table 6-2 lists the COR bit definition.

0 = Get out of reset state

0 = Edge mode interrupt

000001 = I/O mode

Table 6-2. COR Bit Definition

6.2 Card Configuration and Status Register (CCSR)

The DAQP card uses two bits i n this register. W hen bit 1 is set to ‘ 1’, it indic ates a pending
interrupt. The bit will remain as ‘1’ until the interrupt source is cleared. Bit 2 is used for
power down control. Setting a ‘1’ at this bit will put the card into power down mode, while a
‘0’ brings it back to full power mode. The remaining bits are not used.

0 = Full powered mode

0 = No interrupt pending

Table 6-3. CCSR Bit Definition

7. I/O Registers

Auxiliary Control Register

Write Only

base + 7

111

Pacer Clock, high byte

Write Only

base + 6

110

Pacer Clock, middle byte

Write Only

base + 5

101

Pacer Clock, low byte

Write Only

base + 4

100

Digital Output Register

Write

base + 3

011

Control Register

Write

base + 2

010
Scan List (Queue)

Write Only

base + 1

001

Data FIFO

Read/Write

base + 0

000

Register Description

Port Access

I/O Address

Address Lines

DAQP-12/12H/16 Users Manual 29

The DAQP card uses eight consecutive I/O locations within the system I/O address space.
The base address of the adapter is determined by the Client Driver or Enabler as discussed in
Chapters 3 and 4. The ei ght I/O locations are used by the D AQP card as summarized in the
following table.

(A2A1A0)

Read

Read

Table 7-1. DAQP Series Card Address Map

All registers are 8-bits wide and each is discussed in detail in the following sections.

Status Register

Digital Input Register

7.1 Data FIFO Register (base + 0)
Note:

register be accessed as a 16 bit word to guarantee integrity. The low byte (LSB or the least
significant byte) should always be accessed first, followed by the high byte (MSB or the most
significant byte).

Although the data FIFO register is 8 bits wide, it is strongly recommended that the

The data FIFO register is considered as the access port to the data FIFO, which holds up to
2048 data words of the A/D conversion results. The port is also used for programming the
data FIFO thresholds, as explained later in this section.

Two consecutive by tes should be rea d from or written into the port each time it is accessed.

D8D9D10

D11

D12

D13

D14

D15

MSB

D0D1D2D3D4D5D6

D7

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

--

Read data FIFO

Read

Run

1, data FIFO

3

Verify data FIFO threshold

Read

Run

0, threshold

2

Read data FIFO

Read

Idle

1, data FIFO

1

Verify data FIFO threshold

Read

Idle

0, threshold

0

512

1..1023

7

Almost Full

Irrelevant

Irrelevant

7

Almost Empty

Suggested Value

Threshold Range

Default

Threshold

DAQP-12/12H/16 Users Manual 30

The following table illustrates bit allocation.

LSB

Table 7-2. Data FIFO Register Bit Allocation

7.1.1 Data FIFO Operation Modes

Depending on the mode of operation, the 16-bit word read from or written into the register
has different meanings, as described in the following table.

OperationAccessA/DSelection BitMode

Write

Write

Write

Write

Table 7-3. Data FIFO Operation Mode

The “selection bit” is also called the “program/access” control bit, as defined in the auxiliary
control register (base + 7). Mode 0 is the FIFO program mode, under which the two
consecutive words (four bytes) written into the register address will set the almost full and
almost empty threshol ds (in b ytes). The first wor d specif ies the almost empty threshold, (not
used, can be set to anything), while the second word determines the almost full threshold.
The threshold shoul d b e set to a value f rom 1 to FIF O si ze mi nus 1. (D efa ult is set to 7 at re set
or power up). Refer to Table 7-4 for FIFO threshold settings.

Program data FIFO threshold

Write data FIFO (diagnosis)

Not allowed

Not allowed

Table 7-4. Data FIFO Threshold Setting

Mode 1 is FIFO test mode, in which data bytes will be written into the data FIFO and read

True

True

False

FIFO size (either 1024 or 4096)

False

True

False

Threshold to (FIFO size - 1)

False

False

False

1 to (Threshold - 1)

False

False

True

0

DAQP-12/12H/16 Users Manual 31

back from it. The FIFO flags (empty, almost full, and full) will change according to the data
bytes available in the data FIFO and the configured threshold.

Mode 2 should be avoid ed. The d ata bytes can not be written into the FIFO under this mode,
while the bytes read from the FIFO will be the same as in mode 0.

Mode 3 is data transfer mode. Data bytes will be written into the FIFO by the A/D converter.
The data byte read from the address is the first available byte in the data FIFO if it is not
empty. If the FIFO is empty then the most recent byte written into the FIFO will be returned.
The data F IF O r eg i ste r is read- onl y under this mode therefore the user cannot w r i te data bytes
into the data FIFO through I/O instructions.

7.1.2 Mode Setting

The FIFO operation mode setting is always initiated by the data FIFO flush command with the
access/program b it set to ‘0’ (bi t 0 at base + 7) befor e data acquisition is started. This will set
mode 0 (threshol d setti ng mode) . A fter the threshold is progra mmed or verif ied , set the bit to
‘1’ so the following read/write operation to the FIFO will be data access operation.

The DAQP card is in idle mode before it is triggered into run mode. For one-shot operation,
the DAQP card will be set to run mode after it receives the trigger signal. It will not return to
idle mode until the specified scan list is completed or an A/D stop command is received. For
continuous trigger operation, the DAQP card will stay in run mode after being triggered until
an A/D stop command is received.

7.1.3 FIFO Flags

When readi ng the registe r under mod e 1 or 3, the fi rst avail able d ata byte f rom the data FIF O
will be returned if it is not empty, otherwise the returned byte is not defined. The FIFO full
flag will be cleared after the data FIFO register is read provided there are no more data bytes
written into the FIFO by the A/D converter under mode 1 or 3. The same will happen to the
FIFO almost full flag if the data bytes available in the FIFO are less than the almost full
threshold. The FIFO empty flag will be set immediately after the last byte is read from the
FIFO. FIFO size is measured in bytes (4096). Table 7-5 lists the FIFO flag status.

EmptyData bytes in FIFO

Full

Table 7-5. Data FIFO Flag Status

FullAlmost

7.2 Scan List Queue Register (base + 1)

0000..1111 : channel 0..15

External channel

LSB

3-0

00/01/10/11 : 1/2/4/8 (or

External gain selection

LSB

5-4

for expansion cards (as SSH)

Reserved

LSB

6

Set to ‘1’ for the 1st entry in the list

Starting channel mark

LSB

7

0000..1111 : channel 0..15

Internal channel

MSB

11-8

00/01/10/11 : 1/2/4/8 or

Internal gain selection

MSB

13-12

1/0 : differential/single-ended

Analog input mode

MSB

14

as 0

Reserved

MSB

15

DAQP-12/12H/16 Users Manual 32

The Scan List Queue Register is considered the access port to the scan list queue which can
hold up to 2048 entri e s ( each has two bytes). E ach entry specifies an analog input channel and
it’s associated gain as well as other settings. The bit definition of an entry to the scan list
queue is explained in Table 7-6.

Note: Although the scan list queue register is 8 bits wide, it is required that the register be

accessed as a 16 bit word to guarantee integrity. The low byte (LSB or the least significant
byte) should always be accessed first, followed by the high byte (MSB or the most significant
byte).

ExplanationDefinitionByteBit

00/01/10/11 : 1/10/100/1000

selection

Set to ‘0’ for all the rest entries

1/10/100/1000)

selection

Table 7-6. Scan List Queue Entry Bit Definition

7.2.1 Scan List Queue Programming

The scan list queue must be programmed when the DAQP card is idle. Each queue entry
contains two b ytes as d escri bed above a nd the in tegri ty of the e ntry must be g uarante ed. (T he
scan list queue is write only). The queue should be flushed before writing into it. Refer to
section 7.7: Auxiliary Control Register for information on scan list queue reset. The first entry
of the queue should have bit 7 (LSB) set to ‘1’ as the first channel mark. For the remaining
entries, set the b it to ‘0’ . The synchronous sample hold b it ( LSB ) is not used by D AQP ca rd. It
is reserved for the expansion cards.

Example 1.

Table 7-7 lists the required queue entri es to specify a scan list of three single-ended internal

Select channel 7, gain 4

2700

0010 0111 0000 0000

3

Select channel 12, gain 4

2C00

0010 1100 0000 0000

2

Select channel 0, gain 2, 1st

0180

0001 0000 1000 0000

1

Select channel 7, gain 1

4700

0100 0111 0000 0000

4

Select channel 6, gain 1

4600

0100 0110 0000 0000

3

Select channel 1, gain 1

4100

0100 0001 0000 0000

2

Select channel 2, gain 1, 1st

4280

0100 0010 1000 0000

1

Explanation

Hex

Binary

Entry

DAQP-12/12H/16 Users Manual 33

channels: 0, 12, and 7; with a gain of 2 for channel 0 and a gain of 4 for channels 12 and 7:

ExplanationHexBinaryEntry

Table 7-7. Scan List Queue Programming Example 1

Example 2.

Table 7-8 lists the required queue entries to specify a scan list of 4 differential internal
channels: 2, 1, 6 and 7; with gain of 1 for all channels:

Table 7-8. Scan List Queue Programming Example 2

7.2.2 Channel Configuration

Bits 5 and 4 (LSB) in a queue entry specify the gain of the external expansion card for the
external channel selected by bits 0-3 of the same byte. Each expansion card has up to 16
channels (0, 1, 2, ..., 15). Each channel may have a gain of 1, 2, 4 or 8 (DAQP-12/16) or 1, 10,
100 or 1000 (DAQP-12H). If there is no expansion card for the internal channel specified then
the external channel and gain selection in the LSB will be ignored. However, the first channel
mark on bit 7 should always be properly set. The internal channel is selected by bits 8-11
(MSB), while the internal gain for the selected channel is specified by bit 12 and 13 (MSB).
The internal gain can only be 1, 2, 4 or 8. Bit 14 (MSB) determines whether the input is
differential (1) or single-ended (0). There are 16 singled-ended channels, but only 8
differential channels. This bit should always be set to ‘0’ if the selected internal channel is
connected to an expansion card because the ex pansion channels are always single- ended. Bit
15 (MSB) is not used by the DAQP card and should be set to ‘0’.

7.2.3 Analog Input Offset Correction

The input to the A/D converter is shorted to ground if bit 14 (MSB) is set to ‘1’ while the
internal channel selection bits 8-11 specifies an internal channel of 8 or above. This can be
used for analog input offset correction.

7.3 Control Register (base + 2, write)

0/1 : rising/falling

Trigger edge

0

0/1 : internal/external

Trigger source

1

0/1 : one-shot/continuous

Trigger mode

2

0/1 : disable/enable

FIFO interrupt

3

0/1 : disable/enable

EOS interrupt

4

0/1 : disable/enable

Expansion mode

5

00 : External clock

Pacer clock

7-6

DAQP-12/12H/16 Users Manual 34

The control reg ister specif ies the pacer clock source and pr e-scaler , expansi on mod e, inter rupt
enable control and trigger control. Table 7-9 lists the control register bit definition.

ExplanationFunctionBit

source and
pre-scaler

Table 7-9. Control Register Bit Definition

7.3.1 Clock Source

If selected, the external cl ock source must not exceed 5 MHz with a minimum pulse wid th of
200 ns. The external clock frequency can be as low as necessary or even a DC signal and there
is no limit on maximum pulse width.

01 : Internal, 5 MHz
10 : Internal, 1 MHz
11 : Internal, 100 kHz

7.3.2 Expansion Mode

Bit 5 must b e se t to ‘1 ’ if there is an ex pansion car d(s) conne cted to the DA QP card. All of the
digital output lines (bits 0-3) will be used for external channel selection and two of the four
digital input lines (bit 1 and 3) will be used for external gain selection.

7.3.3 Interrupt Enable

Bits 4 and 3 are used for interrupt enable control. The end-of-scan (EOS) interrupt will be
enabled (disabled) by setting bit 4 to ‘1’ (‘0’). Setting bit 3 to ‘1’ (‘0’) will enable (disable) the
data FIFO interrupt when the A/D data available in the FIFO passes the almost full threshold.
Since the EOS and FIFO threshold events are latched into the status register, temporarily
disabling and then re-enabling the interrupt will not cause an interrupt to be lost as long as
there are no repeated events during the time the interrupt is disabled.

7.3.4 Trigger Mode/Source

0/1 : false / true

Data FIFO empty

0

0/1 : false / true

Data FIFO almost full

1

0/1 : false / true

Data FIFO full

2

0/1 : no / yes

FIFO threshold event

3

0/1 : no / yes

End of scan event

4

0/1 : no / yes

Data lost event

5

0/1 : no / yes

Triggered status

6

0/1 : busy / idle

Scanning status

7

DAQP-12/12H/16 Users Manual 35

Bit 2 determines the trigger mode and is set to ‘0’ for one-shot mode and ‘1’ for continuous
trigger mode.

Bit 1 specifies the trigger source and is set to ‘1’ for external trigger (TTL trigger) and ‘0’ for
internal tr igger (softw are trigge r). When set to internal tri gger, the tri gger edge sele ction can
be ignored. The external trigger signal shares the same pin on the interface connector with
digital input bit 0.

7.3.5 Trigger Edge

Bit 0 selects the external trigger edge. To chose the falling edge of the external trigger signal,
set this bit to ‘1’, otherwise the rising edge is selected. Edge selection is ignored if the internal

trigger source is specified.

7.4 Status Register (base + 2, read)

The status register is read only and shares the same offset as the control register. It reports
data FIFO flag, interrupt and A/D conversion status. Table 7-10 lists the status register bit
definition.

ExplanationStatusBit

Table 7-10. Status Register Bit Definition

Bit 7 shows the scan status and is set to ‘0’ when the DAQP card is scanning the input
channels specified by the scan list and then ‘1’ upon scan completion. ‘1’ at bit 6 indicates the
DAQP card has been triggered and is acquiring data (busy). ‘0’ at bit 6 indicates the card is
waiting for a trigger (idle). Bits 3, 4 and 5 are the event latches. When an event is detected,
the correspondin g bit is set to ‘1’ until the host reads the status reg ister which then clears al l
event bits to ‘0’. Bits 5, 4 and 3 are used for data lost, EOS and FIFO threshold events
respectively. When the corresponding interrupt is enabled a ‘1’ in bits 3 or 4 will cause an
interrupt. Bits 0, 1 and 2 are the data FIFO flags.

7.5 Digital I/O Register

Ignored

Reserved as all ‘0’

4-7

Ignored, the four output lines will be

Digital output bits 0-3

0-3

Expansion Mode

Normal Mode

Bits

All ‘0’

All ‘0’

4-7

External gain select, high bit

Digital input bit 3

3

The same as in normal mode

Digital input bit 2, also serve as external clock

2

External gain select, low bit

Digital input bit 1

1

The same as in normal mode

Digital input bit 0, also serve as external trigger

0

Expansion Mode

Normal Mode

Bit

DAQP-12/12H/16 Users Manual 36

7.5.1 Digital Output

The four digital output lines share the same pins on the interface connector as the four
external channel selection bits. When using an expansion card(s), bit 5 of the control register
(base + 2) should be set to ‘1’ so that the four digital output lines will be driven by the external
channel selection bits from the scan FIFO. If bit 5 of the control register is set to “0”(default
after reset) , then the f our output line s are d riven b y the val ues in bits 0 to 3 la tched d uring the
last write operation. In other words, the digital output bits are valid only when the DAQP
card is NOT in expansion mode. Table 7-11 lists the digital output register bit definition.

driven by the external channel
selection bits in the scan list FIFO

Table 7-11. Digital Output Register Bit Definition

7.5.2 Digital Input

Two of the dig ital input l ines are shared wi th the external tri gger (bit 0 ) and the external clock
(bit 2). The other two line s ar e used for external ga i n contr ol in expansi on mod e (if bit 2 of the
control register is set to ‘1’ ). The digital input lines are not latched.

Although the digital input lines are also used as external trigger, external clock and the
external gain selection; the current status of these lines will always be returned when reading
the port. T he line status does not af f ect the digi tal output r e g i ster . It’s contents cannot b e r e ad
back directly, even though they share the same port offset with the digital input register.
Table 7-12 lists the digital input register bit definition.

s

Table 7-12. Digital Input Register Bit Definition

7.6 Pacer Clock (base + 4, + 5, + 6)

DAQP-12/12H/16 Users Manual 37

The pacer clock is actually a 24-bit auto-reload frequency divider. It contains a 24-bit divisor
register, a 24-bit counter, an inter nal clock pre-scaler and a clock source multiplex er. Figure
7-1 shows the pacer clock block diagram.

10 MHz

Divide by 2

24 bit Counter

Divide by 10

Pacer Clock
Output

Divide by 100

External Clock Input

Figure 7-1. Pacer Clock Block Diagram

The clock source selection is specified by bits 6 and 7 in the control register (base + 2). The
24-bit register occupies 3 ports, in which the low byte is located at base + 3, the middle byte at
base + 4 and the high byte a t base + 5. All three reg isters are wri te only. The pacer clock w ill
not generate a clock pulse output until it is trigg ered (either by an internal software trig ger or
an external TTL trigger signal in continuous mode only). In continuous mode, the trigger will
serve as the first clock output pulse, and load the counter from the register . The counter will
count down the input clock pulse until it is zero and then an output clock pulse is generated
and the counter is reloaded. Pacer clock output will continue until the DAQP card receives the
stop command which is generated by writing a ‘1’ to bit 4 of the auxiliary control register
(base + 7).

The clock rate is determined as follows: Rate = Source Frequency / (Divisor Count + 1) .

Example 1

24 bit Register

If an internal clock source i s applied at 100 kHz (control register bits 7, 6 = 11) and the divi sor
count is 49, then the pacer clock output frequency = 100 kHz / (49 + 1) = 2 kHz.

Example 2

If an external clock source is applied at 120 kHz (control register bits 7, 6 = 00) and the divisor
count is 39, then the pacer clock output frequency = 120 kHz / (39 + 1) = 3 kHz.

7.7 Auxiliary Control Register (base + 7)

1 = data access, 0 = program

Data FIFO program/access

0

00 = 100, 01 = 50, 10 = 25 (kHz)

Scan rate selection

2-1

as ‘0’

Reserved

3

1 = stop, 0 = no action

Stop A/D command

4

1 = flush, 0 = no action

Flush scan list command

5

1 = flush, 0 = no action

Flush data FIFO command

6

1 = send trigger/arm, 0 = no action

Trigger/Arm command

7

DAQP-12/12H/16 Users Manual 38

The auxiliary control register is used to send control commands to the DAQP card. It also sets
the data progra m/access mode for the data FIFO. The command bits (bits 4 to 7) are actually
“monostable” or self-cleared after the specified command function is completed. They do
NOT require clearing. The data FIFO program/access bit is latched each time it is written.
Table 7-13 lists the auxiliary control register bit definition.

ExplanationFunctionBit

threshold

Table 7-13 . Auxiliary Control Register Bit Definition

7.7.1 Trigger/Arm Command

If the trigger source is internal (software trigger), writing a ‘1’ to bit 7 will send a trigger to the
DAQP card and start the A/D conversion process. If the trigger source is external (TTL
trigger), writing a ‘1’ to bit 7 will serve as an ARM command. The ARM command tells the
DAQP card to look for the specified external trigger edge from the moment the ARM
command is r ece i ve d . Never i ssue the ARM command tog ether with the A/D stop command.
The ARM command initiates data acquisition and the A/D stop command terminates it.

7.7.2 Flush Scan List Queue Command

The scan list queue must be flushed before it can be programmed. This command should be
issued before the flush data FIFO command. The queue may have up to 2048 word entries,
each containing two bytes. It is the user’s responsibility to guarantee the integrity of the
entries.

7.7.3 Flush Data FIFO Command

The data FIFO should be flushed before data acquisition is initiated by the trigger/arm
command, but not until after the scan list has b een configured . The flush command may also
be followed by FIFO threshold programming. After the FIFO is flushed, the FIFO empty flag
will be set to ‘1’ and the almost full and full flags reset to ‘0’. Anytime the data FIFO is
flushed, the default threshold setting will be restored (7 bytes to full) by the hardware. The
data FIFO threshold should always be programmed after flushing if the required threshold is
different from the default one.

7.7.4 A/D Stop Command

0..15

High byte of the almost full threshold

3

0..255

Low byte of the almost full threshold

2

0..15

High byte of the almost empty threshold

1

0..255

Low byte of the almost empty threshold

0

Valid Range

Definition

Byte

DAQP-12/12H/16 Users Manual 39

Once data acquisition is initiated by the trigger/arm command, it can only be stopped by
receiving the A/D stop command. The A/D stop command should b e issued as soon as the
required data points are collecte d to prevent data FIFO overfl ow. Data FIFO overfl ow is the
only flag that indicates lost data during the acqui sition process. Without the stop command,
the A/D can continue to run, filling the data FIFO. When the FIFO is full, it will ignore data
samples coming from the A/D converter.

7.7.5 Data FIFO Program/Access Control

The A/D data FIFO has two programmable thresholds (almost empty and almost full) and
two associated flags. The almost empty threshold and flag are not used. By default, the
thresholds ar e set to 7 bytes (7 to ful l and 7 to empty) when reset, powered up or anytime the
FIFO is flushed. It can be programmed to any value between 1 and FIFO size - 1 (in bytes).

To program the FIFO threshold, make sure the A/D has been stopped. Set this bit to ‘0’ by
writing an all ‘0’ byte to the auxiliary control register. Then send an A/D FIFO flush
command with the same bit setti ng by writing a byte of 40H to the same registe r. This will
put the FIFO into program mode. The following read/write operation will be directed to the
threshold registers instead when accessing the data FIFO at base +1. The 4 byte threshold
setting should be written into the data FIFO by doing four consecutive write operations.
Optionally, the threshold setting can be read back for verificati on by doing four consecutive
read operations. Table 7-14 lists the 4 byte threshold setting format.

No.

Table 7-14. Data FIFO Threshold Setting

After the thre sholds are programmed , set the access control b it to ‘1’ b y writing a byte of 0 1H
into the auxiliary control register. This will make the following read/write operation access
the data bytes i n the FIFO in stead of it’ s thresholds. It is recommend ed that the access control
bit be set to ‘1’ when sending other command s (flush scan li st, stop A/D or trig/arm) to the
DAQP card by writing into the auxiliary control register. A useful tip for safe operation is to
set the bit to ‘0’ only when flushing and programming the FIFO thresholds. Although the
almost empty threshold i s never used, i t must be programmed because the f our configur ation
bytes must be accessed as an entire entity.

7.7.6 Scan Rate Selection

DAQP-12/12H/16 Users Manual 40

Depending on the input mode and the gain selection, the analog front end may have different
settling time s. In ord er to g i ve the best per f or mance , the DAQP card al lows the user to choose
three different scanning rates by setting bit 2 and bit 3 while the start A/D command is
issued. The d efault scanning rate is 100 kHz (bi ts 2-3 set to ‘00’). A scan rate of 50kHz can be
selected b y setting the bits to ‘01’ and 25 kHz b y setting them to ‘10’. Setting the bits to ‘ 11’
gives the same result as ‘01’.

It is recommended that the scan rate setting be issued in conjunction with the trigger/arm
command and kept unchanged during data acquisition. For example, writing 81H to the
auxiliary control register will start data acquisition with the scan rate set to 100 kHz, (use 83H
for 50 kHz and 85H for 25 kHz).

8. I/O Connections

The DAQP card is fitted wi th a 32-pin shielded connector. See Figure 8-1 for pin assignments.

DAQP-12/12H/16 Users Manual 41

A mating connector and shield are available from Hirose for the D-32 output connector.

32

303

25

20

15

10

Ch0
Ch0 (-)/ Ch8

Ch1
Ch1 (-)/ Ch9

Ch2
Ch2 (-)/ Ch10
Ch3
Ch3 (-)/ Ch11

Ch4
Ch4 (-)/ Ch12

Ch5
Ch5 (-)/ Ch13

Ch6
Ch6 (-)/ Ch14

Ch7
Ch7 (-)/ Ch15
GND
Full Power

SSH (Sync Sample Hold)
DI 0/ External Trigger

DI 1/ GS 0 (Ext Gain Select)
DI 2/ External Clock

DI 3/ GS 1 (Ext Gain Select)
DO 0/ CS 0 (Ext Channel Select)

DO 1/ CS 1 (Ext Channel Select)
DO 2/ CS 2 (Ext Channel Select)

DO 3/ CS 3 (Ext Channel Select)

5

GND
GND

GND
GND

Reserved

SERIES

CARD

DAQP

Figure 8-1. DAQP Series Card Hirose-32 Output Connector

9. Optional Accessories

DAQP-12/12H/16 Users Manual 42

9.1 UIO-37 Screw Terminal Block

For applications requiring discrete wiring connections, the UIO-37 terminal block provides a
simple way of connecting signals to the DAQP card. The D37 connector is availab le in either
male or femal e and has tw o rows of screw te rmina ls. T he fi rst row is number ed f rom pin 1 to
pin 19 and the second row from pin 20 to pin 37, (see Figure 9-1).

D37 Connector (Male or Female available)

Screw Terminal Connections

Figure 9-1. UIO-37 Terminal Block

Ground

9.2 CP-DAQP Cable Assembly

DAQP-12/12H/16 Users Manual 43

An optional cable assembly, part number CP-DAQP, is available for converting the DAQP
card’s Hirose 32- pin I/O connector to a standard D -37 male connector. The D -37 connector is
compatible with the P-1 connector of the Keithley DAS-1600®. Figure 9-1 illustrates accessory
connections.

DAQP Series Card

UIO-37

Hirose 32

Figure 9-1. DAQP Series Card Accessory Connection

D37

CP-DAQP

Figure 9-3 illustrates the D-37 connector pin assignments for the CP-DAQP and UIO-37.

DAQP-12/12H/16 Users Manual 44

GND
Ch0- / Ch8
Ch1- / Ch9

Ch2- / Ch10
Ch3- / Ch11
Ch4- / Ch12
Ch5- / Ch13
Ch6- / Ch14
Ch7- / Ch15

FullPower

Reserved

N/C

N/C
DI1 / GS0
DI3 / GS1

DO1 / CS1
DO3 / CS3

N/C

N/C

19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

37

Ch0+ / Ch0

36

Ch1+ / Ch1

35

Ch2+ / Ch2

34

Ch3+ / Ch3

33

Ch4+ / Ch4

32

Ch5+ / Ch5

31

Ch6+ / Ch6

30

Ch7+ / Ch7

29

GND

28

GND

27

Reserved

26

SSH

25

DI0 / Ext. Trigger

24

DI2 / Ext. Clock

23

DO0 / CS0

22

DO2 / CS2

21

N/C

20

N/C

Figure 9-3. CP-DAQP/UIO-37 D-37 Pin Diagram

Table 9-1 lists cable mapping for the CP-DAQP Hirose-32 to D37 connector.

DAQP-12/12H/16 Users Manual 45

DescriptionNameD-37Hirose-32

Channel 0Channel 0 (+)3732
A/D input, differential / single-endedChannel 8Channel 0 (-)1831
A/D input, differential / single-endedChannel 1Channel 1 (+)3630
A/D input, differential / single-endedChannel 9Channel 1 (-)1729
A/D input, differential / single-endedChannel 2Channel 2 (+)3528
A/D input, differential / single-endedChannel 10Channel 2 (-)1627
A/D input, differential / single-endedChannel 3Channel 3 (+)3426
A/D input, differential / single-endedChannel 11Channel 3 (-)1525
A/D input, differential / single-endedChannel 4Channel 4 (+)3324
A/D input, differential / single-endedChannel 12Channel 4 (-)1423
A/D input, differential / single-endedChannel 5Channel 5 (+)3222
A/D input, differential / single-endedChannel 13Channel 5 (-)1321
A/D input, differential / single-endedChannel 6Channel 6 (+)3120
A/D input, differential / single-endedChannel 14Channel 6 (-)1219
A/D input, differential / single-endedChannel 7Channel 7 (+)3018
A/D input, differential / single-endedChannel 15Channel 7 (-)1117
A/D input, differential / single-endedGND2916
1/0 : Full power / Power downFullPower (org. D/A 0 ref. in)1015
Synchronous Sample HoldSSH (org. D/A 1 ref. in)2614
External trigger (same as in DAS-16)Digital in bit 0 (shared)2513
External gain, LSB (expansion mode)Digital in bit 1 (normal mode)612
External clock (org. DAS-16 Ctr 0 Gate)Digital in bit 2 (shared)2411
External gain, MSB (expansion mode)Digital in bit 3 (normal mode)510
External channel bit 0 (expansion mode)Digital out bit 0 (normal239
External channel bit 1 (expansion mode)Digital out bit 1 (normal48
External channel bit 2 (expansion mode)Digital out bit 2 (normal227

External channel bit 3 (expansion mode)Digital out bit 3 (normal36
GND285
GND284
GND193
GND192

D/A output channel 1Reserved271

Table 9-1. DAQP Series Card Cable Mapping

10. Specifications

DAQP-12/12H/16 Users Manual 46

A/D Converter 12-Bit Version 16-Bit Version

Acquisition + Conversion 2 ms + 8 ms 2 ms + 8 ms
Monotonicity No missing codes No missing codes
Integral linearity error ± 1 LSB ± 3 LSB
Differential linearity error ± 1 LSB +3/-2 LSB
Full scale error ± 0.5 % ± 0.5 %
Aperture delay 40 ns 40 ns

Analog Input

Number of input channels 8 differential / 16 single-ended, expandable to 256
Input range ±10, ±5, ±2.5, ±1.25V (DAQP-12/DAQP-16)

±10, ±1, ±0.1, ±0.01V (DAQP-12H)

Programmable gain 1, 2, 4, 8 (DAQP-12/DAQP-16)

1, 10, 100, 1000 (DAQP-12H)
Maximum over-voltage ±30 V
Input impedance 100 MW (DC)

A/D Miscellaneous Specifications

Data FIFO depth 2048 samples
Scan list length 2048 entries
Scan speed 10 ms, 20 ms, 40 ms
Trigger source Internal (Software) / External (TTL)
Trigger mode Continuous / One-shot
External (TTL) trigger 0.8 V (low) / 2.2 V (high), Rising / Falling edges

Latency to A/D scan < 1 ms
Sampling rate 0.006 Hz to 100 kHz (with internal clock source)
External clock rate DC - 5 MHz

Digital I/O

Digital input channels 4 (no latch)
Digital output channels 4 (latched)
Maximum source current 0.5 mA
Maximum sinking current 2.5 mA
Minimum logic ‘1’ level 2.4 V
Maximum logic ‘0’ level 0.8 V

General Specifications

Power consumption 160 mA (full power), 40 mA (power down)
Operating temperature 0 °C to 50 °C
Storage temperature 0 °C to 70 °C
Humidity 0 to 95%, non-condensing
Size (cable not included) Standard PCMCIA type II
Weight 1.5 oz (for reference only)

DAQP-12/12H/16 PCMCIA
Data Acquisition System Users Manual
Version 2.40
January 22, 1999
Part No. 940-0092-240