Omega Products DAQ-1201 Installation Manual

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DAQ-1201/1202

Data Acquisition System

For 16 bit ISA compatible machines

Users Manual

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OMEGA ENGINEERING, INC., warrants this unit to be free of defects in materials and workmanship for a period of
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DAQ-1200 Series Users Manual 2

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DAQ-1200 Series Users Manual 3

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DAQ-1200 Series Users Manual 4

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Table of Contents

34

3.2.2 Differential Input

33

3.2.1 Single Ended Input

3.1 I/O Terminal Connection

3 Field Wiring

30

2.4.2 Changing Resources with Device Manager

28

2.4.1 Using the "Add New Hardware Wizard"

2.4 Installation under Windows 95/98®

27

2.3.7 Simultaneous Sample and Hold (SSH)

26

2.3.6 Timer0 and +15v/-15v Selection

25

2.3.5 ADC Clock Source

25

2.3.4 Timer0 Internal/External Clock Selection

24

2.3.3 Bipolar/Unipolar Output Range Selection

23

2.3.2 D/A Voltage Reference

21

2.3.1 I/O Base Address Selection

2.3 Configuring the DAQ-1201/1202

2.2 Auxiliary Connector Cable

2.1 Unpacking

2 Hardware Configuration and Initial Setup

1 Introduction

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DAQ-1200 Series Users Manual 5

1.1 Analog Input Features

1.2 Analog Output Features

1.3 Digital I/O

1.4 Counter / Timer

1.5 Interrupts

1.6 Software Support

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1.7 Power Requirements

1.8 Applications

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1.9 DAQ-1201/1202 Specifications

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8
9

91.1.1 D37 Connector Pin Diagrams ..........................................

101.1.2 Gain Selection Ranges ...............................................

101.1.3 Source and Trigger Mode for Analog-to-Digital Conversions ..............

111.1.4 Scan List (Scan FIFO) ................................................

121.1.5 Sampling Rate .....................................................

121.1.6 Simultaneous Sample Hold (SSH) .....................................

131.1.7 Data FIFO .........................................................

131.1.8 Direct Memory Access (DMA) Data Transfer ............................

13
14
14
15
16
16
17
18

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3.2 Analog Input Field Wiring

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3.3 Analog Output Field Wiring

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20
20
20
21

28

31
31
33

35

5.8 Analog Trigger Example

5.7 Remaining Base Addresses

5.6 Base + 6 (Digital I/O & Expansion Control)

5.5 Base + 5 (Interrupt Status Register)

5.4 Base + 4 (Status Register)

5.3 Base + 3 (Index Registers)

5.2 Base + 2 (Index Register)

5.1 Base + 0, 1 (Data/Scan FIFO)

5 Address Map

4.5 Timer/Counter

4.4 Digital I/O

4.3 Analog Output

4.2 Analog Input

4.1 Signal Flow

4 Theory of Operation

3.4 Timer/Counter Field Wiring

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DAQ-1200 Series Users Manual 6

36

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37
37
39
39
40
40

41
41
43
44
47
48
49
49
50

List of Figures and Tables

41

Table 5-1. DAQ-1200 Series Address Map

26

Table 2-3. Jumper J3 and J6 Configuration Options

24

Table 2-2. DA1 Output Voltage Ranges

24

Table 2-1. DA0 Output Voltage Ranges

10

Table 1-2. Bipolar Analog Input Voltage Ranges

10

Table 1-1. Unipolar Analog Input Voltage Ranges

37

Figure 4-1. DAQ-1201/1202 Signal Flow Block Diagram

36

Figure 3-6. Timer/Counter Field Wiring

35

Figure 3-5. Analog Output Field Wiring

34

Figure 3-4. Differential Analog Input Field Wiring

33

Figure 3-3. Single-Ended Analog Input Field Wiring

32

Figure 3-2. Connection of UIO-37 Terminal Blocks to DAQ-1200 Series Connectors

31

Figure 3-1. UIO-37 Screw Terminal Block

27

Figure 2-8. Simultaneous Sample and Hold Jumper

26

Figure 2-7. Timer0 and +15v/-15v Selection Jumpers

25

Figure 2-6. Internal/External Clock Selection Jumper

24

Figure 2-5. Bipolar/Unipolar Output Range Selection Jumper

23

Figure 2-4. D/A Voltage Reference Jumper

22

Figure 2-3. I/O Base Address Selection

21

Figure 2-2. I/O Base Address Selection Switches

20

Figure 2-1. Auxiliary Connector Cable

9

Figure 1-2. D37 Pin Diagrams

8

Figure 1-1. Component Layout Diagram

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DAQ-1200 Series Users Manual 7

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1 Introduction

The Omega DAQ-1201 and DAQ-1202 are cost effective high speed data acquisition boards

DAQ-1200 Series Users Manual 8

that plug into ISA expansion slots in IBMTM compatible personal computers. The DAQ-1200
series circui t board provi des 12-bit analog input, 3 2-bit digital input/output (I /O) and three
16-bit programmable timer/counters. E ach version of the DAQ-1200 seri es board has it's own
selectable gain range. The DAQ-1201 is software programmabl e for gains of 1, 10, 100 or 1000.
The DAQ-1202 is software programmable for gains of 1, 2, 4 or 8.

The maximum sampling rate of the DAQ-1201/1202 is 400kHz with digital or analog
threshold tri g g er i ng . The analog a nd d igital I/Os and the external trigger si gn al a r e conne cted
via a 37-pin "D" ty pe connector which is compatibl e with the Keithley Metr aByteTM DAS-1600.
An auxiliary D37 connector is employed to support an additional 24-bits of digital I/O.

The component layout diagram for the DAQ-1200 series circuit board is depicted in Figure
1-1.

DAQ-1200

DC/DC

AD7892

Auxiliary I/O

FIFO

FPGA3042

FIFO

FIFO

J3

PGA

J4
J5

8255A

8254

J2

SW1

Base I/O Addres s

1234

56

1234

J1

56

D/A

SW2

D/A

Figure 1-1. Component Layout Diagram

J6

1.1 Analog Input Features

The DAQ-1201/1202 supports 8 differential (positive and negative connections) or 16 single

DAQ-1200 Series Users Manual 9

ended analog input signals. The 16 single ended channels can be further expanded to 256
channels with the addition of an external analog multiplexer card and by using four of the
eight digital I/O lines for multiplexing control. Selection of either single ended or differential
analog inputs is software programmabl e. The DA Q-1201/1202 contains one high speed 12- bit
analog-to-digital converter (ADC) which can be configured to receive analog input voltages
within the range of -10v to +10V.

1.1.1 D37 Connector Pin Diagrams

Analog I/O connections are made through D37 connectors as shown in Figure 1-2.

Analog GND

-CH0

-CH1

-CH2

-CH3

-CH4

-CH5

-CH6

-CH7

DA0 Ref/SSH Out

DA 0 Out
Vref (-5V)

Power GND

IP1/GS0

IP3/GS1
OP1/CHS1
OP3/CHS3

Timer0 Out/-15V

+5V

Main I/O Connector

19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20

+CH0
+CH1
+CH2
+CH3
+CH4
+CH5
+CH6
+CH7
Analog GND
Analog GND
DA1 Out
DA1 Ref
IP0/Ext TTL Tr i g / Timer 1 C l k
IP2/Ti mer0 GATE
OP0/CHS0
OP2/CHS2
Timer0 Clk/+15V
Timer2 Out

Auxiliary Connector

DIG COM

+5V

DIG COM

DIG COM

DIG COM

DIG COM

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20

OP=Digital Output (4 bit port) DA=D/A Channel PA=Port A (bit 0-7)
CHS=Channel Select GS=Gain Select PB=Port B (bit 0-7)
IP=Digital Input

PC=Port C (bit 0-7)

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
DIG COM
+5V

Figure 1-2. D37 Pin Diagrams

Pins 11 through 18 and pins 30 through 37 are the available analog input channels. For
differential input, the eight available channels are numbered 0 through 7 and each channel
consists of one positive input (+CHx) and one negative input (-CHx). In single-ended
operation, the available channels are numbered 0 through 15. Inputs +CH0 through +CH7
correspond to channels 0 through 7 respectively. Inputs -CH0 through -CH7 correspond to
channels 8 through 15 respectively.

1.1.2 Gain Selection Ranges

The DAQ-1201 provides gains of 1, 10, 100 and 1000 versus the DAQ-1202, which provides

DAQ-1200 Series Users Manual 10

gains of 1, 2, 4 and 8. Tables 1-1 and 1-2 show the analog input unipolar and bipolar voltage
ranges for the respective gain range.

DAQ-1202 DAQ-1201

GainInput RangeGainInput Range

10 to 10V10 to 10V
20 to 5V100 to 1V
40 to 2.5V1000 to 100mV
80 to 1.25V1,0000 to 10mV

Table 1-1. Unipolar Analog Input Voltage Ranges

For a gain setting of 1, the 12-bi t resolution (4096 count) provides a least signif icant bit (LSB)
value of 2.44 mV in the 0 to +10V range.

DAQ-1202 DAQ-1201

GainInput RangeGainInput Range

1-10V to +10V1-10V to +10V
2-5 V to +5 V10-1 V to +1V
4-2.5 V to +2.5V100-100mV to +100mV
8-1.25 V to +1.25V1,000-10mV to +10mV

Table 1-2. Bipolar Analog Input Voltage Ranges

For a gain setting of 1, the 12-bi t resolution (4096 count) provides a least signif icant bit (LSB)
value of 4.88mV in the ±10V range.

1.1.3 Source and Trigger Mode for Analog-to-Digital Conversions

Upon initial power up, the DAQ-1201/1202 is in idle mode and no conversions are performed.
Conversions begin upon receiving a trigger. Three types of triggers are available: internal
trigger, external trigger and analog trigger. The internal trigger is initiated by a software
program, whereas the external trigger is connected through hardware. The analog trigger
occurs when the input signal exceeds a preset level set by the user. The preset level or
"threshold voltage" is generated by the output of the second D/A converter. A comparator
circuit sets of f the analog tr igger when the input signal rises above threshold voltag e. When
the trigger is initiated, the ADC immediately converts the analog signal into 12-bit digital data
which is stored in the data FIFO (First In First Out) register. In addition to varied triggering
sources, a triggering mode is available to select whether conversions and channel scans are
completed only once or multiple times. Trigger source and trigger mode types are software
selectable.

Triggering functions are summarized as follows:

DAQ-1200 Series Users Manual 11

(a) Trigger source :

y

Software trigger

y

External TTL trigger on falling or rising edge

y

External analog trigger with low to high or high to low transition

For the external TTL trigger, the default trigger pin on the main D37 connector is pin 25
(IP0/Trig).

(b) Trigger mode:

y

Single -- one scan/conversion for each trigger

y

Continuous -- continuous scanning/conversions for one trigger

1.1.4 Scan List (Scan FIFO)

The DAQ-1201/1202 scan list function performs high speed A/D conversions from channel to
channel. A scan FIFO regi ster is provided with a depth of 512 points that contains the channel
scan sequence and gain information. The scan FIFO must be programmed according to the
scan sequence desired . Scan sequence order can be random with channels configured in any
sequence desired. Channel sequences can also be repeated in an arbitrary order.

Each FIFO locati on occupies two bytes with the fi rst byte (low byte) storing the sequence for
extended channels beyond the on board 16 channels and their associated gain information.
The second byte (high byte) stores the sequence of on board channels and their gain
information. A bit in each location i n the FIFO (bit 7 of the high byte) is used to identify the
beginning channel . This bit, whi ch signals the completion of one scan cycl e, is registered as a
logic 1 for the beginning sequence and logic 0 for the others. When the scan list function is
initiated, A/D conversion begins from the start channel. After the conversion is completed,
digitized data is entered into the data FIFO and the board selects the next location to repeat
the same task. This process continues until the stop channel is reached. For single trigger
mode, it scans once and then stops. I n continuous mode, scanning continues at a speed set by
the sampling rate until the desired number of scan times is reached.

The scan FIFO is programmable for up to a 256 channel scan list with an individual gain
setting for each channel. The scan speed from channel to channel is 2.7µs. This speed is
sufficient for the ampli fier settling time of all gain selection values except 1000. Wi th a gain
setting of 1000 for the DAQ-1201, it requires 10µs for the amplifier to settle down. By
programming the scan FIFO to repeat the same channel scan four times for each channel , the
scan speed can be slowed to 10.8µs.

1.1.5 Sampling Rate

DAQ-1200 Series Users Manual 12

When digitizing the analog signal, one user selectable parameter is the sampling rate which
determines how fast the analog signal is digitized. The minimum sampling rate must be at
least two times the input signal frequency to accurately recover digitized data from the
original anal og input signal. The max imum sampling rate of the DA Q-1201/1202 is 400 kHz
and is derived from the on board 8254 chip which has three 16-bit counter/timers. The clock
input to Timer1 is 10MHz. Timer1 and Timer2 are cascaded to generate the sampling rate
pulse which in turn tr iggers A/D conversion. T he counting range of both timers is fr om 2 to

65535. Sampling period is computed as follows:

Sampling period = (Timer1 data) x (Timer2 data) x (100 nanoseconds)

The sampling rate in hertz is the i nverse of the sampl ing peri od. To set the highest sampli ng
rate of 400 kHz, the sampling period must be ms, or 2.5µs.

1

400

Timer1 and Timer2 values are calculated as follows:

(Timer1 data) x (Timer2 data) = 2500100

= 25

Timer1 and Timer2 data should be an integer ranging from 2 to 65535.

1.1.6 Simultaneous Sample Hold (SSH)

SSH uses a TTL signal which is logic high in "sample" mode and logic low in "hold" mode.
SSH is set to sample mode be fore the conversi on of the fir st channel in the scan list a nd then
switches to hold mode after the first conversion is completed. Hold mode remains set until the
last channel in the scan l ist is converted. Due to the settling time of the Programmable Gain
Amplifier (PGA), which is about 2µS for gain settings less than 1000, the first channel is not
perfectly si multaneous wi th the rest of the channels in the scan list. T his can be over come by
programming the first channel twice in the scan list and discar ding the non-simulta neous data
while processing.

If the need arises to write code for access to the DAQ-1201/1202 registers independent of
DAQDRIVE®, complete the following actions to implement SSH:

1. Set bit D6 of the even byte (low byte) in the scan FIFO to 1 for the first channel in the
scan list.

2. Set bit D6 of the even byte (low byte) in the scan FIFO to 0 for rest of the channels in
the scan list.

1.1.7 Data FIFO

DAQ-1200 Series Users Manual 13

DAQ-1201/1202 uses a data FIFO register between the output of the ADC and the ISA bus to
buffer data from the ADC output. Unlike conventional A/D boards where the di gitized data
output is fetched directly to the PC memory, the output data from the ADC is fed into the
FIFO first for temporary storage. The length of the FIFO register is 1024 sampling points and
the register circuit provides hardware flags for half full, full and empty signals. Utilizing these
signals, the b oard ca n genera te an inter rupt to the PC when the FIFO i s ha lf f ull . Once the PC
interrupt is complete, the interrupt service routine program uses the "MOVE STRING"
instruction to move the FIFO da ta directly in to PC memory at a very high speed. In this case,
it only interrupts the PC every 512 samples and thereby improves the speed of operation. In
Windows appl ications, the latency of the inte rrupt d oes not effect the i ntegr ity of the di gi tized
data as it continues into the FIFO. The status register (see Chapter 5, Table 1-5: Address map)
provides information about FIFO empty, half full and full conditions.

1.1.8 Direct Memory Access (DMA) Data Transfer

Another way of transferring digitized data from the A/D converter to memory is DMA
transfer. D MA operation is accompli shed by transf erring the data at the I/O l ocation directl y
to the PC memory by-passing the CPU. The DAQ-1201/1202 i mplements this DMA transfer
utilizing an AT style ISA bus with 8-bit DMA transfer channels (1,2,3) and 16-bit transfer
channels (5,6,7). The DAQ-1201/1202 employs word transfer to improve its efficiency and
allows for software programmable selection of the DMA channel. Proceeding any DMA
transfer, the PC DMA controller must be programmed with mode of operation, number of
words transferred and memory location. After programming the controller, then the FPGA
will initiate a DMA request to start the operation. When the data transfer is complete, a
terminal count pulse is generated by the controller and is used as an interrupt to inform the
PC at the completion of data transfer.

The DMA contr olle r only handl es d ata tra nsfer of 64 K points (one se gment) . Be yond that, the
controller must be reprogrammed again. When acquiring data beyond 64K points with a fast
pace sampling rate, data points can be missed during reprogramming of the DMA controller.
The DAQ-1201/1202 remedies this by utilizing two DMA channels. When one channel is
performing DMA operations, the other channel can be reprogrammed by the user. At the
terminal count, operation then switches to the reprogrammed channel and the completed
DMA channel is then available for reprogramming. This dual channel operation guarantees
the integrity of the data stream and is limited only by the memory size of the PC.

1.2 Analog Output Features

In addition to the analog input channels, the DAQ-1201/1202 contains two analog output
channels. Each channel has its own 12-bit digital-to-analog converter (DAC). The analog
outputs are buffe r ed and capable of 1 mA of output current. Th e output vol ta ge range for each
channel is jumper selectable as unipolar or bipolar. The 12-bit resolution provides a LSB value
of 4.88mV on the ±10V range and 2.44mV in the 0 to +10V range.

Both channels use multiplying DACs which require a reference voltage input in addition to

DAQ-1200 Series Users Manual 14

the 12-bit digital values. The DAQ1201/1202 provides an internal reference voltage while an
external reference voltage can also be supplied via jumper configuration.

Analog output has two modes of operation: I/O write operation and DMA write operation.
DMA write oper ation for analog output performs faster than I/O operation. Opposi te to the
DMA analog i nput function, DMA for analog output can transfer data in PC memory to the
DAC port at a pace set by the timer. Once again dual channel configuration is available for
DMA output operation which provides for data transfer beyond 64K points. Note that only
one port can be operating at a time.

1.3 Digital I/O

The DAQ-1201/1202 has 32 digital I/O lines. Of the 32 lines, 8 of them can be accessed
through the main D37 connector. There are 4 inputs: IP0 through IP3, and 4 outputs: OP0
through OP3, ( refer to F igure 1- 3 for pi n locations) . The remainin g 24 I/O lin es are g enerated
by an 8255 programmable peripheral interface chip and are accessed through the auxiliary
D37 connector. The 8255 has three ports (A, B and C) and one control register. Any port can b e
programmed as in put or output. Ports A and B ar e 8 bit I /O por ts whil e port C can be f urther
divided into two 4-bi t I/O ports. T he 8255 has three modes of operation whi ch are d etermi ned
by values wr itten into the control regi ster. Mode 0 i s for basic input/output config uration in
which the output port is l atched and the input por t is not. Mode 1 employs Port A or B a s the
data port while using Port C for handshake, interrupt, and digital I/O lines. Mode 2 uses Port
A as the bi-directional data port with Port B and C as control and digital I/O lines. For a
detailed functional description, the reader is referred to the Intel® 8255 data manual.

1.4 Counter / Timer

The 8254 counter/timer chip on the DAQ-1201/1202 provides three 16-bit counter/timer
channels for time-related applications. Timer1 and Timer2 are cascaded together with an
input clock of 10 MHz and the output of Ti mer 2 is used as the sampl i ng r ate cl ock f or the A /D
converter. Three terminals for Timer0 are available to the user via the main I/O D37
connector. The three terminals are Pin 2 (Timer0 output), Pin 21 (Timer0 Clk) and Pin 24
(Timer0 Ga te). The gate te rminal should b e logic high in order for the counter to f unction. If
gate is held at logic low, the counter is disabled.

1.5 Interrupts

DAQ-1200 Series Users Manual 15

The DAQ-1201/1202 supports AT style ISA bus interrupts which includes IRQ 2-7, 10-12 and
14-15. The selection of inter rupts is softwa re programmabl e through the reg ister setting of the
FPGA. Any interrupt conflict can be conveniently resolved by moving the selection to another
available line without opening the computer case. There are five interrupt sources from
DAQ-1201/1202:

y

End of scan

y

Data FIFO Half Full

y

Data FIFO Full

y

Timer0

y

Terminal count

The end of scan interrupt is normally used in conjunction with single trigger mode. After the
scan list is completed , the end of scan generates an interr upt to inform the computer to fetch
the data.

The data FIFO half full interrupt is used during continuous trigger mode. When the FIFO is
half full, i t interrupts the PC to fetch at least 512 sample points. This interrupt is works well in
the Windows environment because of interrupt latency problems inherent in the Windows
operating system.

The data FIFO full interrupt is not recommended for applications unless the interrupt routine
is executed promptly before the next data points are accepted. Otherwise an overflow can
occur and data may be lost.

Timer0 in terrupt is used in conjunction with the external ti mer at the main D37 connector. The
external cl ock pulses are connected to the Ti mer0 clk input (pi n 21) and the output of Timer 0
can be used as an interrupt source. When the user must interrupt the PC at a certain time
interval, timer0 can be programmed to meet the requirement.

Terminal count interrupt occurs at the completion of DMA transfer. The terminal count
interrupt informs the user that DMA transfer has finished.

1.6 Software Support

DAQ-1200 Series Users Manual 16

Software drivers are provided to support various programming languages like Microsoft
C/C++, Borland C/C++, QuickBasic, Visual Basic for DOS and Turbo Pascal. A Dynamic
Link Library (DLL) is provided for numerous programming languages under Microsoft
Windows as well as Visual Basic Controls. Software support is available on the Omega
"DaqSuite" compact disk in the following categories:

1. DAQDRIVE® Software driver

2. DaqEZ™ Data Acquisition Package

3. VISUALDAQ ® Data Acquisition Package

DAQDRIVE is a low level generic driver consisting of a set of user commands that act as a
library routine for all Quatech data acquisition boards. Programs written for the
DAQ-1201/1202 can be ported to other boards i n the event the user decides to change boards
in the fu ture. DAQDRIVE is avai lable for Wi ndow DLLs and the MS-DOS environment. In
the case of Visual Basic applications, Omega provides VISUALDAQ®. Because of it's user
friendly nature, this software is very practical for interaction with data acquisition boards and
for creating graphic presentations.

Omega also provides driver support for third party data acquisition packages such as
TestPoint® (Capital Equipment Corporation) and LabVIEW® (National Instruments). These
packages allow the user to create custom test, measurement and data acquisition applications.

1.7 Power Requirements

The DAQ-1201/1202 is powered di rectly by the +5V and +12V power source provided b y the
computer bus.