Omega OME-PIO-D144 User Manual

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User’s Guide

OME-PIO-D144
PCI-Bus

Digital I/O Board

Hardware Manual

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OME-PIO-D144

User’s Manual

OME-PIO-D144 User’s Manual (Ver.2.1, Sep/2001, PPH-009-21) ----- 1

Table of Contents

1. INTRODUCTION ........................................................................................................................4

1.1 SPECIFICATIONS ..................................................................................................................4

1.2 PRODUCT CHECK LIST ........................................................................................................4

2. HARDWARE CONFIGURATION ............................................................................................5

2.1 BOARD LAYOUT.................................................................................................................. 5

2.2 I/O PORT LOCATION ...........................................................................................................6

2.3 ENABLE I/O OPERATION .....................................................................................................6

2.4 D/I/O ARCHITECTURE ........................................................................................................7

2.5 INTERRUPT OPERATION ......................................................................................................8

2.6 DAUGHTER BOARDS .........................................................................................................13

2.6.1 OME-DB-37 ...............................................................................................................13

2.6.2 OME-DN-37 & OME-DN-50 .....................................................................................13

2.6.3 OME-DB-8125 ...........................................................................................................13

2.6.4 OME-ADP-37/PCI & OME-ADP-50/PCI ..................................................................14

2.6.5 OME-DB-24P/24PD Isolated Input Board.................................................................15

2.6.6 OME-DB-24R/24RD Relay Board.............................................................................. 16

2.6.7 OME-DB-24PR/24POR/24C ......................................................................................17

2.6.8 Daughter Board Comparison Table ...........................................................................18

2.7 PIN ASSIGNMENT ................................................................................................................. 19

3. I/O CONTROL REGISTER.....................................................................................................21

3.1 HOW TO FIND THE I/O ADDRESS........................................................................................21

3.1.1 PIO_DriverInit ............................................................................................................... 23

3.1.2 PIO_GetConfigAddressSpace ........................................................................................24

3.1.3 Show_PIO_PISO............................................................................................................25

3.2 THE ASSIGNMENT OF I/O ADDRESS......................................................................................26

3.3 THE I/O ADDRESS MAP........................................................................................................28

3.3.1 RESET\ Control Register...........................................................................................28

3.3.2 AUX Control Register.................................................................................................29

3.3.3 AUX data Register...................................................................................................... 29

3.3.4 INT Mask Control Register.........................................................................................29

3.3.5 Aux Status Register ..................................................................................................... 30

3.3.6 Interrupt Polarity Control Register ............................................................................30

3.3.7 Read/Write 8-bit data Register ...................................................................................31

3.3.8 Active I/O Port Control Register.................................................................................31

3.3.9 I/O Selection Control Register....................................................................................32

OME-PIO-D144 User’s Manual (Ver.2.1, Sep/2001) ---- 2

4. DEMO PROGRAM....................................................................................................................33

4.1 OME-PIO-D144.H .............................................................................................................. 34

4.2 DEMO1: USE D/O OF CN1....................................................................................................35

4.3 DEMO2: USE D/O OF CN1~CN6.......................................................................................... 37

4.4 DEMO3: INTERRUPT DEMO1 .................................................................................................39

4.5 DEMO4: INTERRUPT DEMO2 .................................................................................................41

4.6 DEMO5: INTERRUPT DEMO3 .................................................................................................43

4.7 DEMO 6: OUTPORT OF CN1-CN6 .......................................................................................46

4.8 DEMO10: FIND CARD NUMBER ............................................................................................48

OME-PIO-D144 User’s Manual (Ver.2.1, Sep/2001) ----- 3

1. Introduction

The OME-PIO-D144 consists of one D-Sub 37 & five 50-pin flat-cable

connectors. There are three 8-bit ports - PA, PB & PC - in each connector. Every port

consists of 8-bit programmable D/I/O. So the OME-PIO-D144 can provide 144

channels of TTL-compatible D/I/O.

1.1 Specifications

• PC compatible PCI bus

• One D-Sub37 connector and five 50-pin flat-cable connectors

• Each port consists of three 8-bit ports - PA, PB & PC - in every connector

• Each port can be programmed as D/I or D/O independently.

• Each board = 6 connector = 6×3 ports = 6×3×8 bits =144 bits

• 4 interrupt sources: PC0, PC1, PC2, PC3

• All signals are TTL compatible

• Operating Temperature: 0°C to 60°C

• Storage Temperature: -20°C to 80°C

• Humidity: 0 to 90% RH non-condensing

• Dimension: 180mm X 105mm

• Power Consumption: +5V @ 1100mA

1.2 Product Check List

In addition to this manual, the package includes the following items:

• OME-PIO-D144 card

• Software diskette/CD

Attention!

If any of these items is missing or damaged, please contact

Omega Engineering immediately. Save the shipping materials

and the box in case you want to ship or store the product.

OME-PIO-D144 User’s Manual (Ver.2.1, Sep/2001) ---- 4

2. Hardware configuration

2.1 Board Layout

PCI BUS

OME-PIO-D144

D-Sub 37 PIN

50-PIN

50-PIN

50-PIN

CN1_PC

CN1_PB

CN2_PC

CN2_PB

CN3_PC

CN3_PB

CN4_PC

CN4_PB

CN1_PA

CN2_PA

CN3_PA

CN4_PA

CN1

CN2

CN3

CN4

50-PIN

50-PIN

CN5_PC

CN6_PC

CN5_PA

CN5_PB

CN6_PA

CN6_PB

CN5

CN6

OME-PIO-D144 User’s Manual (Ver.2.1, Sep/2001) ----- 5

2.2 I/O Port Location

There are eighteen 8-bit I/O ports in the OME-PIO-D144. Every I/O port can be

programmed as D/I or D/O port. When the PC is first powered up, all eighteen ports

are used as D/I ports. The I/O port location is given as following:

Connector of OME-PIO-D144 PA0 to PA7 PB0 to PB7 PC0 to PC7

CN1 CN1_PA CN1_PB CN1_PC

CN2 CN2_PA CN2_PB CN2_PC

CN3 CN3_PA CN3_PB CN3_PC

CN4 CN4_PA CN4_PB CN4_PC

CN5 CN5_PA CN5_PB CN5_PC

CN6 CN6_PA CN6_PB CN6_PC

Refer to Sec. 2.1 for board layout & I/O port location.

Note: PC0, PC1, PC2, PC3 of CN1 can be used as interrupt signal source. Refer

to Sec. 2.5 for more information.

2.3 Enable I/O Operation

When the PC is first powered up, all operation of D/I/O port are disable. The

enable/disable of D/I/O is controlled by the RESET\ signal. Refer to Sec. 3.3.1 for

more information about RESET\ signal. The power-on states are given as following:

• All D/I/O operations are disable

• All eighteen D/I/O ports are configured as D/I port

• All D/O latch register are undefined.(refer to Sec. 2.4)

The user has to perform some initialization before using these D/I/Os. The

recommended steps are given as following:

Step 1: Make sure which ports are D/O ports.

Step 2: Enable all D/I/O operation.(refer to Sec. 3.3.1).

Step 3: Select the active port (refer to Sec. 3.3.8).

Step 4: Send initial-value to the D/O latch register of this active port.

(Refer to Sec. 2.4 & Sec. 3.3.7)

Step 5: Repeat Step3 & Step4 for all D/O ports

Step 6: Configure all eighteen D/I/O ports to their expected D/I or D/O state.

(Refer to Sec. 3.3.9)

Refer to DEMO1.C for demo program.

OME-PIO-D144 User’s Manual (Ver.2.1, Sep/2001) ---- 6

2.4 D/I/O Architecture

I/O select (Sec. 3.3.9)

RESET\ (Sec. 3.3.1)

Data

(Sec. 3.3.7)

Data

(Sec. 3.3.7)

disable\

input Latch

Clock input

D/O latch CKT

disable

Buffer input

Clock input

D/I buffer CKT

D/I/O

• The RESET\ is in Low-state Æ all D/I/O operation is disable

• The RESET\ is in High-state Æ all D/I/O operation is enable.

• If D/I/O is configured as D/I port Æ D/I=external input signal

• If D/I/O is configured as D/O port Æ D/I = read back of D/O

• If D/I/O is configured as D/I port Æ send to D/O will change the D/O latch

register only. The D/I & external input signal will not change.

OME-PIO-D144 User’s Manual (Ver.2.1, Sep/2001) ----- 7

2.5 Interrupt Operation

The PC0, PC1, PC2, PC3 of CN1_PC can be used as interrupt signal source. Refer

to Sec. 2.1 for PC0/1/2/3 location. The interrupt of OME-PIO-D144 is

& Active_High
inverted

1. make sure the initial level is High or Low

2. if the initial state is High Æ select the inverted signal (Section. 3.3.6)

3. if the initial state is Low Æ select the

4. enable the INT function (Section. 3.3.4)

5. If the interrupt signal is active Æ program will transfer into the interrupt

DEMO5.C for four interrupt sources.

have to identify the interrupt source. (Refer to DEMO3.C & DEMO4.C)

state. The programming procedure is as follows:

service routine Æ if INT signal is High now Æ select the inverted input

Refer to DEMO3.C & DEMO4.C for single interrupt source. Refer to

If only one interrupt signal source is used, the interrupt service routine does not

If there are more than one interrupt source, the interrupt service routine has to

. The interrupt signal can be programmed to inverted or non-

non-inverted signal (Section. 3.3.6)

Æ if INT signal is Low now Æ select the non-inverted input

level-trigger

identify the active signals as following: (refer to DEMO5.C)

1. Read the new status of the interrupt signal source

2. Compare the new status with the old status to identify the active signals

3. If PC0 is active, service CN1_PC0 & non-inverter/inverted the CN1_PC0 signal

4. If PC1 is active, service CN1_PC1 & non-inverted/inverted the CN1_PC1 signal

5. If PC2 is active, service CN1_PC2 & non-inverted/inverted the CN1_PC2 signal

6. If PC3 is active, service CN1_PC3 & non-inverted/inverted the CN1_PC3 signal

7. Save the new status to old status

Note: If the interrupt signal is too short, the new status may be as same as old

status. So the interrupt signal must be held active until the interrupt service

routine is executed. This hold time is different for different operating systems.

The hold time can be as short as micro-second or as long as second. In general,

20ms is enough for most operating systems.

OME-PIO-D144 User’s Manual (Ver.2.1, Sep/2001) ---- 8

Example 1: assume initial level=Low, PC0 is used as interrupt source:

Initial=Low

Iniaial_sub()

{ now_int_state=0

_outpd(wBase+0x2a,0)

/*(select the non-inverted signal)*/

ISR_sub()

{

If (now_int_state==0) /* old state=low Æ change to high now */

{

now_int_state=1; /* now int_signal is High */

/*** application codes are given here ***/

_outpd(wBase+0x2a,1); /* select the inverted signal */

}

else /* old state=highÆ change to low now */

{

now_int_state=0; /* now int_signal is Low */

/*** application codes are given here ***/

_outpd(wBase+0x2a,0); /* select the non-inverted signal */

}

if (wIrq>=8) outp(A2_8259,0x20); /* EOI */
outp(A1_8259,0x20); /* EOI */

}

Refer to DEMO3.C for source code.

OME-PIO-D144 User’s Manual (Ver.2.1, Sep/2001) ----- 9

Example 2: assume initial level=High, PC0 is used as interrupt source:

Initial=High

Inverted=Low

Iniaial_sub()

{ now_int_state=1

_outpd(wBase+0x2a,1)

/*(select the inverted signal)*/

ISR_sub()

{

If (now_int_state==0) /* old state=low Æ change to high now */

{

now_int_state=1; /* now int_signal is High */

/*** application codes are given here ***/

_outpd(wBase+0x2a,1); /* select the inverted signal */

}

else /* old state=highÆ change to low now */

{

now_int_state=0; /* now int_signal is Low */

/*** application codes are given here ***/

_outpd(wBase+0x2a,0); /* select the non-inverted signal */

}

if (wIrq>=8) outp(A2_8259,0x20); /* EOI */
outp(A1_8259,0x20); /* EOI */

}

Refer to DEMO4.C for source code.

OME-PIO-D144 User’s Manual (Ver.2.1, Sep/2001) ---- 10

Example 3: assume CN1_PC0 is initial Low, active High,

CN1_PC1 is initial High, active Low

CN1_PC2 is initial Low, active High

CN1_PC3 is initial High, active Low

As follows:

CN1_PC0

CN1_PC1

CN1_PC2

CN1_PC3

CN1_PC0 &

CN1_PC1 are

active at the same

time.

CN1_PC0 &

CN1_PC1 are

return to normal

at the same time.

CN1_PC2 &

CN1_PC3 are

active at the same

time.

CN1_PC2 &

CN1_PC3 are

return to normal

at the same time.

Refer to DEMO5.C for source program. All these four falling-edge & rising-edge

can be detected by DEMO5.C.

Note: When the interrupt is active, the user program has to identify the active

signals. These signals maybe all active at the same time. So the interrupt

service routine has to service all active signals at the same time.

OME-PIO-D144 User’s Manual (Ver.2.1, Sep/2001) ----- 11

void interrupt irq_service()
{
char cc;
int_num++;

/* 1. Read interrupt signal status */
new_int_state=inp(wBase+0x07)&0xff;

/* 2. Find the active signal */
int_c=new_int_state ^ now_int_state;

/* 3. IF PC0 is active */

if ((int_c&0x01) != 0)
{
cc=new_int_state&0x01;
if (cc !=0) CNT_H1++; else CNT_L1++;
invert=invert ^ 1;
}

/* 4. IF PC1 is active */
if ((int_c&0x02) != 0)
{
cc=new_int_state&0x02;
if (cc !=0) CNT_H2++; else CNT_L2++;
invert=invert ^ 2;
}

/* 5. IF PC2 is active */

if ((int_c&0x04) != 0)
{
cc=new_int_state&0x04;
if (cc !=0) CNT_H3++; else CNT_L3++;
invert=invert ^ 4;
}

/* 6. IF PC3 is active */

if ((int_c&0x08) != 0)
{
cc=new_int_state&0x08;
if (cc !=0) CNT_H4++; else CNT_L4++;
invert=invert ^ 8;
}

now_int_state=new_int_state;
outp(wBase+0x2a,invert);

if (wIrq>=8) outp(A2_8259,0x20);
outp(A1_8259,0x20);
}

OME-PIO-D144 User’s Manual (Ver.2.1, Sep/2001) ---- 12

2.6 Daughter Boards

p

2.6.1 OME-DB-37

The OME-DB-37 is a general purpose daughter board with D-sub 37 pin

connector. It is designed for easy wire connection.

37-PIN cable

OME-DB-37

2.6.2 OME-DN-37 & OME-DN-50

The OME-DN-37 is a general purpose daughter board for D-sub 37 pin connector.

The OME-DN-50 is designed for 50-pin flat-cable header. They are designed for easy

wire connection. Both boards are DIN rail mountable.

37-PIN cable

OME-DN-37

2.6.3 OME-DB-8125

The OME-DB-8125 is a general purpose screw terminal board. It is designed for

easy wire connection. There is one D-Sub37 & two 20-pin flat-cable headers on the OME-

DB-8125.

OME-PIO-D144 User’s Manual (Ver.2.1, Sep/2001) ----- 13

37pin cable

OME-DB-8125

(D-Sub37 or

20-

in flat-cable header)

2.6.4 OME-ADP-37/PCI & OME-ADP-50/PCI

The OME-ADP-37/PCI & OME-ADP-50/PCI are extenders for the 50-pin

headers. One side of the OME-ADP-37/PCI & OME-ADP-50/PCI can be connected

to a 50-pin header. The other side can be mounted on the PC chassis as following:

OME-ADP-37/PCI: 50-pin header to D-Sub37 extender.

OME-ADP-50/PCI: 50-pin header to 50-pin header extender.

OME-PIO-D144 User’s Manual (Ver.2.1, Sep/2001) ---- 14