OKI MSM7732-01 Technical data
FEDL7732-01-10
OKI Semiconductor
Issue Date: Nov. 2, 2005
MSM7732-01
Audio CODEC
GENERAL DESCRIPTION
The MSM7732 is a single-channel full duplex CODEC CMOS IC which performs mutual transcoding between the
analog voice band signals and 64 kbps PCM serial data.
This device performs such functions as DTMF tone and several types of tone generation, transmit/receive data
mute and gain control, and side tone path.
FEATURES
· Single 3 V power supply operation V
· PCM interface data format : µ-law/A-law/linear (2’s complement) selectable
· PCM interface timing : long frame synchronous timing/short frame synchronous timing
· Full-duplex single channel operation
· Serial PCM transmission data rate: 64 kbps to 2048 kbps
· Low power consumption
Operating mode: 15 mW typ. (V
Power-down mode: 3 µW typ. (V
· Master clock frequency: 2.048 MHz
· Analog output stage
35 mW drive for receiver speaker (differential drive of 32 Ω)--Gain adjustable
66 mW drive for receiver speaker (differential drive of 30 Ω)--Gain adjustable
6.6 mW drive for earphone speaker (single drive of 32 Ω) --Gain adjustable
· Transmit/receive mute, transmit/receive programmable gain control
· Side tone path with programmable attenuation (8-step adjustment level)
· Built-in DTMF tone generator
· Built-in various ringing/function tone generator
· Built-in various ring back tone generator
· Serial MCU interface control: 3 bit
· Built-in transmit voice signal detector
· Built-in op amps and analog switches for various analog interface
· Package options :
30-pin plastic SSOP (SSOP30-P-56-0.65-K) (MSM7732-01 MB)
48-pin plastic TQFP (TQFP48-P-0707-0.50-K) (MSM7732-01 TB)
48-pin plastic LGA (P-TFLGA48-0707-0.8) (MSM7732-01 LB)
48-pin plastic BGA (P-LFBGA48-0707-0.8) (MSM7732-01 LA)
= 3.0 V)
DD
= 3.0 V)
DD
: 2.4 V to 3.3 V
DD
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FEDL7732-01-10
Ω
Ω
p
OKI Semiconductor
BLOCK DIAGRAM
AMPAI
AMPAO
Microphone
amp input
AIN–
+
GSX
AOUT+
35 mW
for receiver
8.8 mW
for earphone
AOUT–
PWI
VFRO
SAO
SWA
SWB
SWC
SWD
SWE
SG
AMPA
20 kΩ
20 kΩ
32
32Ω
20 kΩ
32
–1
CR4-B5
A/D
D/A
CR1-B1
V
A
V
REF
AG1
Slope
Filter
AG2
V
CR0-B2
CR3-B7, 6, 5
off,–15 to –3 dB
2 dB ste
LPF
DD
DG
MCK
BPF
PDN
CR4-B6
CR3-B3, 2, 1, 0
–36 to –6 dB
2 dB step
CR2-B2, 1, 0
-12 to +9 dB
3dB step
CR2-B7
TX ON/OFF
CR2-B6, 5, 4
–6 to +8 dB
2 dB step
CR2-B3
RX ON/OFF
CR1-B0
Through
(0 dB loss)
or -12 loss
MCU I/F
DIO
DEN
CR0-B0
EXCK
Voice
Detect
PCM
Compand
TONE
GEN.
PCM
Expand
MSM7732-01
to MCUI/F
PCMOUT
CR0-B0
PCMIN
BCLK
SYNC
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FEDL7732-01-10
OKI Semiconductor
PIN CONFIGURATION (TOP VIEW)
VDD
SWA
SWB
SWC
AMPAI
AMPAO
AIN+
AIN–
GSX
SWD
SWE
SG
VFRO
AG1
SAO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NC
AMPAI
AMPAO
AIN+
AIN–
GSX
NC
NC
SWD
SWE
SG
NC
1
2
3
4
5
6
7
8
9
10
11
12
NC
48
13
NC
SWC
47
14
NC
30-Pin Plastic SSOP
SWA
45
16
AG1
DD
V
44
17
NC
NC
43
18
SAO
NC
42
19
A
V
DG
41
20
PWI
SWB
46
15
VFRO
NC: No Connection
48-Pin Plastic TQFP
MCK
40
21
NC
DEN
DIO
39
38
22
23
AOUT–
AOUT+
NC
37
24
NC
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
36
NC
35
EXCK
34
PCMOUT
33
PCMIN
32
SYNC
31
NC
30
BCLK
29
PDN
28
NC
27
AG2
26
NC
25
NC
MSM7732-01
DG
MCK
DEN
DIO
EXCK
PCMOUT
PCMIN
SYNC
BCLK
PDN
AG2
AOUT+
AOUT–
PWI
V
A
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FEDL7732-01-10
OKI Semiconductor
8 7 6 5 4 3 2 1
H
G
F
E
D
C
B
A
AG2 AOUT+
PDN
BCLK NC
SYNC NC
PCMIN NC
PCMOUT
EXCK DIO
DEN MCK
NC
NC
AOUT- PWI
NC NC
NC NC
DG VDD
VA SAO
NC NC
NC NC
SWA SW B
Index (A1)
NC: No Connection
48-Pin Plastic LGA
48-Pin Plastic BGA
MSM7732-01
AG1 VFRO
SG SWE
NC SWD
NC GSX
NC AIN-
NC AIN+
NC AMPAO
SWC AMPAI
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FEDL7732-01-10
OKI Semiconductor
PIN DESCRIPTION
Pin Symbol Type Description
1 VDD — Power supply (3.0 V)
2 SWA IO Analog switch A
3 SWB IO Analog switch B
4 SWC IO Analog switch C
5 AMPAI I Amplifier A inverting input
6 AMPAO O Amplifier A output
7 AIN+ I Transmit side amplifier non-inverting input
8 AIN– I Transmit side amplifier inverting input
9 GSX O Transmit side amplifier output
10 SWD IO Analog switch D
11 SWE IO Analog switch E
12 SG O Analog signal ground (1.4 V)
13 VFRO O Receive side voice output
14 AG1 — Analog ground 1 (0 V)
15 SAO O Receive side sounder amplifier output
16 VA — Analog power supply (3.0 V)
17 PWI I Receive side voice amplifier input
18 AOUT– O Receive side voice amplifier output –
19 AOUT+ O Receive side voice amplifier output +
20 AG2 — Analog ground 2 (0 V)
21
22 BCLK I PCM data shift clock input
23 SYNC I PCM data shift sync signal input
24 PCMIN I Receive side PCM signal input
25 PCMOUT O Transmit side PCM signal output
26 EXCK I Clock signal input for control register
27 DIO IO Address and data input or output for control register
28 DEN I Enable signal input for control register
29 MCK I Master clock input (2.048 MHz)
30 DG — Digital ground (0 V)
PDN
I Power down control input
MSM7732-01
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FEDL7732-01-10
A
–
A
A
A
OKI Semiconductor
MSM7732-01
PIN FUNCTIONAL DESCRIPTION
AIN+, AIN–, GSX
Transmit analog inputs and the output for transmit gain adjustment.
AIN– connects to inverting input of the internal transmit amplifier. AIN+ connects to non-inverting input of the
internal transmit amplifier. GSX connects to the internal transmit amplifier output. Refer to Figure 1 for gain
adjustment.
VFRO, SAO, AOUT+, AOUT–, PWI
Receive analog outputs and the outputs for receive gain adjustment.
VFRO is the receive filter output for the voice signal. SAO is the receive filter out put for an acoustic component of
the sound tone. SAO can directly drive 32 Ω load. AOUT+ and AOUT– are differential analog signal outputs
which can directly drive a 32 Ω load. Refer to Figure 1.
R2
GSX
IN–
IN+
SG
OUT+
OUT–
PWI
VFRO
SAO
–
+
Transmit Gain:
V/Vi
–1
to ENCODER
VREF
D/A
Conv.
Vi
C1
R1
0.1 µF
10 µF
+
Vo = VVFRO (R3/R4) ×2
R3
R4
Sounder output signal
Figure 1 Analog Input/Output Interface
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FEDL7732-01-10
OKI Semiconductor
MSM7732-01
SG
Analog signal ground.
The output voltage of this pin is approximately 1.4 V. Put the bypass capacitors (10 µF in parallel with 0.1 µF
ceramic type) between this pin and AG to get the specified noi se characteristics. During power-down, this output
voltage is 0 V.
AMPAI, AMPAO
Used for amplifier A. The pin AMPAI is connected to the amplifier A inverting input, and the pin AMPAO is
connected to the amplifier A output.
SWA, SWB, SWC
Used for the internal analog switch. The pin SWB connects to the pin SWA o r the pin SWC. This is controlled by
CR1-B1.
SWD, SWE
Used for the internal analog switch. The pin SWD connects to the pin SWE or not. This is controlled by CR1-B2.
V
, VA
DD
+3 V power supply for analog. V
is the digital power supply. VA is the analog power supply.
DD
Since these pins are separated in the device, connect them as close as possible on the PCB.
DG, AG1, AG2
Ground. DG is the digital system ground. AG1 and AG2 are connected to the analog system ground.
The DG pin must be kept as close as possible to AG1 and AG2 on the PCB.
PDN
Power down and reset control input.
When set to digital “0”, the system changes to the power down state and control registers are reset. Since the power
down mode is controlled by a logical OR wi th CR0-B5 of t he control re gister, set C R0-B5 to logi c “0” when usi ng
this pin.
Be sure to reset the control registers by executing this power down to keep this pin to digital “0” level for 200 ns or
longer after the power is turned on and V
exceeds 2.4 V.
DD
MCK
Master clock input.
The frequency must be 2.048 MHz. MCK can be asynchronous with SYNC and BCLK.
BCLK
Shift clock input for the PCM data.
The frequency is set in the range of 64 kHz to 2048 kHz.
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FEDL7732-01-10
OKI Semiconductor
MSM7732-01
SYNC
8 kHz synchronous signal input for transmit and receive PCM data.
Synchronize this signal with BCLK signal. Refer to Figure 2.
PCMOUT
Transmit PCM data output.
This PCM output signal is output from MSB synchronously with the rising edge of BCLK and SYNC. Refer to
Figure 2. This is a logic o utput pin s o that external pull-up is not require d. This pin outputs logi c "L" except during
effective PCM data bits, and outputs logic "H" during power-down.
PCMIN
Receive PCM data input.
This PCM input signal is shifted in on the falling edge of BCLK and is input from MSB.
Refer to Figure 2.
SYNC
8 kHz (125 µs)
BCLK
PCMIN or
PCMOUT
MSB LSB
∗ 14 bit in the case of linear mode
(a) Long frame synchronous interface
8 kHz (125 µs)
SYNC
BCLK
PCMIN or
PCMOUT
MSB
LSB
∗ 14 bit in the case of linear mode
(b) Short frame synchronous interface
Figure 2 PCM Interface Basic Timing Diagram
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FEDL7732-01-10
A
A
A
A0 A1A
OKI Semiconductor
MSM7732-01
DEN, EXCK, DIO
Serial control ports for MCU interface.
Reading and writing data is perf ormed by an external MCU through these pins. Eight registers with eight bits are
provided on the devices.
DEN is the "Enable" control signal input, EXCK is the data shift clock input, and DIO is the address and data input
or output. Figure 3 shows the input or output timing diagram.
DEN
EXCK
DIO
W
2
(a) Write Data Timing Diagram
0
1
B7
B6
B4 B5
B2B3
B1
B0
DEN
EXCK
DIO
R
B6
2
B7
B5
B4
B3
B2
B0 B1
input
(b) Read Data Timing Diagram
output
Figure 3 MCU Interface Input/Output Timing
Table 1 shows the register map.
Table 1
Name
CR0 0 0 0 A/µ SEL
CR1 0 0 1
CR2 0 1 0
CR3 0 1 1
CR4 1 0 0
CR5 1 0 1
CR6 1 1 0
CR7 1 1 1 VOX OUT
Address Control and Detect Data
A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
PON
AOUT
— — — —
TX
ON/OFF
Side Tone
GAIN2
DTMF/
OTHERS
ON/OFF
R/W : Read/Write enable R : Read only register
TX GAIN2 TX GAIN1 TX GAIN0
Side Tone
GAIN1
TONE
SEL
VOX
SEND
— — — — — — — —
ON LVL1 ON LVL0
TX NOISE
PDN ALL PDN TX PDN RX SLP SLP SEL LNR R/W
LVL1
Side Tone
GAIN0
SAO/
VFRO
TX NOISE
LVL0
SHORT
FRAME
ON/OFF
TONE
ON/OFF
TONE4 TONE3 TONE2 TONE1 TONE0 R/W
— — — — —
— — — — —
TONE
GAIN3
SW D/E SW C/A RX PAD R/W
RX
RX GAIN2 RX GAIN1 RX GAIN0 R/W
TONE
GAIN2
TONE
GAIN1
TONE
GAIN0
R/W
R/W
R/W
R/W
R
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