OKI MSM7718-01TS-K Datasheet

E2U0052-18-86

¡ Semiconductor

This version: Aug. 1998

MSM7718-01

¡ Semiconductor

MSM7718-01

Echo Canceler with ADPCM CODEC

GENERAL DESCRIPTION

The MSM7718, developed for PHS (Personal Handyphone System) applications, is a CMOS LSI device and contains a line echo canceler and a single channel full-duplex ADPCM transcoder that performs interconversion between voice-band analog signal and 32 kbps ADPCM data. This device includes DTMF tone and several types of tone generation, transmit/receive data mute and gain control, and VOX function and is best suited for master telephones in PHS applications.

FEATURES

• Single 3 V power supply VDD : 2.7 V to 3.6 V

• ADPCM : ITU-T Recommendations G.726 (32 kbps)

• Full-Duplex single channel operation

• Transmit/receive synchronous mode

• PCM interface coding format : µ-law

• Built-in line echo canceler Echo attenuation : 30 dB (typ.) Cancelable echo delay time :

Normal speech mode : 23 ms (max.) Line echo canceler expansion mode : 54 ms (max.)

• Serial PCM/ADPCM transmission data rate : 64 kbps to 2048 kbps

• Low power consumption Operating mode : Typically 66 mW (VDD = 3.0 V) Power-down mode : Typically 0.3 mW (VDD = 3.0 V)

• Two analog input gain adjustable amplifier stages

• Analog output stage : Push-pull drive, (direct drive of 350 W + 120 nF)

• Master clock frequency : 9.600/19.200 MHz

• Transmit/receive mute, transmit/receive programmable gain control

• Built-in DTMF tone generator and various ringing tones generator

• DTMF tone and call progress tone detection

• Serial MCU interface control

• Built-in VOX control Transmit side : Voice/silence detect Receive side : Background noise generation at the absence of voice signal

• Built-in 2100 Hz tone detection (bidirectional)

• Package:

100-pin plastic TQFP (TQFP100-1414-0.50-K) (Product name : MSM7718-01TS-K)

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BLOCK DIAGRAM

MSM7718-01

VOXO

SGR

SGT

AIN1– AIN1+

GSX1

AIN2

GSX2 VFRO

PWI

AOUT–

AOUT+

ATTtx

SinL

RoutL

Voice Detect

PCM CODEC

– +

1.2 kW

– +

–1

1.2 kW

ATTtgrx

ATTsL

–

Line

Adapive FIR Filter

(LAFF)

Coeff.L0 Coeff.L1

Howling Detector

Double Talk Detector

GainL ATTrL

Line Echo Canceler

L/m

m/L

VREF

L/m

BPF

ADC

RC LPF

DAC

LPF

m/L

Center

Clip

Power Calc.

Tone Generator (DTMF etc.)

Tone Detector (DTMF etc.)

SoutL

RinL

2100 Hz Detect

m/L

L/m

ATTtgtx

ATTrx

Power Detect

Mute

Flash

Memory

Controller

(Reserved)

ADPCM TRANSCODER

ADPCM

CODER

ADPCM

DECODER

Noise

Gen.

P/S

S/P

VOXI

MLV0 MLV1 MLV2 MUTE

D7-0 A20-0

WE OE CS1 CS2 RP

IS BCLKA SYNCA

DDA

DDD1,2,3

DG1,2,3

MCU Interface

DEN

EXCK

DIN

INT

DOUT

PCMPCI

PCMPCO

P/S&S/P

PCMLNI

PCMLNO

PCMACI

PCMACO

PCMADI

PCMADO

Timing

Gen.

SYNCP

BCLKP

MCKSL

Clock Gen.

MCK

PDN/RST

Test Interface

PDWN

TSTO

TSTI1-4

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MSM7718-01

DDD1

DDD3

TSTI1

BCLKA

SYNCA

BCLKP

PCMPCI

PCMLNI

PCMACI

PCMADI

DOUT

PCMPCO

PCMLNO

DG3

PCMACO

PCMADO

100

1 2TSTI2 3PDN/RST 4DIN 5EXCK 6DEN 7V 8SYNCP

9TSTI4 10TSTI3 11MCK 12MCKSL 13GNDA 14VFRO 15PWI 16AOUT– 17AOUT+ 18SGT 19SGR 20NC 21NC 22AIN1– 23GSX1 24AIN1+ 25NC

PDWN

CS1

NC 76

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

CS2 INT

TSTO VOXO VOXI MLV0 MLV1 MLV2 MUTE DG2 D7 NC D6 D5 D4 D3 D2 D1 D0 A0 A1 A2 V

DDD2

GSX2

AIN2

DDA

DG1

A15

A16

A17

A18

A19

A20

NC: No-connect pin

100-Pin Plastic TQFP

A14

A13

A12

A11

A10

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MSM7718-01

PIN FUNCTIONAL DESCRIPTION

AIN1+, AIN1–, AIN2, GSX1, GSX2

Transmit analog inputs and the outputs for transmit gain adjustment. AIN1– (AIN2) connects to inverting input of the internal transmit amplifier. AIN1+ connects to noninverting input of the internal transmit amplifier. GSX1 (GSX2) connects to the internal transmit amplifier output. Refer to Fig.1 for gain adjustment.

VFRO, AOUT+, AOUT–, PWI

Receive analog outputs and the output for receive gain adjustment. VFRO is the receive filter output. AOUT+ and AOUT– are differential analog signal outputs which can directly drive ZL (= 350 W + 120 nF) or a 1.2 kW load. Refer to Fig.1 for gain adjustment. However, these outputs are in high impedance state during power-down.

Differential

Analog Input

+ –

Transmit Gain: V = (R2/R1) ¥ (R4/R3)

Receive Gain: V = 2 ¥ (R5/R6)

C1 R1

GSX2

O/VVFRO

/Vi

AIN1–

AIN1+

GSX1 SGT

AIN2

GSX2

VFRO

PWI

AOUT–

–

VREF

to ENCODER

from DECODER

ZL=120 nF + 350 W

Differential

Analog Output

AOUT+

Figure 1 Analog Interface

–1

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MSM7718-01

SGT, SGR

Outputs of the analog signal ground voltage. SGT outputs the analog signal ground voltage of the transmit system, and SGR outputs the analog signal ground voltage for the receive system. The output voltage is approximately 1.4 V. Connect bypass capacitors of 10 mF and 0.1 mF (ceramic type) between these pins and the AG pin. However to reduce the response time of the receiver power-on, it is recommended to apply bypass capacitors of 1 mF and 0.1 mF. During power-down, the output changes to 0 V.

Analog ground.

DG1, 2, 3

Digital ground.

DDA

+3 V power supply for analog circuits.

DDD1, 2, 3

+3 V power supply for digital circuits.

PDN/RST

Power-down reset control input. A logic “0” makes the LSI device enter a power-down state. At the same time, all control register data is reset to the initial state. Set this pin to a logic “1” during normal operating mode. Since the PDN/ RST pin is ORed with CR0-B5 of the control register, set CR0-B5 to digital “0” when using this pin.

PDWN

Power-down control input. When set to a logic “0”, the device changes to the power-down state, but each bit of control register and internal variables of control register are retained. During normal operation, set this pin to logic “1”. Since the PDWN pin is ORed with CR0-B6 of the control register, set CR0-B6 to logic “0” when using this pin.

MCK

Master clock input. The frequency must be 9.6 MHz or 19.2 MHz. The master clock signal is allowed to be asynchronous with SYNCP, SYNCA, BCLKP, and BCLKA.

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MCKSL

Master clock selection input. Set MCKSL to logic “0” when the master clock frequency is 9.6 MHz, and to logic “1” when it is 19.2 MHz.

PCMPCO

PCM data output of the PCM CODEC. PCM is output from MSB, synchronizing with the rising edge of BCLKP and SYNCP. This pin is in a high impedance state except during 8-bit PCM output. (It is also in a high impedance state during power-down mode.) A pull-up resistor must be connected to this pin because its output is configured as an open drain.

PCMPCI

PCM data input of the PCM CODEC. PCM is shifted in at the falling edge of the BCLKP signal. The start of the PCM data (MSB) is identified at the rising edge of SYNCP.

MSM7718-01

PCMADO

PCM data output of the ADPCM transcoder. PCM is the output data after ADPCM decoder processing and is serially output from MSB in synchronization with the rising edge of BCLKP and SYNCP. However, this signal timing can be controlled at PCM multiplexing by the control register CR1-B5. (The time slot 1 or 2 can be selected. Refer to Figs. 2-4.) This pin is in a high impedance state except during 8-bit PCM output. (It is also in an high impedance state during power-down mode.) A pull-up resistor must be connected to this pin because its output is configured as an open drain.

PCMADI

PCM data input of the ADPCM transcoder. PCM is shifted in at a falling edge of the BCLKP signal and input from MSB. The start of the PCM data (MSB) is identified at the rising edge of SYNCP. However, this signal timing can be controlled at PC M multiplexing by the control register CR1-B5. (The time slot 1 or 2 can be selected. Refer to Figs. 2-4.)

PCMLNO

PCM receive data output of the line echo canceler. PCM is output from MSB in a sequential order, synchronizing with the rising edge of BCLKP and SYNCP. However, this signal timing can be controlled at PCM multiplexing by the control register CR2-B3 to B5. (The time slot of 1 to 7 can be selected. Refer to Figs. 2-4.) This pin is in a high impedance state except during 8-bit PCM output. (It is also in a high impedance state during power-down mode.) A pull-up resistor must be connected to this pin because its output is configured as an open drain.

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MSM7718-01

PCMLNI

PCM transmit data input of the line echo canceler. PCM is shifted in at a falling edge of the BCLKP signal and input from MSB. The start of the PCM data

(MSB) is identified at the rising edge of SYNCP. However, this signal timing can be controlled

at PCM

mutiplexing by the control register CR2-B3 to B5.

(One of the time slots 1 to 7 can be selected. Refer to Figs. 2-4.)

PCMACO

PCM transmit data output of the line echo canceler. PCM is output from MSB in a sequential order, synchronizing with the rising edge of BCLKP and SYNCP. However, this signal timing can be controlled at PCM multiplexing by the control register CR2-B0 to B2. (The time slot 1 to 7 can be selected. Refer to Figs. 2 - 4.) This pin is in a high impedance state except during 8-bit PCM output. (It is also in a high impedance sate during power down mode.) A pull-up resistor must be connected to this pin because its output is configured as an open drain.

PCMACI

PCM receive data input of the line echo canceler. PCM is shifted in at a falling edge of BCLKP and input from MSB. The start of the PCM data (MSB) is identified at the rising edge of SYNCP. However, this signal timing can be controlled at PCM multiplexing by the control register CR2-B0 to B2. (One of the time slots 1 to 7 can be selected. Refer to Figs. 2-4.)

BCLKP SYNCP

PCM Multiple

time slot 1 time slot 2 time slot 3 time slot 7

Note : The PCM signals (PCMPCI and PCMPCO) of the PCM CODEC are always assigned to time

slot 1. The PCM signals (PCMADI and PCMADO) of the ADPCM transcoder can be assigned to time slot 1 or 2. The PCM signals (PCMLNI, PCMLNO, PCMACI, PCMACO) of the line echo canceler can be assigned to one of the time slots 1 to 7. (Multiple timing is controlled by CR1 and CR2.)

Figure 2 PCM Multiple Timing

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MSM7718

MSM7718-01

Line Echo

Canceler

Line Slave telephone

PCM

CODEC

PCMPCO

PCMPCI

PCMLNI

PCMLNO

PCMACI

PCMACO

PCMADI

ADPCM

Transcoder

PCMADO

Note : In this connection, PCMLNI, PCMLNO, PCMACI, and PCMACO should all be assigned

to time slot 1 for their output timing (the output timing for the PCM CODEC is always assigned to time slot 1). Turn on the line echo canceler and establish a route between the slave telephone and the line.

Figure 3 PCM Signal Connection Example 1

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MSM7718

MSM7718-01

Line Echo

Canceler

Line Slave telephone

Microphone and speaker of the master telephone

PCM

CODEC

PCM

CODEC

PCMPCO

PCMPCI

PCMLNI

PCMLNO

PCMACI

PCMACO

PCMADI

ADPCM

CODEC

PCMADO

Notes : The PCM signals of the ADPCM transcoder are assigned to time slot 2. (The PCM signals

of the PCM CODEC are always assigned to time slot 1.) The PCM signals of an external PCM CODEC are assigned to time slot 3.

Route between the line and the slave telephone

PCMLNI and PCMLNO are assigned to time slot 1 and PCMACI and PCMACO are assigned to time slot 2. Turn on the line echo canceler, and establish the route between the line and the slave

telephone. Route between the master telephone's microphone/speaker (handsfree) and the slave telephone

PCMLNI and PCMLNO are assigned to time slot 3 and PCMACI and PCMACO are

assigned to time slot 2.

Turn on the line echo canceler, and establish the

speaker of the master telephone and the

slave telephone.

route between the microphone/

Route between the line and the master telephone's microphone/speaker (handsfree)

PCMLNI and PCMLNO are assigned to time slot 1 and PCMACI and PCMACO are

assigned to time slot 3.

Put the line echo canceler into “through mode”, and establish the route between

the line and the microphone/speaker of the master telephone.

Various routing can be implemented providing extension of external PCM CODECs.

Figure 4 PCM Signal Connection Example 2

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BCLKP

Shift clock input for the PCM data (PCMPCO, PCMPCI, PCMADO, PCMADI, PCMLNO, PCMLNI, PCMACO, PCMACI). The frequency is set in the range of 64 kHz to 2048 kHz. This signal must be synchronized with the SYNCP signal. (Refer to Fig. 2.)

SYNCP

8 kHz synchronous signal input for transmit and receive PCM data. This signal must be synchronized with the BCLKP signal. (Refer to Fig. 2.)

Transmit ADPCM data output. This data is the output data after ADPCM encoding, and is serially output from MSB in synchronization with the rising edge of BCLKA and SYNCA. This pin is an open drain output which remains in a high impedance state during power-down, and requires a pull-up resistor.

MSM7718-01

Receive ADPCM data input. ADPCM is shifted in on the rising edge of BCLKA in synchronization with SYNCA and input orderly from MSB.

BCLKA

Shift clock input for the ADPCM data (IS, IR). The frequency is from 64 kHz to 2048 kHz. This signal must be synchronized with the SYNCA signal.

SYNCA

8 kHz synchronous signal input for transmit and receive ADPCM data. Synchronize this data with BCLKA signal. SYNCA is used for indicating the MSB of the serial ADPCM data stream.

DEN, EXCK, DIN, DOUT, INT

Serial control ports for MCU interface. Reading and writing data is performed by an external MCU through these pins. 17-byte control registers are provided in this device. DEN is the “Enable” control signal input, EXCK is the data shift clock input, DIN is the address and data input, and DOUT is the data output. Input/output timing is shown in Fig. 5. INT goes to logic “0” when any change has been found in the tone detection results in the tone detection mode (change in the control register bits CR7-B3, B2), and goes to logic “1” when the data of control register CR7 is read out.

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DEN EXCK

MSM7718-01

DIN

DOUT

DEN

EXCK

DIN

DOUT

R A2A1A0

High Impedance

A1 A0 B7 B6 B5 B4 B3 B2 B1 B0

High Impedance

(a) Data Write Timing

B6 B5 B4 B3 B2 B1 B0

(b) Data Read Timing

Figure 5 MCU Interface Input/Output Timing

VOXO

Signal output for transmit VOX function. The VOX function recognizes the presence or absence of the transmit voice signal by detecting the level of the transmit signal to the line echo canceler . “1” and “0” levels set to this pin correspond to the presence and the absence of voice, respectively. This result appears also at the register data CR7-B7. The signal energy detect threshold is set by the control register data CR6-B6, B5. The timiging diagram of the VOX function is shown in Fig 6. The transmit signal to the line echo canceler refers to the signal input to the PCMLNI pin.

VOXI

Signal input for receive VOX function. The “1” level at VOXI indicates the presence of a voice signal, the decoder block processes normal receive signal, and the voice signal on the PCMACI pin goes through. The “0” level indicates the absence of a voice signal and the background noise generated in this device is output to the line echo canceler. The background noise amplitude is set by the control register CR6. Because this signal is ORed with the register data CR6-B3, set the control register data CR6-B3 to logic “0”.

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Voice Input GSX2

MSM7718-01

Silence

VOXO

VXON

Voice Detect

Voice

VXOFF

Silence Detect (Hangover time)

(a) Transmit VOX Function Timing Diagram (for Analog Input)

Silence

VOXI

Voice Output VFRO

Normal Voice Signal Decoded Time Period

(b) Receive VOX Function (CR6-B3: lo

Voice

Background Noise

ic “0”) Timing Diagram (for Analog Input)

Voice

Note: The VOX function is valid when CR6-B7 is set to logic “1”.

Figure 6 VOX Function

MUTE

This pin is used to enable the receive side voice path mute level. To set the mute level, set this pin to “1”.

MLV0, MLV1, MLV2

These pins are used to set the receive side voice path mute level. For the control method, refer to the control register description (CR1). Since these pins are ORed with CR1-B2, B1, and B0 internally, set the bits of the register to “0“ before using this pin.

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