OKI MSM7717-03MS-K, MSM7717-02MS-K, MSM7717-01GS-K, MSM7717-01MS-K, MSM7717-03GS-K Datasheet

E2U0041-28-81

¡ Semiconductor MSM7717-01/02/03

¡ Semiconductor

This version: Aug. 1998

Previous version: Nov. 1996

MSM7717-01/02/03

Single Rail CODEC

GENERAL DESCRIPTION

The MSM7717 is a single-channel CODEC CMOS IC for voice signals ranging from 300 to 3400
Hz with filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, the device is
optimized for ISDN terminals and telephone terminals in digital wireless systems.
The device uses the same transmission clocks as those used in the MSM7508B and MSM7509B.
The analog output, which can drive a 1.2 kW load, can directly drive a handset receiver
differentially.

FEATURES

• Single power supply: 2.7 V to 3.8 V

• Low power consumption
Operating mode: 20 mW Typ. VDD = 3 V
Power-down mode: 0.03 mW Typ. VDD = 3 V

• Conforms to ITU-T Companding law

MSM7717-01: m/A-law pin selectable
MSM7717-02: m-law
MSM7717-03: A-law

• Built-in PLL eliminates a master clock

• Serial data rate: 64/128/256/512/1024 kHz

96/192/384/768/1536/1544/2048/200 kHz

• Adjustable transmit gain

• Adjustable receive gain

• Built-in reference voltage supply

• Package options:
24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: MSM7717-01GS-K)

(Product name: MSM7717-02GS-K)
(Product name: MSM7717-03GS-K)

20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name: MSM7717-01MS-K)

(Product name: MSM7717-02MS-K)
(Product name: MSM7717-03MS-K)

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¡ Semiconductor MSM7717-01/02/03

BLOCK DIAGRAM

AIN–
AIN+

GSX

SGC

SG

VFRO

PWI

AOUT–

AOUT+

–
+

SG

GEN

RC

LPF

–
+

SG

–
+

SG

–
+

SG

8th

BPF

VR

GEN

5th

LPF

CONV.

DA

CONV.

PWD

AD

AUTO
ZERO

TCONT

PLL

RTIM

RCONT

PWD

Logic

PCMOUT

XSYNC

BCLK

RSYNC

(ALAW)

PCMIN

PDN
V

DD

AG
DG

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¡ Semiconductor MSM7717-01/02/03

PIN CONFIGURATION (TOP VIEW)

SG

AOUT+

AOUT–

NC

PWI

VFRO

NC

V

DD

DG

PDN

RSYNC

PCMIN

1

2

3

4

5

6

7

8

9

10

11

12 13

NC : No connect pin

24-Pin Plastic SOP

24

23

22

21

20

19

18

17

16

15

14

SGC

AIN+

AIN–

GSX

NC

NC

(ALAW)*

NC

AG

BCLK

XSYNC

PCMOUT

1

SG

AOUT+

AOUT–

VFRO

RSYNC

PCMIN

2

3

4

PWI

5

V

6

DD

7

DG

8

PDN

9

10 11

NC : No connect pin

20-Pin Plastic SSOP

20

19

18

17

16

15

14

13

12

SGC

AIN+

AIN–

GSX

NC

(ALAW)*

AG

BCLK

XSYNC

PCMOUT

* The ALAW pin is only supported by the MSM7717-01GS-K/MSM7717-01MS-K.

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¡ Semiconductor MSM7717-01/02/03

PIN AND FUNCTIONAL DESCRIPTIONS

AIN+, AIN–, GSX

Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp.
The level adjustment should be performed in any method shown below. When not using AIN–
and AIN+, connect AIN– to GSX and AIN+ to SG. During power-saving and power-down
modes, the GSX output is at AG voltage.

1) Inverting input type

Analog input

2) Noninverting input type

Analog input

AG

Analog signal ground.

C1

C2

R5

R1

R3

R2

R4

GSX
AIN–
AIN+
SG

AIN+
AIN–
GSX

SG

R1 : variable

–
+

+
–

R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1) (F)

Gain = R2/R1 < 10

R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5) (F)

Gain = 1 + R4 / R3 £ 10

VFRO

Receive filter output.
The output signal has an amplitude of 2.0 VPP above and below the signal ground voltage (SG)
when the digital signal of +3 dBm0 is input to PCMIN and can drive a load of 20 kW or more.
For driving a load of less than 20 kW, connect a resistor of 20 kW or more between the pins VFRO
and PWI.
During power-saving mode this output is in a high impedance state, and during power-down
mode, the VFRO output is at an SG level.
When adjusting the receive signal on the basis of frequency characteristics, refer to the Frequency
Characteristics Adjustment Circuit.

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¡ Semiconductor MSM7717-01/02/03

PWI, AOUT+, AOUT–

PWI is connected to the inverting input of the receive driver.
The receive driver output is connected to the AOUT– pin. Therefore, the receive level can be
adjusted with the pins VFRO, PWI, and AOUT–. When the PWI pin is not used, the PWI pin to
the AOUT– pin, and leave the pins AOUT– and AOUT+ open. The output of AOUT+ is inverted
with respect to the output of AOUT–. Since these outputs provide differential drive of an
impedance of 1.2 kW, these outputs can directly be connected to a receiver of handset using a
piezoelectric earphone. Refer to the application example. Since the driver amplifiers are being
activated during the power-saving mode, the amplifiers can output other external signals from
AOUT+ and AOUT– pins. AOUT+ and AOUT– outputs are in a high impedance state during
the power-down mode.

External Signal Input

Receive filter

–
+

SG

–
+

SG

V

DD

VFRO

PWI

AOUT–

AOUT+

VI

R6

R7

Analog output

VO

Analog inverted output

ZL

ZL > 1.2 k

R6 > 20 kW

Gain = VO/VI = R7/R6 £ 1

W

Power supply for 2.7 V to 3.8 V. (Typically 3.0 V)

PCMIN

PCM data input.
A serial PCM data input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of PCM is equal to the frequency of the BCLK signal.
PCM signal is shifted in at a falling edge of the BCLK signal and latched into the internal register
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.

BCLK

Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048
kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power
saving state.
The power-saving state means that the reference voltage generator (VRGEN), PLL, and receive
driver amplifiers are in the operating mode and the other circuits are in the non-operating mode.

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¡ Semiconductor MSM7717-01/02/03

RSYNC

Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be

synchronized in phase with the BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the

AC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device

can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are

not guaranteed.

XSYNC

Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this signal. This
synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLK.

The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly

the frequency characteristics of the transmit section.
However, if the frequency characteristic of an applied system is not specified exactly, this device

operates in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are

not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving
state.

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