OKI MSM7708-02TS-K Datasheet

E2U0044-16-X2

¡ Semiconductor MSM7708-02

¡ Semiconductor

This version: Jan. 1998

Previous version: Nov. 1996

MSM7708-02

Serial Register Interface ADPCM CODEC for Telephone Recording

GENERAL DESCRIPTION

The MSM7708-02 is a CMOS IC developed for applying to PHS (Personal Handyphone System). This device provides a CODEC function which performs transcoding between the voice band analog signal and 32 kbps ADPCM data. It also provides a serial register interface function for telephone call recording. Provided with such functions as DTMF tone and several kinds of tone generation, transmit/ receive data mute and gain control, side-tone pass, and voice/silence detection, the MSM770802 is best suited for PHS handsets.

FEATURES

• Single 3 V power supply operation (VDD: 2.7 V to 3.6 V)

• Low power consumption When system is operating: 6 mA typ. When powered down: 0.02 mA typ.

(ADPCM CODEC)

• ADPCM: ITU-T Recommendations G.721 (32 kbps)

• Transmit/receive full duplex capability

• PCM interface code format: m-law or A-law selectable

• Serial ADPCM and PCM transmission rate: 64 kbps to 2,048 kbps

• Transmit/receive mute function; transmit/receive programmable gain setting

• Side tone generator (8-step level adjustment)

• Built-in DTMF tone, ringing tone, and various tone generators

• Built-in VOX function

(Serial Register Interface)

• Interface for a serial register: 1 Mb (MSM63V89C), 4 Mb (MSM6684), 8 Mb (MSM6685)

• Interface for a serial voice ROM: 1 Mb (MSM6595A), 2 Mb (MSM6596A), 3 Mb (MSM6597A)

• Maximum recording time: 32 s (1 Mb), 128 s (4 Mb), 256 s (8 Mb)

• Maximum recording channels: 32 ch

• Playback data transmit/receive selectable

• Package: 64-pin plastic TQFP (TQFP64-P-1010-0.50-K) (Product name : MSM7708-02TS-K)

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¡ Semiconductor MSM7708-02

BLOCK DIAGRAM

SGR

SGT

AIN1– AIN1+

GSX1

AIN2

GSX2

AOUT+

AOUT–

PWI

VFRO

SAO

1.2 kW

To various units

EXCK DEN

VREF

MCU

Interface

DIN DOUT

RESET

– +

Filter

A/D

Converter

BPF

ATT

–1

– +

ATT

Voice

Detect

Compan-

DTMF /Tone

Generator

der

ADPCM

Coder

P/S

S/P

VOXO

IS PCMSI PCMSO XSYNC

BCLK RSYNC

PCMRI

Filter

D/A

Converter

LPF

+ +

ATT

Expan-

der

ADPCM

Decoder

PCMRO IR

DIO

Noise

Generator

Power Detect

Serial

Controller

SAD

SAS TAS

RWCK CS1

To various units

To receive unit

CS2

PDN

MCK

MLV0

MLV1

MLV2

MUTE

VOXI

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PIN CONFIGURATION (TOP VIEW)

DIOWENC

SAD 60

SAS

TAS

RWCK

CS1

CS2NCBCLK

RSYNC

XSYNCNCDG

AG NC

SAO

NC NC

VFRO

PWI AOUT– AOUT+

SGR

SGT

AIN1–

GSX1

AIN+

10 11 12 13 14 15 16

32 NC

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

NC PCMSO PCMSI NC IS IR NC PCMRO PCMRI NC MCK

PDN RESET

DOUT DIN NC

1 2 3 4 5 6 7 8 9

GSX2

AIN2

MLV2

MLV1

MLV0

MUTE

VOXI

VOXO

DEN

EXCK

NC : No connect pin

64-Pin Plastic TQFP

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PIN DESCRIPTIONS

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I Receive side PCM signal input

Symbol

AG NC

SAO

NC NC

VFRO

PWI AOUT– AOUT+

SGR

SGT

AIN1–

GSX1

AIN1+

NC NC

GSX2

AIN2

NC MLV2 MLV1 MLV0 MUTE

VOXI

VOXO

DEN

EXCK

DIN

DOUT

RESET

PDN

MCK

PCMRI

Type Description

I Analog ground

— No connection

O Receive side sounder amplifier output — No connection — No connection

O Receive side voice output

I Receive side voice amplifier input O Receive side voice amplifier output (–) O Receive side voice amplifier output (+) O Receive side analog signal ground

— No connection

O Transmit side analog signal ground

I Transmit side amplifier 1 inverting input O Transmit side amplifier 1 output

I Transmit side amplifier 1 non-inverting input

— No connection — No connection

O Transmit side amplifier 2 output

I Transmit side amplifier 2 inverting input

I Power supply

— No connection

I Receive side voice path mute level set

I Receive side voice path mute enable signal input

— No connection

I Receive side voice/silence detect function input O Transmit side voice/silence detect function output

— No connection

I Enable signal input for control register

I Clock signal input for control register

— No connection — No connection

I Address and data input for control O Data output for control register

I RESET control input for control register

I Power down control input

I Master clock input

— No connection

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PIN DESCRIPTIONS (Continued)

41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 — No connection

Symbol

PCMRO

IR IS

PCMSI

PCMSO

NC XSYNC RSYNC

BCLK

CS2 CS1

RWCK

TAS SAS

SAD

DIO

Type Description

O Receive side PCM signal output

— No connection

I Receive side ADPCM signal input

O Transmit side ADPCM signal output

— No connection

I Transmit side PCM signal input

O Transmit side PCM signal output

— No connection

I Digital ground

— No connection

I Transmit side PCM and ADPCM data sync signal input I Receive side PCM and ADPCM data sync signal input I PCM and ADPCM data shift clock input

— No connection

O Voice ROM chip select output O Serial register chip select output O Serial register data clock output O Serial register transfer address-strobe output O Serial register address-strobe output O Serial register address data output

— No connection

O Serial register write enable output

I/O Serial register data input/output

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PIN AND FUNCTIONAL DESCRIPTIONS

AIN1+, AIN1-, AIN2, GSX1, GSX2

The transmit analog input and the output for transmit gain adjustment. The pin AIN1– (AIN2) connects to inverting input of the internal transmit amplifier, and the pin AIN1+ connects to non-inverting input of the internal transmit amplifier. The pin GSX1 (GSX2) connects to output of the internal transmit amplifier. Gain adjustment should be referred to Fig. 1.

VFRO, AOUT+, AOUT-, PWI

Used for the receive analog output and the output for receive gain adjustment. VFRO is an output of the receive filter. AOUT+ and AOUT– are differential analog signal outputs which can directly drive ZL = 350 W+120 nF or the 1.2 kW load. Gain adjustment should be referred to Fig. 1. These outputs are in high impedance state during power down.

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SAO

Differential analog output for a sounder. Variable tones including "Audio sound", "DTMF tone", "S tone", "F tone", and "R tone", and telephone call signals can be output to either VFRO pin or SAO pin by CR0 - B1 of the control register. These output pins are in the high impedance state during power down.

Differential analog input signal

+ –

= 120 nF

+ 350 W

Transmit gain : (V = (R2/R1) ¥ (R4/R3)

Receive gain : (V = 2 ¥ (R6/R5)

C1 R1

GSX2/VI

Analog output signal Vo

)

VFRO

AIN1–

AIN1+

GSX1

SGT AIN2

GSX2

AOUT+

AOUT–

PWI

VFRO

–

–1

–

Reference

voltage

generator

to ENCODER

from DECODER

Sounder output signal

Figure 1 Analog Interface

SAO

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¡ Semiconductor MSM7708-02

SGT, SGR

Outputs of the analog signal ground voltage. SGT outputs the analog signal ground voltage of the transmit system, and SGR outputs the same for the receive system. The output voltage value is approximately 1.4 V. Connect bypass 10 mF and 0.1 mF (ceramic type) capacitors between these pins and the AG pin. To reduce the response time of the receiver power on, it is recommended to apply 1 mF and 0.1 mF bypass capacitors. During power down, the output changes to 0 V.

Power supply.

DG, AG

Ground. DG is the digital system ground. AG is the analog system ground. Since DG and AG are separated in the device, connect them as close as possible on the circuit board.

PDN

Power down control input. When set to a digital "0", the system changes to the power down state and control register is not reset. Since the power down mode is controlled by CRC0 - B5 of the control register ORed with the signal from the PDN pin, set CRC0 - B5 to digital "0" when using this pin.

RESET

Reset control input of the CODEC control register. When set to digital "0," each bit of the control register is reset and the internal circuit changes to the power down state. During normal operation, set this pin to digital "1".

MCK

Master clock input. The clock frequency is 19.2 MHz. MCK can be asynchronous with XSYNC, RSYNC, and BCLK.

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PCMSO

Transmit PCM data output. This PCM output signal is output from MSB synchronously with the rising edge of BCLK and XSYNC.

PCMSI

Transmit PCM data input. This signal is converted to the ADPCM data. The PCM signal is shifted in on the falling edge of BCLK. Normally, this pin is connected to PCMSO.

PCMRO

Receive PCM data output. This PCM signal is the output signal after ADPCM decoder processing. This signal is serially output from MSB synchronously with the rising edge of BCLK and RSYNC.

PCMRI

Receive PCM data input. This PCM input signal is shifted in on the rising edge of BCLK and is input from MSB. Normally, this pin is connected to PCMRO.

Transmit ADPCM signal output. This signal is the output signal after ADPCM encoding, and is serially output from MSB synchronously with the rising edge of BCLK and XSYNC. This pin is an open drain output which remains in a high impedence state during power down. It requires pull-up resistor.

Receive ADPCM signal input. This input signal is shifted in serially on the rising edge of BCLK synchronously with RSYNC and is input from MSB.

BCLK

Shift clock input for the PCM data (PCMSO, PCMSI, PCMRO, PCMRI) and the ADPCM data(IS, IR) . The frequency is in the 64 kHz to 2048 kHz range.

XSYNC

8 kHz synchronous signal input for transmit PCM and ADPCM data. This signal should be synchronized with BCLK. XSYNC is used for indicating the MSB of the transmit serial PCM and ADPCM data stream.

RSYNC

8 kHz synchronous signal input for receive PCM and ADPCM data. This signal should be synchronized with BCLK signal. RSYNC is used for indicating the MSB of the receive serial PCM and ADPCM data stream.

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(b)

VOXO

Transmit side voice/silence detect signal output. This output is valid when CR6 - B7 is set to "1". VOXO shows the presence or absence of the transmit voice signal by detecting the signal. "1" and "0" set to this pin correspond to the presence and the absence, respectively. This result also appears at the register data CR7 - B7. The signal detect threshold is set by the control register CR6 - B6, B5. When control register CR0 - B6 is set to "1" and VOXI input is "1" during the voice detection (VOXO = "1"), receive signal is automatically suppressed by 6 dB.

VOXI

Receive side voice/silence detect signal input. This output is valid when CR6 - B7 is set to "1". A "1" level at VOXI indicates the presence of voice signal, in which case the decoder block processes normal receive signal and the voice signal appears at analog output pins. A "0" level indicates the absence of voice signal, in which case the background noise generated in this device is transferred to the analog output pins. The background noise amplitude is set by the control register CR6 - B1, B0. Since this signal is ORed with the register CR6 - B3, set the control register CR6 - B3 to "0" when using this pin. When control register CR0 - B6 is set to "1" and VOXI input is "1" during the voice detection (VOXO = "1") receive signal is automatically suppressed by 6 dB.

Input voice signal

GSX2

VOXO pin

VOXI pin

Regenerated voice

VFRO

Voice Silence Voice

Voice Detection Time T

VXON

(a) Transmission Side Voice/Silence Detect Function Timing Diagram

Voice Silence Voice

Silence Detection Time (Hangover Time) T

VXOFF

Regenerated Voice Signal

Generation Time

Receive Side Voice/Silence Detect Function Timing Diagram

Internal Background

Noise Generation Time

Note: The VOXO and VOXI pin functions are enabled when CR6 - B7 is set to "1".

Figure 2 Voice/Silence Detect Function

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¡ Semiconductor MSM7708-02

DEN, EXCK, DIN, DOUT

Serial control ports for MCU interface. Reading and writing data is performed by an external CPU through these pins. 14-byte control registers (CR0 - 13) are provided in this device. DEN is the "Enable" control signal input, EXCK is the data shift clock input, DIN is the address and data input, and DOUT is the data output. Input/output timing is shown in Fig. 3.

DEN EXCK

DIN

DOUT

DEN

EXCK

DIN

DOUT

R A2A1A0

High Impedance

A1 A0 B7 B6 B5 B4 B3 B2 B1 B0

High Impedance

(a) Write Data Timing Diagram

B7 B6 B5 B4 B3 B2 B1 B0

(b) Read Data Timing Diagram

Figure 3 MCU Interface Input/Output Timing

MUTE

This pin is used to enable the receive side voice path mute level. To set the mute level, set this pin to "1".

MLV0, MLV1, MLV2

This pin is used to set the receive side voice path mute level. For the control method, refer to the control register description (CR1). Since these signals are ORed with CR1 - B2, B1, and B0 internally, set these register data to "0" when using this pin.

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The register map is shown in Table 1.

Table 1 Control Register (CR0 to CR13) Map

Name

CR0 0 0

CR1 0 001

CR2 0 100

CR3 0 101

CR4 0 010

CR5 0 011

CR6 0 110

CR7 0 111

CR8 1 000

CR9 1 001

Address

A3 A1

GAIN3TXGAIN2

Side Tone

OTHERS SEL

SEND/

ON/OFFONLVL1

A/m

SEL

MUTERXON/OFF

GAIN2

DTMF/

REC VOX

VOX OUT

ST0 ST1

ST8 ST9

B6 B5 B4 B3 B2 B1 B0

Spprs

Side Tone

GAIN1

TONE SEND

ROW/

SILENCE

LVL1

Data Description

PDN

ALL

ADPCM

RESETTXON/OFFRXMUTERXMLV2RXMLV1RXMLV0

GAIN1TXGAIN0RXGAIN3RXGAIN2RXGAIN1RXGAIN0

Side Tone

GAIN0

TONE5 4M8M/

LVL0

SILENCE

LVL0

ST2 ST3 ST4 ST5 ST6 ST7

ST10 ST11 ST12 — — —

PDN

TONE

ON/OFF

TONE4 TONE3 TONE2 TONE1 TONE0

—

OFF

TIME

— — — BUSY RPM

PDNRXSA,VF

OUT

TONE

GAIN3

— — CMD1 CMD0

VOX

TONE

GAIN2

RX NOISE

LEVEL SEL

SAO/

VFRO

TONE

GAIN1

RX NOISE

LVL1

GAIN0

RX NOISE

AOUT

PON

TONE

LVL0

R/W

CR10 1 100

CR11 1 101

CR12 1 010

CR13 1 011

SPY0 SPY1

SP0 SP1

SP8 SP9

CH0 CH1

SPY2 SPY3 SPY4 SPY5 SPY6 SPY7

SP2 SP3 SP4 SP5 SP6 SP7

SP10 SP11 SP12 — — —

CH2 CH3 CH4 — ADRD ADWT

Note : Details are explained in the Control Register Description.

R/W: Both read and write are supported R: Read-only register

R/W

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