OKI MSM7705-03GS-2K, MSM7705-01GS-2K, MSM7705-02GS-2K Datasheet

E2U0042-28-81

¡ Semiconductor MSM7705-01/02/03

¡ Semiconductor

This version: Aug. 1998

Previous version: Nov. 1996

MSM7705-01/02/03

4ch Single Rail CODEC

GENERAL DESCRIPTION

The MSM7705-01/02/03 are four-channel CODEC CMOS ICs for voice signals ranging from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, these devices contain four-channel A/D and D/A converters in a single chip and achieve a reduced footprint and a reduced number of external components. The MSM7705-01/02/03 are best suited for digital telephone terminals, digital PABXs, and pushbutton phones.

FEATURES

• Single power supply: +5 V

• Power consumption Operating mode: 70 mW Typ. 140 mW Max. Power-saving mode: 14 mW Typ. 32 mW Max. Power-down mode: 0.05 mW Typ. 0.3 mW Max.

• Conforms to ITU-T Companding law

MSM7705-01: m/A-law pin-selectable MSM7705-02: m-law MSM7705-03: A-law

• Built-in PLL eliminates a master clock

• The PCM interface can be switched between 4 channel serial/parallel

• Transmission clock: 64/128/256/512/1024/2048 kHz

96/192/384/768/1536/1544 kHz (During 4 channel serial mode, the 64, 96, 128, and 192 kHz clocks are disabled)

• Transmit gain adjustable for each channel

• Built-in reference voltage supply

• Analog output can directly drive a 600 W line transformer

• Package: 44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name : MSM7705-01GS-2K)

(Product name : MSM7705-02GS-2K) (Product name : MSM7705-03GS-2K)

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¡ Semiconductor MSM7705-01/02/03

BLOCK DIAGRAM

AIN1

GSX1

AIN2

GSX2

AIN3

GSX3

AIN4

GSX4

AOUT1

AOUT2

AOUT3

AOUT4

SGC

– +

LPF

8th

BPF

CONV.

TCONT

– +

LPF

8th

BPF

AUTO ZERO

– +

LPF

8th

BPF

CONV.

PLL

DOUT1 DOUT2

DOUT3 DOUT4

XSYNC

BCLK

(ALAW)

CHPS

– +

LPF

8th

BPF

AUTO ZERO

RTIM

– +

5th

LPF

S&H

RSYNC

CONV.

– +

5th

LPF

S&H

RCONT

DIN1 DIN2 DIN3

– +

5th

LPF

S&H

DIN4

CONV.

– +

5th

LPF

S&H

PWD

PDN

Logic

GEN

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¡ Semiconductor MSM7705-01/02/03

PIN CONFIGURATION (TOP VIEW)

(

AIN3

GSX3

GSX4

AIN4

SGC

AOUT1

AOUT2

AOUT3

AOUT4 44

NC NC

(

NC NC

5 6 7

33 32 31 30 29 28 27

AIN2 GSX2 GSX1 AIN1 NC NC

NC DIN4 DIN3 DIN2 DIN1

10 11

8 9

XSYNC

RSYNC

BCLK

NC : No connect pin

44-Pin Plastic QFP

(

DOUT4

DOUT3

DOUT2

26 25 24 23

DOUT1

(ALAW)*

PDN

CHPS

VDD, DG, and AG have two pins each. Each of these pairs are internally connected with each other. * The ALAW pin is only supported by MSM7705-01GS-2K.

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¡ Semiconductor MSM7705-01/02/03

PIN AND FUNCTIONAL DESCRIPTIONS

AIN1, AIN2, AIN3, AIN4, GSX1, GSX2, GSX3, GSX4

AIN1, AIN2, AIN3, and AIN4 are the transmit analog inputs for channels 1, 2, 3 and 4 respectively. GSX1, GSX2, GSX3, and GSX4 are the transmit level adjustments for channels 1, 2, 3 and 4 respectively. AIN1, AIN2, AIN3, and AIN4 are connected to the inverting inputs for the op-amps. GSX1, GSX2, GSX3, and GSX4 are connected to the outputs for the op-amps. They are used to adjust levels as shown below, and are connected to the outputs of the op-amps. During power saving mode and power down mode, the GSX1, GSX2, GSX3, and GSX4 outputs are at 0 V. When these pins are not used, connect AIN1 to GSX1, AIN2 to GSX2, AIN3 to GSX3, and AIN4 to GSX4.

CHn Analog Input

R2n

C1n R1n

GSXn AINn

CHn Gain – +

Gain = R2n/R1n £ 10

R1n: Variable

R2n > 20 k

C1n > 1/(2 ¥ 3.14 ¥ 30 ¥ R1n) (F)

AOUT1, AOUT2, AOUT3, AOUT4

AOUT1, AOUT2, AOUT3, and AOUT4 are the receive filter outputs for channels 1, 2, 3, and 4 respectively. When the digital signal of +3 dBm0 is input to DIN1, DIN2, DIN3, and DIN4, the output signal has an amplitude of 3.4 VPP above and below the signal ground voltage (SG : 1/2 VDD). The output can drive a load of 600 W or more. During power saving or power down mode, these outputs are at the voltage level of SG with a high impedance.

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¡ Semiconductor MSM7705-01/02/03

DIN1, DIN2, DIN3

PCM signal inputs for channels 1, 2, and 3 when the parallel mode is selected. D/A conversion is performed by the serial PCM signals to these pins, the RSYNC signals synchronous with the serial PCM signals, and the BCLK signal. Then the analog signals are output from AOUT1, AOUT2, and AOUT3 pins, respectively. The data rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. When the serial mode is selected, this pin is not used and should be connected to GND (0 V).

DIN4

PCM signal input for channel 4 when the parallel mode is selected. D/A conversion is performed by the serial PCM signal to this pin, the RSYNC signal synchronous with the serial PCM signal, and the BCLK signal. Then the analog signal is output from AOUT4 pin. The data rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. When the serial mode is selected, this pin is used for the 4ch multiplexed PCM signal input.

BCLK

Shift clock signal input for DIN1, DIN2, DIN3, DIN4, DOUT1, DOUT2, DOUT3, and DOUT4. The frequency is equal to the data rate. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state.

RSYNC

Receive synchronizing signal input. Eight bits of PCM data required are selected from a series of PCM signal to the DIN1, DIN2, DIN3, and DIN4 pins by the receive synchronizing signal. All timing signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLK (generated from the same clock source as

BCLK). The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are

mainly the frequency characteristics of the receive section. However, this device operates in the range of 6 kHz to 10 kHz unless the frequency characteristics of the system used are strictly specified, but the electrical characteristics specified in the data sheet are not guaranteed.

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¡ Semiconductor MSM7705-01/02/03

XSYNC

Transmit synchronizing signal input. PCM output signal from the DOUT1, DOUT2, DOUT3, and DOUT4 pins is output in synchronization with this transmit synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. This synchronizing signal must be synchronized in phase with BCLK.

The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly

the frequency characteristics of the transmit section. However, this device can be operated in the range of 6 kHz to 10 kHz unless the frequency characteristics of the system used are strictly specified, but the electrical characteristics are not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to power saving state.

DOUT1

PCM signal output of channel 1 when the parallel mode is selected. The PCM output signal is output from MSD in a sequential order, synchronizing with the rising edge of the BCLK signal. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power-saving state or power-down state. When the serial mode is selected, this pin is configured to be the output of serial multiplexed 4ch PCM signal. A pull-up resistor must be connected to this pin because it is an open drain output. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7705-03 (A-law) outputs the character signal, inverting the even bits.

Input/Output Level

+Full scale

+0 –0

–Full scale

PCMIN/PCMOUT

MSM7705-02 (m-law)

MSD 1000 0000 1111 1111 0111 1111 0000 0000

MSM7705-03 (A-law)

MSD 1010 1010 1101 0101 0101 0101 0010 1010

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