OKI MSM7704-01GS-K, MSM7704-02GS-K, MSM7704-03GS-K Datasheet

E2U0021-28-81

¡ Semiconductor MSM7704-01/02/03

¡ Semiconductor

This version: Aug. 1998

Previous version: Nov. 1996

MSM7704-01/02/03

2ch Single Rail CODEC

GENERAL DESCRIPTION

The MSM7704-01/7704-02/7704-03 are two-channel CODEC CMOS ICs for voice signals ranging
from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, these devices
contain two-channel AD/DA converters in a single chip and achieve a reduced footprint and a
reduced number of external components.
The MSM7704-01/7704-02/7704-03 are best suited for an analog interface to an echo canceller
DSP used in digital telephone terminals, digital PABXs, and hands free terminals.

FEATURES

• Single power supply: +2.7 V to +3.8 V

• Power consumption
Operating mode: 30 mW Typ. 50 mW Max.
Power-saving mode: 3 mW Typ. 6 mW Max.
Power-down mode: 0.03 mW Typ. 0.3 mW Max.

• ITU-T Companding law

MSM7704-01: m/A-law pin-selectable
MSM7704-02: m-law
MSM7704-03: A-law

• Built-in PLL eliminates a master clock

• The PCM interface can be switched between 2 channel serial/parallel

• Transmission clock: 64/128/256/512/1024/2048 kHz

96/192/384/768/1536/1544/200 kHz
(During 2 channel serial mode, the 64 and 96 kHz clocks are disabled)

• Adjustable transmit gain

• Built-in reference voltage supply

• Analog output can directly drive a 1.2 kW load

• Package:
24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7704-01GS-K)

(Product name : MSM7704-02GS-K)
(Product name : MSM7704-03GS-K)

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¡ Semiconductor MSM7704-01/02/03

BLOCK DIAGRAM

AIN1

GSX1

AIN2

GSX2

AOUT1

AOUT2

SGC

–
+

–
+

–
+

–
+

SG

GEN

5th

LPF

5th

LPF

RC

LPF

RC

LPF

VR

GEN

8th

BPF

8th

BPF

S&H

S&H

AUTO
ZERO

DA

CONV.

AD

CONV.

TCONT

PLL

RTIM

RCONT

PWD

Logic

DOUT1
DOUT2

XSYNC

BCLK

RSYNC

(ALAW)

CHPS
DIN1
DIN2

PDN

V

DD

AG
DG

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¡ Semiconductor MSM7704-01/02/03

PIN CONFIGURATION (TOP VIEW)

SGC

1

AOUT2

AOUT1

CHPS

RSYNC

2

NC

3

4

PDN

5

6

NC AG

7

V

8

DD

DG

9

10

DIN2

11

DIN1

12 13

NC : No connect pin

24-Pin Plastic SOP

24

23

22

21

20

19

18

17

16

15

14

AIN2

GSX2

GSX1

AIN1

NC

(ALAW)*

NC

BCLK

XSYNC

DOUT2

DOUT1

* The ALAW pin is only applied to the MSM7704-01GS-K.

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¡ Semiconductor MSM7704-01/02/03

PIN AND FUNCTIONAL DESCRIPTIONS

AIN1, AIN2, GSX1, GSX2

AIN1 and AIN2 are the transmit analog inputs for channels 1 and 2.
GSX1 and GSX2 are the transmit level adjustments for channels 1 and 2.
AIN1 and AIN2 are inverting inputs for the op-amps. GSX1 and GSX2 are connected to the
outputs of the op-amps and are used to adjust the level, as shown below.
When AIN1 and AIN2 are not used, connect AIN1 to GSX1 and AIN2 to GSX2. During power
saving mode and power down mode, the GSX1 and GSX2 outputs are in high impedance state.

CH1
Analog Input

CH2
Analog Input

R2

C1 R1

R4

C2 R3

GSX1

AIN1

GSX2

AIN2

CH1 Gain
–
+

–
+

Gain = R2/R1 £ 10

R1: Variable

R2 > 20 kW

C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)

CH2 Gain

Gain = R4/R3 £ 10

R3: Variable

R4 > 20 kW

C2 > 1/(2 ¥ 3.14 ¥ 30 ¥ R3)

AOUT1, AOUT2

AOUT1 is the receive analog output for channel 1 and AOUT2 is used for channel 2.
The output signal has an amplitude of 2.0 VPP above and below the signal ground voltage (SG
: 1/2 VDD). When the digital signal of +3 dBmO is input to DIN1 and DIN2, it can drive a load
of 1.2 kW or more.
During power saving mode, or power down mode, these outputs are at the voltage level of SG
with a high impedance.

V

DD

Power supply for +3 V.
A power supply for an analog circuit in the system to which the device is applied should be used.
A bypass capacitor of 0.1 mF to 1 mF with excellent high-frequency characteristics and a capacitor
of 10 mF to 20 mF should be connected between this pin and the AG pin if needed.

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¡ Semiconductor MSM7704-01/02/03

DIN1

PCM signal input for channel 1 when the parallel mode is selected.
D/A conversion is performed with the serial PCM signal input to this pin, the RSYNC signal
synchronous with the serial PCM signal, and the BCLK signal, and then the analog output is
output from AOUT1 pin.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
When the serial mode is selected, this pin is not used and should be connected to GND (0 V).

DIN2

PCM signal input for channel 2 when the parallel mode is selected.
D/A conversion is performed with the serial PCM signal input to this pin, the RSYNC signal
synchronous with the serial PCM signal, and the BCLK signal, and then the analog output is
output from AOUT2 pin.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
When the serial mode is selected, this pin is used for the 2ch multiplexed PCM signal input.

BCLK

Shift clock signal input for the DIN1, DIN2, DOUT1, and DOUT2 signals.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,
or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the
power saving state.

RSYNC

Receive synchronizing signal input.
Eight bits PCM data required are selected from a series of PCM signal to the DIN1 and DIN2 pins
by the receive synchronizing signal.
All timing signals in the receive section are synchronized by this synchronizing signal. This
signal must be synchronized in phase with the BCLK (generated from the same clock source as

BCLK). The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are

mainly the frequency characteristics of the receive section.
However, unless the frequency characteristics of the system used are strictly specified, this
device can operate in the range of 6 kHz to 9 kHz, but the electrical characteristics specified in
the data sheet are not guaranteed.

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¡ Semiconductor MSM7704-01/02/03

XSYNC

Transmit synchronizing signal input.
PCM output signal from the DOUT1 and DOUT2 pins is output in synchronization with this
transmit synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all
timing signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLK.

The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly

the frequency characteristics of the transmit section.
However, unless the frequency characteristics of the system used are strictly specified, this
device can operate in the range of 6 kHz to 9 kHz, but the electrical characteristics are not
guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to power saving
state.

DOUT1

PCM signal output of channel 1 when the parallel mode is selected.
The PCM output signal is output from MSD in a sequential order, synchronizing with the rising
edge of the BCLK signal.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK
and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power-saving state or power-down state.
When the serial mode is selected, this pin is configured to be the output of serial multiplexed 2ch
PCM signal.
A pull-up resistor must be connected to this pin because it is an open drain output.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7704-03 (A-law) outputs the character signal, inverting the even bits.

Input/Output Level

+Full scale

+0

–0

–Full scale

PCMIN/PCMOUT

MSM7704-02 (m-law)

MSD

1000 0000

1111 1111

0111 1111

0000 0000

MSM7704-03 (A-law)

MSD

1010 1010

1101 0101

0101 0101

0010 1010

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