OKI MSM7702-02MS-K, MSM7702-03GS-K, MSM7702-01MS-K, MSM7702-03MS-K, MSM7702-02GS-K Datasheet

E2U0018-28-81

¡ Semiconductor MSM7702-01/02/03

¡ Semiconductor

This version: Aug. 1998

Previous version: Nov. 1996

MSM7702-01/02/03

Single Rail CODEC

GENERAL DESCRIPTION

The MSM7702 is a single-channel CODEC CMOS IC for voice signals ranging from 300 to 3400
Hz with filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, the device is
optimized for telephone terminals in digital wireless systems or ISDN systems.
The MSM7702 utilizes low-voltage operational amplifiers (Op-amps) to provide low-power
consumption.
The device uses the same transmission clocks as those used in the MSM7508B and MSM7509B.
The analog output signal can directly drive a piezoelectric type handset receiver.

FEATURES

• Single power supply: +2.7 V to +3.8 V

• Low power consumption
Operating mode: 15 mW Typ. VDD = 3 V
Power save mode: 3.6 mW Typ. VDD = 3 V
Power down mode: 0.05 mW Typ. VDD = 3 V

• ITU-T Companding law

MSM7702-01: m/A-law pin selectable
MSM7702-02: m-law
MSM7702-03: A-law

• Built-in PLL eliminates a master clock

• Serial data rate: 64/128/256/512/1024/2048 kHz

96/192/384/768/1536/1544/200 kHz

• Adjustable transmit gain

• Built-in reference voltage supply

• Analog output can directly drive a load equivalent to 1.2 kW

• Pin-for-pin compatible with the MSM7578 and MSM7579

• Package options:
24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7702-01GS-K)

(Product name : MSM7702-02GS-K)
(Product name : MSM7702-03GS-K)

20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name : MSM7702-01MS-K)

(Product name : MSM7702-02MS-K)
(Product name : MSM7702-03MS-K)

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¡ Semiconductor MSM7702-01/02/03

BLOCK DIAGRAM

AIN–
AIN+

GSX

SGC

SG

AOUT

–
+

–
+

SG

RC

LPF

SG

GEN

8th

BPF

VR

GEN

5th

LPF

CONV.

DA

CONV.

PWD

AD

AUTO
ZERO

TCONT

PLL

RTIM

RCONT

PWD

Logic

PCMOUT

XSYNC

BCLK

RSYNC
(ALAW)

PCMIN

PDN
V

DD

AG
DG

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¡ Semiconductor MSM7702-01/02/03

PIN CONFIGURATION (TOP VIEW)

SGC

NC

SG

NC

AOUT

V

DD

DG

NC

NC

PDN

RSYNC

PCMIN

1

2

3

4

5

6

7

8

9

10

11

12 13

NC : No connect pin

24-Pin Plastic SOP

24

23

22

21

20

19

18

17

16

15

14

AIN+

AIN–

NC

GSX

NC

(ALAW)*

AG

NC

BCLK

NC

XSYNC

PCMOUT

1

SGC

2

SG

AOUT

RSYNC

PCMIN

3

4

V

DD

5

NC

6

NC

7

DG

8

PDN

9

10 11

NC : No connect pin

20-Pin Plastic SSOP

20

19

18

(ALAW)*

17

16

15

14

13

12

* The ALAW pin is only applied to the MSM7702-01GS-K/MSM7702-01MS-K.

AIN+

AIN–

GSX

NC

NC

AG

BCLK

XSYNC

PCMOUT

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¡ Semiconductor MSM7702-01/02/03

PIN AND FUNCTIONAL DESCRIPTIONS

AIN+, AIN–, GSX

Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp and is used to adjust the level, as shown below.
When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving
and power down modes, the GSX output is at AG voltage.

1) Inverting input type

AG

C1

Analog input

R1

2) Non inverting input type

C2

Analog input

R5

R3

R2

R4

GSX
AIN–
AIN+
SG

AIN+
AIN–
GSX

SG

R1 : variable

–
+

+
–

R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)

Gain = R2/R1 £ 10

R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5)

Gain = 1 + R4 / R3 £ 10

Analog signal ground.

AOUT

Analog output.
The output signal has a maximum amplitude of 2.0 VPP above and below the signal ground
voltage (VDD/2).
The output load resistance is a minimum of 1.2 kW.
During power saving or power down mode, the output of AOUT is at the voltage level of the
signal ground.

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¡ Semiconductor MSM7702-01/02/03

V

DD

Power supply for +2.7 V to +3.8 V. (Typically 3.0 V)

PCMIN

PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at a falling edge of the BCLK signal and latched into the internal register
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.

BCLK

Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,
or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the
power saving state.

RSYNC

Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be

synchronized in phase with the BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the

AC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device

can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are

not guaranteed.

XSYNC

Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this transmit
synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing
signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLK.

The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly

the frequency characteristics of the transmit section.
However, if the frequency characteristic of an applied system is not specified exactly, this device

can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are

not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving
state.

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¡ Semiconductor MSM7702-01/02/03

DG

Ground for the digital signal circuits.
This ground is separate from the analog signal ground. The DG pin must be connected to the AG
pin on the printed circuit board to make a common analog ground.

PDN

Power down control signal.
A logic "0" level drives both transmit and receive circuits to a power down state.

PCMOUT

PCM signal output.
The PCM output signal is output from MSD in a sequential order, synchronizing with the rising
edge of the BCLK signal.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK
and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power saving or power down.
A pull-up resistor must be connected to this pin because its output is configured as an open drain.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7702-03 (A-law) outputs the character signal, inverting the even bits.

Input/Output Level

+Full scale

+0

–0

–Full scale

PCMIN/PCMOUT

MSM7702-02 (m-law)

MSD

1000 0000

1111 1111

0111 1111

0000 0000

MSM7702-03 (A-law)

MSD

1010 1010

1101 0101

0101 0101

0010 1010

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