OKI MSM7586-01TS-K, MSM7586-03TS-K Datasheet

E2U0034-28-82

¡ Semiconductor MSM7586-01/03

¡ Semiconductor

This version: Aug. 1998

Previous version: Nov. 1996

MSM7586-01/03

p/4 Shift QPSK MODEM/ADPCM CODEC

GENERAL DESCRIPTION

The MSM7586 is a CMOS IC developed for use with digital cordless telephones. The device
provides a p/4 shift QPSK modem function and a CODEC function which performs transcoding
between the voice band analog signal and 32 kbps ADPCM data.
The MSM7586 performs DTMF tone and several types of tone generation, transmit/receive data,
mute and gain control, side-tone pass and its gain control, and VOX function.

FEATURES

(p/4 Shift QPSK Modem Unit)

• 384 kbps transmission speed

• Built-in root Nyquist digital filter for the baseband band limiter

• Built-in D/A converters for the analog outputs of the quadrature signal component I and Q

• The DC offset and gain can be adjusted with respect to the differential I and Q analog outputs

• Completely digitized p/4 shift QPSK demodulator system

(ADPCM CODEC Unit)

• ADPCM system: built-in ITU-T Recommendations G.726 (32kbps, 24 kbps, 16 kbps)

• Transmit/receive full-duplex capability

• PCM interface code format: selectable between m-law and A-law

• Serial ADPCM and PCM transmission rate: 64 kbps to 2,048 kbps

• Transmit/receive mute function; transmit/receive programmable gain setting

• Side tone generator (8-step level adjustment)

• Built-in DTMF tone, ringing tone, and various ringing tone generators

• Built-in VOX function

(Common Unit)

• Operate with a single 3 V power supply (VDD: 2.7 V to 3.6 V)

• Low power consumption
When entire system is operating: 20 mA Typ.
When powered down: 0.02 mA Typ.

• Package:
100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name: MSM7586-01TS-K)

(Product name: MSM7586-03TS-K)

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¡ Semiconductor MSM7586-01/03

BLOCK DIAGRAM

PDN0
PDN1
PDN2

IFIN

MCK

IFCK

EXCKM

DENM

DINM

DOUTM

R7, R6
R5, R4

SGM

SGCR

SGCT

IO1

IO2

AIN1–
AIN1+

GSX1

AIN2–

GSX2

AOUT+

AOUT–

PWI

VFRO

SAO

AIN3

GSX3

AIN4

GSX4

X2

X1

Q+

Q–

VDAM

Phase
detector

VDDM

DGM

AGM

Delay
detector

SL1

SL2

AFC

RXSC

Decision

AFC

RXD

RXC

SL1

To each block

SL2

MODEM
MCU

To each block

interface

4

I+

I–

+1

–1

+1

–1

DC Adjust

DC Adjust

SW1

SW2

T

CRC4-B5

–
+

–
+

–1

CRC5-B7
CRC5-B6

VDAC

–
+

R

–
+

R

–
+

T

LPF

LPF

R

T

RC

Filter

RC

Filter

CRC5-B5

SW3

CRM1-B7 to B4

ATT

CRM1-B3 to B0

ATT

Receiver
Transmitter

Convertor

Convertor

SW4

VREF

A/D

D/A

CRC5-B4

D/A

D/A

BPF

CRC3-B7 to B5

LPF

Noise

generator

SW5

Root Nyquist LPF

<MODEM Unit>

<CODEC Unit>

CRC4-B6

ATT

+

+

Power detect

CRC2-B6 to B4

ATT

Sign bit

CRC3-B3 to B0

CRC2-B2 to B0

ATT

To each

block

3.84M

DTMF
/Tone
Generator

To D/A

VOICE
DETECT

COMPA
NDER

EXPAN

DER

To each
block

DPLLDEC

CRM0-B6

MAPPING

ADPCM
CODER

ADPCM
DE­CODER

S/P

PLL

1/10

CODEC
MCU
interface

384k

P

/

S
S

/

P
P

/

S

S

/

P
P

/

S
S

/

P

RPR

RCW

SLS

BSTO

TXD
TXW

TXCI

TXCO

VOXO
XSYNC

IS

PCMSI

PCMSO

BCLK

PCMRI

PCMRO

IR
RSYNC

EXCKC
DENC
DINC
DOUTC

IO3

IO4

IO5

IO6

IO7

VDDC

VDAC

DGC

AGC

PDN3

VOXI

TOUT1

TOUT2

TOUT3

RESET

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¡ Semiconductor MSM7586-01/03

PIN CONFIGURATION (TOP VIEW)

NC

DENM

EXCKM

DOUTM

DINM

78

77

76

100 VDDM

RXSC

SLS

IFINNCX1NCNCX2IFCK

99

98

97

96

95

9493929190

MCK

PDN0

89

PDN1

PDN2NCRCW

88

87

AFC

RPR

RXC

RXD

86

85

84

83

82

81

80

79

VDAM

Q–
Q+

NC
SGM
AGM

AGC

SGCR

SGCT
AIN1+
AIN1–

GSX1

IO5
IO6
IO7

AIN2

GSX2

IO1
IO2

VFRO

PWI
AOUT–
AOUT+

1
2
3

I–

4

I+

5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NC
TXW
TXD
TXCO
TXCI
NC
BSTO
DGM
DGC
R7
R6
R5
R4
NC
BCLK
XSYNC
RSYNC
NC
PCMSO
PCMSI
IS
NC
IR
PCMRO
PCMRI

26

SAO

27

AIN3

28

GSX3

29

VDAC

30

VDDC

31

NC

3233343536

NC

AIN4

GSX4

IO3

IO4

37

NC

38

TOUT1

NC : No connect pin

100-Pin Plastic TQFP

39

TOUT2

40

TOUT3

41

PDN3

42

RESET

43

NC

44

DINC

45

46

EXCKC

DOUTC

47

DENC

48

NC

49

VOXI

50

VOXO

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¡ Semiconductor MSM7586-01/03

PIN AND FUNCTIONAL DESCRIPTIONS

(Modem Unit)

TXD

Transmit data input for 384 kbps.

TXCI

Transmit clock input.
When the control register CRM0 - B6 is "0", a 384 kHz clock pulse synchronous with TXD should
be input to this pin. This clock pulse should be continuous because this device use APLL to
generate an internal clock pulse.
When CRM0 - B6 is "1", a 3.84 MHz clock pulse should be input to this pin. When the 3.84 MHz
clock pulse is applied to TXCL, TXCO outputs a 384 kHz clock pulse, which is generated by
dividing the TXCL input by 10. The transmit data, synchronous to the 384 kHz clock pulse,
should be input to the TXD. In this case the devices do not use APLL, and the 3.84 MHz clock pulse
need not be continuous. (Refer to Fig. 1.)

TXCO

Transmit clock output.
When CRM0 - B6 is "0", TXCO outputs the 384 kHz clock pulse (APLL output) for monitoring
purposes. When CRM0 - B6 is "1", this pin outputs a 384 kHz clock pulse generated by dividing
the TXCI input by 10. (Refer to Fig. 1.)

TXW

Transmit data window signal input.
The transmit timing signal for the burst data is input to this pin. If TXW is "1", the modulation
data is output. (Refer to Fig. 1)

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¡ Semiconductor MSM7586-01/03

(1) CRM0 – B6 = "0"

TXD

TXCI
(384 kHz)

TXW

TXCO
(384 kHz)

I, Q

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 Dn-1 D

n

(2) CRM0 – B6 = "1"

TXD

TXCI
(3.84 MHz)

TXW

TXCO
(3.84 kHz)

I, Q

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 Dn-1 D

Ramp rise-up

Delay of 6.25 symbols Delay of 6.25 symbols

Delay of 6.25 symbols Delay of 6.25 symbols

2 symbols

n

Ramp rise-up
2 symbols

Figure 1 Transmit Timing Diagram

Ramp
Fall-down
2 symbols

Ramp
Fall-down
2 symbols

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¡ Semiconductor MSM7586-01/03

BSTO

BSTO is the modulator side burst window output.
The burst position of the I and Q baseband modulator output is output.

I+, I–

Quadrature modulation signal I Component differential analog output.
Their output levels are 500 mVpp (when TXD = "0": 360 mVpp typ.) with 1.6 Vdc as the center

value. The output pin load conditions are: R ≥ 10 kW, C £ 20 pF. The gain of these pins can be

adjusted using the control register CRM1 - B7 to B4, and the offset voltage at the I– pin can be
adjusted using CRM3 - B7 to B3.

Q+, Q–

Quadrature modulation signal Q component differential analog outputs.
Their output levels are 500 mVpp (when TXD = "0": 360 mVpp typ.) with 1.6 Vdc as the center

value. The output pin load conditions are: R ≥ 10 kW, C £ 20 pF. The gain of these pins can be

adjusted using the control register CRM1 - B3 to B0, and the offset voltage at the Q– pin can be
adjusted by using CRM4 - B7 to B3.

SGM

Internal reference voltage output.
The output voltage value is approximately 2.0 V. Insert a bypass capacitor between this pin and
the AGM pin. During power down, this output is at 0 V.
The external SG voltage if necessary should be used via a buffer.

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¡ Semiconductor MSM7586-01/03

PDN0, PDN1, PDN2

Various power down control.
PDN0 controls the standby mode/communication mode; PDN1 controls the modulator unit;
and PDN2 controls the demodulator unit. Refer to Table 1 for details.
The control register reset input width should be 200ns or more.

Table 1: Description of Modem Power Down Control

Standby
Mode

Commu­nication
Mode

PDN0

PDN2 PDN1

0 0/1 1 Mode A

0 0 0 Mode BEntire system is powered down. The control register is not reset.

0 1 0 Mode CModulator unit is powered off. (VREF and PLL also powered off.)

1 0 0 Mode D

1 0 1 Mode EModulator unit is powered on.

1 1 0 Mode FModulator unit is powered off. (VREF and PLL are powered off.)

1 1 1 Mode G

Entire system is powered down. The control register is reset.

Demodulator unit is powered on.
Modulator unit is powered off. (VREF and PLL are powered on.)
I and Q outputs are in a high impedance state.
Only the demodulator clock regenerator unit is powered on.

Only the demodulator clock regenerator unit is powered on.

I and Q outputs are in a high impedance state.
Demodulator unit is powered on.
Modulator unit is powered on.
Demodulator unit is powered on.

Operation State

Mode Name

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¡ Semiconductor MSM7586-01/03

VDDM, VDAM

+3 V power supply for the modem unit.
Supplied to the digital circuits through the VDDM pin and to the analog circuits through the
VDAM pin. VDDM and VDAM, and VDDC and VDAC should be connected as close as possible
on the PC board.

DGM, AGM

Ground pins for the modem unit.
DGM is the ground pin of the digital system, and AGM is the ground pin of the analog system.
Since DGM and AGM are isolated inside the IC, connect them as close as possible on the circuit
board.

MCK

Master clock input.
The clock frequency is 19.2 MHz.

IFIN

Modulated signal input for the demodulator block.
Select the IF frequency can be selected from 1.2 MHz, 10.7 MHz, 10.75 MHz, and 10.8 MHz, based
on CRM0 - B4 and B3.

IFCK

Clock frequency 19.0222 MHz input for demodulator block IF frequencies of 10.7 MHz.
If the IF frequency is 1.2 MHz or 10.8 MHz, set this pin to "0" or "1". (Refer to Fig. 2.)

X1, X2

Crystal oscillator connection pins.
When supplying a 19.0222 MHz clock to IFCK, use these pins. (Refer to Fig. 2.)

When IFIN = 10.7 MHz

MSM7586

When IFIN = 1.2 MHz or 10.8 MHz

MSM7586

X1 X2 IFCK

19.0222 MHz

Figure 2 How to Use IFCK, X1, and X2

X1 X2 IFCK

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¡ Semiconductor MSM7586-01/03

RXD, RXC, RXSC

Receive data and receive clock outputs.
When the modem unit is powered on, RXD, RXC and RXSC are selected based on SLS as shown
in Figure 3. These outputs are used by the clock regenerator circuit.

RXD
RXC

RXSC

SLS

1 Symbol

The regenerated data and clock are
selected asynchronously by the SLS signal.

Figure 3 Timing Diagram of RXD, RXC, and RXSC

SLS

Receive side operation slot selection signal.
This device has two clock regenerator circuits and two AFC data memory registers. If SLS is "0",
slot 1 is selected, if SLS is "1", slot 2 is selected.

RPR

High-speed phase clock control signal input for the clock recovery circuit.
If this pin is at "0", the circuit is always in the low-speed phase clock mode. If this pin is at "1",
the clock recovery circuit enters the high-speed phase clock mode. When the phase difference
is less than a defined value, the circuit shifts to the low-speed phase clock mode automatically.

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¡ Semiconductor MSM7586-01/03

AFC

AFC operation range specification signal input.
As shown in Fig. 4, the AFC information is reset when both AFC and RPR are set to "1". AFC
operation starts after a fixed number of clock cycles and the AFC information is reset. If RPR is
set to "1", an average number of times that AFC turns on is low. If RPR is "0", AFC is high. If AFC
is "0", frequency error is not calculated, but the frequency is corrected using an error that is held.

RCW

Clock recovery circuit operation ON/OFF control signal input.
If RCW this pin is "0", DPLL does not make any phase corrections.

(CASE1)

AFC

RPR

Average number of times
AFC is high.

AFC information
is maintained.

(CASE2)

AFC information
is reset.

Average
number of times
AFC is low.

AFC

RPR

The clock recovery circuit
starts with the previous
AFC information.

"0"

Average number of times
AFC is high.

AFC information
is maintained.

Figure 4 AFC Control Timing Diagram

DENM , EXCKM, DINM, DOUTM

Serial control ports for the microprocessor interface.
The device contains a 6-byte control register (CRM0 - 5). An external CPU uses these pins to read
data from and write data to the control register. DENM is the "Enable" signal input pin. EXCKM
is a data shift clock pulse input pin. DINM is an address and data input pin. DOUTM is a data
output pin. Figure 5 shows input/output timing diagram.

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¡ Semiconductor MSM7586-01/03

,

DENM
EXCKM

W

A2

DINM

A1 A0 B7 B6 B5 B4 B3 B2 B1 B0

DOUTM

DENM

EXCKM

DINM

DOUTM

High Impedance

R A2A1A0

Figure 5 Modem Unit MCU Interface I/O Timing

The register map is shown below.

Table 2: Modem Unit Control Register (CRM0 to 5) Map

Register

Name

CRM0

CRM1

Address

A2 A1 A0

000

001

B7 B6 B5 B4 B3 B2 B1 B0

—

Ich

GAIN3

GAIN2

High Impedance

(a) Write Data Timing Diagram

B7 B6 B5 B4 B3 B2 B1 B0

(b) Read Data Timing Diagram

Data Description

TXC
SEL

Ich

MOD

OFF

Ich

GAIN1

IFSEL1 IFSEL0 — TEST1 TEST0

Ich

GAIN0

Qch

GAIN3

Qch

GAIN2

Qch

GAIN1

R/W

R/W

Qch

R/W

GAIN0

CRM2

CRM3

CRM4

CRM5

010

011

100

101

R7 R6 R5 R4 — — — —

Ich

Offset4

Qch

Offset4

ICT5 ICT4 ICT3 ICT2

Ich

Offset3

Qch

Offset3

Ich

Offset2

Qch

Offset2

Ich

Offset1

Qch

Offset1

Ich

Offset0

Qch
Offset0
LOCAL

INV1

R/W: Read/Write enable R: Read-only register

R7, R6, R5, R4

These are the control register data output pins.
These output the data CRM2 - B7, B6, B5, and B4, respectively.

———

———

LOCAL

INV0

ICT1 ICT0

R/W

R/W

R/W

R/W

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¡ Semiconductor MSM7586-01/03

(CODEC Unit)

AIN1+, AIN1-, AIN2, GSX1, GSX2

The transmit analog input and the output for transmit gain adjustment.
The pin AIN1–(AIN2) connects to the inverting input of the internal transmit amplifier, and the
pin AIN1+ connects to the non-inverting input of the internal transmit amplifier. The pin GSX1
(GSX2) connects to output of the internal transmit amplifier. See Fig. 6 for gain adjustment.

VFRO, AOUT+, AOUT-, PWI

Used for the receive analog output and the output for receive gain adjustment.
VFRO is an output of the receive filter. AOUT+ and AOUT– are differential analog signal outputs
which can directly drive ZL = 350 W+120 nF or the 1.2 kW load. See Fig. 6 for gain adjustment.
However, these outputs are in high impedance state during power down.

SAO, AIN3, AIN4, GSX3, GSX4

Input pins for the internal operational amp.
Refer to Fig.␣ 6 for connection information. However, these output pins are in the high impedance
state during power down.

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¡ Semiconductor MSM7586-01/03

Vi

Differential analog input signal

C1

C1 R1

+
–

= 120 nF

Z

L

+ 350 W

Transmit gain : (V
= (R2/R1) ¥ (R4/R3)

Receive gain : (VO/V
= 2 ¥ (R6/R5)

C2

GSX2

R1

R2

R3

R4

Analog output signal
Vo

/Vi)

VFRO

)

R6

R5

R2

AIN1–

AIN1+

GSX1

SGCT
AIN2

GSX2

AOUT+

AOUT–

VFRO

–

+

Reference

voltage

generator

–

+

to ENCODER

–1

–

+

from

+1

DECODER

Sounder output signal

Sounder output gain : (V
= V

¥ (R8/R7)

SAO

Figure 6 CODEC Unit Analog Interface

GSX3

R7

R8

SAO

AIN3

GSX3

+1

–

+

)

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