OKI MSM7581TS-K Datasheet

E2U0032-28-82

¡ Semiconductor MSM7581

¡ Semiconductor

This version: Aug. 1998

Previous version: Nov. 1996

MSM7581

ITU-T G.721 4ch ADPCM TRANSCODER

GENERAL DESCRIPTION

The MSM7581 is an ADPCM transcoder which is used by the new digital cordless system. It converts 64 kbps voice PCM serial data to 32 kbps ITU-T G.721 ADPCM serial data, and vice versa.

This device is consists of four systems with full-duplex voice data channels and a data-through mode.

The MSM7581 provides cost effective solutions for digital cordless office telephone systems which are incorporated into PABXs, and for the public base stations which are connected to the Central Office through digital PSTNs.

FEATURES

• Conforms to ITU-T G.721

• Built-in Full-duplex Transcoder with Four Data Channels

• PCM companding Law: A-law/µ-law selectable

• Serial PCM Data Transmission Speed: 64 kbps to 2048 kbps

• Serial ADPCM Data Transmission Speed: 32 kbps to 2048 kbps

• Hardware Reset – ITU-T G.721 Optional Reset – for each channel

• Power Down Control for each channel

• Decoder (ADPCM Æ PCM ) Mute Mode and PAD Mode for each channel

• ADPCM Data-through Mode

• Capable of time slot conversion

• Special ADPCM Input Data Code (”0000”) Detector for each channel

• Master Clock Signal : Not necessary

• Power supply voltage/Consumption current : +2.7 V to +5.5 V, 2 mA/channel (max)

• Package : 100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name : MSM7581TS-K)

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BLOCK DIAGRAM

PAD11 PAD10 SYXP1 BCKP1

SIP1

SOP1

SYRP1

RES1

PAD21 PAD20 SYXP2 BCKP2

SIP2

SOP2

SYRP2

RES2

CODER

S→P

DECODER

S←P

CODER

S→P

DECODER

S←P

+2.7 V to 5.5 V

PAD/

MUTE

PAD/

MUTE

PLL

CODER

DECODER

PLL

CODER

DECODER

0 V

MCK

LAW

PLCKENGND

"0000"

DETECT

"0000"

DETECT

CODER

P→S

DECODER

P←S

CODER

P→S

DECODER

P←S

THR1 PLCK1 SYXA1 BCKA1

SOA1

SIA1

DET1

SYRA1

PDN1

THR2 PLCK2 SYXA2 BCKA2

SOA2

SIA2

DET2

SYRA2

PDN2

PAD31 PAD30 SYXP3 BCKP3

SIP3

SOP3

SYRP3

RES3

PAD41 PAD40 SYXP4 BCKP4

SIP4

SOP4

SYRP4

RES4

CODER

S→P

DECODER

S←P

CODER

S→P

DECODER

S←P

PAD/

MUTE

PAD/

MUTE

PLL

MCK

CODER

DECODER

PLL

MCK

CODER

DECODER

"0000"

DETECT

"0000"

DETECT

CODER

P→S

DECODER

P←S

CODER

P→S

DECODER

P←S

THR3 PLCK3 SYXA3 BCKA3

SOA3

SIA3

DET3

SYRA3

PDN3

THR4 PLCK4 SYXA4 BCKA4

SOA4

SIA4

DET4

SYRA4

PDN4

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PIN CONFIGURATION (TOP VIEW)

THR1

PLCK1

SYXA1

SOA1

SIA1

DET1

SYRA1

BCKA1

PDN1

PDN2

BCKA2

SYRA2

DET2

SIA2

SOA2

SYXA2

PLCK2

THR2

PLCKENNCPAD41

PAD40

SYXP4NCBCKP4

SOP4

SIP4

SYRP4

RES4

THR4

PLCK4

SYXA4

SOA4

SIA4

DET4

SYRA4

BCKA4

PDN4

PDN3

BCKA3

SYRA3

DET3

SIA3

SOA3

SYXA3

PLCK3

THR3

RES1

SYRP1

SIP1

SOP1

BCKP1NCSYXP1

100

PAD10

PAD11NCGND

262728

RES2

SYRP2

SIP2

SOP2

BCKP2NCSYXP2

PAD20

PAD21

NC : No connect pin

100-Pin Plastic TQFP

GND

LAW

PAD31

PAD30

SYXP3NCBCKP3

SOP3

SIP3

RES3

SYRP3

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PIN AND FUNCTIONAL DESCRIPTIONS

GND

Ground, 0 V.

SIP1, SOP1

PCM serial data input (SIP1) and output (SOP1) for Channel 1. SOP1 is an open-drain output, which goes into a high impedance state after a continuous 8-bit serial data output.

SIP2, SOP2

PCM serial data input (SIP2) and output (SOP2) for Channel 2. SOP2 is an open-drain output, which goes into a high impedance state after a continuous 8-bit serial data output.

SIP3, SOP3

PCM serial data input (SIP3) and output (SOP3) for Channel 3. SOP3 is an open-drain output, which goes into a high impedance state after a continuous 8-bit serial data output.

SIP4, SOP4

PCM serial data input (SIP4) and output (SOP4) Channel 4. SOP4 is an open-drain output, which goes into a high impedance state after a continuous 8-bit serial data output.

PAD10 - PAD40, PAD11 - PAD41

PAD mode control. The PCM output can be attenuated by 12 dB or 6 dB and set to an out-of-service pattern (idle pattern) by controlling these pins. Set these pins to digital "0" level during normal operation.The control sequences are as follows:

PAD11 - PAD41 PAD10 - PAD40

Normal

6 dB Loss

12 dB Loss

Out-of-service Pattern

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THR1, THR2, THR3, THR4

Control pins for the data-through modes. THR (1 - 4) are for Channel (1 - 4), respectively. The data-through mode is selected when digital “1” is applied to THR (1 - 4). In this mode, 8-bit serial input data applied to SIA (1 - 4) (ADPCM data input) is passed to the PCM serial data output pins, SOP (1 - 4), without any data modification. SOP (1 - 4) go to the high impedance state after the output of 8-bit data has been applied to SIA (1 - 4). Conversely 8-bit serial input data applied to SIP (1 - 4) (PCM data input) is passed to ADPCM serial data output pins, SOA (1 - 4), without any data modification. SOA (1 - 4) go to the high impedance state after the output of 8-bit serial data has been applied to SIP (1 - 4). ADPCM and PCM data interfaces have the mutually independent signal input pins for synchronizing signals. The time slots for data input and output can be exchanged between them. Some timing at which data may be deleted or duplicated as described in "Note on Usage" should not be used.

SYXP1 - 4, SYRP1 - 4

Synchronous signal input pins to define PCM data input and output timing for Channel 1 (SIP1, SOP1), Channel 2 (SIP2, SOP2), Channnel 3 (SIP3, SOP3), and Channel 4 (SIP4, SOP4). The synchronous signals SYXA1 and SYRAI (Channel 1), SYXA2 and SYRA2 (Channel 2), SYXA3 and SYRA3 (Channel 3), and SYXA4 and SYRA4 (Channel 4), which define ADPCM data input and output timing are provided. PCM and ADPCM data interfaces can be used at a mutually independent timing except some timing. Note: When PCM and ADPCM data interfaces are used at a mutually independent timing, the

timing described in "Note on Usage" should not be used. SYXP signals must be input for PAD signal input processing.

BCKP1 - 4

Bit clock input. These signals define the PCM data transmission speed at the PCM data input/output terminals. BCKP (1 - 4) are used for Channel (1 - 4). Since BCKA (1 - 4) defines the data rate of the ADPCM data interface, the PCM and ADPCM data can be input or output at different speeds.

LAW

PCM data companding law selection.

Digital “1” and “0” correspond to A-law and µ-law, respectively.

PDN1, PDN2, PDN3, PDN4

Power down mode selection. PDN1 - 4 can be independently set to power down mode. When digital “0” is applied, these pins are in the power-down mode.

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SIA1, SOA1

ADPCM serial data input (SIA1) and output (SOA1) pins for Channel 1. SOA1 is an open-drain pin and enters to the high impedance state after outputting a continuous 4-bit serial data stream. When the data-through mode is selected, SOA1 enters to the high impedance state after outputting an 8-bit serial data stream.

SIA2, SOA2

ADPCM serial data input (SIA2) and output (SOA2) pins for Channel 2. These pins function the same as SIA1 and SOA1.

SIA3, SOA3

ADPCM serial data input (SIA3) and output (SOA3) pins for Channel 3. These pins function the same as SIA1 and SOA1.

SIA4, SOA4

ADPCM serial data input (SIA4) and output (SOA4) pins for Channel 4. These pins function the same as SIA1 and SOA1.

SYXA1 - 4 , SYRA1 - 4

SYXA1, SYXA2, SYXA3, and SYXA4 are synchronous signal input pins to define ADPCM data input and output timings for Channel 1 (SIA1, SOA1), Channel 2 (SIA2, SOA2), Channel 3 (SIA3, SOA3), and Channel 4 (SIA4, SOA4), respectively. Therefore, PCM data interfaces can be used at a mutually independent timing except some timing. Since master clocks are generated by the internal PLL using SYXA1 to SYXA4, a synchronous signal should be input to these pins. Note: When PCM and ADPCM data interfaces are used at a mutually independent timing, the

timing described in "Note on Usage" should not be used.

DET1, DET2, DET3, DET4

Special ADPCM input data pattern detect pins. When detecting a 4-bit continuous "0" pattern at the ADPCM input pins Channel 1 (SIA1), Channel 2 (SIA2), Channel 3 (SIA3), and Channel 4 (SIA4), DET (1 - 4) goes from a digital "0" to a digital "1" state. A digital "1" is output at the rising edge of the clock. The fourth data bit (LSB) is clocked into the register by the bit clock (BCKA 1 - 4) and held there until the rising edge in the next time frame. When detecting the special data pattern in the next time frame, the digital "1" on the pins DET (1 - 4) is remains.

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