OKI MSM7578H, MSM7578V, MSM7579 Technical data

E2U0017-28-81

查询MSM7578HGS-K供应商

¡ Semiconductor MSM7578H/7578V/7579

¡ Semiconductor

This version: Aug. 1998

Previous version: Nov. 1996

MSM7578H/7578V/7579

Single Rail CODEC

GENERAL DESCRIPTION

The MSM7578 and MSM7579 are single-channel CODEC CMOS ICs for voice signals ranging
from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, these devices are
particularly optimized for telephone terminals in digital wireless systems and ISDN systems.
The devices use the same transmission clocks as those used in the MSM7508B and MSM7509B.
The analog output signal can directly drive a piezoelectric type handset receiver.

FEATURES

• Single power supply: +5.0 V ±5%

• Low power consumption
Operating mode: 25 mW Typ. 47 mW Max. VDD = 5 V
Power down mode: 0.05 mW Typ. 0.3 mW Max. VDD = 5 V

• ITU-T Companding law

MSM7578H: m-law
MSM7579: A-law
MSM7578V: m/A-law pin-selectable

• Built-in PLL eliminates a master clock

• Serial data rate: 64/128/256/512/1024/2048 kHz

96/192/384/768/1536/1544/200 kHz

• Adjustable transmit gain

• Built-in reference voltage supply

• Directly drive a line transformer of 600 W

• The 16-pin DIP and 24-pin SOP package products provide pin compatibility with the MSM7508B/
7509B

• The 20-pin SSOP package products have 1/3 the foot print of conventional products

• Package options:
16-pin plastic DIP (DIP16-P-300-2.54) (Product name : MSM7578HRS)

(Product name : MSM7579RS)
(Product name : MSM7578VRS)

24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7578HGS-K)

(Product name : MSM7578VGS-K)
(Product name : MSM7579GS-K)

20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name : MSM7578HMS-K)

(Product name : MSM7579MS-K)
(Product name : MSM7578VMS-K)

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¡ Semiconductor MSM7578H/7578V/7579

BLOCK DIAGRAM

AIN–
AIN+

GSX

SGC

SG

AOUT

–
+

RC

LPF

SG

GEN

–
+

SG

8th

BPF

GEN

5th

LPF

VR

CONV.

AUTO
ZERO

DA

CONV.

PWD

AD

TCONT

PLL

RTIM

RCONT

PWD

Logic

PCMOUT

XSYNC

BCLK

RSYNC
(ALAW)

PCMIN

PDN
V

DD

AG
DG

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¡ Semiconductor MSM7578H/7578V/7579

PIN CONFIGURATION (TOP VIEW)

1

SGC

2

SG

AOUT

3

V

4

DD

5

DG

6

PDN

RSYNC

7
8 9

PCMIN PCMOUT

16-Pin Plastic DIP

16

AIN+

15

AIN–

14

GSX

13

(ALAW)*

12

AG

11

BCLK
XSYNC

10

1

SGC

2

NC
SG

3
4

NC

AOUT

5

V

6

DD

DG AG

7
8

NC

9

NC

PDN

10
11

RSYNC

12 13

PCMIN

24

AIN+

23

AIN–

22

NC

21

GSX

20

NC

19

(ALAW)*

18

NC

17
16

BCLK
NC

15
14

XSYNC
PCMOUT

1

SGC

2

SG

AOUT

3

V

4

DD

NC

5
6

NC
DG AG

7
8

PDN

9

RSYNC

10 11

PCMIN PCMOUT

20

AIN+

19

AIN–

18

GSX

17

(ALAW)*

NC

16

NC

15
14

BCLK

13
12

XSYNC

NC : No connect pin

20-Pin Plastic SSOP

NC : No connect pin

24-Pin Plastic SOP

* The ALAW pin is only applied to the MSM7578VRS/MSM7578VGS-K/MSM7578VMS-K.

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¡ Semiconductor MSM7578H/7578V/7579

PIN AND FUNCTIONAL DESCRIPTIONS

AIN+, AIN–, GSX

Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp and is used to adjust the level, as shown below.
When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving
and power down modes, the GSX output is at AG voltage.

1) Inverting input type

Analog input

2) Non inverting input type

Analog input

AG

Analog signal ground.

AOUT

C1

C2

R5

R1

R3

R4

R2

GSX
AIN–
AIN+
SG

AIN+
AIN–
GSX

SG

R1 : variable

–
+

+
–

R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)

Gain = R2/R1 £ 10

R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5)

Gain = 1 + R4 / R3 £ 10

Analog output.
The output signal has a maximum amplitude of 2.4 VPP above and below the signal ground
voltage (VDD/2).
The output load resistance is a minimum of 600 W.
During power saving, or power down mode, the output of AOUT is at the voltage level of the
signal ground.

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¡ Semiconductor MSM7578H/7578V/7579

V

DD

Power supply for +5 V.

PCMIN

PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at a falling edge of the BCLK signal and latched into the internal register
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.

BCLK

Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,
or 200 kHz. Setting this signal to logic “1” or “0” drives both transmit and receive circuits to the
power saving state.

RSYNC

Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be
synchronized in phase with the BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the
AC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are
not guaranteed.

XSYNC

Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this transmit
synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing
signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLK.
The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly
the frequency characteristics of the transmit section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are
not guaranteed.
Setting this signal to logic “1” or “0” drives both transmit and receive circuits to the power saving
state.

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¡ Semiconductor MSM7578H/7578V/7579

DG

Ground for the digital signal circuits.
This ground is separate from the analog signal ground. The DG pin must be connected to the AG
pin on the printed circuit board to make a common analog ground.

PDN

Power down control signal.
A logic "0" level drives both transmit and receive circuits to a power down state.

PCMOUT

PCM signal output.
The PCM output signal is output from MSD in a sequential order, synchronizing with the rising
edge of the BCLK signal.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK
and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power saving or power down mode.
A pull-up resistor must be connected to this pin because its output is configured as an open drain.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7579 (A-law) outputs the character signal, inverting the even bits.

Input/Output Level

+Full scale

+0
–0

–Full scale

PCMIN/PCMOUT

MSM7578H (m-law)

MSD
1000 0000
1111 1111
0111 1111
0000 0000

MSM7579 (A-law)

MSD
1010 1010
1101 0101
0101 0101
0010 1010

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