OKI MSM7542TS-K, MSM7542GS-K, MSM7541RS, MSM7542RS, MSM7541TS-K Datasheet

E2U0014-28-81

¡ Semiconductor MSM7541/7542

¡ Semiconductor

This version: Aug. 1998

Previous version: Nov. 1996

MSM7541/7542

Single Rail CODEC

GENERAL DESCRIPTION

The MSM7541 and MSM7542 are single-channel CODEC CMOS ICs for voice signals ranging
from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, these devices are
optimized for telephone terminals in digital wireless systems.
The MSM7541 and MSM7542 use newly designed operational amplifiers to maintain small
current deviations caused by power voltage fluctuations.
The devices use the same transmission clocks as those used in the MSM7508B and MSM7509B.
The analog output signal, which is of a differential type, directly drives a piezoelectric type
handset receiver.

FEATURES

• Single power supply: +3.0 V to +3.8 V

• Low power consumption
Operating mode: 23 mW Typ. VDD = 3.3 V
Power save mode: 1 mW Typ. VDD = 3.3 V
Power down mode: 0.04 mW Typ. VDD = 3.3 V

• ITU-T Companding law

MSM7541: m-law
MSM7542: A-law

• Built-in PLL eliminates a master clock

• Serial data rate: 64/128/256/512/1024/2048 kHz

96/192/384/768/1536/1544/200 kHz

• Adjustable transmit gain

• Adjustable receive gain

• Built-in reference voltage supply

• Built-in analog loop back test mode

• Differential type analog output. Directly drives a piezoelectric type receiver equivalent to 1.2
kW + 55 nF

• Package options:
20-pin plastic skinny DIP (DIP20-P-300-2.54-S1) (Product name : MSM7541RS)

(Product name : MSM7542RS)

24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7541GS-K)

(Product name : MSM7542GS-K)

26-pin plastic TSOP (TSOPII26/20-P-300-1.27-K) (Product name : MSM7541TS-K)

(Product name : MSM7542TS-K)

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¡ Semiconductor MSM7541/7542

BLOCK DIAGRAM

AIN+
AIN–

GSX

TMC

VFRO

PWI

AOUT–

AOUT+

+
–

–
+

SG

–
+

SG

–
+

SG

RC

Active

SG

Power
Down

BPF

(8th)

LPF

(5th)

AD

Conv.

Auto
Zero

DA

Conv.

PWD

Logic

Voltage

Ref.

Transmit

Controller

PLL

R–TIM

Receive

Controller

SG

Signal

Ground

PCMOUT
XSYNC
BCLOCK

RSYNC
PCMIN

PDN
V

DD

AG
DG

SGC
SG

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¡ Semiconductor MSM7541/7542

y

PIN CONFIGURATION (TOP VIEW)

SG

AOUT+

AOUT–

PWI

VFRO

V

DD

DG

PDN

RSYNC

PCMIN

1

2

3

4

5

6

7

8

9

20

19

18

17

16

15

14

13

12

10 11

SGC

AIN+

AIN–

GSX

TMC

NC

AG

BCLOCK

XSYNC

PCMOUT

SG

AOUT+

AOUT–

NC

PWI

VFRO

NC

V

DD

DG

PDN

RSYNC

PCMIN

1

2

3

4

5

6

7

8

9

10

11

24

23

22

21

20

19

18

17

16

15

14

12 13

NC : No connect pin

24-Pin Plastic SOP

SGC

AIN+

AIN–

GSX

NC

TMC

NC

NC

AG

BCLOCK

XSYNC

PCMOUT

SG

AOUT+

AOUT–

PWI

VFRO

V

DD

DG

PDN

RSYNC

PCMIN

1

2

3

4

5

9

10

11

12

26

25

24

23

22

18

17

16

15

13 14

NC : No connect pin

26-Pin Plastic TSOP

SGC

AIN+

AIN–

GSX

TMC

NC

AG

BCLOCK

XSYNC

PCMOUT

NC : No connect pin

20-Pin Plastic Skinn

DIP

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¡ Semiconductor MSM7541/7542

PIN AND FUNCTIONAL DESCRIPTIONS

AIN+, AIN–, GSX

Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp and is used to adjust the level, as shown below.
When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving
and power down modes, the GSX output is at AG voltage.

1) Inverting input type

AG

C1

Analog input

R1

2) Non inverting input type

C2

Analog input

R5

R3

R2

R4

GSX
AIN–
AIN+
SG

AIN+
AIN–
GSX

SG

R1 : variable

–
+

+
–

R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)

Gain = R2/R1 £ 10

R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5)

Gain = 1 + R4 / R3 £ 10

Analog signal ground.

VFRO

Receive filter output.
The output signal has an amplitude of 2.0 VPP above and below the signal ground voltage (SG)
when the digital signal of +3 dBmO is input to PCMIN and can drive a load of 20 kW or more.
For driving a load of 20 kW or less, the output signal of AOUT+ and AOUT– is available.
To apply the output signal of AOUT+ and AOUT– for driving, connect a resistor of 20 kW or more
between the pins VFRO and PWI.
When adding the frequency characteristics to the receive signal, refer to the application example.
During power saving or power down mode, the output of VFRO is at the voltage level of AG.

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¡ Semiconductor MSM7541/7542

PWI, AOUT+, AOUT–

PWI is connected to the inverting input of the receive driver. The receive driver output is
connected to the AOUT– pin. Therefore, the receive level can be adjusted with the pins VFRO,
PWI, and AOUT–. When the PWI pin is not used, connect the PWI pin to the AOUT– pin, and
leave open the pins AOUT– and AOUT+. The output of AOUT+ is inverted with respect to the
output of AOUT–. Since the signal from which provides differential drives of an impedance of

1.2 kW + 55 nF, these outputs can directly be connected to a receiver of handset using a

piezoelectric earphone. Refer to the application example.

VI

Receive Filter

–
+

SG

–
+

SG

VFRO

PWI

AOUT–

AOUT+

R6

R7

ZLVO

R6 > 20 kW
ZL ≥ 2.4 kW

Gain = VO/VI = 2 ¥ R7/R6 £ 2

During power saving and power down modes, the outputs of AOUT+ and AOUT– are in a high
impedance state.

The electrical driving capability of the AOUT– pin and AOUT+ pin is ±1.3 V maximum. The

output load resistor has a minimum value of 1.2 kW.

If an output amplitude less than ±1.3 V is allowed, these outputs can drive a load resistance less

than that described above.
For more details, refer to SINGLE POWER SUPPLY PCM CODEC APPLICATION NOTE.

V

DD

Power supply for +3.0 V to +3.8 V. (Typically 3.3 V)

PCMIN

PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLOCK signal.
The data rate of the PCM signal is equal to the frequency of the BCLOCK signal.
The PCM signal is shifted at a falling edge of the BCLOCK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.

BCLOCK

Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,
or 200 kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the
power saving state.

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¡ Semiconductor MSM7541/7542

RSYNC

Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be

synchronized in phase with the BCLOCK. The frequency should be 8 kHz ±50 ppm to guarantee

the AC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device

can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are

not guaranteed.

XSYNC

Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this transmit
synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing
signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLOCK.

The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly

the frequency characteristics of the transmit section.
However, if the frequency characteristic of an applied system is not specified exactly, this device

can operate in the range of 8 kHz ±2 kHz, but the electrical characteristics in this specification are

not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving
state.

TMC

Control signal input for mode selection.
This pin select the normal operating mode or the analog loop-back mode.
In the analog loop-back mode, the receive filter output is connected to the transmit filter input
and the digital signal input to the PCMIN pin is converted from a digital to an analog signal (D/
A conversion). Next, the analog signal is converted to a digital signal (A/D conversion) through
the receive filter and transmit filter. The result is output to the PCMOUT pin.
When in the analog loop-back mode, the VFRO pin outputs the SG level. (signal ground)

TMC Input

< 0.16 ¥ V

> 0.45 ¥ V

DD

DD

Mode

Normal operation

Analog loop-back

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