OKI MSM7509BRS, MSM7509BGS-K, MSM7508BJS, MSM7508BRS, MSM7508BGS-K Datasheet

E2U0013-28-81

¡ Semiconductor MSM7508B/7509B

¡ Semiconductor

This version: Aug. 1998

Previous version: Nov. 1996

MSM7508B/7509B

Single Rail CODEC

GENERAL DESCRIPTION

The MSM7508B and MSM7509B are single-channel CODEC CMOS ICs for voice signals ranging
from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, these devices are
optimized for telephone terminals in ISDN and digital wireless systems.
The MSM7508B/MSM7509B are the transmission-clocks extended versions of the MSM7508/
MSM7509. It is recommended to use the MSM7508/MSM7509 for the transmission clocks of 64,
128, 256kHz.

FEATURES

• Single power supply: +5 V ±5%

• Low power consumption
Operating mode: 17.5 mW Typ. 37 mW Max.
Power down mode: 1.5 mW Typ. 3 mW Max.

• ITU-T Companding law

MSM7508B: m-law
MSM7509B: A-law

• Built-in PLL eliminates a master clock

• Transmission clock: 64/128/256/512/1024/2048 kHz

96/192/384/768/1536/1544/200 kHz

• Adjustable transmit gain

• Built-in reference voltage supply

• Package options:
16-pin plastic DIP (DIP16-P-300-2.54-W1) (Product name : MSM7508BRS)

(Product name : MSM7509BRS)

24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM7508BGS-K)

(Product name : MSM7509BGS-K)

28-pin plastic QFJ (PLCC) (QFJ28-P-S450-1.27) (Product name : MSM7508BJS)

(Product name : MSM7509BJS)

Note: The product names are indicated in PIN CONFIGURATION.

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¡ Semiconductor MSM7508B/7509B

BLOCK DIAGRAM

AIN+
AIN–

GSX

SGC

SG

AOUT

+
–

Signal

Ground

Voltage

Ref.

RC

Active

+
–

BPF

(8th)

LPF

(5th)

PWD

AD

Conv.

Auto
Zero

DA

Conv.

PWD

Logic

Transmit

Controller

TPLL

RPLL

Receive

Controller

PCMOUT
XSYNC
BCLOCK

RSYNC
PCMIN

PDN
V

DD

AG
DG

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¡ Semiconductor MSM7508B/7509B

(

)

PIN CONFIGURATION (TOP VIEW)

1

SGC

2

SG

AOUT

RSYNC

PCMIN PCMOUT

3
4

V

DD

5

DG

6

PDN

7
8 9

AIN+

16

AIN–

15

GSX

14
13

NC NC

12

AG
BCLOCK

11
10

XSYNC

NC : No connect pin

16-Pin Plastic DIP

AOUTNCSG

4

3

SGC

AIN+

2

1

28

AIN–

27

GSX

26

SGC

NC
SG

AOUT

V

DD

DG
NC
NC

PDN

RSYNC

PCMIN

1
2
3
4
5
6
7
8

9
10
11

24
23
22
21
20
19
18
17
16
15
14

12 13

NC : No connect pin

24-Pin Plastic SOP

AIN+
AIN–
NC
GSX
NC
NC
AG
NC
BCLOCK
NC
XSYNC
PCMOUT

5

V

DD

6

NC

7

NC

8

NC

9

NC

10

NC

11 19

DG

12

13

14

15

16

PDN

RSYNC

NC

PCMIN

PCMOUT

NC : No connect pin

28-Pin Plastic QFJ

PLCC

17

18

XSYNC

BCLOCK

25
24
23
22
21
20

NC
NC
NC
NC
NC
NC
AG

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¡ Semiconductor MSM7508B/7509B

PIN AND FUNCTIONAL DESCRIPTIONS

AIN+, AIN–, GSX

Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp and is used to adjust the level, as shown below.
When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving
and power down modes, the GSX output is in a high impedance state.

1) Inverting input type

AG

C1

Analog input

R1

2) Non inverting input type
C2

Analog input

R5

R3

R4

R2

GSX
AIN–
AIN+
SG

AIN+
AIN–
GSX

SG

R1 : variable

–
+

+
–

R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)

Gain = R2/R1 £ 10

R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5)

Gain = 1 + R4 / R3 £ 10

Analog signal ground.

AOUT

Analog output.
The output signal amplitude is a maximum of 2.4 VPP above and below the signal ground voltage
level (VDD/2).
The output load resistance is a minimum of 20 kW.
During power saving or power down mode, the output of AOUT is at the voltage level of signal
ground.

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¡ Semiconductor MSM7508B/7509B

V

DD

Power supply for +5 V.

PCMIN

PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLOCK signal.
The data rate of the PCM signal is equal to the frequency of the BCLOCK signal.
The PCM signal is shifted at a falling edge of the BCLOCK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.

BCLOCK

Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048
kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power
saving state.

RSYNC

Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be

synchronized in phase with the BCLOCK. The frequency should be 8 kHz ±50 ppm to guarantee

the AC characteristics which are mainly frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 to 10 kHz, but the electrical characteristics in this specification are
not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to
the power saving state.

XSYNC

Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this transmit
synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing
signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLOCK.

The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly

frequency characteristics of the transmit section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 to 10 kHz, but the electrical characteristics in this specification are
not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving
state.

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¡ Semiconductor MSM7508B/7509B

DG

Ground for the digital signal circuits.
This ground is separate from the analog signal ground. The DG pin must be connected to the AG
pin on the printed circuit board to make a common analog ground.

PDN

Power down control signal.
A logic "0" level drives both transmit and receive circuits to a power down state.

PCMOUT

PCM signal output.
The PCM output signal is output from MSD in a sequential order, synchronizing with the rising
edge of the BCLOCK signal.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between
BCLOCK and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power saving or power down modes.
A pull-up resistor must be connected to this pin because its output is configured as an open drain.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The MSM7509B (A-law) outputs the character signal, inverting the even bits.

Input/Output Level

+Full scale

+0
–0

–Full scale

MSM7508B (m-law)

MSD
1000 0000
1111 1111
0111 1111
0000 0000

PCMIN/PCMOUT

MSM7509B (A-law)

MSD
1010 1010
1101 0101
0101 0101
0010 1010

SG

Signal ground voltage output.
The output voltage is 1/2 of the power supply voltage.

The output drive current capability is ±300 mA.

This pin provides the SG level for CODEC peripherals.
This output voltage level is undefined during power saving or power down modes.

SGC

Used to generate the signal ground voltage level by connecting a bypass capacitor.
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and
the SGC pin.

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