OKI MSM7502GS-BK Datasheet

E2U0023-28-81

¡ Semiconductor MSM7502

¡ Semiconductor

This version: Aug. 1998

Previous version: Nov. 1996

MSM7502

Multi-Function PCM CODEC

GENERAL DESCRIPTION

The MSM7502, developed especially for low-power and multi-function applications in touchtone telephone sets and digital telephone terminals of digital PBXs, is a single +5 V power supply CODEC device. The device consists of the analog speech paths directly connectable to a handset, the calling circuit directly connectable to a piezosounder, the push-button key scanning interface between push buttons and control processors, the dial tone generator, the m-law/A-law CODEC, and the processor interface. The functions can be controlled via 8-bit data bus. For the CODEC of the MSM7502, an MSM7543 is used as a core CODEC, so the MSM7502 provides the available bit clock range wider than the family product MSM6895. In addition, the MSM7502 performs the greater key interface function and offers the upgraded side-tone level, receive level, and speaker pre-amplifier output level.

FEATURES

• Single +5 V Power Supply

• Low Power Dissipation Power ON Mode : 30 mW Typ. 53 mW Max. Power Saving Mode : 2 mW Typ. 5 mW Max.

• In compliance with ITU-T’s companding law

• Transmission clocks : 64, 128, 256, 512, 1024, 2048 kHz

96, 192, 384, 768, 1536, 1544 kHz

• Built-in PLL

• Built-in Reference Voltage Supply

• Calling Tone Interval : Controlled by processor

• Calling Tone Combination : Controlled by processor, 6 modes

• Calling Tone Volume : Controlled by processor, 4 modes

• Ringing Tone Interval : Controlled by processor

• Ringing Tone Frequency : Controlled by processor, 6 modes

• Ringing Tone Level : Controlled by processor, 4 levels

• Built-in PB Tone Generator

• Built-in Speech path Control Switches

• General Latch Output for External Control : 2 bits

• Watch-dog Timer : 500 ms

• Key Scanning I/O Output : 8 bits Input : 8 bits

• Direct Connection to Handset : 1.2 kW driving available

• Built-in Pre-amplifier for Loud-speaker

• Hand-free Interface

• m-law/A-law Switchable CODEC

• LCD Deflection Angle Voltage : Controlled by processor, 8 levels

• Package :

80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name : MSM7502GS-BK)

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BLOCK DIAGRAM

TPAI

CAO

R1I

R2I

RPO

RMI

RMO0

RMO1

TPAO

20 dB

++–

SW 9 0 dB

0 dB

MPAI MPAO MPBO TOTPBI MPBI MLDYI

VOL 9

VOL 10

–

VOL 8

–

VOL 1

VOL 2

–8.7 dB

0 dB

VOL 7

SW 5 SW 5

SW 3

SW 4

SW 17

SW 14

SW 13

––

SW 1

SW 2

SW 7

SW 16

0 dB

5.7 dB

VOL 3

VOL 4

PLL

PB GEN.

R-TONE GEN.

400 425 440 450 400*16 400*20

F-TONE GEN.

1 kHz

CAI

–

AIN

m/A

CODEC

AOUT

SW 12

PROCESSOR INTF

PCMOUT

PCMIN

BCLOCK XSYNC

RSYNC

WRN RDN CEN RESETN

D0 to D7

AD0 AD1

INTT TIMEN

SPI

SPO

SA0

SA1

SW 10 VOL 6

–

VOL 13

0 dB

–3 dB

–6.8 dB

VOL 5

–22 dB

VOL 11

VOL 12

VA VD AG DG SGT SGC PO0 to PO7 PI0 to PI7

SW 6

SW 8

SW 18

SW 21

SW 15

SW 11

SW 20

SW 19

SG GEN.

S-TONE GEN. WAMBLE TONE

1000 Hz

800 Hz 400 Hz

Latch

VLCD GEN.

KEY INTF

SCANNING OUTPUT SCANNING INPUT

LA LB LML

VLCD

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PIN CONFIGURATION (TOP VIEW)

TIMEN

INTT 80

RESETN

CEN 77

RDN

WRN 75

AD1 74

AD0 73

DB7

DB6 71

DB5

DB4 69

DB3

DB2 67

DB1 66

DB0

LML

LA LB

VLCD

SA1

SA0

AG RMO1

RMO0

RMI

SPI

SPO

13 14

2 3

4 5

7 8 9

63 62

61 60

58 57 56 55

52 51

PI7 PI6

PI5 PI4

PI3

PI2 PI1 PI0 NC

PO0

PO1

PO2 PO3

RPO

R2I

R1I

MLDYI

MPBO

MPBI

MPAO

MPAI

17 18

20 21 22

25 NC

TPBI

TPAO

28 NC

SGT

TPAI

NC : No connect pin

80-Pin Plastic QFP

CAI

SGC

CAO

48 47

45 44 43

PO4

PO5

PO6 PO7

PCMOUT

BCLOCK XSYNC RSYNC

PCMIN NC

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PIN AND FUNCTIONAL DESCRIPTIONS

LA, LB

General latch outputs for external control. Statuses of these outputs are controlled via the processor interface. Refer to the description of the control data for details. These outputs provide the capability to drive one TTL.

Digital Ground. DG is separated from the analog ground AG inside the device. But, DG should be connected as close to the AG pin on PCB as possible.

Analog Ground.

SA0, SA1

Sounder (calling tone) driving outputs. The output signal on SA1 is inverted against the signal on SA0. The sounder circuit can be easily configured by connecting a piezo-sounder between SA0 and SA1. Through processor control, the calling tone volume is selectable from four levels and one of six tone combinations is selectable. Initially, the ringing tone volume is set at a maximum and the tone combination is set at a 16 Hz Wamble tone by a combination of 1 kHz and 1.3 kHz. If these pins are used with no-load, tone volume cannot be controlled. When tone volume control is required, a load resistor must be connected between SA0 and SA1.

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RMI, RMO0, RMO1

Receive main amplifier input and outputs. RMI is the inverted input and RMO0 and RMO1 are the outputs of the receive main amplifier. The output signal on RMO1 is inverted against RMO0 by a gain 1 (0 dB), so the earphone of a handset is directly connected between RMO0 and RMO1. During the system power down, the RMO0 and RMO1 outputs are in a high impedance state. The receive main amplifier gain is determined by a resistor connected between RPO and RMI, and a resistor connected between RMI and RMO0. The receive main amplifier gain varies between 0 and +20 dB in effect. A piezoreceiver with an impedance greater than 1.2 kW is available.

If the adjusting of receive path frequency characteristics is required, insert the following circuit for adjustment. During the whole system Power ON, the speech path from RMI to RMO0 and RMO1 is disconnected and the output of RMO0 and RMO1 is at the SG level (VA/2). The speech path is provided by processor control.

A circuit example for adjustment of frequency characteristics

RPO RMI

Main amplifier gain without capacitors

C1 R2

RMO0

R2 R1

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SPI

Addit0ion input of speaker amplifier. The typical gain between SPI and SPO is 0 dB. But, the 2-stage gain amplifier allows to set up a gain between 0 dB and –18 dB in a 6 dB step, or a gain between 0 dB and –28 dB in a 4 dB step through processor control. The input resistance of SPI is typically 20 kW to 150 kW (it varies by gain setting).

SPO

Output of pre-amplifier for speaker. Since the driving capability is 2.4 VPP for the load of 20 kW, SPO can not directly drive a speaker. During the whole system power down mode, SPO is at an analog ground level. During the whole system power on mode, SPO is in a non-signal state (SG level), and a receive voice signal, R-tone, F-tone, hold acknowledge tone, PB signal acknowledge tone, and sounder tone are output from the speaker by processor control.

When the speaker is used as a sounder, the sounder tone is output via the SPO pin by connecting the SPI input with the sounder output (SA0 or SA1). In addition, when the AD-converted sounder tone is sent from the main device, the sounder tone is output via the SPO pin since the CAO pin for CODEC output is internally connected.

R1I, R2I, RPO

R1I and R2I are for the inputs and RPO is for the output of the receive pre-amplifier. Normally, R1I is connected via an AC-coupling capacitor to the CODEC analog output (CAO), and R2I is used as the mixing signal input pin. The typical gain between R1I and PRO is –6 dB. Through processor control, gains are variable from –14 dB to 0 dB in 2 dB steps. In addition, the receive pad can control the gain of –9, –6, –3, or 0 dB. The gain between R2I and RPO is fixed to 0 dB.

During the whole system power-on mode, the RPO output is in non-signal state, and speech signal, R-tone, F-tone, PB acknowledge tone, side tone signal are output by processor control. During the whole system power-down mode, the RPO output is the analog ground level.

The input resistance of R1I is typically between 20 kW and 100 kW (it varies by gain setting). The input resistance of R2I is typically 20 kW.

MLDYI

Hold tone signal input. For example, the output of external melody IC is connected to this pin. Through processor control, the signal applied to MLDYI is output from the TO output pin as a hold tone on the transmit path, and from the SPO output pin as a hold acknowledge tone on the receive path. The typical gain between MLDYI and TO is –2 dB. Through processor control, a gain between –2 dB and –11 dB is also settable at 3 dB steps. The typical gain between MLDYI and SPO is –3 dB. Through processor control, a gain between –3 dB to –31 dB is also settable at 4 dB steps. MLDYI is a high impedance input, so insert an about 100 kW bias resistor between MLDYI and SGT.

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TPBI, TO

TPBI is the input and TO is the output of the transmit pre-amplifier (B). When the handset is used, TPBI is connected to the transmit pre-amplifier (A) output pin (TPAO). If adjustment of frequency characteristics on the transmit path is required, insert a circuit for adjustment of characteristic between TPAO and TPBI. Through processor control, the signal applied to this pin is output via the TO pin on the transmit path and its side tone via the RPO pin. During the whole system power down mode, TO is at an analog ground level. The typical gain between TPBI and TO is +17.7 dB. Through processor control, a gain between +17.7 dB and +8.7 dB is also settable at 3 dB steps.

The typical gain between TPBI and RPO is +3.0 dB. Through processor control, a gain between –9 dB and +9 dB is variable in 3 dB steps. Changing the gain between TPBI and TO may change the gain between TPBI and RPO. TPBI is a high impedance input, so insert an about 100 kW resistor between TPBI and SGT.

A circuit example for adjustment of frequency characteristics

TPAO TPBI SGT

C3R3

MPAI, MPAO

Handfree microphone pre-amplifier (A) input and output. MPAI is the input and MPAO is the output. The speech path between MPAI and MPAO is always active regardless of processor control. During the whole system power saving mode, MPAO is at an analog ground level. The gain between MPAI and MPAO is typically +20 dB. Through processor control, gains between +14 dB and +11 dB are also settable. MPAI is a high impedance input, so insert an about 100 kW between MPAI and SGT.

MPBI, MPBO

The handfree microphone (B) input and output. MPBI is the inverted input and MPBO is the output. With an external resistance, the amplifier gain is adjusted in the range between –25 dB and +25 dB. A signal on the MPBO is output via the TO pin through processor control. During the whole system power down mode, MPBO is at an analog ground level. The gain between MPBO and TO is fixed to 0 dB.

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TPAI, TPAO

The transmit pre-amplifier input and output. TPAI is the input and TPAO is the output. TPAI should be connected to the microphone of handset via an AC-coupling capacitor if the DC offset appears at a transmit signal (offset from SGT). The transmit path from TPAI to TPAO is always active regardless of processor control. During the whole system power down mode, TPAO is at an analog ground level. The gain between TPAI and TPAO is fixed to 20 dB.

SGT

Transmit path signal ground. SGT outputs half the supply voltage. During the whole power down mode, SGT is in a high impedance state.

SGC

Bypass capacitor connecting pin for signal ground level. Insert a 0.1 mF high performance capacitor between SGC and AG.

VA, VD

+5 V power supply. VA is for an analog circuit and VD is for digital supply. Connect both VA and VD to the +5 V analog path of the system.

CAI, CAO

CODEC analog input and output. CAI is the analog input of CODEC to be connected to the TO pin. If the DC offset voltage on the TO signal is great, CAI should be connected via AC-coupling capacitor. At this time, insert an about 100 kW bias resistor between CAI and SGT.

CAO is the analog output of CODEC. CAO should be connected to R1I via AC-coupling capacitor. A bias resistor is not required to R1I. During the whole system or CODEC power down mode, CAO is at the SG voltage level.

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BCLOCK

CODEC PCM data I/O shift clock input. The frequency is one of 64 kHz, 128 kHz, 256 kHz, 512 kHz, 1024 kHz, 2048 kHz, 96 kHz, 192 kHz, 384 kHz, 786 kHz, 1536 kHz, and 1544 kHz. If the BCLOCK signal is not applied, PLL is out of synchronization and the CODEC path goes into the power down mode.

XSYNC, RSYNC

Synchronous signal input. CODEC PCM data is sent out sequencially via the PCMOUT pin from MSB at the rising edge of the BCLOCK signal in synchronization with the rise of the XSYNC signal. PCM data should be entered via the PCMIN pin with MSB at the head in synchronization with the rise of the RSYNC signal. PCM data is shifted in at the falling edge of the BCLOCK signal.

Since the XSYNC signal is used for a trigger signal for PLL and for a clock signal to the tone generator, if this signal is not applied, not only any tone can not be output, but also PLL goes out of synchronization and the CODEC path goes into a power down mode. This signal has to be

synchronous with the BCLOCK signal and its frequency must be within 8 kHz ±50 ppm to ensure

the CODEC AC characteristics (mainly frequency characteristics).

PCMIN

PCM signal input. PCMIN data is shifted in at the falling edge of the BCLOCK signal and is latched into the internal register after eight bits are shifted.

PCMOUT

PCM signal output. PCMOUT data is shifted out at the rising edge of the BCLOCK signal. PCMOUT is left open after eight bits are shifted or when PLL goes out of synchronization. PCMOUT also is left open through processor control. In addition, a digital path between PCMIN and PCMOUT is formed through processor control. PCMOUT needs a pull-up resistor because of its open-drain circuit.

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PO0, PO1, PO2, PO3, PO4, PO5, PO6, PO7

Key scanning outputs. These output pins need external pull-up resistors because of their open- drain circuits. But, when these are used in combination with PI0 to PI7, pull-up resistors are not required. Through processor control, these outputs can be set open or to digital "0". Initially, these outputs are set at an opened state.

PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7

Key scanning inputs. In the READ mode, data on PI0 to PI7 can be read out of the processor via data bus (DB0 to DB7). Since these inputs are pulled up inside the IC, external resistors are not required.

INTT

Interrupt signal output to the processor. INTT outputs interrupt signals (digital "0") at intervals of 8 ms by the interrupt release control signal from the processor. This output keeps digital "0" unless the interrupt is released. INTT does not output any signal while no XSYNC signal is input. When the RESETN signal is in "0" state, INTT is in "1" state. INTT goes from "1" state to "0" state 8 ms after the RESETN signal goes to "1" state.

Interrupt release signal

from processor

INTT output

t < 8 ms 8 ms < t < 16 ms t < 8 ms

8 ms 16 ms 8 ms

DB0, DB1, DB2, DB3, DB4, DB5, DB6, DB7

Data bus inputs and outputs. These pins are configured as an output during the READ mode only and as an input during other modes.

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AD0, AD1

Address data inputs for the internal control registers. Addressing of the internal control registers is executed by AD0 and AD1 and sub address data, DB7 and DB6.

AD1 AD0 DB7 DB6 Function

0 0 ON/OFF controls of sounder, R-Tone, F-Tone 0 1 Level/Frequency controls of sounder, R-Tone

WRITE

1 0 — — Key scanning output control 1 1 0 0 Key scanning interrupt reset 1 1 0 1 LCD deflection angle control voltage setting 1 1 1 0 Power ON/OFF control 1 1 1 1 CODEC control (Controls of companding law and digital loop)

1 0 PB tone control

0 0 Controls of receive gain and side tone gain 0 1 Controls of transmit hold tone, PB tone, handfree input, handset inputs gain 1 0 Controls of speaker pre-amplifier gain and additional speaker gain 1 1 Controls of receive PAD and incoming tone input gain

Controls of internal speech path switch and general latch Watchdog timer reset

READ

1 0 — — Key scanning data read-out

WRN

Write signal for internal control registers. Data on the data bus is written into the registers at the rising edge of WRN under the condition of digital "0" of CEN (Chip Enable). While CEN is in digital "1" state, WRN becomes invalid. The Write cycle is a minimum of 2 ms regardless of the presence or absence of clock signals.

RDN

Read signal input to read PI0 to PI7 out of the processor. When CEN and RDN are in digital "0" state, the digital values on PI0 to PI7 are output onto the data buses DB0 to DB7. While CEN is in digital "1" state, the RDN signal becomes invalid.

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