OKI MSM5412222A-25JS, MSM5412222A-25TS-K, MSM5412222A-30JS, MSM5412222A-30TS-K Datasheet
The OKI MSM5412222A is a high performance 3-Mbit, 256K X 12-bit, Field Memory. It is
especially designed for high-speed serial access applications such as HDTVs, conventional
NTSC TVs, VTRs, digital movies and Multi-media systems. MSM5412222A is a FRAM for wide
or low end use in general commodity TVs and VTRs exclusively. MSM5412222A is not
designed for high end use in medical system s, professional graphics system s which require
long term picture stor ag e, da ta s t or age systems and others . T wo or more MSM5412222As can
be cascaded directly without any delay devices between them. (Cascading provides larger
storage depth or a longer delay).
Each of the 12-bit planes has separ ate seri al write and read ports. Thes e emplo y independ ent
control clocks to support asynchronous read and write operations. Different clock rates are also
supported, which allow alternate data rates between write and read data streams.
The MSM5412222A provides high speed FIFO, First-In First-Out, operation without external
refreshing: MSM541 2222A refreshes its DRAM s torage cells autom atically, so that it appears
fully static to the users.
Moreover, fully static t ype m emor y cells a nd dec oder s for s eria l acces s ena ble the ref resh f ree
serial access operation, so that s erial read a nd/or write contro l clock can be halted h igh or low
for any duration as long as t he power is on. Interna l conf licts of mem or y access and ref reshi ng
operations are prevented by special arbitration logic.
The MSM5412222A ’s function is s imple, and s imilar to a d igital delay device whos e delay-bitlength is easily set by reset timing. The delay length, and the number of read delay clocks
between write and read, is determined by externally controlled write and read reset timings.
Additional SRAM serial registers, or line buffers for the initial access of 256 X 12-bit enable high
speed first-bit-access with no clock delay just after the write or read reset timings.
Additionally, the MSM54122 22A has a write mask function or input enable function (IE) , and
read-data skipping function or output enable function (OE). The differences between write
enable (WE) and input enable (IE), and between read en able (RE) and out put ena ble ( OE) are
that WE and RE can stop serial wr ite/read addr ess incr em ents, but IE and OE cannot stop the
increment, when write/read clocking is continuously applied to MSM5412222A. The input
enable (IE) function a llows the user to wr ite into s elec ted loc atio ns of the mem or y only, leaving
the rest of the memory contents unchanged. This facilitates data processing to display a
“picture in picture” on a TV screen.
The MSM5412222A is similar in operation and functionality to OKI 1-Mbit Field Memor
y
MSM514222C and 2-Mbit Field Memory MSM518222A. Three MSM514222Cs or one
MSM514222C plus one MSM518222A can be replaced simply by one MSM5412222A.
OKI
Semiconductor
MSM5412222A
262,214-Word x 12-Bit Field Memory
DESCRIPTION
REVISION-3 1999.6.10
OKI Semiconductor MSM5412222A
2
Single power supply : 5 V ±10%
512 Rows X 512 Columns X 12 bits
Fast FIFO (First-In First-Out) operation
High speed asynchronous serial access
Read/write cycle time 25 ns/30 ns
Access time 23 ns/25 ns
Direct cascading capab il ity
Write mask function (Input enable control)
Data skipping function (Output enable control)
Self refresh (No refresh control is required)
Package options:
44-pin 400 mil plastic TSOP (Type II) (TSOPII44-P-400-0.80-K) (Product : MSM5412222A-xxTS-K)
40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM5412222A-xxJS)
xx indicates speed rank.
FEATURES
Package
400 mil 44-Pi n TSOP (þ)
400 mil 40-pin S OJ
Cycle Ti me(M in . )
25ns
30ns
25ns
30nsMS M5412222A -30JS
Acce ss Tim e(M ax.)
23ns
25ns
23ns
Family
MS M5412222A -25TS-K
MS M5412222A -30TS-K
MS M5412222A -25JS
25ns
PRODUCT FAMILY
OKI Semiconductor MSM5412222A
3
PIN CONFIGURATION(TOP VIEW)
Pin Name Function
SWCK
SRCK
Serial Write Clock
Serial Read Clock
Write EnableWE
RE Rea d Enabl e
IE In p ut Enable
OE Output Enable
RSTW Write Reset Clock
RSTR Rea d Reset Clo ck
D
IN
0-11
Data Input
D
OUT
0-11
Data Output
Vcc
Vss
NC
Power Suppl
y(5V)
Ground(0V
)
No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
33
34
32
31
30
29
28
27
26
25
24
23
22
21
Vss
NC
D
IN
11
D
IN
10
D
IN
9
D
IN
8
D
IN
7
D
IN
6
D
IN
5
D
IN
4
D
IN
3
D
IN
2
D
IN
1
D
IN
0
SWCK
RSTW
WE
IE
NC
Vcc
Vss
NC
D
OUT
11
D
OUT
10
D
OUT
9
D
OUT
8
D
OUT
7
D
OUT
6
D
OUT
5
D
OUT
4
D
OUT
3
D
OUT
2
D
OUT
1
D
OUT
0
SRCK
RSTR
RE
OE
Vss
Vcc
Vss
D
OUT
11
D
OUT
10
NC
D
OUT
9
D
OUT
8
D
OUT
7
D
OUT
6
NC
D
OUT
5
D
OUT
4
D
OUT
3
D
OUT
2
Vss
D
OUT
1
D
OUT
0
SRCK
RSTR
NC
RE
OE
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Vss
D
IN
11
D
IN
10
NC
D
IN
9
D
IN
8
D
IN
7
D
IN
6
NC
D
IN
5
D
IN
4
D
IN
3
D
IN
2
NC
D
IN
1
D
IN
0
SWCK
RSTW
NC
WE
IE
Vcc
40-PIN Pla stic SOJ
44-PIN Plastic TSOP()
(K Type)
NOTE:The same power supply voltage must be provided to every Vccpin, and the same GND
voltage level must be provided to every Vss pin.
OKI Semiconductor MSM5412222A
4
BLOCK DIAGRAM
Clock
Oscillator
VBB
Generator
-
256k (
q
12)
Memory
Array
512 Word Serial Read Register (
q
12)
Read Line Buffer
Low-Half (
q
12)
Read Line Buffer
High-Half (
q
12)
Write Line Buffer
Low-Half (
q
12)
Write Line Buffer
High-Half (
q
12)
512 Word Serial Write Register (
q
12)
256 (
q
12) 256 (
q
12)
256 (
q
12) 256 (
q
12)
Serial
Read
Controller
RE
RSTR
SRCK
WE RSTW
SWCK
71 Word
Sub-Register (
q
12)
Data-In
Buffer (
q
12)
Data-Out
Buffer (
q
12)
D
OUT
(
q
12)
D
IN
(
q
12)
Read/Write
and Refresh
Controller
IE
71 Word
Sub-Register (
q
12)
Decoder
OE
Serial
Write
Controller
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