2,097,152-Word ¥ 36-Bit DRAM MODULE : FAST PAGE MODE TYPE
DESCRIPTION
The Oki MSC23B236A-xxBS8/DS8 is a fully decoded 2,097,152-word ¥ 36-bit CMOS dynamic
random access memory composed of four 16-Mb (1M ¥ 16) DRAMs in SOJ and four 2-Mb (1M
¥ 2) DRAMs in SOJ. The mounting of eight DRAMs together with decoupling capacitors on a 72pin glass epoxy SIMM Package supports any application where high density and large capacity
of storage memory are required.
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to the conditions as detailed in the
operational sections of this data sheet. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Notes: 1. ICC Max. is specified as ICC for output open condition.
2. Address can be changed once or less while RAS=VIL.
3. Address can be changed once or less while CAS=VIH.
163
MSC23B236A-xxBS8/DS8¡ Semiconductor
AC Characteristics (1/2)
Parameter
Random Read or Write Cycle Time
Fast Page Mode Cycle Timet
Access Time from RASt
Access Time from CASt
Access Time from Column Addresst
Access Time from CAS Precharget
Output Low Impedance Time from CAS
Output Buffer Turn-off Delay Timet
Transition Timet
Refresh Periodt
RAS Precharge Timet
RAS Pulse Widtht
RAS Pulse Width (Fast Page Mode)t
RAS Hold Timet
CAS Precharge Timet
CAS Pulse Widtht
CAS Hold Timet
CAS to RAS Precharge Timet
RAS to CAS Delay Timet
RAS to Column Address Delay Timet
Row Address Set-up Timet
Row Address Hold Timet
Column Address Set-up Timet
Column Address Hold Timet
Column Address Hold Time from RASt
Column Address to RAS Lead Timet
Symbol
t
RC
PC
RAC
CAC
AA
CPA
t
CLZ
OFF
T
REF
RP
RAS
RASP
RSH
CP
CAS
CSH
CRP
RHCP
RCD
RAD
ASR
RAH
ASC
CAH
AR
RAL
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1,2,3
MSC23B236A
-60BS8/DS8
Min.
Max.
110
40
—
—
—
—
0
0
3
—
40
60
60
10k
100k
15
10
15
10k
60
5
35
20
15
0
10
0
15
50
30
—
—
60
15
30
35
—
15
50
16
—
—
—
—
—
—
45
30
—
—
—
—
—
—
MSC23B236A
-70BS8/DS8
Min.
130
45
—
—
—
—
0
0
3
—
50
70
70
20
10
20
70
5
40ns
20
15
0
10
0
15
55
35
Max.
—
—
70
20
35
40
—
20
50
16
—
10k
100k
—
—
10k
—
—
—RAS Hold Time from CAS Precharget
50
35
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
4, 5, 6
4, 5
4, 6
4
4
7
3
5
6
164
MSC23B236A-xxBS8/DS8¡ Semiconductor
AC Characteristics (2/2)
Parameter
Read Command Set-up Time
Read Command Hold Timet
Read Command Hold Time referenced to RAS
Write Command Set-up Timet
Write Command Hold Timet
Write Command Hold Time from RASt
Write Command Pulse Widtht
Write Command to RAS Lead Timet
Write Command to CAS Lead Timet
Data-in Set-up Timet
Data-in Hold Timet
Data-in Hold Time from RASt
CAS Active Delay Time from RAS Precharge
RAS to CAS Set-up Time (CAS before RAS)t
RAS to CAS Hold Time (CAS before RAS)t
WE to RAS Precharge Time (CAS before RAS)
WE Hold Time from RAS (CAS before RAS)t
Symbol
t
RCS
RCH
t
RRH
WCS
WCH
WCR
WP
RWL
CWL
DS
DH
DHR
t
RPC
CSR
CHR
t
WRP
WRH
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1,2,3
MSC23B236AMSC23B236A
-60BS8/DS8-70BS8/DS8
Min.
0
0
0
0
10
45
10
15
15
0
15
50
5
5
10
10
10
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
Max.
0
0
0
0
15
55
15
20
20
0
15
55
5
5
15
10
10ns
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
8
8
165
MSC23B236A-xxBS8/DS8¡ Semiconductor
Notes:1. A start-up delay of 200 µs is required after power-up followed by a minimum of
eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before
proper device operation is achieved.
When using the internal refresh counter, a minimum of eight CAS before RAS
initialization cycles is required.
2. AC mesurement assume tT = 5 ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.
Transition times are measured between VIH and VIL.
4. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the t
(Max.) limit ensures that t
RCD
(Max.) is specified as a reference point only. If t
(Max.) limit, access time is controlled by t
6. Operation within the t
(Max.) limit ensures that t
RAD
(Max.) is specified as a reference point only. If t
(Max.) limit, access time is controlled by tAA.
7. t
(Max.) defines the time at which the output achieves an open circuit condition
OFF
and is not referenced to output voltage levels.
8. t
RCH
or t
must be satisfied for a read cycle.
RRH
CAC
(Max.) can be met. t
RAC
is greater than the specified t
RCD
.
(Max.) can be met. t
RAC
is greater than the specified t
RAD
RCD
RCD
RAD
RAD
166
See ADDENDUM B for AC Timing Waveforms
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