Semiconductor MSC23836C
Notes: 1. A start-up delay of 200µs is required after power-up, followed by a mini mum of eight init ialization cycles
(/RAS only r efresh or /CAS before /RAS refresh) befor e pr oper devic e oper ation is achieved.
2. The AC characteristics assume t
T
= 5ns.
3. V
IH
(Min.) and VIL(Max.) are refer enc e levels for measuring input timing signals. Transition times (tT) are
measured between V
IH
and VIL.
4. This parameter is measured wit h a load circuit equivalent t o 2TTL loads and 100pF.
5. Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only. If t
RCD
is greater than the specified t
RCD
(Max.) limit, then
the access tim e is controll ed by t
CAC
.
6. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RAD
(Max.) is specified as a reference point only. If t
RAD
is greater than the specified t
RAD
(Max.) limit, then
the access tim e is controll ed by t
AA
.
7. t
OFF
(Max.) defi ne the t i m e at which the out put achi eves the open circui t c ondit i on and is not ref erenc ed
to output voltage levels.
8. t
RCH
or t
RRH
must be satisfi ed for a read cycle.
9. The test mode is initiated by performing a /W E and /CAS before /RAS refresh cycle. This mode i s
latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet
is a 4-bit parallel test f unct ion. CA0 and CA1 are not used. I n a read cycle, if all i nt ernal bi ts are equal,
the D Q p in w ill indica t e a hig h level. If a n y intern al bits are not equal, the DQ pin will indicate a low le vel.
The test mode is cl eared and t he mem ory devic e retur ned to i ts norm al operati ng state by a / RAS onl y
refresh or /CAS before /RAS refresh cycle.
10. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value.
These parameters should be specifi ed in test m ode cycle by adding the abov e v alue t o the specif ied
value in this data sheet.