PEDL9041-03
1
Semiconductor
ML9041-xxA/xxB
DOT MATRIX LCD CONTROLLER DRIVER
Preliminary
This version: Mar. 2001
Previous version: D ec. 1999
GENERAL DESCRIPTION
The ML9041 used in combination with an 8-bit or 4-bit microcontroller controls the operation of a character type
dot matrix LCD.
FEATURES
•
Easy interfacing with 8-bit or 4-bit microcontroller
•
Switchable between serial and parallel interfaces
•
Dot-matrix LCD controller/driver for a small (5 × 7 dots) or large (5 × 10 dots) font
•
Built-in circuit allowing automatic resetting at power-on
•
Built-in 17 common signal drivers and 100 segment signal drivers
•
Built-in character generation ROM capable of generating 160 small characters (5 × 7 dots) or 32 large
characters (5 × 10 dots)
•
Creation of character patterns by programming: up to 8 small character patterns (5 × 8 dots) or up to 4 large
character patterns (5 × 11 dots)
•
Built-in RC oscillation circuit using external or internal resistors
•
Program-selectable duties: 1/9 duty (1 line: 5 × 7 dots + cursor + arbitrator), 1/12 duty (1 line: 5 × 10 dots +
cursor + arbitrator), or 1/17 duty (2 lines: 5 × 7 dots + cursor + arbitrator)
•
Built-in bias dividing resistors to drive the LCD
•
Bi-directional transfer of segment outputs
•
Bi-directional transfer of common outputs
•
Equipped with a 100-dot arbitrator
•
Display shifting on each line
•
Built-in contrast contr ol circuit
•
Built-in voltage multiplier circuit
•
Chip (Gold Bump)
Product name: ML9041-xxA/xxB CVWA
xxA: With dummy bumps on both sides of the chip
xxB: Without dummy bumps on both sides of the chip
*xx indicates a code number.
*01A and 01B are general code numbers.
1/60
1
W
S
T
A
Semiconductor
BLOCK DIAGRAM
1
COM
Common
signal
PEDL9041-03
ML9041-xxA/xxB
17
1
SEG
100
SEG
COM
Segment Signal - driver
driver
100-bit latch
shift
17-bit
register
100-bit shift register
Parallel-
serial
converter
5
blink
Cursor
controller
generator
Character
(ID)
decoder
Instruction
8
7
(IR)
register
Instruction
8
Timing
generator
5
RAM
8
(CG RAM)
ROM
generator
Character
(CG ROM)
RAM
8
Display data
8
(ADC)
counter
Address
5
RAM
Arbitrator
(DD RAM)
decoder
instruction
Expansion
(AB RAM)
(ED)
8
circuit
Voltage
Data
(DR)
register
(BF)
Busy flag
instruction
Expansion
register (ER)
8
8
I/O
buffer
4
Test
circuit
LCD bias
voltage
4
multiplier
5
circuit
dividing
SSR
CSR
BEBV
IN
V
V
CC
C
2
1
DD
V
GND
R
OSC
OSC
OSC
0
RS1RS
R/
3
7
1
E
C
/S
P
SH
SI
SO
to DB
0
DB
to DB
4
DB
T
T2T
3V1V2
3
5
5IN
V4V
V3BV
V
2/60
1
A
A
A
A
A
A
A
A
A
T
A
A
A
A
A
A
A
Semiconductor
I/O CIRCUITS
V
DD
P
PEDL9041-03
ML9041-xxA/xxB
V
DD
P
V
DD
V
DD
P
N
Applied to pins SSR, CSR,
P
/S, and BEB
pplied to pin E
pplied to pin
SH
V
DD
P
t serial I/F
t parallel I/F
t serial I/F
t parallel I/F
V
DD
P
N
N
pplied to pins T1, T2, and T
: 0
: 1
: 1 (CS = 1)
: 0 (CS = 0)
: 1
V
DD
P
3
pplied to pin SI
pplied to pin
N
pplied to pins R/W, RS1, and RS
t serial I/F
: 1 (CS = 0)
: 0 (CS = 1)
t parallel I/F
t serial I/F
t parallel I/F
: 0
: 0
: 1
CS
0
N
Output Enable signal
pplied to pins DB0 to DB
V
V
DD
DD
7
PP
N
Output Enable signal
pplied to pin SO
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Semiconductor
PIN DESCRIPTIONS
Symbol Description
W
R/
PEDL9041-03
ML9041-xxA/xxB
The input pin with a pu ll-up resi stor to s elect Read (“H”) or Write (“L”) in the Parallel I/F
Mode.
This pin should be open in the Serial l/F Mode.
The input pins with a pull-up resistor to select a register in the Parallel l/F Mode.
RS0, RS
1
E
DB0 to DB
DB4 to DB
OSC
1
OSC
2
OSC
R
COM1 to COM
SEG1 to SEG
RS
1
RS
0
Name of register
H H Data register
H L Instruction register
L L Expansion Instruction register
This pin should be open in the Serial I/F Mode.
The input pin for data input/output between the CPU and the ML9041 and for
activating instructions in the Parallel l/F Mode.
This pin should be open in the Serial l/F Mode.
The input/output pins to transfer data of lower-order 4 bits between the CPU and the
ML9041 in the Parallel l/F Mode. The pins are not used for the 4-bit interface and
3
serial interface.
Each pin is equipped with a pull-up r esistor, so thi s pin should be open when no t used.
The input/output pins to transfer data of upper 4 bits between the CPU and the
ML9041 in the Parallel l/F Mode. The pins are not used for the serial interface.
7
Each pin is equipped w ith a pull-u p resistor, so thi s pin shoul d be open in the Ser ial I/F
Mode when not used.
The clock oscillation pins required for LCD drive signals and the operation of the
ML9041 by instructions sent from the CPU.
To input external clock, the OSC
pin should be used. The OSCR and the OSC2 pins
1
should be open.
To start oscillation w ith an ex ternal resistor, t he resistor should be connected between
the OSC
To start oscillation with an internal resistor, the OSC
short-circuited outside the ML9041. The OSC
and OSC2 pins. The OSCR pin should be open.
1
and OSCR pins should be
2
pin should be open.
1
The LCD common signal output pins.
to COM17. For
10
to COM17.
13
100
17
For 1/9 duty, non-selectable voltage waveforms are output via COM
1/12 duty, non-selectable voltage waveforms are output via COM
The LCD segment signal output pins.
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Semiconductor
Symbol Description
CSR
SSR
V1 , V2, V3A, V3B, V
BEB
V
V5, V
V
V
PEDL9041-03
ML9041-xxA/xxB
The input pin to select the transfer direction of the common signal output data.
At 1/n duty, data is transferred from CO M1 to COM n when “L” is applied to this pin and
transferred from COMn to COM1 when “H” is applied to this pin.
The input pin to select the transfer direction of the segment signal output data.
“L”: Data transfer from SEG
“H”: Data transfer from SEG
The pins to output bias voltages to the LCD.
For 1/4 bias : The V2 and V3B pins are shorted.
4
For 1/5 bias : The V
3A
The input pin to enable or disable the voltage multiplier circuit.
"L" disables the voltage multiplier circuit. "H" enables the voltage multiplier circuit.
The voltage multiplier circuit doubles the input voltage V
referenced to V
is output to the V
DD
only when generating a level lower than GND.
IN
The pin to input voltage to the voltage multiplier.
The pins to supply the LCD drive voltage.
The LCD drive voltage is supp lied to the V5 pin when the voltage multiplier is not used
(BEB = 0) and the internal contrast adjusting circuit is also not used. At this time, the
V
pin should be open.
5IN
The LCD drive voltage is supplie d to the V
5IN
(BEB = 0) but the internal contrast adjusting circuit is used. At this time, the V
should be open.
When the voltage multiplier is used (BEB = 1), the V
multiplied voltage is output to the V
circuit must be used. Capacitors for the voltage multiplier should be connected
between the V
C
CC
The pin to connect the positive pin of the capacitor for the voltage multiplier.
The pin to connect the negative pin of the capacitor used for the voltage multiplier.
pin and the V
DD
to SEG
1
100
to SEG
100
1
and V3B pins are shorted.
pin. The voltage multiplier circuit can be used
5IN
pin when the voltage multip lier is not used
5IN
pin). In this case, the internal contrast adjusting
5IN
pin.
5IN
and the multiplied voltage
MUL
pin should be open (the
5
pin
5
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Semiconductor
Symbol Description
T1, T2, T
3
V
DD
GND The ground level input pin.
P
/S
CS
SHT
Sl
SO
The input pins for test circuits (normally open). Each of these pins is equipped with a
pull-down resistor, so this pin should be left open.
The power supply pin.
The input pin to select the parallel or serial interface.
“L” selects the parallel interface.
“H” selects the serial interface.
The pin to enable this IC in the serial l/F mode.
“L” enables this IC.
“H” disables this IC.
This pin should be open in the parallel l/F mode.
The pin to input shift clock in the serial l/F mode.
Data inputting to the SI pin is carried out synchronizing with the rising edge of this
clock signal.
Data outputting from the SO pin is carried out synchronizing with the falling edge of
this clock signal.
This pin should be open in the parallel l/F mode.
The pin to input DATA in the serial l/F mode.
Data inputting to this pin is carried out synchronizing with the rising edge of the
signal.
This pin should be open in the parallel l/F mode.
The pin to output DATA in the serial l/F mode.
Data inputting to this pin is carried out synchronizing with the falling edge of the
signal.
This pin should be open in the parallel l/F mode.
PEDL9041-03
ML9041-xxA/xxB
SHT
SHT
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Semiconductor
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Condition Rating Unit Applicable pins
Supply Voltage V
LCD Driving Voltage
V1, V2, V3,
V
4
Input Voltage V
Storage Temperature T
DD
, V
I
STG
Ta = 25°C –0.3 to +6.5 V VDD–GND
Ta = 25°C VDD–7.5 to VDD+0.3 V V1, V4, V5, V
5
Ta = 25°C –0.3 to VDD+0.3 V
— –55 to +150 °C —
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Condition Range Unit Applicable pins
Supply Voltage V
LCD Driving Voltage
V
(See Note)
Voltage Multipler
Operating Voltage
Operating Temperature T
DD
DD–V5
V
MUL
op
— 2.5 to 5.5 V VDD–GND
— 2.8 to 7.0 V
BEB = 1
— –40 to +85 °C —
V
DD
V
–1.40 to
–3.5
DD
PEDL9041-03
ML9041-xxA/xxB
(GND = 0 V)
, V2, V3A, V
5IN
R/W, E,
SSR, Sl, RS0, RS1, BEB, CS,
T
VV
SHT
, CSR, P/S,
to T3, DB0 to DB7, V
1
(GND = 0 V)
V
DD–V5
(V
)
5IN
DD–VIN
IN
3B
Note: This voltage should be applied across VDD and V5. The following voltages are output to the V1, V2,
V
(V3B) and V4 pins:
3A
•
1/4 bias
= {VDD – (VDD – V5)/4} ±0.15 V
V
1
V
= V3B = {VDD – (VDD – V5)/2} ±0.15 V
2
= {VDD – 3 × (VDD – V5)/4 } ±0.15 V
V
4
•
1/5 bias
V
= {VDD – (VDD – V5)/5} ±0.15 V
1
= {VDD – 2 × (VDD – V5)/5} ±0.15 V
V
2
V
= V3B = {VDD – 3 × (VDD – V5)/5} ±0.15 V
3A
V
= {VDD – 4 × (VDD – V5)/5} ±0.15 V
4
The voltages at the V
V
> V1 > V2 > V3A (V3B) > V4 > V5.
DD
(Higher
←
, V2, V3A (V3B), V4 and V5 pins should satisfy
1
→ Lower)
* Do not apply short-circuiting across output pins and across an output pin and an input/output
pin or the power supply pin in the output mode.
7/60
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Semiconductor
ML9041-xxA/xxB
ELECTRICAL CHARACTERISTICS
DC Characteristics
(GND = 0 V, V
Parameter Symbol Condition Min. Typ. Max. Unit Applicable pin
“H” Input Voltage 1 V
“L” Input Voltage 1 V
“H” Input Voltage 2 V
“L” Input Voltage 2 V
“H” Output Voltage 1 V
“L” Output Voltage 1 V
“H” Output Voltage 2 V
“L” Output Voltage 2 V
COM Voltage Drop
SEG Voltage Drop
V
V
V
V
IH1
IL1
IH2
IL2
OH1IOH
OL1IOL
OH2IOH
OL2IOL
V
CHlOCH
CMHlOCMH
CMLlOCML
V
CLlOCL
V
SHlOSH
SMHlOSMH
SMLlOSML
V
SLlOSL
—
—
= –0.1 mA 0.75V
= +0.1 mA — — 0.2V
= –13 µA0.9V
= +13 µA——0.1V
= –4 µAV
= ±4 µAV
= ±4 µAV
V
–V5 = 5 V
DD
Note 1
= +4 µA
= –4 µAV
= ±4 µAV
= ±4 µAV
V
–V5 = 5 V
DD
Note 1
= +4 µA
0.8V
DD
–0.3 — 0.2V
0.8V
DD
–0.3 — 0.2V
DD
DD
–0.3 V
DD
–0.3 V1+0.3
1
–0.3 V4+0.3
4
V
5
–0.3 V
DD
–0.3 V2+0.3
2
–0.3 V3+0.3
3
V
5
Input Leakage Current | IIL | VDD = 5 V, VIN = 5 V or 0 V — — 1.0
VDD = 5 V, VIN = GND 10 25 61
= 5 V, VIN = VDD,
V
Input Current 1 | II1 |
DD
Excluding current flowing
through the pull-up resistor
——2.0
and the output driving MOS
Input Current 2 | II2 |
VDD = 5 V, VIN = V
DD
VDD = 5 V, VIN = VDD,
Excluding current flowing
15 45 105
——2.0
through the pull-down resistor
Supply Current l
LCD Bias Resistor R
Oscillation Frequency
of External Resistor Rf
Oscillation Frequency
of Internal Resistor Rf
Clock Input
Frequency
Input Clock Duty f
Input Clock Rise
Time
External Clock
Input Clock Fall Time f
VDD = 5 V Note 2 — — 1.2 mA VDD–GND
DD
LB
Rf = 180 kΩ±2% Note 3 175 270 400 kHz OSC1, OSC
f
osc1
OSC1: Open Note 4
f
osc2
OSC
and OSCR: Short-
2
140 270 480 kHz
circuited
OSC2, OSCR: Open
f
in
Input from OSC
duty
f
rf
ff
1
Note 5 45 50 55 %
Note 6 — — 0.2
Note 6 — — 0.2
125 480 kHz
= 2.5 to 5.5 V, Ta = –40 to +85°C)
DD
—V
DD
V
DD
—V
——
——
DD
V
DD
VDB0 to DB7, SO
DD
VOSC
DD
DD
V
V5+0.3
DD
V
V5+0.3
µ
A
µ
A
µ
AT
4.0 k
Ω
µ
s
µ
s
PEDL9041-03
R/W, RS
E, DB
SHT, P
, RS1,
0
to DB7,
0
/S, Sl,
CS
, SSR,
OSC
1
CSR, BEB
2
to
COM
1
COM
17
to
SEG
1
SEG
100
E, SSR, CSR,
SHT, P
BEB,
/S,
CS, Sl
R/W, RS
DB
1
V
DD
V
3A
OSC
OSC
OSC
, RS1,
0
to DB7, SO
0
, T2, T
3
, V1, V2,
, V3B, V4, V
, OSC2,
1
R
1
5
2
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Semiconductor
PEDL9041-03
ML9041-xxA/xxB
(GND = 0 V, V
Parameter Symbol Condition Min. Typ. Max. Unit
= 5 V, 1/5 bias
Maximum and
minimum LCD
drive voltages
when internal
variable resistors
are used.
Bias Voltage for
Driving LCD by
External Input
V
MAX
V
MIN
V
V
V
LCD
DD
V
5IN
Contrast data: 1F
VDD = 5 V, 1/5 bias
LCD
V
5IN
Contrast data: 00
LCD1
VDD–V
LCD2
= 0 V,
= 0 V,
5
Note 7
4.6 — V V
1/5 bias 2.8 — 7.0 V V
1/4 bias 2.8 — 7.0
= 2.5 to 5.5 V, Ta = –40 to +85°C)
DD
Applicable
pins
DD–V5
—3.4 V
5
VDD = 3 V, VIN = 0 V
f = 270 kHz
Voltage Multiplier
Output Voltage
V
A capacitor for the voltage
5OUT
multiplier = 4.7 µF
–(VDD–VIN)
V
DD
×
2–0.1
—
VDD–(VDD–
V
) × 2+1.2 V
IN
VV
5
, V
5IN
No load
BEB = H
Voltage Multiplier
Input Voltage
V
IN
VDD–3.5 V VDD/2 V V
IN
Note 1: Applied to the voltage drop occurring between any of the VDD, V1, V4 and V5 pins and any of the
common pins (COM
to COM17) when the current of 4 µA flows in or flows out at one common
1
pin.
Also applied to the voltage drop occurring between any of the V
any of the segment pins (SEG
to SEG
1
) when the current of 4 µA flows in or flows out at one
100
, V2, V3A (V3B) and V5 pins and
DD
common pin.
The current of 4 µA flows out when the output level is V
.
V
5
Note 2: Applied to the current flowing into the V
fed to the internal R
= 5 V
V
DD
GND = V
V
, V2, V3A (V3B) and V4: Open
1
= 0 V,
5
oscillation or OSC1 under the following conditions:
f
E, SSR, CSR, and BEB: “L” (fixed)
Other input pins: “L” or “H” (fixed)
Other output pins: No load
or flows in when the output level is
DD
pin when the external clock (f
DD
= fin = 270 kHz) is
OSC2
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1
A
A
Semiconductor
Note 3: Note 4:
OSC
OSC
OSC
OSC
1
= 180 kΩ±2%
R
R
2
f
OSC
OSC
PEDL9041-03
ML9041-xxA/xxB
1
R
2
The wire between OSC1 and Rf and the wire between
and Rf should be as short as possible.
OSC
2
Keep OSC
open.
R
Note 5:
t
V
DD
2
f
IN
waveform
pplied to the pulses entering from the OSC1 pin
= tHW/(tHW + tLW) ×100 (%)
f
duty
Note 6:
0.7V
DD
0.3V
DD
The wire between OSC2 and OSCR should be as short
as possible. Keep OSC
HW
V
DD
2
0.7V
DD
0.3V
t
LW
V
DD
open.
1
DD
2
t
rf
t
ff
pplied to the pulses entering from the OSC1 pin
Note 7: For 1/4 bias, V2 and V3B pins are short-circuited. V3A pin is open.
For 1/5 bias, V
and V3B pins are short-circuited. V2 pin is open.
3A
10/60
PEDL9041-03
W
1
Semiconductor
ML9041-xxA/xxB
Switching Characteristics (The following ratings are subject to change after ES evaluation.)
•
Parallel Interface Mode
The timing for the input from the CPU (see 1) and the timing for the output to the CPU (see 2) are as shown below:
1) WRITE MODE (Timing for input from the CPU)
(VDD = 2.5 to 5.5 V, Ta = –40 to +85°C)
Parameter Symbol Min. Typ. Max. Unit
R/W, RS0, RS1 Setup Time t
E Pulse Width t
R/W, RS0, RS1 Hold Time t
E Rise Time t
E Fall Time t
E Pulse Width t
E Cycle Time t
DB0 to DB7 Input Data Hold Time t
DB0 to DB7 Input Data Setup Time t
B
W
A
r
f
L
C
I
H
40 — — ns
450 — — ns
10 — — ns
— — 25 ns
— — 25 ns
430 — — ns
1000 — — ns
195 — — ns
10 — — ns
RS1, RS
DB
to DB
0
R/
V
0
E
7
V
IH
V
IL
V
IL
t
t
B
t
L
IL
V
IL
r
V
IH
t
C
t
W
t
I
V
V
Input
IH
Data
IL
V
IH
V
IL
V
IL
t
f
V
IH
t
A
V
IL
t
H
V
IH
V
IL
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W
Semiconductor
2) READ MODE (Timing for output to the CPU)
Parameter Symbol Min. Typ. Max. Unit
R/W, RS1, RS0 Setup Time t
E Pulse Width t
R/W, RS1, RS0 Hold Time t
E Rise Time t
E Fall Time t
E Pulse Width t
E Cycle Time t
DB0 to DB7 Output Data Delay Time t
DB0 to DB7 Output Data Hold Time t
PEDL9041-03
ML9041-xxA/xxB
(VDD = 2.5 to 5.5 V, Ta = –40 to +85°C)
B
W
A
r
f
L
C
D
O
40 — — ns
450 — — ns
10 — — ns
— — 25 ns
— — 25 ns
430 — — ns
1000 — — ns
— — 350 ns
20 — — ns
RS1, RS
to DB
DB
0
R/
V
0
E
7
V
IH
V
IL
V
IH
t
t
B
t
L
IL
V
IL
r
V
IH
t
D
t
C
t
W
V
OH
Output
Data
V
OL
V
IH
V
IL
V
IH
t
f
V
IH
t
A
V
IL
t
O
V
OH
V
OL
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CS
SHT
Semiconductor
•
Serial Interface Mode
Parameter Symbol Min. Typ. Max. Unit
SHT
Cycle Time t
CS
Setup Time t
CS
Hold Time t
SHT
Setup Time t
SHT
Hold Time t
SHT
“H” Pulse Width t
SHT
“L” Pulse Width t
SHT
Rise Time t
SHT
Fall Time t
Sl Setup Time t
Sl Hold Time t
Data Output Delay Time t
Data Output Hold Time t
SCY
CSU
CH
SSU
SH
SWH
SWL
SR
SF
DISU
DIH
DOD
CDH
PEDL9041-03
ML9041-xxA/xxB
(VDD = 2.5 to 5.5 V, Ta = –40 to +85°C)
500 — — ns
100 — — ns
100 — — ns
60 — — ns
200 — — ns
200 — — ns
200 — — ns
——50ns
——50ns
100 — — ns
100 — — ns
— — 160 ns
0——ns
SI
SO
t
CSU
t
SCY
V
IL
t
SSU
t
t
SWL
V
IH
V
IH
V
t
DOD
V
SR
V
IL
t
DISU
t
SWH
V
IH
t
DIH
V
IL
OL
V
t
SF
V
IH
IL
V
IH
t
DOD
IL
V
OH
t
SH
V
IH
t
t
CDH
CH
V
OH
13/60
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Semiconductor
FUNCTIONAL DESCRIPTION
Instruction Register (IR), Data Register (DR), and Expansion Instruction Register (ER)
PEDL9041-03
ML9041-xxA/xxB
These registers are selected by setting the level of the Register Selection input pins RS
selected when both RS
when both RS
and RS1 are “L”. (When RS0 is “H” and RS1 is “L”, the ML9041 is not selected.)
0
and RS1 are “H”. The IR is selected when RS0 is “L” and RS1 is “H”. The ER is selected
0
and RS1. The DR is
0
The IR stores an instruction code and sets the address code of the display data RAM (DDRAM) or the character
generator RAM (CGRAM).
The microcontroller (CPU) can write to the IR but cannot read from the IR.
The ER stores a contrast adjusting code and sets the address code of the arbitrator RAM (ABRAM).
The CPU can write to or read from the ER.
The DR stores data to be written in the DDRAM, ABRAM and CGRAM and also stores data read from the
DDRAM, AM RAM and CG RA M .
The data written in the DR by the CPU is automatically written in the DDRAM, ABRAM or CGRAM.
When an address code is written in the IR or ER, the data of the specified address is automatically transferred from
the DDRAM, ABRAM or CGRAM to the DR. The data of the DDRAM, ABRAM and CGRAM can be checked
by allowing the CPU to read the data stored in the DR.
After the CPU writes data in the DR, the data of the next addres s in the DDRAM, ABRAM or CGRAM is selected
to be ready for the next writing by the CPU. Similarly, after the CPU reads the data in the DR, the data of the next
address in the DDRAM, ABRAM or CGRAM is set in the DR to be ready for the next reading by the CPU.
Writing in or reading from these 3 registers is controlled by changing the status of the R/W (Read/Write) pin.
Table 1 R/W pin status and register operation
W
R/
L L H Writing in the IR
H L H Reading the Busy flag (BF) and the ad dress counter (ADC )
L H H Writing in the DR
H H H Reading from the DR
L L L Writing in the ER
H L L Reading the contrast code
RS
RS
0
1
Operation
Busy Flag (BF)
The status “1” of the Busy Flag (BF) indicates that the ML9041 is carrying out internal operation.
When the BF is “1”, any new instruction is ignored.
When R/W = “H”, RS
= “L” and RS1 = “H”, the data in the BF is output to the DB7.
0
New instructions should be input when the BF is “0”.
When the BF is “1”, the output code of the address counter (ADC) is undefined.
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Address Counter (ADC)
The address counter provides a read/write address for the DDRAM, ABRAM or CGRAM and also provides a
cursor display address.
When an instruction code specifying DDR AM, ABRAM or CGRAM addr ess setting is inpu t to the pre-defined
register, the register selects the specified DDRAM, ABRAM or CGRAM and transfers the address code to the
ADC. The address data in the ADC is automatically incremented (or decremented) by 1 after the display data is
written in or read from the DDRAM, ABRAM or CGRAM.
The data in the ADC is output to DB
to DB6 when R/W = “H”, RS0 = “L”, RS1 = “H” and BF = “0”.
0
Timing Generator
The timing generator generates timing sign als for th e internal operation of the ML 9041 activ ated by the instruction
sent from the CPU or for the operation of the internal circuits of the ML9041 such as DDRAM, ABRAM,
CGRAM and CGROM. Timing signals are generated so that the internal operation carried out for L CD displaying
will not be interfered by the internal operation initiated by accessing from the CPU. For example, when the CPU
writes data in the DDRAM, the display of the LCD not corresponding to the written data is not affected.
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Display Data RAM (DDRAM)
This RAM stores the display data represented in 8-bit character coding (see Table 2).
The DDRAM addresses correspond to the display positions (digits) of the LCD as shown below. The DDRAM
addresses (to be set in the ADC) are represented in hexadecimal.
DB
6DB5DB4DB3DB2DB1DB0
DC
(Example) Representation of DDRAM address = 12
MSB
Hexadecimal Hexadecimal
LSB
DC 0 1 0 0 1 0
0
1
2
1) Relationship between DDRAM addresses and display positions (1-line display mode)
Digit
2 3 4 5 19 20
1
00 01 02 03 04 12 13
Left
end
Right
end
Display position
DD RAM address (hexadecimal)
In the 1-line display mode, the ML9041 can display up to 20 characters from digit 1 to digit 20. While the
DDRAM has addresses “00” to “4F” for up to 80 character codes, the area not used for display can be used as a
RAM area for general data. When the display is shifted by instruction, the relationship between the LCD
display and the DDRAM address changes as shown below:
Digit
1
234 1920
(Display shifted to the right)
(Display shifted to the left)
4F 00 01 02 11 12
Digit
2340551920
1
01
02 03 04 13 14
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2) Relationship between DDRAM addresses and display positions (2-line display mode)
In the 2-line mode, the ML9041 can display up to 40 characters (20 characters per line) from digit 1 to digit 20.
Digit
1
Line 1
Line 2
2345
00 01 02 03 04
40 41 42 43 44 52 53
19 20
12 13
Display position
DD RAM
address (hexadecimal)
Note: T he DDRAM addr ess at digi t 20 in the first line is n ot consecutive to the DD RAM addres s at
digit 1 in the second line.
When the display is shifted by instruction, the relationship between the LCD display and the DDRAM address
changes as shown below:
Digit
(Display shifted to the right)
234
1
Line 1
27 00 01 02
Line 2
67 40 41 42 51 52
5
03
43
19 20
11 12
(Display shifted to the left)
Line 1
Line 2
Digit
1
234
01 02 03 04
41 42 43 44
5
05
45 53 54
19 20
13 14
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Character Generator ROM (CGROM)
The CGROM generates small character patterns (5 × 7 dots, 160 patterns) or large character patterns (5 × 10 dots,
32 patterns) from the 8-bit character code signals in the DDRAM.
When the 8-bit character code corresponding to a character pattern in the CGROM is written in the DDRAM, the
character pattern is displayed in the display position specified b y the DDRAM address.
Character codes 20 to 7F and A0 to FF are contained in the character code area in the CG ROM.
Character codes 20 to 7F and A0 to DF are contained in the character code area f or the 5 × 7-dot character patterns.
Character codes E0 to FF are contained in the ROM area for 5 × 10-dot character patterns.
The general character generator ROM codes are 01A/01B.
The relationship between character codes and general purpose character patterns are indicated in Table2.
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Character Generator RAM (CGRAM)
The CGRAM is used to generate user-specific character patterns that are not in the CGROM. CGRAM (64 bytes =
512 bits) can store up to 8 small character patterns (5 × 8 dots) or up to 4 large character patterns (5 × 11 dots).
When displaying a character pattern stored in the CGRAM, write an 8-bit character code (00 to 07 or 08 to 0F;
hex.) assigned in Table 2 to the DDRAM. This enables outputting the character pattern to the LCD display
position corresponding to the DDRAM address.
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the
cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM addr ess.
The following describes how character patterns are written in and read from the CGRAM.
1) Small character patterns (5 × 8 dots) (See Table 3-1.)
(1) A method of writing character patterns to the CGRAM from the CPU
The three CGRAM address bits 0 to 2 select one of the lines constituting a character pattern.
First, set the mode to increment or decrement from the CPU, and then input the CG RAM address.
Write each line of the character pattern code in the CGRAM through DB
The data lines DB
to DB7 correspond to the CGRA M data bits 0 t o 7, respectiv ely (s ee Table 3-1). In put
0
to DB7.
0
data “1” represents the ON status of an LCD dot and “0” represents the OFF status. Since the ADC is
automatically incremented or decremented by 1 after the data is written to the CGRAM, it is not necessary
to set the CGRAM address again.
The bottom line of a character pattern (the CGRAM address bits 0 to 2 are all “1”, which means 7 in
hexadecimal) is the cursor line. The ON/OFF pattern of this line is ORed with the cursor pattern for
displaying on the LCD. Therefore, the pattern data for the cursor position should be all zeros to display
the cursor.
Whereas the data given by the CGRAM data bits 0 to 4 is output to the LCD as display data, the data given
by the CGRAM data bits 5 to 7 is not. Therefore, th e CGRAM data bits 5 to 7 can be used as a RAM area.
(2) A method of displaying CGRAM character patterns on the LCD
The CGRAM is selected when the higher-order 4 bits of a character code are all zeros. Since bit 3 of a
character code is not used, the character pattern “0” in Table 3-1 can be selected us ing the ch aracter code
“00” or “08” in hexadecimal.
When the 8-bit character code corresponding to a character pattern in the CGRAM is written to the
DDRAM, the character pattern is displayed in the display position specified by the DDRAM address.
(The DDRAM data bits 0 to 2 correspond to the CGRAM address bits 3 to 5, respectively.)
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2) Large character patterns (5 × 11 dots) (See Table 3-2.)
(1) A method of writing character patterns to the CGRAM from the CPU
The four CGRAM address bits 0 to 3 select one of the lines constituting a character pattern.
First, set the mode to increment or decrement from the CPU, and then input the CG RAM address.
Write each line of the character pattern code in the CGRAM through DB
The data lines DB
to DB7 correspond to the CGRA M data bits 0 t o 7, respectiv ely (s ee Table 3-2). In put
0
data “1” represents the ON status of an LCD dot and “0” represents the OFF status. Since the ADC is
automatically incremented or decremented by 1 after the data is written to the CGRAM, it is not necessary
to set the CGRAM address again.
The bottom line of a character pattern (the CGRAM address bits 0 to 3 are all “1”, which means A in
hexadecimal) is a cursor line. The ON/OFF patter n of this line is ORed with the cursor pattern for
displaying on the LCD. Therefore, the pattern data for the cursor position should be all zeros to display
the cursor.
Whereas the data given by the CGRAM data bi ts 0 to 4 with th e CGRAM addresses 0 to A in h exadecimal
(set by the CGRAM address bits 0 to 3) is output as display data to the LCD, the data given by the
CGRAM data bits 5 to 7 or the CGRAM addresses B to F in hexadecimal is not. These bits can be written
and read as a RAM area.
(2) A method of displaying CGRAM character patterns on the LCD
The CGRAM is selected when the higher-order 4 bits of a character code are all zeros. Since bits 0 and 3
of a character code are not used, the character pattern “β” in Table 3-2 can be selected with a character
code “00”, “01”, “08” or “09” in hexadecimal.
When the 8-bit character code corresponding to a character pattern in the CGRAM is written to the
DDRAM, the character pattern is displayed in the display position specified by the DDRAM address.
(The DDRAM data bits 1 and 2 correspond to the CGRAM address bits 4 and 5, respectively.)
to DB7.
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Arbitrator RAM (ABRAM)
The arbitrator RAM (ABRAM) stores arbitrator display data.
The ABRAM address is set at the ADC with the relationship illustrated below. Its valid address area is 00 to 19
(00H to 13H).
Although an address exceeding 19 (13H) can be set or the address already set may exceed it due to automatic
increment or decrement processing, any address out of the valid address area is ignored.
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the
cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address.
DC
DB6DB5DB4DB3DB2DB1DB
MSB
0
LSB
Hexadecimal Hexadecimal
The arbitrator RAM can store a maximum of 100 dots of the arbitrator Display-ON data in units of 5 dots.
The arbitrator display is not shifted b y any instructions and has the following relationship with the LCD displa y
positions.
Relationship between display-O N
Configuration of input display data
Input data
DB
6
7
* * E4 E3 E2 E1 E0
*
DB5DB4DB3DB2DB1DB
DB
* Don’t Care
Display - ON data
5XSn+1 5XSn+5
0
data and segment pins
E4 E4
Sn = AB RAM address
0 to 19
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Table 2 Relationship between Character Codes and Character Patterns of the ML9041-01A/01B
(General Character Codes)
The character code area in the CG ROM: Character codes 20H to 7FH, A0H to FFH.
5×7-dot ROM area: 20H to 7FH, A0H to DFH
5×10-dot ROM area: E0H to FFH
The CG RAM area : Character codes 00H to 0FH
00H:
20H: 28H: ( 30H: 0 38H: 8
08H:
40H: @ 48H: H 50H: P
CG RAM(1)
01H:
CG RAM(2)
02H:
CG RAM(3)
03H:
CG RAM(4)
04H:
CG RAM(5)
CG RAM(1)
09H:
CG RAM(2)
0AH:
CG RAM(3)
0BH:
CG RAM(4)
0CH:
CG RAM(5)
21H: ! 29H: ) 31H: 1 39H: 9
22H: " 2AH: *32H: 2 3AH: :
23H: # 2BH: + 33H: 3 3BH: ;
24H: $ 2CH: , 34H: 4 3CH: <
41H: A 49H: I 51H: Q
42H: B 4AH: J 52H: R
43H: C 4BH: K 53H: S
44H: D 4CH: L 54H: T
05H:
CG RAM(6)
06H:
CG RAM(7)
07H:
CG RAM(8)
0DH:
CG RAM(6)
0EH:
CG RAM(7)
0FH:
CG RAM(8)
25H: % 2DH: - 35H: 5 3DH: =
26H: & 2EH: . 36H: 6 3EH: >
27H: ' 2FH: / 37H: 7 3FH: ?
45H: E 4DH: M 55H: U
46H: F 4EH: N 56H: V
47H: G 4FH: O 57H: W
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001
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Table 3-1 Relationship between CGRAM address bits, CGRAM data bits (character pattern)
and DDRAM data bits (character code) in 5 ×××× 7 dot character mode. (Examples)
CG RAM
address
543210
MSB
000000
001000
111000
×
LSB MSB LSB MSB LSB
010
011
100
101
110
111
010
011
100
101
110
111
010
011
100
101
110
111
: Don’t Care
CG RAM data
Character pattern
76543210 76543210
01110
×××
10001
10001
10001
10001
10001
01110
00000
×××
10001
10010
10100
11000
10100
10010
10001
00000
×××
01110
00100
00100
00100
00100
00100
01110
00000
DD RAM data
Character code
0000×000
0000×001
0000×111
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Table 3-2 Relationship between CGRAM address bits, CGRAM data bits (character pattern)
and DDRAM data bits (character code) in 5 ×××× 10 dot character mode (Examples)
CG RAM CG RAM data
address
54321076543210 76543210
MSB
000000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
010000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Character pattern
LSB
MSB LSB MSB LSB
×××
01000
01111
10010
01111
01010
11111
00010
00000
00000
00000
00000
ЧЧЧЧЧ
00000
×××
00000
01111
10001
10001
10001
01111
00001
00001
01110
00000
ЧЧЧЧЧ
DD RAM data
(Character code)
0000×00
0000×01
×
×
110000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
×
: Don’t Care
×××
00000
00000
11011
01010
10001
10001
01110
00000
00000
00000
00000
ЧЧЧЧЧ
0000×11
×
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Cursor/Blink Control Circuit
This circuit generates the cursor and blink of the LCD.
The operation of this circuit is controlled by the program of the CPU.
The cursor/blink display is carried out in the position corresponding to the DDRAM address set in the ADC
(Address Counter).
For example, when the ADC stores a value of “07” (hexadecimal), the cursor or blink is displayed as follows:
DC
In 1-line display mode
In 2-line display mode
First line
Second line
DB
6
0
000111
Digit
1
2345 89
01 02 03 04 07 08
00
Digit
1
2345 89
00 01 02 03 04 07 08
40 41 42 43 44 47 48 52 5345 46
DB
0
70
05 06
Cursor/blink position
05 06
Cursor/blink position
19 2067
12 13
19 2067
12 13
Note: The cursor or blink is also displa yed even when a CGRAM or ABR AM addres s is set in
the ADC. Therefore, the curs or or blink display sho uld be inhibited while the ADC is
holding a CGRAM or ABRAM address .
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LCD Display Circuit (COM1 to COM17, SEG1 to SEG100, SSR and CSR)
The ML9041 has 17 common signal ou tputs and 100 s egmen t signal outpu ts to display 20 charact ers (in the 1- line
display mode) or 40 characters (in the 2-line display mode).
The character pattern is converted into serial data and transferred in series through the shift register.
The transfer direction of serial data is determined by the SSR pin. The shift direction of common signals is
determined by the CSR pin. The following tables show the transfer and shift directions:
SSR Transfer direction
L SEG1 → SEG
H SEG
CSR duty AS bit Shift Direction Arbitrator’s common pin
L1/9L COM1
L1/9HCOM2
L1/12L COM1
L1/12HCOM2
L1/17L COM1
L1/17HCOM2
H1/9L COM9
H1/9HCOM8
H 1/12 L COM12 → COM1 COM1
H 1/12 H COM11 → COM1, COM12 COM12
H 1/17 L COM17 → COM1 COM1
H 1/17 H COM16 → COM1, COM17 COM17
100
→ SEG
→
→
100
1
→
COM9 COM9
→
COM9, COM1 COM1
→
COM12 COM12
COM12, COM1 COM1
→
COM17 COM17
COM17, COM1 COM1
→
COM1 COM1
→
COM1, COM9 COM9
* Refer to the Expansion Instruction Codes section about the AS bit.
Signals to be input to the SSR and CSR pins should be determined at power-on and be kept unchanged.
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Built-in Reset Circuit
The ML9041 is automatically initialized when the power is turned on.
During initialization, the Busy Flag (BF) is “1” and the ML9041 does not accept any instruction from the CPU
(other than the Read BF instruction).
The Busy Flag is “1” for about 15 ms after the V
becomes 2.5 V or higher.
DD
During this initialization, the ML9041 performs the following instructions:
1) Display clearing
2) CPU interface data length = 8 bits (DL = “1”)
3) 1-line LCD display (N = “0”)
4) Font size = 5 × 7 dots (F = “0”)
5) ADC counting = Increment (I/D = “1”)
6) Display shifting = None (S = “0”)
7) Display = Off (D = “0”)
8) Cursor = Off (C = “0”)
9) Blinking = Off (B = “0”)
10) Arbitrator = Displayed in the lower line (AS = “0”)
11) Setting 1FH (hexadecimal) to the Contrast Data
To use the built-in reset circuit, the power supply conditions shown below should be satisfied. Otherwise, the
built-in reset circuit may not work properly. In such a case, initialize the ML9041 with the instructions from the
CPU. The use of a battery always requires such initialization from the CPU. (See “Initial Setting of Instructions”)
2.5 V
0.2 V 0.2 V 0.2 V
t
ON
0.1 ms ≤ tON ≤100 ms
1 ms ≤ t
OFF
t
OFF
Figure 1 Power-on and Power-off Waveform
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I/F with CPU
Parallel interface mode
The ML9041 can transfer either 8 bits once or 4 bits twice on the data bus for interfacing with any 8-bit or 4-bit
microcontroller (CPU).
1) 8-bit interface data length
The ML9041 uses all of the 8 data bus lines DB
to DB7 at a time to transfer data to and from the CPU.
0
2) 4-bit interface data length
The ML9041 uses only th e higher-order 4 data bu s lin es D B
to DB7 twice to transfer 8-bit data to and from the
4
CPU.
The ML9041 first transfers the higher-order 4 bits of 8-bit data (DB
length) and then the lower-order 4 bits of the data (DB
to DB3 in the case of 8-bit interface data length).
0
to DB7 in the case of 8-bit interface data
4
The lower-order 4 bits of data should always be transferred even when only the transfer of the higher-order 4
bits of data is required. (Example: Reading the Busy Flag)
Two transfers of 4 bits of data complete the transfer of a set of 8-bit data. Therefore, when only one access is
made, the following data transfer cannot be completed properly.
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Busy
(Internal operation)
RS
RS
R/
E
DB
DB
DB
DB
DB
DB
DB
DB
PEDL9041-03
ML9041-xxA/xxB
1
0
No
IR
IR
IR
IR
IR
IR
IR
IR
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Busy
Busy
ADC
ADC
ADC
ADC
ADC
ADC
ADC
6
5
4
3
2
1
0
DR
DR
DR
DR
DR
DR
DR
DR
7
6
5
4
3
2
1
0
RS
1
RS
0
W
R/
E
Busy
(Internal operation)
DB
7
DB
6
DB
5
DB
4
IR
IR
7
IR
IR
6
IR
IR
5
IR
IR
4
Writing In IR
(Instruction
Register)
Writing In IR
(Instruction
Reading BF (Busy Flag)
and ADC (Address Counter)
Register)
Figure 2 8-Bit Data Transfer
3
2
1
0
Busy
Reading BF (Busy Flag)
and ADC (Address Counter)
No
Busy
ADC
ADC
ADC
ADC
ADC
6
ADC
5
ADC
4
Writing In DR
(Data Register)
3
2
1
0
DR
DR
7
3
DR6DR
DR5DR
DR4DR
2
1
0
Writing In DR
(Data Register)
Figure 3 4-Bit Data Transfer
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Serial Interface Mode
PEDL9041-03
ML9041-xxA/xxB
In the Serial I/F Mode, the ML9041 interfaces with the CPU via the CS,
SHT
, SI and SO pins.
Writing and reading operations are executed in units of 16 bits after the CS signal falls down. If the CS signal rises
up before the completion of 16-bit unit access, this access is ignored.
When the BF bit is “1”, the ML9041 cannot accept any other instructions. Before inputting a new instruction,
check that the BF bit is “0”. Any access when the BF bit is “1” is ignored.
Data format is LSB-first.
Examples of Access in the Serial I/F Mode
1) WRITE MODE
S
12345
6 7 8 9 10 11 12 13 14 15 16
HT
SI
11111
R/
7
6
5
4
3
2
1
0
1
0
D
D
D
D
D
D
D
D
RS
RS
W
SO
2) READ MODE
SI
12345
11111
6 7 8 9 10 11 12 13 14 15 16
RS
R/
RS
1
0
D
D
D
D
D
D
D
1
0
3
2
5
4
D
7
6
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Instruction Codes
Table of Instruction Codes
Instruction
Display Clear 1 0 0 0 0 0 0 0 0 0 1
Cursor Home 1 0 0 0 0 0 0 0 0 1 X
Entry Mode
Setting
Display
ON/OFF Control
Cursor/Display
Shift
Function Setting 1 0 0 0 0 1 DL N F X X
CGRAM
Address Setting
DDRAM
Address Setting
Busy Flag/
Address Read
RAM Data Write 1 1 0 WRITE DATA
RAM Data Read 1 1 1 READ DATA
Arbitrator
Display Line Set
Contrast Control
Data Write
Contrast Control
Data Read
ABRAM
Address Setting
—
RS
1 0 0 0 0 0 0 0 1 I/D S
100 00001DCB
100 0001S/CR/LXX
100 01 ACG
100 1 ADD
101BF ADC
0 0 0 0 0 0 0 0 0 1 AS Sets the arbitrator display line. 37 µs
000 001
001 000
000 011 AAB
I/D = “1” (Increment) I/D = “0” (Decrement)
S = “1” (Shifts the display.)
S/C = “1”(Shifts display.) S/C = “0” (Moves the cursor.)
R/L = “1” (Right shift) R/L = “0” (Left shift)
D/L = “1” (8-bit dat a) DL = “0” (4-bit data)
N = “1” (2 lines) N = “0” (1 line)
F = “1” (5 x 10 dots) F = “0” (5 x 7 dots)
BF = “1” (Busy) BF = “0” (Ready to accept
B = “1” (Enables blinki ng)
C = “1” (Displays the cursor.)
D = “1” (Displays a character pattern.)
AS = “1” (Arbitrator Displays AS = “0” (Arbitrator Displays
R/WDB7DB6DB5DB4DB3DB2DB1DB
1RS0
arbitrator on the arbi t rator on the
upper line) lower line)
Code
WRITE (Contrast Data)
DATA
READ (Contrast Data)
DATA
an instruction)
ML9041-xxA/xxB
0
Clears all the displayed digits of the
LCD and sets the DDRAM address 0 in
the address counter. The arbitrator
data is cleared.
Sets the DDRAM address 0 in the
address counter and shifts the display
back to the original. The content of the
DDRAM remains unchanged.
Determines the direction of movement
of the cursor and whether or not to shift
the display. This instruction is
executed when data is written or read.
Sets LCD display ON/OFF (D), cursor
ON/OFF or cursor-position character
blinking ON/OFF.
Moves the cursor or shifts the display
without changing the content of the
DDRAM.
Sets the interface data length (DL), the
number of display lines (N) or the type
of character font (F).
Sets on CGRAM address. After that,
CGRAM data is transferred to and from
the CPU.
Sets a DDRAM address. After that,
DDRAM data is transferred to and from
the CPU.
Reads the Busy Flag (indicating that
the ML9041 is operating) and the
content of the address counter.
Writes data in DDRAM, ABRAM or
CGRAM.
Reads data from DDRAM, ABRAM or
CGRAM.
Writes data to control the contrast of
the LCD.
Reads data to control the contrast of
the LCD.
Sets an ABRAM address. After that,
ABRAM data is transferred to and from
the CPU.
DD RAM: Display data RAM
CG RAM: Character generator RAM
ABRAM: Arbitrator data RA M
ACG: CGRAM address
ADD: DDRAM address
AAB: ABRAM address
ADC: Address counter (Used by
Function
(Corresponds to the cursor
address)
DDRAM, ABRAM and
CGRAM)
PEDL9041-03
Execution
Time
f = 270 kHz
1.52 ms
1.52 ms
37 µs
37 µs
37 µs
37 µs
37 µs
37 µs
0 µs
37 µs
37 µs
37 µs
37 µs
37 µs
The
execution
time is
dependent
upon
frequencies.
×
: Don't Care
33/60
PEDL9041-03
1
Semiconductor
ML9041-xxA/xxB
Instruction Codes
An instruction code is a signal sent from the CPU to access the ML9041. The ML9041 starts operation as
instructed by the code received. The busy status of the ML9041 is rather longer than the cycle time of the CPU,
since the internal process ing of the ML 9041 st arts at a t iming w hich does not aff ect the display on the LCD. In th e
busy status (Busy Flag is “1”), the ML9041 executes the Busy Flag Read instruction only. Therefore, the CPU
should ensure that the Busy Flag is “0” before sending an instruction code to the ML9041.
1) Displa y Clear
W
R/
0
DB
DB
7
0
0
DB
6
0
DB
5
0
DB
4
0
DB
3
0
DB
2
0
DB
1
0
1
Instruction Code:
RS
RS
1
1
0
When this instruction is executed, the LCD display including arbitrator display is cleared and the I/D entry
mode is set to “Increment”. The value of “S” (Display shifting) remains unchanged. The position of the cursor
or blink being displayed moves to the left end of the LCD (or the left end of the line 1 in the 2-line display
mode).
Note: All DDRAM and ABRAM data turn to “ 20” an d “00” in h exadecimal , res pecti v ely. The v alu e of the
address counter (ADC) turns to the one corresponding to the address “00” (hexadecimal) of the
DDRAM.
The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 kHz.
2) Cursor Home
W
R/
0
DB
DB
7
0
0
DB
6
0
DB
5
0
DB
4
0
DB
3
0
DB
2
0
DB
1
1
×
Instruction code:
RS
1
1
×
: Don’t Care
RS
0
When this instruction is executed, the cursor or blink position moves to the left end of the LCD (or the left end
of line 1 in the 2-line display mode). If the display has been shifted, the display returns to the original display
position before shifting.
Note: The value of the address counter (ADC) goes to the one corresponding to the address “00”
(hexadecimal) of the DDRAM).
The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 kHz.
0
0
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Semiconductor
3) Entry Mode Setting
PEDL9041-03
ML9041-xxA/xxB
W
R/
0
DB
0
DB
7
0
DB
6
0
DB
5
0
DB
4
0
DB
3
0
DB
I/D
DB
1
S
2
1
Instruction code:
RS
RS
1
1
0
(1) When the I/D is set, the cursor or blink shifts to the right by 1 character position (ID= “1”; increment) or to
the left by 1 character position (I/D= “0”; decrement) after an 8-bit character code is written to or read
from the DDRAM. At the same time, the address counter (ADC) is also incremented by 1 (when I/D =
“1”; increment) or decremented by 1 (when I/D = “0”; decrement). After a character pattern code is
written to or read from the CGRAM, the address counter (ADC) is incremented by 1 ( when I/D = “1”;
increment) or decremented by 1 (when I/D = “0”; decrement).
Also after data is written to or read from the ABRAM, the address counter ( ADC) is incremented by 1
(when I/D = “1”; increment) or decremented by 1 (when I/D = “0”; decrement).
(2) When S = “1”, the cursor or blink stops and the entire display shifts to the left (I/D = “1”) or to the right
(I/D = “0”) by 1 character position after a character code is written to the DDRAM.
In the case of S = “1”, when a character code is read from the DDRAM, when a character pattern data is
written to or read from the CGRAM or when data is written to or read from the ABRAM, normal
read/write is carried out without shifting of the entire display. (The entire display does not shift, but the
cursor or blink shifts to the right (I/D = “1”) or to the left (I/D = “0”) by 1 character position.)
When S = “0”, the display does not shift, but normal write/read is performed.
Note: The execution time of this instruction is 37 µs (maximum) at an oscillation frequency of
270 kHz.
4) Display Mode Setting
0
W
R/
0
DB
0
DB
7
0
DB
6
0
DB
5
0
DB
4
0
DB
3
1
DB
2
D
DB
1
C
0
B
Instruction code:
RS
RS
1
1
0
(1) The “D” bit (DB2) of this instruction determines whether or not to display character patterns on the LCD.
When the “D” bit is “1”, character patterns are displayed on the LCD.
When the “D” bit is “0”, character patterns are not displayed on the LCD and the cursor/blink setting is
also canceled.
Note: Unlike the Display Clear instruction, this instruction does not change the character code in the
DDRAM and ABRAM.
(2) W hen the “C” bit (DB1) is “0”, the cursor turns off. When both the “C” and “D” bits are “1”, the cursor
turns on.
(3) When the “B” bit (DB0) is “0”, blinking is canceled. When both the “ B” and “D” bits are “1”, blink ing is
performed.
In the Blinking mode, all dots including those of the cursor, the character pattern and the cursor are
alternately displayed.
Note: The execution time of this instruction is 37 µs (maximum) at an oscillation frequency of
270 kHz.
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Semiconductor
5) Cursor/Display Shift
PEDL9041-03
ML9041-xxA/xxB
W
R/
0
DB
DB
7
0
0
DB
6
0
DB
5
0
DB
4
1
S/C
DB
3
2
R/L
DB
×
DB
1
0
×
Instruction code:
RS
1
1
×
: Don’t Care
RS
0
S/C = “0”, R/L = “0” This instruction shifts left the cursor and blink positions by 1 (decrements the
content of the ADC by 1).
S/C = “0”, R/L = “1” This instruction shifts right the cursor and blink positions by 1 (increments the
content of the ADC by 1).
S/C = “1”, R/L = “0” This instruction shifts le ft the entire display by 1 character position. The cursor
and blink positions move to the left together with the entire display.
The Arbitrator display is not shifted.
(The content of the ADC remains unchanged.)
S/C = “1”, R/L = “1” This instruction shifts right the entire disp la y by 1 character position. The cursor
and blink positions move to the right together with the entire display.
The Arbitrator display is not shifted.
(The content of the ADC remains unchanged.)
In the 2-line mode, the cursor or blink moves from the first line to the second line when the cursor at digit 40
(27; hex) of the first line is shifted right.
When the entire display is shifted, the character pattern, cursor or blink will not move between the lines (from
line 1 to line 2 or vice versa).
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
6) Function Setting
W
R/
0
DB
0
DB
7
0
DB
6
0
DB
5
1
DL
DB
4
DB
3
N
DB
2
F
DB
1
×
×
Instruction code:
RS
RS
1
1
×
: Don’t Care
0
(1) When the “DL” b it (DB4) of this instruction is “1”, the data transfer to and from the CPU is performed
once by the use of 8 bits DB
When the “DL” bit (DB
twice by the use of 4 bits DB
(2) The 2-line display mode is selected when the “N” bit (DB
to DB0.
7
) of this instruction is “0”, the data transfer to and from the CPU is performed
4
to DB4.
7
) of this instruction is “1”. The 1-line display
3
mode is selected when the “N” bit is “0”.
×
(3) T he character font represented by 5
The character font represented by 5
7 dots is selected when the “F” bit (DB2) of this instruction is “1”.
×
10 dots is selected when the “F” bit is “1” and the “N” bit is “0”.
After the ML9041 is powered on, this initial setting should be carried out before execution of any
instruction except the Busy Flag Read. After this initial sett ing, no instructions other than the DL Set
instruction can be executed. In the Serial I/F Mode, DL setting is ignored.
NF
Number of
display lines
Font size Duty
00 1 5 × 7 1/9 4 9
01 1 5 × 10 1/12 4 12
10 2 5 × 7 1/17 5 17
11 2 5 × 7 1/17 5 17
Number of
biases
Number of
common signals
0
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of
270 kHz.
36/60
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Semiconductor
7) CGRAM Address Setting
PEDL9041-03
ML9041-xxA/xxB
W
R/
0
DB
0
DB
7
0
DB
6
1
DB
5
C
5
DB
4
C
4
DB
3
C
3
DB
2
C
2
DB
1
C
C
1
Instruction code:
RS
RS
1
1
0
This instruction sets the character data corresponding to the CGRAM address represented by the bits C5 to C
(binary).
The CGRAM addresses are valid until DDRAM or ABRAM addresses are set.
The CPU writes or reads character patterns starting from th e one represented by the CGRAM addres s bits C
set in the instruction code at that time.
C
0
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
8) DDRAM Address Setting
W
R/
0
DB
0
DB
7
1
DB
6
D
6
DB
5
D
5
DB
4
D
4
DB
3
D
3
DB
2
D
2
DB
1
D
1
Instruction code:
RS
RS
1
1
0
This instruction sets the character data corresponding to the DDRAM address represented by the bits D6 to D
(binary).
The DDRAM addresses are valid until CGRAM or ABRAM addresses are set.
The CPU writes or reads character patterns starting f rom the one represented by the DDRAM address bits D
D
set in the instruction code at that time.
0
In the 1-line mode (the “N” bit is “1”), the DDRAM address represented by bits D
to D0 (binary) should be in
6
the range “00” to “4F” in hexadecimal.
In the 2-line mode (the “N” bit is “2”), the DDRAM address represented by bits D
to D0 (binary) should be in
6
the range “00” to “27” or “40” to “67” in hexadecimal.
If an address other than above is input , the ML9041 cannot properly write a character code in or read it f rom the
DDRAM.
0
0
0
to
5
0
D
0
0
to
6
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
9) DDRAM/ABRAM/CGRAM Data Write
W
R/
0
DB
0
DB
7
E
7
DB
6
E
6
DB
5
E
5
DB
4
E
4
DB
3
E
3
DB
2
E
2
DB
1
E
E
1
0
Instruction code:
RS
RS
1
1
1
This instruction writes data represented by bits E7 to E0 (binary) to DDRAM, ABRAM or CGRAM.
After data is written, the cursor, blink or displa y shifts according to the Cursor/Disp lay Shift instruction (see
5)).
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
0
37/60
1
Semiconductor
10) Busy Flag/Address Counter Read (Execution time: 1 µs)
PEDL9041-03
ML9041-xxA/xxB
W
R/
0
DB
1
BF
DB
7
DB
6
O
6
DB
5
O
5
DB
4
O
4
DB
3
O
3
DB
2
O
2
DB
1
O
O
1
0
Instruction code:
RS
RS
1
1
0
The “BF” bit (DB7) of this instruct ion tells whether the ML 9041 is busy in in ternal operation (BF = “1”) or n ot
(BF = “0”).
When the “BF” bit is “1”, the ML9041 cannot accept any oth er instructions. Before inputting a new instruction,
check that the “BF” bit is “0”.
When the “BF” bit is “0”, the ML9041 outputs the correct value of the address counter. The value of the
address counter is equal to the DDRAM, ABRAM or CGRAM address. Which of the DDRAM, ABRAM and
CGRAM addresses is set in the counter is determined by the preceding address setting.
When the “BF” bit is “1”, the value of the address counter is not always correct because it may have been
incremented or decremented by 1 during internal operation.
11) DDRAM/ABRAM/CGRAM Data Read
W
R/
0
DB
1
DB
7
P
7
DB
6
P
6
DB
5
P
5
DB
4
P
4
DB
3
P
3
DB
2
P
2
DB
1
P
P
1
Instruction code:
RS
RS
1
1
1
A character code (P7 to P0) is read from the DDRAM, Display-ON data (P7 to P0) from the ABRAM or a
character pattern (P
to P0) from the CGRAM.
7
The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.
After data is read, the address counter (ADC) is incremented or decremented as set by the Transfer Mode
Setting instruction (see 3).
0
0
0
Note: Conditions for reading correct data
(1) The DDRAM, ABRAM or CGRAM Setting instruction is input before this data read instruction is input.
(2) W hen reading a character code from the DDRAM, the Cursor/Display Shift instruction (see 5) is input
before this Data Read instruction is input.
(3) W hen two or more consecutive RAM Data Read instructions are executed, the following read data is
correct.
Correct data is not output under conditions other than the cases (1), (2) and (3) above.
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
38/60
PEDL9041-03
1
Semiconductor
ML9041-xxA/xxB
Expansion Instruction Codes
The busy status of the ML9041 is rather longer t han th e cycle time of the CPU, since the i nternal processing of th e
ML9041 starts at a timing which does not affect th e display on the LCD. In the busy status (Busy Fl ag is “1”), the
ML9041 executes the Busy Flag Read instruction only. Therefore, the CPU should ensure that the Busy Flag is
“0” before sending an expansion instruction code to the ML9041.
1) Arbitrator Display Line Set
W
R/
0
DB
0
DB
7
0
DB
6
0
DB
5
0
DB
4
0
DB
3
0
DB
2
0
DB
1
1
AS
Expansion instruction code:
RS
RS
1
0
0
This expansion instruction code sets the Arbitrator display line. The relationship between the status of this bit
and the common outputs is as follows:
For display examples, refer to LCD Drive Waveforms section.
CSR duty AS bit Shift direction Arbitrator’s common pin
L1/9 L COM1
L1/9 H COM2
L1/12 L COM1
L1/12 H COM2
L1/17 L COM1
L1/17 H COM2
H1/9 L COM9
H1/9 H COM8
H1/12 L COM12
H1/12 HCOM11
H1/17 L COM17
H1/17 HCOM16
→
COM9 COM9
→
COM9, COM1 COM1
→
COM12 COM12
→
COM12, COM1 COM1
→
COM17 COM17
→
COM17, COM1 COM1
→
COM1 COM1
→
COM1, COM9 COM9
→
COM1 COM1
→
COM1, COM12 COM12
→
COM1 COM1
→
COM1, COM17 COM17
0
2) Contrast Adjusting Data Write
W
R/
0
DB
0
DB
7
0
DB
6
0
DB
5
1
DB
4
F
4
DB
3
F
3
DB
2
1
F
F
2
1
Expansion instruction code:
RS
RS
1
0
0
This instruction writes contrast adjusting data (F4 to F0) to the contrast register.
After contrast adjusting data is written in the register, the potential (VLCD) output to the V
pin varies
5
according to the data written.
The VLCD becomes maximum when the content of the contrast register is “1F” (hexadecimal) and becomes
minimum when it is “00” (hexadecimal).
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
DB
0
F
0
39/60
1
Semiconductor
3) Co ntrast Adjusting Data Read
PEDL9041-03
ML9041-xxA/xxB
W
R/
0
DB
1
DB
7
0
DB
DB
6
5
0
0
DB
4
G
4
DB
3
G
3
DB
2
1
G
G
2
1
Expansion instruction code:
RS
RS
1
0
0
This instruction reads contrast adjusting data (G4 to G0) from the contrast register.
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
4) ABRAM Address Setting
W
R/
0
DB
1
DB
7
0
DB
6
5
1
1
DB
H
DB
4
4
DB
3
H
3
DB
2
1
H
H
2
1
Expansion instruction code:
RS
RS
1
0
0
This instruction sets the character data corresponding to the ABRAM address represented by the bits H4 to H
(binary).
The ABRAM addresses are valid until CGRAM or DDRAM addresses are set.
The CPU writes or reads character patterns starting from the one repres ented by the ABRAM address bits H
H
set in the instruction code at that time.
0
The ABRAM address represented by bits H
to H0 (binary) should be in the range “00” to “13” in h exadecimal.
4
If an address other than above is input , the ML9041 cannot properly write a character code in or read it f rom the
DDRAM.
Note: The execution time of this instruction is 37 µs at an oscillation frequency (OSC) of 270 kHz.
DB
G
DB
H
0
0
0
0
0
to
4
40/60
PEDL9041-03
A
A
1
Semiconductor
ML9041-xxA/xxB
LCD Drive Waveforms
The COM and SEG waveforms (AC signal waveforms for display) vary according to the duty (1/9, 1/12 and 1/17
duties). See 1) to 3) below.
The relationship between the duty ratio and the frame frequency is as follows:
Duty ratio Frame Frequency
1/9 75.0 Hz
1/12 56.3 Hz
1/17 79.4 Hz
Note: At an oscillation frequency (OSC) of 270 kHz
(1) Driving the LCD of one 20-character line under the conditions of the 1-line display mode and the character
font of 5 × 7 dots
(1/9 duty, AS = 0, CSR = L, SSR = H)
COM
COM
COM
•
COM
to COM17 output Display-OFF common signals.
10
(1/9 duty, AS = 1, CSR = L, SSR = H)
COM
COM
COM
1
8
9
1
2
9
SEG
ML9041
100
SEG
Character
Cursor
rbitrator
1
rbitrator
Character
Cursor
SEG
100
SEG
1
ML9041
•
COM
to COM17 output Display-OFF common signals.
10
41/60
1
A
A
Semiconductor
(1/9 duty, AS = 0, CSR = H, SSR = L)
PEDL9041-03
ML9041-xxA/xxB
ML9041
•
SEG
Character
Cursor
rbitrator
COM
to COM17 output Display-OFF common signals.
10
(1/9 duty, AS = 1, CSR = H, SSR = L)
rbitrator
Character
Cursor
1
SEG
SEG
100
COM
9
COM
2
COM
1
ML9041
1
SEG
100
COM
COM
COM
9
8
1
•
COM
to COM17 output Display-OFF common signals.
10
42/60
PEDL9041-03
A
A
1
Semiconductor
ML9041-xxA/xxB
(2) Driving the LCD of one 20-character line under the conditions of the 1-line display mode and the character
font of 5 × 10 dots
(1/12 duty, AS = 0, CSR = L, SSH = H)
COM
1
Character
COM
COM
11
12
Cursor
rbitrator
•
COM
to COM17 output Display-OFF common signals.
13
(1/12 duty, AS = 1, CSR = L, SSR = H)
COM
COM
COM
•
COM
to COM17 output Display-OFF common signals.
13
SEG
ML9041
1
2
12
ML9041
100
SEG
100
SEG
SEG
1
rbitrator
Character
Cursor
1
43/60
1
A
A
Semiconductor
(1/12 duty, AS = 0, CSR = H, SSR = L)
PEDL9041-03
ML9041-xxA/xxB
ML9041
Character
Cursor
rbitrator
•
COM
to COM17 output Display-OFF common signals.
13
(1/12 duty, AS = 1, CSR = H, SSR = L)
rbitrator
Character
SEG
SEG
1
SEG
100
COM
COM
COM
12
2
1
ML9041
1
SEG
100
COM
COM
12
11
•
Cursor
COM
to COM17 output Display-OFF common signals.
13
COM
1
44/60
PEDL9041-03
A
A
1
Semiconductor
ML9041-xxA/xxB
(3) Driving the LCD of two 20-character lines under the conditions of the 2-line display mode and the character
font of 5 × 7 dots
(1/17 duty, AS = 0, CSR = L, SSR = H)
COM
1
Character
COM
8
COM
9
COM
COM
17
SEG
100
ML9041
(1/17 duty, AS = 1, CSR = L, SSR = H)
COM
1
COM
2
COM
9
COM
10
SEG
Cursor
Character
Cursor
rbitrator
1
rbitrator
Character
Cursor
Character
COM
17
SEG
100
SEG
Cursor
1
ML9041
45/60
1
A
A
Semiconductor
(1/17 duty, AS = 0, CSR = H, SSR = L)
PEDL9041-03
ML9041-xxA/xxB
ML9041
SEG
1
Character
Cursor
Character
Cursor
rbitrator
(1/17 duty, AS = 1, CSR = H, SSR = L)
SEG
1
SEG
SEG
100
ML9041
100
COM
COM
COM
COM
COM
17
10
9
2
1
rbitrator
Character
Cursor
Character
Cursor
COM
COM
COM
COM
COM
17
16
9
8
1
46/60
1
Semiconductor
EXAMPLES OF VLCD GENERATION CIRCUITS
•
With 1/4bias, a built-in contrast adjusting circuit and a voltage multiplier
V
DD
V
1
V
2
V
3A
V
3B
V
ML9041
V
V
5IN
V
V
CC
V
BEB
4
5
C
IN
Reference potential for
voltage multiplier
PEDL9041-03
ML9041-xxA/xxB
•
With 1/4 bias, a built-in contrast adjusting circuit
and the V
level input from an external circuit and the V5 level input from an external circuit
5
V
DD
V
1
V
2
V
3A
V
3B
V
ML9041
4
V
5
V
5IN
V
C
V
CC
V
IN
BEB
V5 level
•
With 1/4 bi as, no buil t-in co ntrast ad justing c ircuit
V
DD
V
1
V
2
V
3A
V
3B
V
ML9041
4
V
5
V
5IN
V
C
V
CC
V
IN
V5 level
BEB
47/60
1
Semiconductor
•
With 1/5 bias, a built-in contrast adjusting circuit and a voltage multiplier
V
DD
V
1
V
2
V
3A
V
3B
V
ML9041
V
V
5IN
V
V
CC
V
BEB
4
5
C
IN
Reference potential for
voltage multiplier
PEDL9041-03
ML9041-xxA/xxB
•
With 1/5 bias, a built-in contrast adjusting circuit
and the V
level input from an external circuit and the V5 level input from an external circuit
5
V
DD
V
1
V
2
V
3A
V
3B
V
ML9041
4
V
5
V
5IN
V
C
V
CC
V
IN
BEB
V5 level
•
With 1/5 bi as, no buil t-in co ntrast ad justing c ircuit
V
DD
V
1
V
2
V
3A
V
3B
V
ML9041
4
V
5
V
5IN
V
C
V
CC
V
IN
V5 level
BEB
48/60
1
Semiconductor
1) COM and SEG Waveforms on 1/9 Duty
COM1 (CSR = L, AS = L)
COM
(CSR = L, AS = H)
2
COM
(CSR = H, AS = L)
9
COM
(CSR = H, AS = H)
8
(first character line)
V
V2, V
8
DD
V
1
3B
V
4
V
5
9
1 2 3 4
···
1 frame
7 8 9 1 2 3 4
7 8 9 1 2
···
PEDL9041-03
ML9041-xxA/xxB
(CSR = L, AS = L)
COM
2
COM
(CSR = L, AS = H)
3
COM
(CSR = H, AS = L)
8
COM
(CSR = H, AS = H)
7
(second character line)
(CSR = L, AS = L)
COM
8
COM
(CSR = L, AS = H)
9
(CSR = H, AS = L)
COM
2
COM
(CSR = H, AS = H)
1
(cursor line)
(CSR = L, AS = L)
COM
9
COM
(CSR = L, AS = H)
1
COM
(CSR = H, AS = L)
1
COM
(CSR = H, AS = H)
9
(arbitrator line)
COM10 to
COM
SEG
V
DD
V
1
V2, V
3B
V
4
V
5
V
DD
V
1
V2, V
3B
V
4
V
5
V
DD
V
1
V2, V
3B
V
4
V
5
V
DD
V
1
V2, V
17
3B
V
4
V
5
Display
turning-off
waveform
V
DD
V
1
V2, V
3B
V
4
V
5
Display
turning-on
waveform
49/60
1
Semiconductor
2) COM and SEG Waveforms on 1/12 Duty
(CSR = L, AS = L)
COM
1
COM
(CSR = L, AS = H)
2
COM
(CSR = H, AS = L)
12
COM
(CSR = H, AS = H)
11
(first character line)
V
V2, V
11
DD
V
1
3B
V
4
V
5
12
1 2 3 4 5 6
1 frame
9 10 1112 1 2 3 4 5 6
···
PEDL9041-03
ML9041-xxA/xxB
···
(CSR = L, AS = L)
COM
2
COM
(CSR = L, AS = H)
3
COM
(CSR = H, AS = L)
11
COM
(CSR = H, AS = H)
10
(second character line)
(CSR = L, AS = L)
COM
11
COM
(CSR = L, AS = H)
12
COM
(CSR = H, AS = L)
2
COM
(CSR = H, AS = H)
1
(cursor line)
(CSR = L, AS = L)
COM
12
COM
(CSR = L, AS = H)
1
COM
(CSR = H, AS = L)
1
COM
(CSR = H, AS = H)
12
(arbitrator line)
COM13 to
COM
SEG
V
DD
V
1
V2, V
3B
V
4
V
5
V
DD
V
1
V2, V
3B
V
4
V
5
V
DD
V
1
V2, V
3B
V
4
V
5
V
DD
V
1
V2, V
17
3B
V
4
V
5
Display
turning-off
waveform
V
DD
V
1
V2, V
3B
V
4
V
5
Display
turning-on
waveform
50/60
1
Semiconductor
3) COM and SEG Waveforms on 1/17 Duty
PEDL9041-03
ML9041-xxA/xxB
COM1 (CSR = L, AS = L)
(CSR = L, AS = H)
COM
2
(CSR = H, AS = L)
COM
17
(CSR = H, AS = H)
COM
16
(first character line)
(CSR = L, AS = L)
COM
2
(CSR = L, AS = H)
COM
3
COM
(CSR = H, AS = L)
16
(CSR = H, AS = H)
COM
15
(second character line)
(CSR = L, AS = L)
COM
16
(CSR = L, AS = H)
COM
17
(CSR = H, AS = L)
COM
2
(CSR = H, AS = H)
COM
1
(cursor line)
COM
(CSR = L, AS = L)
17
(CSR = L, AS = H)
COM
1
(CSR = H, AS = L)
COM
1
COM
(CSR = H, AS = H)
17
(arbitrator line)
SEG
V
V
V
V3A (V3B)
V
V
V
V
V
V3A (V3B)
V
V
V
V
V
V3A (V3B)
V
V
V
V
V
V3A (V3B)
V
V
V
V
V
V3A (V3B)
V
V
16
DD
17 1 2 3 4 5 6 7 8 9 10 1112 13
1
2
4
5
DD
1
2
4
5
DD
1
2
4
5
DD
1
2
4
5
DD
1
2
4
5
1 frame
16 17 1 2
···
3
4
Display
turning-off
waveform
Display
turning-on
waveform
51/60
1
W
W
Semiconductor
Initial Setting of Instructions
PEDL9041-03
ML9041-xxA/xxB
(a) Data transfer from and to the CPU using 8 bits of DB
to DB
0
7
1) Turn on the power.
2) Wait for 15 ms or more after V
has reached 2.5 V or higher.
DD
3) Set “8 bits” with t he F unc tion Setting instruction.
4) Wait for 4.1 ms or more.
5) Set “8 bits” with t he F unc tion Setting instruction.
6) Wait for 100 µs or more.
7) Set “8 bits” with t he F unc tion Setting instruction.
8) Check the Busy Flag for No Busy (or wait for 100 µs or more).
9) Set “8 bits”, “Number of LCD lines” and “Font size” with the Function Setting instruction.
(After this, the number of LCD lines and the font size cannot be changed.)
10) Check the Busy Flag for No Busy.
11) Execute the Display Mode Setting Instruction, Display Clear Instruction, Entry Mode Setting
instruction and Arbitrator Display Line Setting Instruction.
12) Check the Busy Flag for No Busy.
13) Initialization is completed.
An example of instruction code for 3), 5) and 7)
RS
1
1
×
: Don’t Care
RS
R/
0
0
DB
0
DB
7
0
DB
6
0
DB
5
1
DB
4
1
DB
3
×
DB
2
×
DB
1
×
0
×
(b) Data transfer from and to the CPU using 8 bits of DB4 to DB
7
1) Turn on the power.
2) Wait for 15 ms or more after V
has reached 2.5 V or higher.
DD
3) Set “8 bits” with t he F unc tion Setting instruction.
4) Wait for 4.1 ms or more.
5) Set “8 bits” with t he F unc tion Setting instruction.
6) Wait for 100 µs or more.
7) Set “8 bits” with t he F unc tion Setting instruction.
8) Check the Busy Flag for No Busy (or wait for 100 µs or longer).
9) Set “4 bits” with t he F unc tion Setting instruction.
10) Wait for 100 µs or longer.
11) Set “4 bits”, “Number of LCD lines” and “Font size” with the Initial Setting instruction. (After this, the
number of LCD lines and the font size cannot be changed.)
12) Check the Busy Flag for No Busy.
13) Execute the Display Mode Setting Instruction, Display Clear Instruction, Entry Mode Setting
instruction and Arbitrator Display Line Setting Instruction.
14) Check the Busy Flag for No Busy.
15) Initialization is completed.
An example of instruction code for 3), 5) and 7)
RS
RS
1
1
R/
0
0
DB
0
DB
7
0
DB
6
0
DB
5
1
4
1
52/60
1
W
Semiconductor
An example of instruction code for 9)
PEDL9041-03
ML9041-xxA/xxB
RS
RS
1
1
R/
0
0
DB
0
DB
7
0
DB
6
0
DB
5
1
4
0
*: In 13), check the Busy Flag for No Busy before executing each instruction.
(c) Data transfer from and to the CPU using the serial I/F
1) Turn on the power.
2) Wait for 15 ms or more after V
has reached 2.5 V or higher.
DD
3) Set “Number of LCD lines” and “Font size” with the Function Setting Instruction.
4) Execute the Display Mode Setting Instruction, the Display Clear Instruction, the Entry Mode
Instruction and the Arbitrator Display Line Setting Instruction.
5) Check the busy flag for No Busy.
6) Initialization is completed .
*: In 3) and 4), check the Busy Flag for No Busy before executing each instruction.
53/60
1
Semiconductor
ML9041-xxA CVWA PAD CONFIGURATION
Pad Layout
Chip Size: 10.62 × 2.55 mm
Chip Thickness: 625±20 µm
Bump Size (1): 72 × 72 µm
(PAD No. 1-62, 183-189)
Bump Size (2): 54 × 96 µm
(PAD No. 63-182)
Y
PEDL9041-03
ML9041-xxA/xxB
182
183
189
1
63
62
56
55
Pad Coordinates
Pad Symbol X (µm) Y (µm) Pad Symbol X (µm) Y (µm)
1V1–5103 –1100 21 DB
2V2–4914 –1100 22 DB
3V3A–4725 –1100 23 DB
4V3B–4536 –1100 24 DB
3
2
1
0
5V4–4347 –1100 25 E –567 –1100
6V5–4158 –1100 26 R/
7V
5IN
–3969 –1100 27 RS
8VCC–3780 –1100 28 RS
W
0
1
9VC–3591 –1100 29 SO 189 –1100
10 V
lN
11 BEB –3213 –1100 31
12 V
DD
13 CSR –2835 –1100 33 OSC
14 SSR –2646 –1100 34 OSC
15
16 V
17 DB
18 DB
19 DB
20 DB
P
/S –2457 –1100 35 OSC
SS
7
6
5
4
–3402 –1100 30 Sl 378 –1100
SHT
–3024 –1100 32
–2268 –1100 36 T
–2079 –1100 37 T
–1890 –1100 38 T
–1701 –1100 39 COM
–1512 –1100 40 COM
CS
2
R
1
3
2
1
1
2
–1323 –1100
–1134 –1100
–945 –1100
–756 –1100
–378 –1100
–189 –1100
0 –1100
567 –1100
756 –1100
945 –1100
1134 –1100
1323 –1100
1512 –1100
1701 –1100
1890 –1100
2079 –1100
2268 –1100
X
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1
Semiconductor
ML9041-xxA/xxB
Pad Symbol X (µm) Y (µm) Pad Symbol X (µm) Y (µm)
41 COM
42 COM
43 COM
44 COM
45 COM
46 COM
47 COM
48 COM
49 COM
50 COM
51 COM
52 COM
53 COM
54 COM
55 COM
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
56 DUMMY 5184 –720 96 SEG
57 DUMMY 5184 –480 97 SEG
58 DUMMY 5184 –240 98 SEG
59 DUMMY 5184 0 99 SEG
60 DUMMY 5184 240 100 SEG
61 DUMMY 5184 480 101 SEG
62 DUMMY 5184 720 102 SEG
63 DUMMY 4998 1088 103 SEG
64 DUMMY 4914 1088 104 SEG
65 DUMMY 4830 1088 105 SEG
66 DUMMY 4746 1088 106 SEG
67 DUMMY 4662 1088 107 SEG
68 DUMMY 4578 1088 108 SEG
69 DUMMY 4494 1088 109 SEG
70 DUMMY 4410 1088 110 SEG
71 DUMMY 4326 1088 111 SEG
72 DUMMY 4242 1088 112 SEG
73 SEG
74 SEG
75 SEG
76 SEG
77 SEG
78 SEG
79 SEG
80 SEG
100
99
98
97
96
95
94
93
2457 –1100 81 SEG
2646 –1100 82 SEG
2835 –1100 83 SEG
3024 –1100 84 SEG
3213 –1100 85 SEG
3402 –1100 86 SEG
3591 –1100 87 SEG
3780 –1100 88 SEG
3969 –1100 89 SEG
4158 –1100 90 SEG
4347 –1100 91 SEG
4536 –1100 92 SEG
4725 –1100 93 SEG
4914 –1100 94 SEG
5103 –1100 95 SEG
4158 1088 113 SEG
4074 1088 114 SEG
3990 1088 115 SEG
3906 1088 116 SEG
3822 1088 117 SEG
3738 1088 118 SEG
3654 1088 119 SEG
3570 1088 120 SEG
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
3486 1088
3402 1088
3318 1088
3234 1088
3150 1088
3066 1088
2982 1088
2898 1088
2814 1088
2730 1088
2646 1088
2562 1088
2478 1088
2394 1088
2310 1088
2226 1088
2142 1088
2058 1088
1974 1088
1890 1088
1806 1088
1722 1088
1638 1088
1554 1088
1470 1088
1386 1088
1302 1088
1218 1088
1134 1088
1050 1088
966 1088
882 1088
798 1088
714 1088
630 1088
546 1088
462 1088
378 1088
294 1088
210 1088
PEDL9041-03
55/60
1
Semiconductor
ML9041-xxA/xxB
Pad Symbol X (µm) Y (µm) Pad Symbol X (µm) Y (µm)
121 SEG
122 SEG
123 SEG
124 SEG
125 SEG
126 SEG
127 SEG
128 SEG
129 SEG
130 SEG
131 SEG
132 SEG
133 SEG
134 SEG
135 SEG
136 SEG
137 SEG
138 SEG
139 SEG
140 SEG
141 SEG
142 SEG
143 SEG
144 SEG
145 SEG
146 SEG
147 SEG
148 SEG
149 SEG
150 SEG
151 SEG
152 SEG
153 SEG
154 SEG
155 SEG
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
126 1088 156 SEG
42 1088 157 SEG
–42 1088 158 SEG
–126 1088 159 SEG
–210 1088 160 SEG
–294 1088 161 SEG
–378 1088 162 SEG
–462 1088 163 SEG
–546 1088 164 SEG
–630 1088 165 SEG
–714 1088 166 SEG
–798 1088 167 SEG
–882 1088 168 SEG
–966 1088 169 SEG
–1050 1088 170 SEG
–1134 1088 171 SEG
–1218 1088 172 SEG
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
–2814 1088
–2898 1088
–2982 1088
–3066 1088
–3150 1088
–3234 1088
–3318 1088
–3402 1088
–3486 1088
–3570 1088
–3654 1088
–3738 1088
–3822 1088
–3906 1088
–3990 1088
–4074 1088
–4158 1088
–1302 1088 173 DUMMY –4242 1088
–1386 1088 174 DUMMY –4326 1088
–1470 1088 175 DUMMY –4410 1088
–1554 1088 176 DUMMY –4494 1088
–1638 1088 177 DUMMY –4578 1088
–1722 1088 178 DUMMY –4662 1088
–1806 1088 179 DUMMY –4746 1088
–1890 1088 180 DUMMY –4830 1088
–1974 1088 181 DUMMY –4914 1088
–2058 1088 182 DUMMY –4998 1088
–2142 1088 183 DUMMY –5184 720
–2226 1088 184 DUMMY –5184 480
–2310 1088 185 DUMMY –5184 240
–2394 1088 186 DUMMY –5184 0
–2478 1088 187 DUMMY –5184 –240
–2562 1088 188 DUMMY –5184 –480
–2646 1088 189 DUMMY –5184 –720
–2730 1088
PEDL9041-03
56/60
1
Semiconductor
ML9041-xxB CVWA PAD CONFIGURATION
Pad Layout
Chip Size: 10.62 × 2.55 mm
Chip Thickness: 625±20 µm
Bump Size (1): 72 × 72 µm
(PAD No. 1-55)
Bump Size (2): 54 × 96 µm
(PAD No. 56-175)
PEDL9041-03
ML9041-xxA/xxB
Y
175
56
X
1
55
Pad Coordinates
Note: T he ML9041-xxB does not have the dummy pads corresponding to the pad numbers 56 to 62 and 183 to
189 for the ML9041-xxA.
Pad Symbol X (µm) Y (µm) Pad Symbol X (µm) Y (µm)
1V1–5103 –1100 21 DB
2V2–4914 –1100 22 DB
3V3A–4725 –1100 23 DB
4V3B–4536 –1100 24 DB
3
2
1
0
5V4–4347 –1100 25 E –567 –1100
6V5–4158 –1100 26 R/
7V
5IN
–3969 –1100 27 RS
8VCC–3780 –1100 28 RS
W
0
1
9VC–3591 –1100 29 SO 189 –1100
10 V
lN
11 BEB –3213 –1100 31
12 V
DD
13 CSR –2835 –1100 33 OSC
14 SSR –2646 –1100 34 OSC
15
16 V
17 DB
18 DB
19 DB
20 DB
P
/S –2457 –1100 35 OSC
SS
7
6
5
4
–3402 –1100 30 Sl 378 –1100
SHT
–3024 –1100 32
–2268 –1100 36 T
–2079 –1100 37 T
–1890 –1100 38 T
–1701 –1100 39 COM
–1512 –1100 40 COM
CS
2
R
1
3
2
1
1
2
–1323 –1100
–1134 –1100
–945 –1100
–756 –1100
–378 –1100
–189 –1100
0 –1100
567 –1100
756 –1100
945 –1100
1134 –1100
1323 –1100
1512 –1100
1701 –1100
1890 –1100
2079 –1100
2268 –1100
57/60
1
Semiconductor
ML9041-xxA/xxB
Pad Symbol X (µm) Y (µm) Pad Symbol X (µm) Y (µm)
41 COM
42 COM
43 COM
44 COM
45 COM
46 COM
47 COM
48 COM
49 COM
50 COM
51 COM
52 COM
53 COM
54 COM
55 COM
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
56 DUMMY 4998 1088 96 SEG
57 DUMMY 4914 1088 97 SEG
58 DUMMY 4830 1088 98 SEG
59 DUMMY 4746 1088 99 SEG
60 DUMMY 4662 1088 100 SEG
61 DUMMY 4578 1088 101 SEG
62 DUMMY 4494 1088 102 SEG
63 DUMMY 4410 1088 103 SEG
64 DUMMY 4326 1088 104 SEG
65 DUMMY 4242 1088 105 SEG
66 SEG
67 SEG
68 SEG
69 SEG
70 SEG
71 SEG
72 SEG
73 SEG
74 SEG
75 SEG
76 SEG
77 SEG
78 SEG
79 SEG
80 SEG
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
2457 –1100 81 SEG
2646 –1100 82 SEG
2835 –1100 83 SEG
3024 –1100 84 SEG
3213 –1100 85 SEG
3402 –1100 86 SEG
3591 –1100 87 SEG
3780 –1100 88 SEG
3969 –1100 89 SEG
4158 –1100 90 SEG
4347 –1100 91 SEG
4536 –1100 92 SEG
4725 –1100 93 SEG
4914 –1100 94 SEG
5103 –1100 95 SEG
4158 1088 106 SEG
4074 1088 107 SEG
3990 1088 108 SEG
3906 1088 109 SEG
3822 1088 110 SEG
3738 1088 111 SEG
3654 1088 112 SEG
3570 1088 113 SEG
3486 1088 114 SEG
3402 1088 115 SEG
3318 1088 116 SEG
3234 1088 117 SEG
3150 1088 118 SEG
3066 1088 119 SEG
2982 1088 120 SEG
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
2898 1088
2814 1088
2730 1088
2646 1088
2562 1088
2478 1088
2394 1088
2310 1088
2226 1088
2142 1088
2058 1088
1974 1088
1890 1088
1806 1088
1722 1088
1638 1088
1554 1088
1470 1088
1386 1088
1302 1088
1218 1088
1134 1088
1050 1088
966 1088
882 1088
798 1088
714 1088
630 1088
546 1088
462 1088
378 1088
294 1088
210 1088
126 1088
42 1088
–42 1088
–126 1088
–210 1088
–294 1088
–378 1088
PEDL9041-03
58/60
1
Semiconductor
ML9041-xxA/xxB
Pad Symbol X (µm) Y (µm) Pad Symbol X (µm) Y (µm)
121 SEG
122 SEG
123 SEG
124 SEG
125 SEG
126 SEG
127 SEG
128 SEG
129 SEG
130 SEG
131 SEG
132 SEG
133 SEG
134 SEG
135 SEG
136 SEG
137 SEG
138 SEG
139 SEG
140 SEG
141 SEG
142 SEG
143 SEG
144 SEG
145 SEG
146 SEG
147 SEG
148 SEG
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
–462 1088 149 SEG
–546 1088 150 SEG
–630 1088 151 SEG
–714 1088 152 SEG
–798 1088 153 SEG
–882 1088 154 SEG
–966 1088 155 SEG
–1050 1088 156 SEG
–1134 1088 157 SEG
–1218 1088 158 SEG
–1302 1088 159 SEG
–1386 1088 160 SEG
–1470 1088 161 SEG
–1554 1088 162 SEG
–1638 1088 163 SEG
–1722 1088 164 SEG
–1806 1088 165 SEG
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
–2814 1088
–2898 1088
–2982 1088
–3066 1088
–3150 1088
–3234 1088
–3318 1088
–3402 1088
–3486 1088
–3570 1088
–3654 1088
–3738 1088
–3822 1088
–3906 1088
–3990 1088
–4074 1088
–4158 1088
–1890 1088 166 DUMMY –4242 1088
–1974 1088 167 DUMMY –4326 1088
–2058 1088 168 DUMMY –4410 1088
–2142 1088 169 DUMMY –4494 1088
–2226 1088 170 DUMMY –4578 1088
–2310 1088 171 DUMMY –4662 1088
–2394 1088 172 DUMMY –4746 1088
–2478 1088 173 DUMMY –4830 1088
–2562 1088 174 DUMMY –4914 1088
–2646 1088 175 DUMMY –4998 1088
–2730 1088
PEDL9041-03
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PEDL9041-03
1
Semiconductor
ML9041-xxA/xxB
NOTICE
1. The information contained herein can change w ithout notice owing to product and/or technical improvem ents.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action an d performan ce of the product. Wh en planning to use t he product, pleas e
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the s pecified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/ or the information and draw ings contained h erein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for u s e in any system or application that requ ires s pecial
or enhanced quality and reliability characteristics nor in any system or applicatio n where the failure of s uch
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traf fic and automotive equ ipment, safety devi ces, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2001 Oki Electric Industry Co., Ltd.
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