OKI ML9041 User Manual

PEDL9041-03

1

Semiconductor

ML9041-xxA/xxB

DOT MATRIX LCD CONTROLLER DRIVER

Preliminary

This version: Mar. 2001 Previous version: D ec. 1999

GENERAL DESCRIPTION

The ML9041 used in combination with an 8-bit or 4-bit microcontroller controls the operation of a character type dot matrix LCD.

FEATURES

•

Easy interfacing with 8-bit or 4-bit microcontroller

•

Switchable between serial and parallel interfaces

•

Dot-matrix LCD controller/driver for a small (5 × 7 dots) or large (5 × 10 dots) font

•

Built-in circuit allowing automatic resetting at power-on

•

Built-in 17 common signal drivers and 100 segment signal drivers

•

Built-in character generation ROM capable of generating 160 small characters (5 × 7 dots) or 32 large characters (5 × 10 dots)

•

Creation of character patterns by programming: up to 8 small character patterns (5 × 8 dots) or up to 4 large character patterns (5 × 11 dots)

•

Built-in RC oscillation circuit using external or internal resistors

•

Program-selectable duties: 1/9 duty (1 line: 5 × 7 dots + cursor + arbitrator), 1/12 duty (1 line: 5 × 10 dots + cursor + arbitrator), or 1/17 duty (2 lines: 5 × 7 dots + cursor + arbitrator)

•

Built-in bias dividing resistors to drive the LCD

•

Bi-directional transfer of segment outputs

•

Bi-directional transfer of common outputs

•

Equipped with a 100-dot arbitrator

•

Display shifting on each line

•

Built-in contrast contr ol circuit

•

Built-in voltage multiplier circuit

•

Chip (Gold Bump) Product name: ML9041-xxA/xxB CVWA

xxA: With dummy bumps on both sides of the chip xxB: Without dummy bumps on both sides of the chip

*xx indicates a code number. *01A and 01B are general code numbers.

1/60

1

W S

T

A

Semiconductor

BLOCK DIAGRAM

1

COM

Common

signal

PEDL9041-03

ML9041-xxA/xxB

17

1

SEG

100

SEG

COM

Segment Signal - driver

driver

100-bit latch

shift

17-bit

register

100-bit shift register

Parallel-

serial

converter

5

blink

Cursor

controller

generator

Character

(ID)

decoder

Instruction

8

7

(IR)

register

Instruction

8

Timing

generator

5

RAM

8

(CG RAM)

ROM

generator

Character

(CG ROM)

RAM

8

Display data

8

(ADC)

counter

Address

5

RAM

Arbitrator

(DD RAM)

decoder

instruction

Expansion

(AB RAM)

(ED)

8

circuit

Voltage

Data

(DR)

register

(BF)

Busy flag

instruction

Expansion

register (ER)

8

I/O

buffer

4

Test

circuit

LCD bias

voltage

4

multiplier

5

circuit

dividing

SSR

CSR

BEBV

IN

V V

CC

C

2

1

DD

V

GND

R

OSC

0

RS1RS

R/

3

7

1

E

C

/S

P

SH

SI

SO

to DB

0

DB

to DB

4

DB

T

T2T

3V1V2

3

5

5IN

V4V

V3BV

V

2/60

1

A

T

A

Semiconductor

I/O CIRCUITS

V

DD

P

PEDL9041-03

ML9041-xxA/xxB

V

DD

P

V

DD

V

DD

P

N

Applied to pins SSR, CSR,

P

/S, and BEB

pplied to pin E

pplied to pin

SH

V

DD

P

t serial I/F t parallel I/F

V

DD

P

N

pplied to pins T1, T2, and T

: 0 : 1

: 1 (CS = 1) : 0 (CS = 0) : 1

V

DD

P

3

pplied to pin SI

pplied to pin

N

pplied to pins R/W, RS1, and RS

t serial I/F

: 1 (CS = 0) : 0 (CS = 1)

t parallel I/F

t serial I/F t parallel I/F

: 0

: 0 : 1

CS

0

N

Output Enable signal

pplied to pins DB0 to DB

V

DD

7

PP

N

Output Enable signal

pplied to pin SO

3/60

1

Semiconductor

PIN DESCRIPTIONS

Symbol Description

W

R/

PEDL9041-03

ML9041-xxA/xxB

The input pin with a pu ll-up resi stor to s elect Read (“H”) or Write (“L”) in the Parallel I/F Mode.

This pin should be open in the Serial l/F Mode. The input pins with a pull-up resistor to select a register in the Parallel l/F Mode.

RS0, RS

1

E

DB0 to DB

DB4 to DB

OSC

1

OSC

2

OSC

R

COM1 to COM

SEG1 to SEG

RS

1

RS

0

Name of register H H Data register H L Instruction register

L L Expansion Instruction register

This pin should be open in the Serial I/F Mode. The input pin for data input/output between the CPU and the ML9041 and for

activating instructions in the Parallel l/F Mode. This pin should be open in the Serial l/F Mode. The input/output pins to transfer data of lower-order 4 bits between the CPU and the

ML9041 in the Parallel l/F Mode. The pins are not used for the 4-bit interface and

3

serial interface. Each pin is equipped with a pull-up r esistor, so thi s pin should be open when no t used. The input/output pins to transfer data of upper 4 bits between the CPU and the

ML9041 in the Parallel l/F Mode. The pins are not used for the serial interface.

7

Each pin is equipped w ith a pull-u p resistor, so thi s pin shoul d be open in the Ser ial I/F Mode when not used.

The clock oscillation pins required for LCD drive signals and the operation of the ML9041 by instructions sent from the CPU.

To input external clock, the OSC

pin should be used. The OSCR and the OSC2 pins

1

should be open. To start oscillation w ith an ex ternal resistor, t he resistor should be connected between

the OSC To start oscillation with an internal resistor, the OSC

short-circuited outside the ML9041. The OSC

and OSC2 pins. The OSCR pin should be open.

1

and OSCR pins should be

2

pin should be open.

1

The LCD common signal output pins.

to COM17. For

10

to COM17.

13

100

17

For 1/9 duty, non-selectable voltage waveforms are output via COM 1/12 duty, non-selectable voltage waveforms are output via COM

The LCD segment signal output pins.

4/60

1

Semiconductor

Symbol Description

CSR

SSR

V1 , V2, V3A, V3B, V

BEB

V

V5, V

V

PEDL9041-03

ML9041-xxA/xxB

The input pin to select the transfer direction of the common signal output data. At 1/n duty, data is transferred from CO M1 to COM n when “L” is applied to this pin and

transferred from COMn to COM1 when “H” is applied to this pin. The input pin to select the transfer direction of the segment signal output data. “L”: Data transfer from SEG “H”: Data transfer from SEG The pins to output bias voltages to the LCD. For 1/4 bias : The V2 and V3B pins are shorted.

4

For 1/5 bias : The V

3A

The input pin to enable or disable the voltage multiplier circuit. "L" disables the voltage multiplier circuit. "H" enables the voltage multiplier circuit. The voltage multiplier circuit doubles the input voltage V

referenced to V

is output to the V

DD

only when generating a level lower than GND.

IN

The pin to input voltage to the voltage multiplier. The pins to supply the LCD drive voltage. The LCD drive voltage is supp lied to the V5 pin when the voltage multiplier is not used

(BEB = 0) and the internal contrast adjusting circuit is also not used. At this time, the V

pin should be open.

5IN

The LCD drive voltage is supplie d to the V

5IN

(BEB = 0) but the internal contrast adjusting circuit is used. At this time, the V should be open.

When the voltage multiplier is used (BEB = 1), the V multiplied voltage is output to the V circuit must be used. Capacitors for the voltage multiplier should be connected between the V

C

CC

The pin to connect the positive pin of the capacitor for the voltage multiplier. The pin to connect the negative pin of the capacitor used for the voltage multiplier.

pin and the V

DD

to SEG

1

100

to SEG

100

1

and V3B pins are shorted.

pin. The voltage multiplier circuit can be used

5IN

pin when the voltage multip lier is not used

5IN

pin). In this case, the internal contrast adjusting

5IN

pin.

5IN

and the multiplied voltage

MUL

pin should be open (the

5

5/60

1

Semiconductor

Symbol Description

T1, T2, T

3

V

DD

GND The ground level input pin.

P

/S

CS

SHT

Sl

SO

The input pins for test circuits (normally open). Each of these pins is equipped with a pull-down resistor, so this pin should be left open.

The power supply pin.

The input pin to select the parallel or serial interface. “L” selects the parallel interface. “H” selects the serial interface. The pin to enable this IC in the serial l/F mode. “L” enables this IC. “H” disables this IC. This pin should be open in the parallel l/F mode. The pin to input shift clock in the serial l/F mode. Data inputting to the SI pin is carried out synchronizing with the rising edge of this

clock signal. Data outputting from the SO pin is carried out synchronizing with the falling edge of

this clock signal. This pin should be open in the parallel l/F mode. The pin to input DATA in the serial l/F mode. Data inputting to this pin is carried out synchronizing with the rising edge of the

signal. This pin should be open in the parallel l/F mode. The pin to output DATA in the serial l/F mode. Data inputting to this pin is carried out synchronizing with the falling edge of the

signal. This pin should be open in the parallel l/F mode.

PEDL9041-03

ML9041-xxA/xxB

SHT

6/60

1

Semiconductor

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Condition Rating Unit Applicable pins

Supply Voltage V LCD Driving Voltage

V1, V2, V3,

V

4

Input Voltage V

Storage Temperature T

DD

, V

I

STG

Ta = 25°C –0.3 to +6.5 V VDD–GND Ta = 25°C VDD–7.5 to VDD+0.3 V V1, V4, V5, V

5

Ta = 25°C –0.3 to VDD+0.3 V

— –55 to +150 °C —

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Condition Range Unit Applicable pins

Supply Voltage V LCD Driving Voltage

V

(See Note) Voltage Multipler Operating Voltage Operating Temperature T

DD

DD–V5

V

MUL

op

— 2.5 to 5.5 V VDD–GND — 2.8 to 7.0 V

BEB = 1

— –40 to +85 °C —

V

DD

V

–1.40 to

–3.5

DD

PEDL9041-03

ML9041-xxA/xxB

(GND = 0 V)

, V2, V3A, V

5IN

R/W, E, SSR, Sl, RS0, RS1, BEB, CS, T

VV

SHT

, CSR, P/S,

to T3, DB0 to DB7, V

1

(GND = 0 V)

V

DD–V5

(V

)

5IN

DD–VIN

IN

3B

Note: This voltage should be applied across VDD and V5. The following voltages are output to the V1, V2,

V

(V3B) and V4 pins:

3A

•

1/4 bias

= {VDD – (VDD – V5)/4} ±0.15 V

V

1

V

= V3B = {VDD – (VDD – V5)/2} ±0.15 V

2

= {VDD – 3 × (VDD – V5)/4 } ±0.15 V

V

4

•

1/5 bias

V

= {VDD – (VDD – V5)/5} ±0.15 V

1

= {VDD – 2 × (VDD – V5)/5} ±0.15 V

V

2

V

= V3B = {VDD – 3 × (VDD – V5)/5} ±0.15 V

3A

V

= {VDD – 4 × (VDD – V5)/5} ±0.15 V

4

The voltages at the V V

> V1 > V2 > V3A (V3B) > V4 > V5.

DD

(Higher

←

, V2, V3A (V3B), V4 and V5 pins should satisfy

1

→ Lower)

* Do not apply short-circuiting across output pins and across an output pin and an input/output

pin or the power supply pin in the output mode.

7/60

1

Semiconductor

ML9041-xxA/xxB

ELECTRICAL CHARACTERISTICS

DC Characteristics

(GND = 0 V, V

Parameter Symbol Condition Min. Typ. Max. Unit Applicable pin

“H” Input Voltage 1 V

“L” Input Voltage 1 V

“H” Input Voltage 2 V “L” Input Voltage 2 V “H” Output Voltage 1 V “L” Output Voltage 1 V “H” Output Voltage 2 V “L” Output Voltage 2 V

COM Voltage Drop

SEG Voltage Drop

V V

IH1

IL1

IH2 IL2

OH1IOH

OL1IOL

OH2IOH

OL2IOL

V

CHlOCH CMHlOCMH CMLlOCML

V

CLlOCL

V

SHlOSH SMHlOSMH SMLlOSML

V

SLlOSL

—

= –0.1 mA 0.75V

= +0.1 mA — — 0.2V

= –13 µA0.9V

= +13 µA——0.1V

= –4 µAV

= ±4 µAV

V

–V5 = 5 V

DD

Note 1 = +4 µA = –4 µAV

= ±4 µAV

V

–V5 = 5 V

DD

Note 1

= +4 µA

0.8V

DD

–0.3 — 0.2V

0.8V

DD

–0.3 — 0.2V

DD

–0.3 V

DD

–0.3 V1+0.3

1

–0.3 V4+0.3

4

V

5

–0.3 V

DD

–0.3 V2+0.3

2

–0.3 V3+0.3

3

V

5

Input Leakage Current | IIL | VDD = 5 V, VIN = 5 V or 0 V — — 1.0

VDD = 5 V, VIN = GND 10 25 61

= 5 V, VIN = VDD,

V

Input Current 1 | II1 |

DD

Excluding current flowing through the pull-up resistor

——2.0

and the output driving MOS

Input Current 2 | II2 |

VDD = 5 V, VIN = V

DD

VDD = 5 V, VIN = VDD, Excluding current flowing

15 45 105

——2.0

through the pull-down resistor

Supply Current l LCD Bias Resistor R Oscillation Frequency

of External Resistor Rf Oscillation Frequency

of Internal Resistor Rf

Clock Input Frequency

Input Clock Duty f Input Clock Rise

Time

External Clock

Input Clock Fall Time f

VDD = 5 V Note 2 — — 1.2 mA VDD–GND

DD

LB

Rf = 180 kΩ±2% Note 3 175 270 400 kHz OSC1, OSC

f

osc1

OSC1: Open Note 4

f

osc2

OSC

and OSCR: Short-

2

140 270 480 kHz

circuited OSC2, OSCR: Open

f

in

Input from OSC

duty

f

rf

ff

1

Note 5 45 50 55 %

Note 6 — — 0.2

125 480 kHz

= 2.5 to 5.5 V, Ta = –40 to +85°C)

DD

—V

DD

V

DD

—V

——

DD

V

DD

VDB0 to DB7, SO

DD

VOSC

DD

V

V5+0.3

DD

V

V5+0.3

µ

A

µ

A

µ

AT

4.0 k

Ω

µ

s

µ

s

PEDL9041-03

R/W, RS E, DB

SHT, P

, RS1,

0

to DB7,

0

/S, Sl,

CS

, SSR,

OSC

1

CSR, BEB

2

to

COM

1

COM

17

to

SEG

1

SEG

100

E, SSR, CSR,

SHT, P

BEB,

/S,

CS, Sl

R/W, RS DB

1

V

DD

V

3A

OSC OSC

OSC

, RS1,

0

to DB7, SO

0

, T2, T

3

, V1, V2,

, V3B, V4, V

, OSC2,

1 R

1

5

2

8/60

1

Semiconductor

PEDL9041-03

ML9041-xxA/xxB

(GND = 0 V, V

Parameter Symbol Condition Min. Typ. Max. Unit

= 5 V, 1/5 bias

Maximum and minimum LCD drive voltages when internal variable resistors are used.

Bias Voltage for Driving LCD by External Input

V

MAX

V MIN

V V

V

LCD

DD

V

5IN

Contrast data: 1F VDD = 5 V, 1/5 bias

LCD

V

5IN

Contrast data: 00

LCD1

VDD–V

LCD2

= 0 V,

5

Note 7

4.6 — V V

1/5 bias 2.8 — 7.0 V V 1/4 bias 2.8 — 7.0

= 2.5 to 5.5 V, Ta = –40 to +85°C)

DD

Applicable

pins

DD–V5

—3.4 V

5

VDD = 3 V, VIN = 0 V f = 270 kHz

Voltage Multiplier Output Voltage

V

A capacitor for the voltage

5OUT

multiplier = 4.7 µF

–(VDD–VIN)

V

DD

×

2–0.1

—

VDD–(VDD–

V

) × 2+1.2 V

IN

VV

5

, V

5IN

No load BEB = H

Voltage Multiplier Input Voltage

V

IN

VDD–3.5 V VDD/2 V V

IN

Note 1: Applied to the voltage drop occurring between any of the VDD, V1, V4 and V5 pins and any of the

common pins (COM

to COM17) when the current of 4 µA flows in or flows out at one common

1

pin. Also applied to the voltage drop occurring between any of the V any of the segment pins (SEG

to SEG

1

) when the current of 4 µA flows in or flows out at one

100

, V2, V3A (V3B) and V5 pins and

DD

common pin. The current of 4 µA flows out when the output level is V

.

V

5

Note 2: Applied to the current flowing into the V

fed to the internal R

= 5 V

V

DD

GND = V V

, V2, V3A (V3B) and V4: Open

1

= 0 V,

5

oscillation or OSC1 under the following conditions:

f

E, SSR, CSR, and BEB: “L” (fixed) Other input pins: “L” or “H” (fixed) Other output pins: No load

or flows in when the output level is

DD

pin when the external clock (f

DD

= fin = 270 kHz) is

OSC2

9/60

1

A

Semiconductor

Note 3: Note 4:

OSC

OSC OSC

OSC

1

= 180 kΩ±2%

R

2

f

OSC

PEDL9041-03

ML9041-xxA/xxB

1

R

2

The wire between OSC1 and Rf and the wire between

and Rf should be as short as possible.

OSC

2

Keep OSC

open.

R

Note 5:

t

V

DD

2

f

IN

waveform

pplied to the pulses entering from the OSC1 pin

= tHW/(tHW + tLW) ×100 (%)

f

duty

Note 6:

0.7V

DD

0.3V

DD

The wire between OSC2 and OSCR should be as short as possible. Keep OSC

HW

V

DD

2

0.7V

DD

0.3V

t

LW

V

DD

open.

1

DD

2

t

rf

t

ff

pplied to the pulses entering from the OSC1 pin

Note 7: For 1/4 bias, V2 and V3B pins are short-circuited. V3A pin is open.

For 1/5 bias, V

and V3B pins are short-circuited. V2 pin is open.

3A

10/60

PEDL9041-03

W

1

Semiconductor

ML9041-xxA/xxB

Switching Characteristics (The following ratings are subject to change after ES evaluation.)

•

Parallel Interface Mode

The timing for the input from the CPU (see 1) and the timing for the output to the CPU (see 2) are as shown below:

1) WRITE MODE (Timing for input from the CPU)

(VDD = 2.5 to 5.5 V, Ta = –40 to +85°C)

Parameter Symbol Min. Typ. Max. Unit R/W, RS0, RS1 Setup Time t E Pulse Width t R/W, RS0, RS1 Hold Time t E Rise Time t E Fall Time t E Pulse Width t E Cycle Time t DB0 to DB7 Input Data Hold Time t DB0 to DB7 Input Data Setup Time t

B

W

A

r

f

L

C

I

H

40 — — ns

450 — — ns

10 — — ns — — 25 ns — — 25 ns

430 — — ns

1000 — — ns

195 — — ns

10 — — ns

RS1, RS

DB

to DB

0

R/

V

0

E

7

V

IH

V

IL

V

IL

t

B

t

L

IL

V

IL

r

V

IH

t

C

t

W

t

I

V V

Input

IH

Data

IL

V

IH

V

IL

V

IL

t

f

V

IH

t

A

V

IL

t

H

V

IH

V

IL

11/60

1

W

Semiconductor

2) READ MODE (Timing for output to the CPU)

Parameter Symbol Min. Typ. Max. Unit R/W, RS1, RS0 Setup Time t E Pulse Width t R/W, RS1, RS0 Hold Time t E Rise Time t E Fall Time t E Pulse Width t E Cycle Time t DB0 to DB7 Output Data Delay Time t DB0 to DB7 Output Data Hold Time t

PEDL9041-03

ML9041-xxA/xxB

(VDD = 2.5 to 5.5 V, Ta = –40 to +85°C)

B

W

A

r

f

L

C

D

O

40 — — ns

450 — — ns

10 — — ns — — 25 ns — — 25 ns

430 — — ns

1000 — — ns

— — 350 ns 20 — — ns

RS1, RS

to DB

DB

0

R/

V

0

E

7

V

IH

V

IL

V

IH

t

B

t

L

IL

V

IL

r

V

IH

t

D

t

C

t

W

V

OH

Output Data

V

OL

V

IH

V

IL

V

IH

t

f

V

IH

t

A

V

IL

t

O

V

OH

V

OL

12/60

1

CS

SHT

Semiconductor

•

Serial Interface Mode

Parameter Symbol Min. Typ. Max. Unit

SHT

Cycle Time t

CS

Setup Time t

CS

Hold Time t

SHT

Setup Time t

SHT

Hold Time t

SHT

“H” Pulse Width t

SHT

“L” Pulse Width t

SHT

Rise Time t

SHT

Fall Time t Sl Setup Time t Sl Hold Time t Data Output Delay Time t Data Output Hold Time t

SCY

CSU

CH

SSU

SH

SWH

SWL

SR

SF

DISU

DIH

DOD

CDH

PEDL9041-03

ML9041-xxA/xxB

(VDD = 2.5 to 5.5 V, Ta = –40 to +85°C)

500 — — ns 100 — — ns 100 — — ns

60 — — ns 200 — — ns 200 — — ns 200 — — ns

——50ns

——50ns 100 — — ns 100 — — ns

— — 160 ns

0——ns

SI

SO

t

CSU

t

SCY

V

IL

t

SSU

t

SWL

V

IH

V

IH

V

t

DOD

V

SR

V

IL

t

DISU

t

SWH

V

IH

t

DIH

V

IL

OL

V

t

SF

V

IH IL

V

IH

t

DOD

IL

V

OH

t

SH

V

IH

t

CDH

CH

V

OH

13/60

1

Semiconductor

FUNCTIONAL DESCRIPTION

Instruction Register (IR), Data Register (DR), and Expansion Instruction Register (ER)

PEDL9041-03

ML9041-xxA/xxB

These registers are selected by setting the level of the Register Selection input pins RS selected when both RS when both RS

and RS1 are “L”. (When RS0 is “H” and RS1 is “L”, the ML9041 is not selected.)

0

and RS1 are “H”. The IR is selected when RS0 is “L” and RS1 is “H”. The ER is selected

0

and RS1. The DR is

0

The IR stores an instruction code and sets the address code of the display data RAM (DDRAM) or the character generator RAM (CGRAM). The microcontroller (CPU) can write to the IR but cannot read from the IR. The ER stores a contrast adjusting code and sets the address code of the arbitrator RAM (ABRAM). The CPU can write to or read from the ER. The DR stores data to be written in the DDRAM, ABRAM and CGRAM and also stores data read from the DDRAM, AM RAM and CG RA M . The data written in the DR by the CPU is automatically written in the DDRAM, ABRAM or CGRAM. When an address code is written in the IR or ER, the data of the specified address is automatically transferred from the DDRAM, ABRAM or CGRAM to the DR. The data of the DDRAM, ABRAM and CGRAM can be checked by allowing the CPU to read the data stored in the DR. After the CPU writes data in the DR, the data of the next addres s in the DDRAM, ABRAM or CGRAM is selected to be ready for the next writing by the CPU. Similarly, after the CPU reads the data in the DR, the data of the next address in the DDRAM, ABRAM or CGRAM is set in the DR to be ready for the next reading by the CPU.

Writing in or reading from these 3 registers is controlled by changing the status of the R/W (Read/Write) pin.

Table 1 R/W pin status and register operation

W

R/

L L H Writing in the IR

H L H Reading the Busy flag (BF) and the ad dress counter (ADC )

L H H Writing in the DR

H H H Reading from the DR

L L L Writing in the ER

H L L Reading the contrast code

RS

0

1

Operation

Busy Flag (BF)

The status “1” of the Busy Flag (BF) indicates that the ML9041 is carrying out internal operation. When the BF is “1”, any new instruction is ignored.

When R/W = “H”, RS

= “L” and RS1 = “H”, the data in the BF is output to the DB7.

0

New instructions should be input when the BF is “0”. When the BF is “1”, the output code of the address counter (ADC) is undefined.

14/60

PEDL9041-03

1

Semiconductor

ML9041-xxA/xxB

Address Counter (ADC)

The address counter provides a read/write address for the DDRAM, ABRAM or CGRAM and also provides a cursor display address. When an instruction code specifying DDR AM, ABRAM or CGRAM addr ess setting is inpu t to the pre-defined register, the register selects the specified DDRAM, ABRAM or CGRAM and transfers the address code to the ADC. The address data in the ADC is automatically incremented (or decremented) by 1 after the display data is written in or read from the DDRAM, ABRAM or CGRAM.

The data in the ADC is output to DB

to DB6 when R/W = “H”, RS0 = “L”, RS1 = “H” and BF = “0”.

0

Timing Generator

The timing generator generates timing sign als for th e internal operation of the ML 9041 activ ated by the instruction sent from the CPU or for the operation of the internal circuits of the ML9041 such as DDRAM, ABRAM, CGRAM and CGROM. Timing signals are generated so that the internal operation carried out for L CD displaying will not be interfered by the internal operation initiated by accessing from the CPU. For example, when the CPU writes data in the DDRAM, the display of the LCD not corresponding to the written data is not affected.

15/60

PEDL9041-03

A

1

Semiconductor

ML9041-xxA/xxB

Display Data RAM (DDRAM)

This RAM stores the display data represented in 8-bit character coding (see Table 2). The DDRAM addresses correspond to the display positions (digits) of the LCD as shown below. The DDRAM addresses (to be set in the ADC) are represented in hexadecimal.

DB

6DB5DB4DB3DB2DB1DB0

DC

(Example) Representation of DDRAM address = 12

MSB

Hexadecimal Hexadecimal

LSB

DC 0 1 0 0 1 0

0

1

2

1) Relationship between DDRAM addresses and display positions (1-line display mode)

Digit

2 3 4 5 19 20

1

00 01 02 03 04 12 13

Left end

Right

end

Display position DD RAM address (hexadecimal)

In the 1-line display mode, the ML9041 can display up to 20 characters from digit 1 to digit 20. While the DDRAM has addresses “00” to “4F” for up to 80 character codes, the area not used for display can be used as a RAM area for general data. When the display is shifted by instruction, the relationship between the LCD display and the DDRAM address changes as shown below:

Digit

1

234 1920

(Display shifted to the right)

(Display shifted to the left)

4F 00 01 02 11 12

Digit

2340551920

1

01

02 03 04 13 14

16/60

PEDL9041-03

1

Semiconductor

ML9041-xxA/xxB

2) Relationship between DDRAM addresses and display positions (2-line display mode) In the 2-line mode, the ML9041 can display up to 40 characters (20 characters per line) from digit 1 to digit 20.

Digit

1

Line 1 Line 2

2345

00 01 02 03 04 40 41 42 43 44 52 53

19 20 12 13

Display position DD RAM address (hexadecimal)

Note: T he DDRAM addr ess at digi t 20 in the first line is n ot consecutive to the DD RAM addres s at

digit 1 in the second line.

When the display is shifted by instruction, the relationship between the LCD display and the DDRAM address changes as shown below:

Digit

(Display shifted to the right)

234

1

Line 1

27 00 01 02

Line 2

67 40 41 42 51 52

5

03 43

19 20 11 12

(Display shifted to the left)

Line 1 Line 2

Digit

1

234

01 02 03 04 41 42 43 44

5

05 45 53 54

19 20 13 14

17/60

PEDL9041-03

1

Semiconductor

ML9041-xxA/xxB

Character Generator ROM (CGROM)

The CGROM generates small character patterns (5 × 7 dots, 160 patterns) or large character patterns (5 × 10 dots, 32 patterns) from the 8-bit character code signals in the DDRAM. When the 8-bit character code corresponding to a character pattern in the CGROM is written in the DDRAM, the character pattern is displayed in the display position specified b y the DDRAM address. Character codes 20 to 7F and A0 to FF are contained in the character code area in the CG ROM. Character codes 20 to 7F and A0 to DF are contained in the character code area f or the 5 × 7-dot character patterns. Character codes E0 to FF are contained in the ROM area for 5 × 10-dot character patterns. The general character generator ROM codes are 01A/01B. The relationship between character codes and general purpose character patterns are indicated in Table2.

18/60