OKI 4w Troubleshooting Manual

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OKIPAGE4w LED Page Printer
Troubleshooting Manual with Component Parts List
(ODA/OEL/INT)
1997.12.10 Rev. 2
All specifications are subject to change without notice.
1. OUTLINE..................................................................................................... 1
2. TOOLS........................................................................................................ 1
3. CIRCUIT DESCRIPTION............................................................................ 2
4. TROUBLESHOOTING.............................................................................. 21
5. CIRCUIT DIAGRAM.................................................................................. 27
6. COMPONENT PARTS LIST
1. OUTLINE
This manual has been written to provide guidance for troubleshooting of the OKIPAGE4w Printer (primarily for its printed circuit boards), on an assumption that the reader is knowledgeable of the printer. Read the maintenance manual for this printer P/N M-521426 if necessary.
Note:
1. High voltage power supply board and power supply unit containing a high voltage power supply is dangerous. From the viewpoint of the safety standards, the local repairing of a defective board is not allowed. Thus, the objects to be locally repaired as a result of troubleshooting are switches and fuses.
2. TOOLS
For troubleshooting the printer, the tools listed below may be needed in addition to general maintenance tools.
Oscilloscope Frequency response 100 MHz or higher Soldering iron A slender tip type, 15-20 watts Ectension code kit P/N : 40105501
Tool Remarks
- 1 -
3. CIRCUIT DESCRIPTION
3.1 Outline
The circuit of OKIPAGE4w consists of a main control board, a high voltage power supply board and a power supply unit. The block diagram is shown in Fig. 3-1. The main control board controls the reception and transmission of data with a host I/f and processes command analysis, bit image development, raster buffer read. It also controls the engine and high voltage outputs.
(1) Reception and transmission control
The main control board has one parallel I/F port which is compliant to the IEEE 1284 specification. An interface task stores all data received from the host into a receive buffer first, and returns the printer status upon request of the host.
(2) Command analysis processing
The OKIPAGE4w printer has the following emulation mode.
Hiper-W: OKI original
An edit task fetches data from the receive buffer, analizes commands, and sets I/O registers.
(3) Raster data processing
The decompression circuit in the CPU expands the compressed data and stores the data into the raster buffer.
(4) Raster data transfer
The LED head control circuit in the CPU sends the data stored in the raster buffer to the LED head.
(5) High voltage control
The high voltage control circuit in the CPU.
The high voltage power supply board generates high voltage outputs, and have sensors, LED for display. The power supply unit generates +24VDC output, +5DC output.
- 2 -
CN
I/F
Parallel
LS07
Main motor
M
Electromagnetic
Driver
Driver
clutch
Manual feed sensor
Paper sensor
Outlet sensor
Toner sensor
Cover open switch
LED
Thermistor
EP cartridge
power
HIgh voltage
Heater
(Halogen lamp)
AC
(120 V/230 V)
supply
<High-voltage Power Supply Board>
Switching
AC output ON/OFF
power supply
<Power Supply Unit>
I/F
Parallel
D0 ~ D7
EPROM
(64 KByte)
A8 ~ A15
A0 ~ A7
latch
Address
AD0 ~ AD7
LED head LED head
Main motor
Electromagnetic
clutch
LED
D0 ~ D3
Sensors
D-RAM
(128 KByte)
A0 ~ A10
TEMP
power
High-voltage
TR-ISEN
TR-VSEN
Driver
HEAT ON
High-voltage power I/F
LED
Driver
+5V
0VL
0VP
+24V
<Main Control Board>
HEAT ON
10MHz
CPU
(MSM65917)
EEPROM
I/F
Parallel
LED head
clutch
Main motor
Electromagnetic
Sensors
Figure 3-1 OKIPAGE4w Block Diagram
- 3 -
TEMP
TR-VSEN
TR-ISEN
Reset
circuit
5V
5V
0VL
3.2 CPU and Memory
(1) CPU (MSM65917)
CPU core nX-8 CPU clock 10 MHz Data bus width External 8 bits, Internal 8 bits
(2) Program ROM
ROM capacity 64k-bytes (512-kbit EPROM) ROM type 512 kbits (64k x 8 bits) Access time 150 nsec
When mask ROM in the CPU is valid, the EPROM is not mounted. (3) Resident RAM
RAM capacity 128k bytes (256k x 4 bits D-RAM one piece) RAM type 1M bits (256k x 4 bits) Access time 70 ns
The block diagram of CPU and memory circuit is shown in Fig. 3-2.
- 4 -
CPU IC 6
ALE
RDN
ROCS
DA10
DWR
CAS
AD00 to AD07
LS373
IC3
A08 to A15
DD00 to DD03
DA00 to DA09
A00 to A07
IC2 
EPROM
(64k x 8 bits)
IC11
DRAM
(256k x 4 bits)
RAS0 RAS1 RAS2
Main Control Board
Figure 3-2 Block Diagram of CPU & Memory in OKIPAGE4w
- 5 -
3.3 Reset Control
When power is turned on, RST-N signal is generated by IC5.
+5V+5V
+5V
Power ON
IC5
1
3
2
Power OFF
63
CPU
RSTN
RST-N
- 6 -
3.4 EEPROM Control
The BR93LC46A on the main control board is an electrical erasable/programmable ROM of 64­bit x 16-bit configuration. Data input to and output from the ROM are bidirectionally transferred in units of 16 bits through I/O port (EEPRMDT-P) in serial transmission synchronized with a clock signal from the CPU.
The EEPROM operates in the following instruction modes.
Instruction Start bit Operation Address Data
Read (READ) 1 10 A5 to A0 Write Enabled (WEN) 1 00 11XXXX Write (WRITE) 1 01 A5 to A0 D15 to D0
CPU
39
38
37
EEPRMDT-P
EEPRMCS-P
EEPRMCLK-P
code
3
DI DO
EEPROM
1
CS
IC4
4
SK
2
Write All Address (WRAL) 1 00 01XXXX D15 to D0 Write Disabled (WDS) 1 00 00XXXX Erase 1 11 A5 to A0 Chip Erasable (ERAL) 1 00 10XXXX
Write cycle timing (WRITE)
Min. 450 ns
CS
SK
DI
DO
1 2 4 9 10 25
10 1
HIGH-Z
A5 A4 A1 A0 D15
D14
D1 D0
Max. 10 ms
Read cycle timing (READ)
CS
SK
DI
12
110
4
A5 A4 A1 A0
910
25 26
STATUS
Max. 500 ns
BUSY READY
DO
HIGH-Z
D15 D14 D1 D00 D15 D14
- 7 -
3.5 Parallel Interface
Parallel data is received from a host system via parallel interface which is compliant to the IEEE1284 specification.
CPU
65 to 68, 71 to 74
64
78
77
79
80
81
82
83
84
PDATA1-P to PDATA8-P
PSTB-N
BUSY-P
ACK-N
PE-P
SEL-P
FAULT-N
IPRIME-N
SELIN-N
AUTOFD-N
IC7
2 to 9
CN4
DATA8-P
to
DATA1-P
STB-N
1
10
12
13
32
31
36
14
BUSY-P
ACK-N
PE-P
SEL-P
FAULT-N
IPRIME-N
SELIN-N
AUTOFEED-N
11
+5V
+5V
18
Compatible mode The CPU sets a BUSY-P signal to ON at the same time when it reads the parallel data (PDATA1­P to PDATA 8-P) from the parallel port at the fall of PSTB-N signal. Furthermore, it makes the store processing of received data into a receive buffer terminate within a certain fixed time and outputs an ACK-N signal, setting the BUSY-P signal to OFF.
PARALLEL DATA (DATA BITs 1 to 8)
0.5 µs min.
DATA STROBE
0.5 µs min.
0.5 µs max.
BUSY
0 min.
ACKNOWLEDGE
0.5 µs to 10 µs
0.5 µs min.
0.5 µs min.
0 min.
0 min.
0 min.
- 8 -
3.6 LED Lamp Control
There is an LED lamp on the high voltage power supply board which is connected to and controled by the CPU on the main control board.
The light from the LED lamp can be seen on the Lens Cover through the LED Lens.
CN1
main control board high voltage power supply board
CPU
LED-P
41
CN1
- 9 -
3.7 LED Head Control
When a paper form is made to arrive at the data write position on print start, the sending of data to the LED head starts as synchronized with the page synchronous signal/line synchronous signal (CPU internal signal).
Bit image data developed on the raster buffer in the CPU are DMA-transferred to the register of a video interface controller (CPU built-in) and then sent to the shift register of the LED head in a serial transmission synchronized with the VCLK-P signal by the VD0-P signal.
When 1-dot line data (2560 bits) is completely shifted, it is latched by means of the VLD-P signal, causing LEDs to be driven by the VSTB1-N through VSTB4-N signals in different timing for each signal.
Some of LED heads have 2496 dots rather than 2560 dots. The controls regarding the number of dots are adjusted to the LED head installed when the printer is shipped from the factory.
Main control board
CPU
CN6 CN1
LED Head
VCLK-P
VD0-P
VLD-P
VSTB 1-N VSTB 2-N VSTB 3-N VSTB 4-N
+5V
0V
90
89
91
92 93
94 95
Chip 40
64 bit shift REG
LATCH
Bit 2560
Chip 1
1 to 640 bits
641 to 1280 1281 to 1920 1921 to 2560
Bit 1
- 10 -
Page  synchronous  signal*
Line  synchronous  signal*
VDT-P
3.33 msec
VCLK-P
VDT-P
VCLK-P
VDT-P
VLD-P
VSTB1-N
VSTB2-N
VSTB3-N
VSTB4-N
* CPU internal signal
8 bits
8 bits
0.2 µs
2560 bits
- 11 -
3.8 Motor and clutch control
The electromagnetic clutch is driven by a control signal from the CPU and the drive circuit shown below. The main motor is driven by the control signals from the CPU and the driver IC.
CPU
DMP1 DMP2
DMP3
0V 0V
+5V
96 97 98
+5V
IC10
27 18
26
19
ENA A
To Out3, 4Logic
DECAY
PHASE A PHASE B
CN7
GATE CIRCUIT
M
Main Motor
+24V OPEN
37 1 1412 24
Out2 Out3
Out1
SW1 SW3
SW1 SW3
8
Out4Vmm A Vmm B
ALARM
120
140
ENA B
GATE CIRCUIT
Signal of 
DECACY
16
17
+5V
+5V +24V
RMON
99
(1) Main motor
+5V
0V
25
BRUNK
0V
0V
SW4SW2
Current
-
Q
R
+
S
Sensor
OSC
Vref A Vref B
Vs A Vs BRs A Rs BLG A PG LG B
23 22 28 15 10 21 20TAB5
CN8
Electromagnetic clutch
0VP
0V
SW4SW2
Current
Sensor
­RQ
+
S
DMON-P
DMPH1-P
DMPH2-P
Rotation
T0 T1 T2 T3
Forward rotation
Reverse rotationStop
Operation at normal speed: T0 to T3 = 1.515 ms
- 12 -
(2) Motor drive control
Time T0 to T3 determines the motor speed, while the phase different direction between phase signals DMPH1-P and DMPH2-P determines the rotation direction. DMON-P signal control a motor coil current. According to the polarity of the phase signal, the coil current flow as follows:
1) +24V SW1 motor coil SW4 resistor earth, or,
2) +24V SW3 motor coil SW2 resistor earth The drop voltage across the resistor is input to comparator, where it is compared with a
reference voltage. If an overcurrent flows, a limiter operates to maintain it within a certain fixed current.
(3) Electromagnetic clutch control
Mechanical operation mode is switched by the combination of the clutch status and the direction of motor rotation.
clutch status
off
off
 
on
on
rotation direction
Forward
Reverse
 
Forward
Reverse
operation mode
cleaning
Hopping from manual
feed slot
illegal operation
Hopping from tray
- 13 -
3.9 Fuser Temperature Control
The temperature change in a heat controller is converted into the electric potential TEMP corresponding to the change in the resistance value of a thermistor, and the resultant potential is fed back to the control circuit. The CPU performs ON/OFF control of the HEATON-P signal to keep the heat roller temperature constant in accordance with the state at which the thermistor voltage (TEMP) is read into directly by the AD converter of the CPU. THCHK-N signal is fixed to “0”. When the paper thickness is set on the menu of the host, the temperature is adjusted to the targeted thickness accordingly.
Main Control Board
CPU
TEMP
27
AI4
(A/D)
THCHK-N
34
85
HEATON-P
High voltage power  supply board
IC20
5
+
6
-
7
+5V +5V
IC20
3
+
2
-
1
+5V
Ther- mistor
HEATON-N
Heater
Thermostat
Heat Roller
+5V
ACIN
Power supply unit
- 14 -
Flowchart of Thermistor Circuit Check
START
HEATER OFF
Short check timer(t16)set
No
Time-out ?
Short error TEMP ?
Thermistor error check
timer (t2) set
Thermistor disconnection
check timer (t35) set
Heater On
Temperature > Tn
No
No
Yes
Yes
Yes
Tn...T0 =
T2 = T4 =
Thermistor short error
End
Light Medium Heavy
To constant
temperature control
Thermistor
error check timer (t2)
within time
Yes
Thermistor
disconnection check timer
(t35) within time
Yes
t2 = t16 = t35 =
90 sec
520 msec
10 sec
No
No
Time-out
A/D value changed?
Yes
- 15 -
No
Fuser error
End
Thermistor disconnection 
error
End
Temperature
Controlled
Temperature
T
HEATER ON
OFF
Time
Temperature table
THCHK-N
O Z
Heater control mode Normal operation Not used
T 135˚C: 140˚C: 150˚C: 155˚C: 155˚C:
Paper Thickness light medium light medium medium heavy heavy
- 16 -
3.10 Sensor Control
The CPU supervises the state of each sensor every 40 ms.
Main Control Board High Voltage Power Supply Board
CN1 CN1
+5V
CPU
Sensor  signal
47
44
46
48
OFF
+5V
+5V
+5V
+5V
TNRSNS-N
PSIN-N
PSOUT-N
WRSNS-N
TransparentShield
PS1
PS2
PS3
PS4
ON
- 17 -
3.11 Cover Open
When the cover is opened, a cover open microswitch is opened. This makes a CVOPN-N signal low, thereby the CPU detects that cover is open. Furthermore, opening the cover stops applying a +5V power to the high voltage power supply part, resulting in stopping all high voltage outputs.
CN1 CN1
Main Control Board
CVOPN-N
CPU
+5V
0V
45
Cover close Cover open
CVOPN-N
Cover  Open Microswitch
+5V
High Voltage Power Supply Board
High
Voltage
Power
Supply
+5V
Part
High 
voltage 
output
- 18 -
3.12 Power Supply Part
(1) Power supply unit
An AC power from an inlet is input to Switching Reg. part .AC power is converted to a +24 VDC output and +5 VDC output.
ACIN
F1 F2L
FG N
Filter
Circuit
Power supply unit
+24V +5V 0V
HEATER
Switching Reg. Part
CONTROLER
HEATON-N
to AC output
Fuse Ratings
AC Input
Fuse
F1 F2
230 V
250 V 6.3 A 250 V 2 A
120 V
125 V 10 A 250 V 2 A
(2) High voltage power supply board
The +5 VDC power supplied to the high voltage power supply part via the cover open microswitch as source voltage. The high voltage power supply part supplies necessary voltage for electro-photography print to output terminals CH, DB, SB, TR, and CB according to a control signal from the CPU. The table on the next page shows the relationship between control signals and high voltage outputs.
CN1
MainControl Board High Voltage Power Supply Board
TR1PWM-P
55
TR2PWM-P
59
CHPWM-P
56
SDB1-P
53
CPU
52 54  45
SDB2-P DBPWM-P
CVOPN-N
+5V
CN1
High Voltage
Power Supply
Part
CH DB SB TR CB
Cover Open Microswitch
- 19 -
Control Signals and High Voltage Outputs
Control signal name Level Function
TR1PWM-P 
TR2PWM-P  CHPWM-P
SDB1-P
SDB2-P
DBPWM-P
H/L (PWM) L H/L(PWM) L H/L(PWM) L H   L H   L H/L(PWM) L 
Makes the part put out a power to TR. 
+3 to 5 µA +0.5 to 4 KV
 Makes the part put out a -750V power to TR.  Makes the part put out a -1.35 KV power to CH.  Makes the part put out the following power:  
+450V or 0V power to SB  +300V power to DB
  Makes the part put out the following power:  
-450V power to SB
-300V power to DB +400V power to CB
 Makes the part put out the power to SB, DB, CB.
- 20 -
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