HIPPO COM
The material in this manual is for information only and is subject to change without
notice.
REVISION: 1.0
IBM, IBM PC/XT/AT, PC-DOS, MS-DOS, OS/2, INTEL, AMI ARE TH
ETRADEMARKS
OR REGISTERED TRADEMARKS OF THEIR RESPECTIV
E
OWNERS.
RADIO FREQUENCY INTERFERENCE STATEMENT
This equipment gene
rates and uses radio frequency energy and
if not installed a
nd used properly, that is, in strict accordance
with
the manufacturer's instructions, may cause interferenc
e
with radio and television reception.
If
this
equipment does cause interference to radio or T
V
recep
tion,
which can be determined by turning the equipmen
t
off
and
on, the user is encouraged to try to correct th
e
interference by one or more of the following measures:
*
Reorient the receiving antenna.
*
Relocate the computer away from the receiver.
*
Move the computer away from the receiver.
*
Plug the computer
into a different outlet so that computer
and receiver are on different branch circuits.
*
Ensure that c
ard slot covers are in place when no card is
installed.
*
Ens
ure
that card mounting screws, attachment connecto
r
screws, and ground wires are tightly secured.
*
If peripherals
are used with this system, it is suggested to
use
shielded, grounded cables, with in-line filters i
f
necessary.
If necessary, the user should consult the dealer servic
e
representative for additional suggestions.
The
ma
nufacturer is not responsible for any radio or T
Vinterference
caused by unauthorized modifications to thi
s
equipment. It is the responsibility of the user to correct such
interference.
Note
1.
Electronic
components are sensitive to dust and dirt
.
Do inspect and clean the computer system regularly.
2.
Turn off the powe
r whenever you install or remove any
connector,
memory module and add-on card. Befor
e
turnin
g
on the power, make sure that all th
e
co
nnectors,
memory modules and add-on cards ar
e
secured.
3.
After power is on, wa
it for a minute. The system BIOS
are
go
ing through a self-test during this period an
d
nothing is shown on
the screen. After the self-test, the
system
BIOS will initialize the display adaptor an
d
show messages.
4.
The SIMM sockets are fragil
e device. Do not force the
SIMM modules into the sockets. It may break th
e
locking latches.
Preface
The manual provide
s information about the installation
and
ma
intenance of HIPPO COM motherboard. In-dept
h
explanations of the functions of
this motherboard are provided.
In the appendix, the system BIOS setup is explained.
The content in
this manual is only for reference and is
intended to provide the basic informatio
n for the general users.
There are also technical informatio
n for hardware and software
engineers.
In this manual, there are 4 chapters. Chapter
1
contains a brief introduction and sp
ecification of HIPPO COM
motherboard. In the Ch
apter 2, the functions of HIPPO COM
are ex
plained. It also outlines many advanced features of the
CPU
a
nd the system architecture. Chapter 3 explains th
e
inst
allation
of coprocessor, DRAM modules and jumpers
.
Technical information is provided in the Chapter 4.
System BIOS is described in the attached BIO
S
Manualw
Table of Content
Chapter 1
INTRODUCTION
Chapter 2
GENERAL FEATURES
Specification
2-1
Chapter 3
CONFIGURING THE SYSTEM
Installing RAM Modules
3-1
Configuration of Memory
3-2
DRAM Configuration
3-3
Control of System Speed
3-4
System Board Jumper Setting
3-5
System Board Connectors
3-9
Chapter 4
TECHNICAL INFORMATION
Memory Mapping
4-1
I/O Address Map
4-2
System Timers
4-4
System Interrupts
4-6
Direct Memory Access (DMA)
4-7
Real Time Clock and CMOS RAM
4-8
CMOS RAM Address Map
4-9
Real Time Clock Information
4-10
System Expansion Bus
4-11
Appendix A
OPERATION AND MAINTENANCE
Static Electricity
A-1
Keeping The System Cool
A-1
Cleaning The `Golden Finger'
A-2
Cleaning The Motherboard
A-2
Appendix B
SUMMERY OF JUMPER SETTING
Appendix C
SYSTEM BOARD LAYOUT
__________________________________
1-1
Chapter 1
Introduction
_______________________________
HIPPO COM is designed
to be a powerful platform for
so
phisticated
software available now and in the future. I
t
contains
the most powerful microprocessor 80486 whic
h
combines CPU, numeric coprocesso
r and internal cache memory
on
a single chip. HIPPO COM fully takes advantage of th
e
power of
80486 and provides high performance, reliability and
compatibility to the user.
Fast A20 gate and fast reset genera
tion are incorporated
to
improve the performance of
advanced operation system and
expanded memory managers.
Comp
atibility and reliability are important issues. I/O
ch
annel
is compatible to standard AT bus and any periphera
l
may be used.
INTRODUCTION
__________________________________
__________________________________
1-2
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__________________________________
2-1
Chapter 2
General Features
_______________________________
SPECIFICATION
Processor :
Intel 80486D
X, 80486DX2, 80486SX or 80487SX CPU
Speed :
Turbo/normal speed
I/O Slot :
Compatible to standard AT bus
Seven 16-bit slots
Memory :
Shadow RAM for system and video BIOS
Page mode and hidden refresh
Flexible configuration
SIMM sockets for 256KB, 1MB or 4MB modules
Cache :
GENERAL FEATURES
__________________________________
__________________________________
2-2
8KB four way set associative internal cache
System Support Functions :
-
8-Channel DMA (Direct Memory Access)
-
16-level interrupt
-
3 programmable timers
-
CMOS RAM for system configuration
-
Real time clock with battery back-up
-
Fast A20 gate and fast reset
Other Features :
-
External battery connector
GENERAL FEATURES
__________________________________
__________________________________
2-3
PROCESSOR
The
power
of HIPPO COM comes from 80486. 80486
is the state-of-art microprocessor which m
erges many innovative
feature
s
on a single chip for advanced applications an
d
operation systems. Fabrica
ting with the 1um process, this CPU
cons
ists of more than one million transistors. With such high
density, this CPU incorporates as many
as new features to make
itself the most powerful microprocessor.
80486
is a 32-bit microprocessor with 32-bit externa
l
data bus and 32-bit external address bus. It not only contai
na
central processing unit, but also integrates a numeri
cprocessor
and a four-way set associate cache memory. It i
s
fully
binary compatible with 80386 and 80387. All existin
g
software for PC XT/AT can be used on HI
PPO COM. However,
due to the ne
w internal architecture, the performance of 80486
is two to four times of 80386.
Cache m
emory can improve the overall performance of
a computer system. Nevertheless, if the cache memory i
s
sep
arated
from CPU, CPU still needs to fetch code and dat
a
through external bus. Tha
t means the data transfer rate should
not be too fast so that the external devices ar
e able to keep pace
with
t
he CPU. In 80486, the cache controller and cach
e
memory
are integrated into the chip. Most of the operation
s
can be carried out inside the CPU, which reduces the bu
s
operations on external da
ta and address bus and thus speeds up
the internal execution.
GENERAL FEATURES
__________________________________
__________________________________
2-4
GENERAL FEATURES
__________________________________
__________________________________
2-5
The cache memory is a 8K bytes, 16 bytes line size
,
four-w
ay
set associative configuration. The hit rate of thi
s
config
uration
is much better than 32K bytes two-way se
t
associative
external cache because a four-way set associativ
e
arc
hitecture provides better performance in a multitasking and
multi-processor environment.
Bus snooping feature keeps the cache mem
ory consistent
with the main memory. Whe
n an external processor overwrites
the content in
the main memory, the corresponding data in the
internal
cache memory will
be invalidated and will be fetched
from main memory when CPU reads this data.
If
a r
ead miss occurs, the CPU will initiate a burs
t
mode
rea
d operation. In burst mode read operation, CP
U
performs
four successive read operations each of which take
s
only one c
ycle. Total 128 bits data are fetched into the CPU's
internal
cache. Since burst mode read operation is very fast
,
the traffic of the CPU bus is greatly reduced and the bus i
s
available to other bus masters, such as DMA controller.
Reading
128 bits data into CPU will
take some times.
In order to reduce the delay, the intern
al cache controller works
parallel
with CPU. It
fetches the data needed by CPU for the
present op
eration and the CPU read cycle is terminated. Then
the
other data are read into the internal cache memory whil
eCPU
is doing something else. This arrangement permits th
e
CPU to run at zero wait state.
GENERAL FEATURES
__________________________________
__________________________________
2-6
By
el
iminating the access to external bus, operation
s
with
the
internal cache can be completed in a single cycle
.
8038
6
at least needs two cycles for an operation. To furthe
rincrease
the rate of data transfer inside the CPU, the interna
l
bus of the cache memory is inc
reased to 128 bits, which is four
times of the externa
l bus. Since, in most of the time, the CPU
is using the internal cache, the large bus size substantiall
y
improves the overall performance.
When
the CPU writes data to the main memory, th
e
data is first stored in a write buffer. There are four writ
e
buffers. When the exte
rnal bus is idle, data will be sent to the
main
me
mory. If all buffers are filled, it can start writ
e
operation
in burst mode. Since the internal cache is update
d
immediately, the CP
U need not suspend its operation and there
is
no need
to wait for the external device to update the mai
n
memory.
Many
o
ften-used instructions are executed in a cloc
k
cycle
an
d some instructions are modified to take fewer cycle
s
than in 80386. On the contrary, 80386 may take two to three
more
cycles for the same instruction. The CPU contains a
n
advanc
ed
instruction pipeline structure and a 32-byte cod
e
queue to speed up the execution.
80486 includes all the functions
of 80386 and is able to
support sophistica
ted software and operation systems which are
wid
ely
employed now. It is able to operate in real mode
,
protected mode and virtual 8086 mode.
GENERAL FEATURES
__________________________________
__________________________________
2-7
Internal
memory management unit provides a flexibl
e
addressing
scheme for the next generation operation system
.
Multitasking, con
current operation and manipulating huge data
bas
e can be accomplished with excellent performance. Paging
mechanism
is employed to
allow powerful operating system to
implement
virtual memory. Each segment is divided int
o
severa
l
pages which are 4K bytes per page. Page mechanis
mis trans
parent to software and allows software to address 6
4
terabytes.
Furthermore, the
64KB segment boundary which is
an
barri
er of 8088 and 80286 is removed and the segmen
t
length can be increased up to 4GB.
The demand for sophisticated, number-crunchin
g
scient
ific
and business applications has rapidly increased i
nrecent
years. In the past, microprocessor features an intege
r
Arithmetic
Logic Unit which only handles simple intege
r
operat
ions such as addition and multiplication. Floating-point
operations
which are actually utilized by applications must b
e
accomplished through software routines.
To
me
et the demand of floating-point calculation,
a
num
eric
coprocessor is necessary. However, an externa
l
coprocessor has been found to be the bottleneck o
f data transfer.
80486
integrates the coprocessor on chip and thus the dat
a
transfer to external bus
is eliminated. The on-chip coprocessor
is compatible with 80387.
It works parallel with other units in
the CPU, which results in a better performance of numeri
c
process.
GENERAL FEATURES
__________________________________
__________________________________
2-8
MEMORY SYSTEM
Two
banks of DRAMs can
be installed on board. So 8
SIMM
mo
dules may be installed on your system and th
e
maximum memory size is up
to 32MB, 256KB, 1MB and 4MB
DRA
M
SIMM modules are supported. The DRAM should b
e
fast-page mode DRAM with staggered refresh capability.
The
memory system provides a flexible memor
yconfiguration.
Several combinations of DRAM types ar
e
allowe
d.
The DRAM type and the memory size ar
e
automatically detected by t
he system BIOS. So, you may easily
change the configuration of the system.
The memory controller system supports fast
page mode. The memory is div
ided into pages with equal size.
Successive
memory accesses within the same page need no
t
require
wait state. Furthermore, a burst line fill mode i
s
implemented. In case of a read miss of cach
e memory, 16 bytes
data
wil
l be fetched from main memory to cache memory
.
Using
page mode operation will speed up the line fil
l
ope
ration.To
enhance the system performance, shadow RA
M
mode
is
supported. In shadow RAM mode, system BIOS an
d
video BIOS contained in low speed memory such as EPRO
M
and
ROM are
copied into DRAM. Improvement is significant
because access to DRAM is mush faster than ROM.
GENERAL FEATURES
__________________________________
__________________________________
2-9
The memor
y refresh logic is redesigned to improve the
system performance and power consumption. In the origina
l
PC/AT
design, the memory refresh operation will suspend th
e
CPU
operation because it has to access the main memory. I
na
high speed system like HIPPO COM, the CPU indeed ca
n
proc
ess
a large amount of operations in the memory refres
h
period.
By implementing hidden refresh method, the refres
h
ope
rations for expansion card on the AT bus and for the main
memory are separated.
To be compatible, the refresh operation
for AT
bus will not be changed. But the refresh operation for
main memory wil
l be carried out individually and will be done
when
th
ere is no access to main memory. Furthermore, th
e
fre
quency of the main memory refresh operation may be set to
'normal' or 'slow'. Al
l types of DRAM can be used in `normal'
mo
de.
When 'slow' mode is selected, the availability of mai
n
memory is increased but the
refresh period of DRAM should be
longer
.
Since the refresh period of DRAM from differen
t
manufacturers may vary, consult your dealer for detail.
GENERAL FEATURES
__________________________________
__________________________________
2-10
8042 EMULATION
Now, there
are many PC designs with a special feature
for OS/2 optimization.
It is intended to speed up the protected
mode
switching operation which is done by the slow spee
d
keyboard
controller in the original PC design. However, thi
s
featur
e
often causes compatibility problem because they us
e
different
hardware logic design to bypass the keyboar
d
controller.
Thus, the BIOS is needed to be modified to tak
e
advantage of it. An application without
modification may cause
problem.
In HIPPO COM, there are some logic designs in th
e
chipset to emulate t
he keyboard controller. An application can
work
in the usual way to send commands to keyboar
d
controller,
but these commands are in fact interpreted by th
e
chip
set.
The protected mode switching operation is muc
h
faster.
There will be no potential problem since modificatio
n
of software is not needed.
GENERAL FEATURES
__________________________________
__________________________________
2-11
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__________________________________
3-1
Chapter 3
Configuring The System
_______________________________
Important Note : Turn off the power before installing or replacing any
component.
INSTALLING RAM MODULES
HIPPO COM has eight sockets on board for SIM
M
modul
es.
Whenever you add memory to the motherboard
,
install four modules at the
same time. Also make sure that the
chips
on the modules face towards the slot for memor
y
expansion board. The modules should be l
ocked by the sockets.
Please check carefully befo
re turning on the power. Otherwise,
the system will not work properly.
To install a module, the m
odule edge is angled into the
socket's
contact and then the module is pivoted into position
,
where the locking
latches will secure it. If the module edge is
not comple
tely inserted into the socket, it cannot be pivoted to
be
in v
ertical position and should be dragged out and re
-
inserted again. Do not force the mod
ule into the SIMM socket.
It will damage the locking latches.
The modules should be l
ocked by the locking latches of
the sockets firmly. Please check car
efully before turning on the
power. Otherwise, the system will not work properly.
CONFIGURING THE SYSTEM
__________________________________
__________________________________
3-2
If
the BIOS reports an memory error or parity error
,
drag
out the modules and insert them again. If the lockin
g
latches a
re damaged, contact your dealer to replace the socket.
CONFIGURATION OF MEMORY
The configuration of the memory is very flexi
ble. There
are several combinations of DRAM types you may consider
.
256KB, 1MB or 4MB SIMM are accepta
ble. So, a basic system
can be equipped with fewer memory and lat
er more memory can
be installed when upgrading the system. There are two banks
of
DRAM on the motherboard and another two banks on
amemory
expansion board. The memory size is detecte
d
automatically by system BIOS and indic
ated during memory test
after reset. No j
umper is needed to be set for the memory size
and DRAM type.
To deter
mine what DRAM speed rating should be used
de
pends
on the system speed and wait state. The highes
t
performance is acc
omplished by using zero wait state, but high
speed DRAM has to be used. If
zero wait state is selected, fast
page mode DRA
M is needed. The wait state setting is applied
to all banks of memory.
Therefore make sure to install DRAM
with
t
he same speed rating, or accommodate the wait stat
e
setting to the slow DRAM type.
CONFIGURING THE SYSTEM
__________________________________
__________________________________
3-3
Be
cause
of the shadow RAM function, the 384K
B
memory
between 640KB to 1MB can not accessed. So, th
e
memory
size found by the system BIOS is not equal to th
e
actual memory size. For example, when there i
s 4MB on board,
the BIOS will show 3712KB.
DRAM CONFIGURATION
Bank 0 Simm
Bank 1 Simm
Total Memory
(2-5)
(6-9)
256K
---1M256K
256K2M1M
---4M1M
256K5M1M1M8M4M---
16M4M256K
17M1M4M
20M4M4M
32M
CONFIGURING THE SYSTEM
__________________________________
__________________________________
3-4
CONTROL OF SYSTEM SPEED
System
speed can be controlled by
keyboard and turbo
switch. To change the speed by keyboard, use
`-'
and
`+'
of the
numeric
keypad. Press
`Ctrl' `Alt'
and
`-'
for slow speed and
press
`Ctrl' `Alt'
and
`+'
for fast speed.
Conn
ect
P2 to the turbo switch of the case and P4 t
o
the
turbo LED of the case. When the turbo mode
is selected,
the turbo LED of the case will be turned on.
Whenever
the system speed is set to be slow by turb
o
switch, it cannot be changed by the keyboard, and vice versa.
CONFIGURING THE SYSTEM
__________________________________
__________________________________
3-5
SYSTEM BOARD JUMPER SETTING
There are several options which
allows user to select by
hardware switches.
CPU Type
CPU
JP2
JP3
JP4
*486DX
1-2
1-2
1-2
486SX
2-3
2-3
OPEN
487SX
1-2
1-2
2-3
System Speed
Speed
JP5
JP6
JP7
25MHz
1-2
1-2
2-3
*33MHz
2-3
1-2
1-2
40MHz
2-3
2-3
1-2
50MHz
1-2
2-3
1-2
REMARK:
Make sure
the 'System Speed' setting matched with
the CPU speed rating.
CONFIGURING THE SYSTEM
__________________________________
__________________________________
3-6
Display Selection
JP1
DISPLAY TYPE
1-2
Monochrome *
2-3
CGA/EVA/VGA
CMOS Jumper
JP19
CMOS OPTION
2-3
NORMAL OPERATION *
1-2
RESET CMOS SETUP
CONFIGURING THE SYSTEM
__________________________________
__________________________________
3-7
I/O SYSTEM
JP8
ON-BOARD IDE
1-2
ENABLE *
2-3
DISABLE
JP9
ON-BOARD FLOPPY
1-2
ENABLE *
2-3
DISABLE
JP10
ON-BOARD GAME PORT
2-3
ENABLE *
1-2
DISABLE
JP11
ON-BOARD PRINTER PORT
1-2
ENABLE *
2-3
DISABLE
JP12
PRINTER PORT SELECT
1-2
LPT2 (378) *
2-3
LPT3 (278)
CONFIGURING THE SYSTEM
__________________________________
__________________________________
3-8
JP14
ON-BOARD SERIAL PORT #1
1-2
ENABLE *
2-3
DISABLE
JP15
SERIAL PORT #1 SELECT
1-2
COM1 (3F8) *
2-3
COM3 (3E8)
JP17
ON-BOARD SERIAL PORT #2
1-2
ENABLE *
2-3
DISABLE
JP18
SERIAL PORT #2 SELECT
1-2
COM2 (2F8) *
2-3
COM4 (2E8)
CONFIGURING THE SYSTEM
__________________________________
__________________________________
3-9
SYSTEM BOARD CONNECTORS
Under typical conditions, these connectors should b
e
connect
ed
to the indicators and switches of the system unit
.The
functions of connectors on the motherboard are liste
d
below.
Description
P1
Hardware reset connector
P2
Turbo switch connector
P3
Harddisk activity LED connector
P4
Turbo LED cwnector
P5
Power LED & Keylock connector
P6
Speaker connector
P7
Harddisk connector
P8
Floppy Diskette Drive connector
P9
Primary Serial Port cable connector
P10
Secondary Serial Port cable connector
P11
Parallel Printer Port cable connector
P12
Game Port cable connector
P13-P14
Power Supply connector
P15
External Battery connector
P16
Cooling Fan connector
KB1
Keyboard connector
CONFIGURING THE SYSTEM
__________________________________
__________________________________
3-10
Pin assignment of the connector are illustrated a
s
follows:
P1 - Hardware Reset Connector
Pin
Assignment
1
Selection Pin
2
Ground
P2 - Turbo Switch Connector
Pin
Assignment
1
Selection Pin
2
Ground
P4 - Turbo LED Connector
Pin
Assignment
1
+5Vdc
2
LED signal
CONFIGURING THE SYSTEM
__________________________________
__________________________________
3-11
P5 - Power LED & Ext-Lock Connector
Pin
Assignment
1
+5 Vdc
2
Key
3
Ground
4
Keyboard inhibit
5
Ground
P6 - Speaker Connector
Pin
Assignment
1
Data out
2
+5 Vdc
3
Ground
4
+5 Vdc
CONFIGURING THE SYSTEM
__________________________________
__________________________________
3-12
P13-P14 - Power Supply Connector
Pin
Assignment
1
POWERGOOD
2
+5 Vdc
3
+12 Vdc
4
-12 Vdc
5
Ground
6
Ground
Pin
Assignment
1
Ground
2
Ground
3
-5 Vdc
4
+5 Vdc
5
+5 Vdc
6
+5 Vdc
CONFIGURING THE SYSTEM
__________________________________
__________________________________
3-13
P15 - External Battery Connector
Pin
Assignment
1
+ Vdc
2
not used
3
Ground
4
Ground
P16 - Cooling Fan connector
Pin
Assignment
1
+ 5Vdc
2
Ground
KB1 - Keyboard Connector
Pin
Assignment
1
Keyboard clock
2
Keyboard data
3
Spare
4
Ground
5
+5 Vdc
CONFIGURING THE SYSTEM
__________________________________
__________________________________
3-14
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__________________________________
4-1
Chapter 4
Technical Information
_______________________________
This section provides technical information abou
t
HIPPO COM and is
intended for advanced users interested in
the basic design and operation of HIPPO COM.
MEMORY MAPPING
Address
Range
Function
000000-
000K-512K
System Board Memory
7FFFFF
(512K)
080000-
512K-640K
System Board Memory
09FFFF
(128K)
0A0000-
640K-768K
Display Buffer (128K)
0BFFFF
0C0000-
768K-896K
Adaptor ROM / Shadow
0DFFFF
RAM (128K)
0E0000-
896K-960K
System ROM / Shadow
0EFFFF
RAM (64K)
0F0000-
960K-1024K
System BIOS ROM /
0FFFFF
Shadow RAM (64K)
100000-
1024K-8192K
System Memory
7FFFFF
800000-
8192K-16318K
System Memory
FFFFFF
TECHNICAL INFORMATION
__________________________________
__________________________________
4-2
I/O ADDRESS MAP
I/O Address Map on System Board
I/O address hex 000 to 0FF are
reserved for the system
board I/O.
ADDRESS
DEVICE
(HEX)
000-01F
DMA Controller 1, 8237
020-03F
Interrupt Controller 1, 8259, Master
040-05F
Timer, 8254
060-06F
Keyboard Controller
070-07F
Real Time Clock, NMI
(non-maskable interrupt) mask
080-09F
DMA Page Register, 74LS612
0A0-0BF
Interrupt Controller 2, 8259
0C0-0DF
DMA Controller 2, 8237
0F0
Clear Math Coprocessor Busy
0F1
Reset Math Coprocessor
0F8-0FF
Math Coprocessor Port
TECHNICAL INFORMATION
__________________________________
__________________________________
4-3
I/O
ad
dress hex 100 to 3FF are available on the I/
O
channel.
ADDRESS
DEVICE
(HEX)
1F0-1F8
Fixed Disk
200-207
Game I/O
278-27F
Parallel Printer Port 2
2F8-2FF
Serial Port 2
300-31F
Prototype Card
360-36F
Reserved
378-37F
Parallel Printer Port 1
380-38F
SDLC, bisynchronous 2
3A0-3AF
Bisynchronous 1
3B0-3BF
Monochrome Display and Printer Adapter
3C0-3CF
Reserved
3D0-3DF
Color Graphics Monitor Adapter
3F0-3F7
Diskette Controller
3F8-3FF
Serial Port 1
TECHNICAL INFORMATION
__________________________________
__________________________________
4-4
SYSTEM TIMERS
HIPP
O COM has three programmable timer/counter
s
cont
rolled
by Headland chipset and they are defined a
s
channels 0 through 2:
Channel 0
System Timer
Gate 0
Tied on
Clk in 0
1.190 Mhz OSC
Clk out 0
8259 IRQ 0
Channel 1
Refresh Request
Generator
Gate 1
Tied on
Clk in 1
1.190 Mhz OSC
Clk out 1
Request Refresh Cycle
TECHNICAL INFORMATION
__________________________________
__________________________________
4-5
Channel 2
Tone Generation of
Speaker
Gate 2
Controlled by bit 0 of
port hex 61 PPI bit
Clk in 2
1.190 Mhz OSC
Clk out 2
Used to drive the
speaker
Note :
Channel 1 is programmed to generate a 15-micro-second period signal.
The 8254 Timer/Counters are treated by syste
m
programs as an arrangement of four progra
mmable external I/O
ports.
Three are treated as counters and the fourth is
a
control register for mode programming.
TECHNICAL INFORMATION
__________________________________
__________________________________
4-6
SYSTEM INTERRUPTS
Sixte
en
levels of system interrupts are provided o
n
HIP
PO COM. The following shows the interrupt-leve
l
assignments in decreasing priority.
Level
Function
Microprocessor NMI
Parity or I/O Channel
Check
Interrupt Controllers
CTLR 1
CTLR 2
IRQ0
Timer Output 0
IRQ1
Keyboard
(Output Buffer Full)
IRQ2
Interrupt from CTLR 2
IRQ8
Real-time Clock Interrupt
IRQ9
Software Redirected to
INT 0AH (IRQ2)
IRQ10
Reserved
IRQ11
Reserved
IRQ12
Reserved
IRQ13
Coprocessor
IRQ14
Fixed Disk Controller
IRQ15
Reserved
IRQ3
Serial Port 2
IRQ4
Serial Port 1
IRQ5
Parallel Port 2
IRQ6
Diskette Controller
IRQ7
Parallel Port 1
*,
*,
TECHNICAL INFORMATION
__________________________________
__________________________________
4-7
DIRECT MEMORY ACCESS (DMA)
HIPPO COM supports seven DMA channels.
Channel
Function
0
Spare (8 bit transfer)
1
SDLC (8 bit transfer)
2
Floppy Disk (8 bit transfer)
3
Spare (8 bit transfer)
4
Cascade for DMA Controller 1
5
Spare (16 bit transfer)
6
Spare (16 bit transfer)
7
Spare (16 bit transfer)
TECHNICAL INFORMATION
__________________________________
__________________________________
4-8
The following shows the addresses for the
page register.
Page Register
I/O Address (HEX)
DMA Channel 0
0087
DMA Channel 1
0083
DMA Channel 2
0081
DMA Channel 3
0082
DMA Channel 5
008B
DMA Channel 6
0089
DMA Channel 7
008A
Refresh
008F
REAL TIME CLOCK AND CMOS RAM
Real time clock and CMOS RAM are contained o
n
boa
rd.
Real time clock provides the system date and time
.
CMOS RAM stores system
information. Both are backed up by
battery
and will not lose information after power off. Th
e
following page shows the CMOS RAM Address Map.
TECHNICAL INFORMATION
__________________________________
__________________________________
4-9
CMOS RAM ADDRESS MAP
Addresses
Description
00-0D
* Real-time clock information
0E
* Diagnostic status byte
0F
* Shutdown status byte
10
Diskette drive type byte
- drives A and B
11
Reserved
12
Fixed disk type byte
- drives C and D
13
Reserved
14
Equipment byte
15
Low base memory byte
16
High base memory byte
17
Low expansion memory byte
18
High expansion memory byte
19-2D
Reserved
2E-2F
2-byte CMOS checksum
30
* Low expansion memory byte
31
* High expansion memory byte
32
* Date century byte
33
* Information flags
(set during power on)
34-3F
Reserved
TECHNICAL INFORMATION
__________________________________
__________________________________
4-10
REAL TIME CLOCK INFORMATION
The following table d
escribes real-time clock bytes and
specifies their addresses.
Byte
Function
Address
0
Seconds
001 Second alarm
012 Minutes
023 Minute alarm
034 Hours
045 Hour alarm
056 Day of week
067 Date of month
078 Month
089 Year
0910 Status Register A
0A11 Status Register B
0B12 Status Register C
0C13 Status Register D
0D
TECHNICAL INFORMATION
__________________________________
__________________________________
4-11
SYSTEM EXPANSION BUS
HIPPO COM provides four 16-bit slots.
The I/O channel supports:
*
I/O address space from hex 100 to hex 3FF
*
Selection of data access (either 8 or 16 bit)
*
24 bit memory addresses (16MB)
*
Interrupts
*
DMA channels
*
Memory refresh signal
TECHNICAL INFORMATION
__________________________________
__________________________________
4-12
The
fol
lowing figure shows the pin numbering for I/
O
channel connectors (A-side and B-side).
TECHNICAL INFORMATION
__________________________________
__________________________________
4-13
The
fol
lowing figure shows the pin numbering for I/
O
channel connectors (C-side and D-side).
TECHNICAL INFORMATION
__________________________________
__________________________________
4-14
The following tables s
ummarize pin assignments for the
I/O channel connectors.
I/O Channel (A-Side)
I/O Pin
Signal Name
I/OA1-I/O CH CK
IA2SD7
I/OA3SD6
I/OA4SD5
I/O
A5
SD4
I/O
A6
SD3
I/OA7SD2
I/OA8SD1
I/OA9SD0
I/O
A10
-I/O CH RDY
I
A11
AENOA12
SA19
I/O
A13
SA18
I/O
A14
SA17
I/O
A15
SA16
I/O
A16
SA15
I/O
A17
SA14
I/O
A18
SA13
I/O
A19
SA12
I/O
A20
SA11
I/O
A21
SA10
I/O
A22
SA9
I/O
A23
SA8
I/O
A24
SA7
I/O
A25
SA6
I/O
A26
SA5
I/O
A27
SA4
I/O
A28
SA3
I/O
A29
SA2
I/O
A30
SA1
I/O
A31
SA0
I/O
TECHNICAL INFORMATION
__________________________________
__________________________________
4-15
I/O Channel (B-Side)
I/O Pin
Signal Name
I/OB1 GND
Ground
B2
RESET DRV
IB3 +5 Vdc
Power
B4
IRQ9
I
B5
-5 Vdc
Power
B6
DRQ2
IB7 -12 Vdc
Power
B8
0WSIB9
+12 Vdc
Power
B10
GND
Ground
B11
-SMEMW
O
B12
-SMEMR
O
B13
-IOW
I/O
B14
-IOR
I/O
B15
-DACK3
I
B16
DRQ3
O
B17
-DACK1
I
B18
DRQ1
O
B19
-Refresh
I/O
B20
CLK
O
B21
IRQ7
I
B22
IRQ6
I
B23
IRQ5
I
B24
IRQ4
I
B25
IRQ3
I
B26
-DACK2
O
B27
T/COB28
BALE
O
B29
+5 Vdc
Power
B30
OSC
O
B31
GND
Ground
TECHNICAL INFORMATION
__________________________________
__________________________________
4-16
I/O Channel (C-Side)
I/O Pin
Signal Name
I/OC1SBHE
I/OC2LA23
I/OC3LA22
I/OC4LA21
I/O
C5
LA20
I/O
C6
LA19
I/OC7LA18
I/OC8LA17
I/OC9-MEMR
I/O
C10
-MEMW
I/O
C11
SD8
I/O
C12
SD9
I/O
C13
SD10
I/O
C14
SD11
I/O
C15
SD12
I/O
C16
SD13
I/O
C17
SD14
I/O
C18
SD15
I/O
TECHNICAL INFORMATION
__________________________________
__________________________________
4-17
I/O Channel (D-Side)
I/O Pin
Signal Name
I/OD1 -MEM CS16
ID2 -I/O CS16
ID3 IRQ10
ID4 IRQ11
I
D5
IRQ12
I
D6
IRQ15
ID7 IRQ14
ID8 -DACK0
OD9 DRQ0
I
D10
-DACK5
O
D11
DRQ5
I
D12
-DACK6
O
D13
DRQ6
I
D14
-DACK7
O
D15
DRQ7
I
D16
+5 Vdc
Power
D17
-MASTER
I
D18
GND
Ground
TECHNICAL INFORMATION
__________________________________
__________________________________
4-18
THIS PAGE IS INTENTIONALLY LEFT BLANK
__________________________________
A-1
Appendix A
Operation and Maintenance
_______________________________
STATIC ELECTRICITY
When installing or removing any add-on card, DRA
M
module
or coprocessor, you should discharge the stati
c
electr
icity
on your body. Static electricity is dangerous t
o
elec
tronic
device and can build-up on your body. When yo
u
touch the add-on card or motherboard, it is li
kely to damage the
device.
To discharge the static electricity, touch the metal o
f
your
computer. When handling the add-on card, don't contact
the components on the cards or t
heir "golden finger". Hold the
cards by their edges.
KEEPING THE SYSTEM COOL
The motherboard contains
many high-speed components
and
the
y will generate heat during operation. Other add-o
n
car
ds and hard disk drive can also produce a lot of heat. The
temperature
inside
the computer system may be very high. In
order
to
keep the system running stably, the temperature must
be kept at a low level. A easy way to do this is to keep th
e
cool air circulating inside
the case. The power supply contains
a
fa
n to blow air out of the case. If you find that th
e
temperature
is still very high, it would be better to instal
l
anoth
er
fan inside the case. Using a larger case i
s
recommended
if there are a number of add-on cards and dis
k
drives in the system.
OPERATION AND MAINTENANCE
__________________________________
__________________________________
A-2
CLEANING THE "GOLDEN FINGER"
Whenever inserting a
n add-on card to the motherboard,
make
sure
that there is no dirt on the "golden finger" of th
e
add-on
c
ard. If not, the contact between the "golden finger
"
and
the slot may be poor and thus the add-on card may no
t
work properly. Use a pencil erase
r to clean the "golden finger"
if dirt is found.
CLEANING THE MOTHERBOARD
The
com
puter system should be kept clean. Dust an
d
dirt
is
harmful to electronic devices. To prevent dust fro
m
accumulating
on the mother-board, installing all mountin
g
plates on the rear o
f the case. Regularly examine your system,
and
if
necessary, vacuum the interior of the system with
a
miniature vacuum.
__________________________________
A-3
THIS PAGE IS INTENTIONALLY LEFT BLANK
__________________________________
C-1
Appendix B
SUMMERY OF
JUMPER SETTING
_______________________________
CPU
JP2
JP3
JP4
*486DX
1-2
1-2
1-2
486SX
2-3
2-3
OPEN
487SX
1-2
1-2
2-3
Speed
JP5
JP6
JP7
25MHz
1-2
1-2
2-3
*33MHz
2-3
1-2
1-2
40MHz
2-3
2-3
1-2
50MHz
1-2
2-3
1-2
JP1
DISPLAY TYPE
1-2
Monochrome *
2-3
CGA/EVA/VGA
JP19
CMOS OPTION
2-3
NORMAL OPERATION *
1-2
RESET CMOS SETUP
__________________________________
C-2
I/O SYSTEM
JP8
ON-BOARD IDE
1-2
ENABLE *
2-3
DISABLE
JP9
ON-BOARD FLOPPY
1-2
ENABLE *
2-3
DISABLE
JP10
ON-BOARD GAME PORT
2-3
ENABLE *
1-2
DISABLE
JP11
ON-BOARD PRINTER PORT
1-2
ENABLE *
2-3
DISABLE
JP12
PRINTER PORT SELECT
1-2
LPT2 (378)
2-3
LPT3 (278)
JP14
ON-BOARD SERIAL PORT #1
1-2
ENABLE *
2-3
DISABLE
JP15
SERIAL PORT #1 SELECT
1-2
COM1 (3F8)
2-3
COM3 (3E8)
__________________________________
C-3
JP17
ON-BOARD SERIAL PORT #2
1-2
ENABLE *
2-3
DISABLE
JP18
SERIAL PORT #2 SELECT
1-2
COM2 (2F8)
2-3
COM4 (2E8)
JUMPER SETTING
__________________________________
__________________________________
C-4
THIS PAGE IS INTENTIONALLY LEFT BLANK
__________________________________
C-1
Appendix C
System Board Layout
_______________________________
HIPPO COM BOARD LAYOUT
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