O2Micro OZ990S Datasheet
FEATURES
• SMBus 1.0 Compliant
• Support Pentium class and x86-based designs
• PMU, GPIO, and Alternative PMU modes
• WAKE output and Suspend Status input operates
synchronously with PMU in notebook chipsets
• LOW power-saving Suspend mode
• Hardware Debounced Wakeup/Suspend input as
pushbutton
• 4 Power Control programmable outputs with built-
in Power Sequencing at 10 ms to 1 second
programmable intervals
• Optional Wakeup-Disable inputs
• Optional Power-On inputs
• 8 programmable interrupt inputs for SMIEVENT
or SMBALERT#
• 8 Suspend/Wakeup edge-triggered
programmable inputs
• 20 possible programmable edge-sensitive
General Purpose Inputs/Outputs
• 8 Auto LED Flash(ALF) programmable outputs
with 10% or 50% duty cycles
• LOW power hardware driven speaker alarm
output
• Up to 6 programmable unique addresses for
device cascade
• 8 power-on modularized hardware ID
programmable inputs
• 32KHz operating frequency
• 5 V tolerant inputs
• Supports both 3.3 V and 5 V operating
environments
• Software programming kit available
ORDERING INFORMATION
OZ990S - 28 SSOP
OZ990
Intelligent Manager
Smart PMU/GPIO
GENERAL DESCRIPTION
Micro’s OZ990 Smart PMU/GPIO (Power
O
2
Management Unit/General Purpose Input Output) unit
allows the implementation of Green PC Desktop
Chipsets in notebook designs at considerably lower
cost than conventional methods while closing the
technology gap between desktop and notebook
computers by offering an extensive number of
powerful power management and general purpose I/O
features. With the OZ990 stand-alone PMU capability,
the ability to provide the One-Shot Design for
PMU/BIOS practically eliminates the need to redesign
PMUs to match the ever-changing core logic chipsets.
The OZ990 provides the perfect solution for leading
notebook vendors to stay ahead of the competition.
The OZ990 is an SMBus 1.0 compliant device with 4
Power Control and 16 Programmable General
Purpose I/Os pins flexible for a variety of functions
such as Power Control with sequencing,
programmable inputs/outputs, SMB/SMI interrupt
service, power-saving, Suspend/Wakeup,
modularized hardware ID, and Auto LED Flash (ALF)
status display. Other features include hardware-driv en
speaker alarm output and Suspend/Wakeup button.
As a Pentium class and x86-based system compatible
device, the OZ990 is a highly cost-effective and
practical solution for today’s notebook and palmtop
computers, pen-based data systems, personal digital
assistants, and portable data-collection terminals.
07/13/00 OZ990-SF-1.6 Page 1
Copyright 1998 by O
Micro All Rights Reserved
2
PIN ASSIGNMENT
OZ990
SMBCLK
SMBDATA
PWRGD
MODE
PC[0] / GPIO[16]
PC[1] / GPIO[17]
PC[2] / GPIO[18]
PC[3] / GPIO[19]
GPIO[0] / SMIEVENT
GPIO[1] / WAKE
GPIO[2] / SMBALERT#
GPIO[3]
GPIO[4]
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
32KHZ
RESETN
SRBTN # / GPIO[15]
GPIO[14]
GPIO[13]
GPIO[12]
GPIO[11]
GPIO[10]
GPIO[9]
GPIO[8]
SMBIDSEL[2] / GPO[7]
SMBIDSEL]1] / GPO[6]
SMBIDSEL[0] / GPO [5]
PIN CONFIGURATION
Name Pin No. Type Input Drive Definition
SMBCLK
1 I TTL SMBus Cl ock Input for SMBus protoc ol communicati on.
SMBDATA
2 I/O TTL 12mA
SMBus Dat a Input/Output for SMBus prot ocol communication.
PWRGD
3 I TTL -
This pin indicates that t he host system’s power, including the Core Logic c hipset s, is st able. Before t he host
system’s power is stable, this input pin will tri-state all the output pins from OZ990 with the exception of the
Power Control pins. The state of the PW RGD pin determines whether the OZ990 is in PMU or Alt ernate
PMU mode when RESETN is active. When pin MODE=1 and pin PW RGD=0, the OZ990 is in PMU mode.
When pin MODE=1 and pin PWRGD=1, the OZ990 is in Alternate PMU mode.
MODE
4 I TTL -
The OZ990 has 3 modes of operation: GP IO(with 20 GPIOs available), PMU(with 16 GPIOs available), and
Alternate PMU(with 16 GPIOs available). To use the OZ990 as a PMU, tie MODE pin to VDD and set
PWRGD LOW . For Alternate PMU mode, tie MODE pin to VDD and set PW RGD HIGH. For GPIO-only
mode, tie MODE pin LOW. Refer to MODE descript i on for more details.
PC[3:0]/
[8:5] I/O TTL 4mA
GPIO[19:16]
Pins PC[3:0]/GPIO[19:16] can be used as Power Control out put s for cold start, reset, Suspend, and Wakeup
or as regular GPIOs. Upon power up, if the OZ990 is in PMU mode, PC[3:0] will default to 0, with OZ990
initially in Suspend mode. B y default, on a falling edge-triggered S RBTN#/GP IO[ 15] (with Wakeup function),
PC[3:0] will be set to 1 to power on the sys tem. On a subsequent trigger of GPIO[15:8]’s Sus pend and
Wakeup functions , the values in PC_SUSPEND[3:0] and PC_W AKE[ 3:0] in register 0Bh will be copied onto
the PC[3:0] output pins. Additionally, the OZ990 provides a power sequencing feature that allows up to 8
different programmabl e values of staggering time for t he PC[3:0] outputs. PC[3:0] are also programmable
just like t he GPIO[19:16] pins but with bits PCI[3:0] in regis ter 0Bh as input data and PCO[3:0] i n register
0Ch as output data values.
GPIO[0]/
9 I/O TTL 4mA
SMIEVENT
Fully programmable GPIOs that can be used for a variety of dedicated or specific funct i ons. Pin GPIO[0] has
SMIEVENT output as an alt ernate function. GPIO[0] defaults as outputs in PMU mode, and as input in
Alternate PMU and GPIO modes . It is also program mable to funct ion as either GPI[0] input, GPO[0]output ,
ALF[0] output, PWRON input, WAKE_DIS input, or ID[0] input (in Alternate PMU and GPIO modes). When
implementing as ID[0] input, GPIO[0]/SMIEVENT pin is internally latched from external pull-ups or pulldowns, when RESETN is LOW. The values will be stored permanently in the ID Register and
GPIO[0]/SMIEVENT pin can then be reconfigured as an out put. Refer to GPIO Config.1&2 Registers for
more details and GPIO Confi g. Tables for input/output s el ections.
SMBus Clock Input
SMBus Data Input/Output
Host System Power Good
OZ990 Mode Input
Power Control Outputs /
General Purpose I/Os
General Purpose I/O /
SMIEVENT
OZ990-SF-1.6 Page 2
Loading...