O2Micro OZ6912T, OZ6912B Datasheet
Single-Slot ACPI CardBus Controller
FEATURES
• ACPI-PCI Bus Power Management Interface
Specification Rev 1.1 Compliant
• Supports OnNow LAN wakeup, OnNow Ring Indicate,
PCI CLKRUN#, PME#, and CardBus CCLKRUN#
• Compliant with PCI specification v2.2, 2000 PC Card
Standard 7.1
• Yenta™ PCI to PCMCIA CardBus Bridge register
compatible
• ExCA (Exchangeable Card Architecture) compatible
registers mappable in memory and I/O space
• Intel
• Supports PCMCIA_ATA Specification
• Supports 5V/3.3V PC Cards and 3.3V CardBus cards
• Supports single PC Card or CardBus slot with hot
• Supports multiple FIFOs for PCI/CardBus data transfer
• Supports Direct Memory Access for PC/PCI and
• Programmable interrupt protocol: PCI, PCI+ISA,
• Win’98 IRQ and PC-98/99 compliant
• Supports parallel or serial interface for socket power
• Zoomed Video Support; Zoomed video buffer enable
• D3
• 3.3Vaux Power Support
• Integrated PC 98/99 -Subsystem Vendor ID support,
• LED Activity Pins
ORDERING INFORMATION
OZ6912T - 144pin LQFP
OZ6912B - 144pin Mini-BGA
GENERAL DESCRIPTION
The OZ6912 is an ACPI and PC98/99 Logo Certified, high
performance, single slot PC Card controller with a
synchronous 32-bit bus master/target PCI interface. This
PC Card to PCI bridge host controller is compliant with the
2000 PC Card Standard. This standard incorporates the
new 32-bit CardBus while retaining the 16-bit PC Card
TM
82365SL PCIC Register Compatible
insertion and removal
PCI/Way on PC Card socket
PCI/Way, or PC/PCI interrupt signaling modes
control including devices from Micrel and TI
pins
state PME# wakeup support
cold
with auto lock bit
OZ6912
specification as defined by PCMCIA release 2.1. CardBus
is intended to support “temporal” add-in functions on PC
Cards, such as Memory cards, Network interfaces,
FAX/Modems and other wireless communication cards, etc.
The high performance and capability of the CardBus
interface will enable the new development of many new
functions and applications.
The OZ6912 CardBus controller is compliant with the latest
ACPI-PCI Bus Power Management Interface Specification.
It supports all four power states and the PME# function for
maximum power savings and ACPI compliance. Additional
compliance to OnNow Power Management includes D3
state support, paving the way for low sleep state power
consumption and minimized resume times. To allow host
software to reduce power consumption further, the OZ6912
provides a power-down mode in which internal clock
distribution and the PC Card socket clocks are stopped. An
advanced CMOS process is also used to minimize system
power consumption.
The OZ6912 single PCMCIA socket supports a mix and
match 3.3V/5V 8/16-bit PC Card R2 card or 32-bit CardBus
R3 card. The R2 card support is compatible with the Intel
82365SL PCIC controller, and the R3 card support is fully
compliant with the 2000 PC Card Standard CardBus
specification. The OZ6912 is a stand alone device, which
means that it does not require an additional buffer chip for
the PC Card socket interface. In addition, the OZ6912
supports dynamic PC Card hot insertion and removal, with
auto configuration capabilities.
The OZ6912 is fully compliant with the 33Mhz PCI Bus
specification, v2.2. It supports a master device with internal
CardBus direct data transfer. The OZ6912 implements a
FIFO data buffer architecture between the PCI bus and
CardBus socket interface to enhance data transfers to
CardBus devices. The bi-directional FIFO buffer permits the
OZ6912 to accept data from a target bus (PCI or CardBus
interface) while simultaneously transferring data. This
architecture not only speeds up data transfers but also
prevents system deadlocks.
The OZ6912 is a PCMCIA R2/CardBus controller, providing
the most advanced design flexibility for PC Cards that
interface with advanced notebook designs.
cold
06/28/00 OZ6912-SF-1.5 Page 1
Copyright 2000 by O
Micro All Rights Reserved Patent Pending
2
Functional Block Diagram
OZ6912
PCI Interface
PCI Configuration/
Function Control Registers
Power Switch
Control
PCI
Function Control
Configuration/
Registers
Power
Contro
Switch
l
PC Card
Machine
8/16-Bit
16-
PC
Bit
Machin
Card
e
PCI
PCI
Arbite
Arbiter
r
CardBu
CardBus FIFO
Data Buffering
Data
s
Buffering
CardBus
PC Card
Machine
and
Arbiter
FIFO
ACPI/ OnNow
Power Management
for PC99
Interrupt
Interrup
Subsystem
Subsyste
t
m
Powe
Power
Switc
r
Switch
h
Interface
Single PC Card Interface
PC Card
Interface
OZ6912-SF-1.5 Page 2
OZ6912
SYSTEM BLOCK DIAGRAM
The following diagram is a typical system block diagram utilizing the OZ6912 ACPI CardBus controller with other related
chipsets.
CPU
PCI Bus
VGA
AGP
OZ6912
CardBus
Controller
PC
Card
Memory
North Bridge
South Bridge
ISA
OZ6912-SF-1.5 Page 3
PIN DIAGRAM - 144 Pin LQFP
D10/CAD31
D1/CAD29
D9/CAD30
D8/CAD28
D2/RFU
WP/IOIS16/CCLKRUN#
CD2/CCD2#
CORE_VCC
D0/CAD27
OZ6912
BVD1/STSCHG#/RI#/CSTSCHG
BVD2/SPKR#/LED/CAUDIO
RDY/IREQ#/CINT#
WAIT#/CSERR#
A2/CAD24
A0/CAD26
A1/CAD25
VS1/CVS1
GND
INPACK#/CREQ#
REG#/CCBE3#
SOCKET_VCC
A3/CAD23
CORE_VCC
RESET/CRST#
A25/CAD18
A4/CAD22
VS2/CVS2
A6/CAD20
A5/CAD21
A7/CAD18
A23/CFRAME#
A22/CTRDY#
A15/CIRDY#
A12/CCBE2#
A24/CAD17
GND
REQ#
GNT#
AD31
AD30
AD29
GND
AD28
AD27
AD26
AD25
AD24
C/BE3#
IDSEL
CORE_VCC
AD23
AD22
AD21
PCI_VCC
AD20
RST#
PCI_CLK
GND
AD19
AD18
AD17
AD16
C/BE2#
FRAME#
IRDY#
PCI_VCC
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
1
1
2
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37383940414243444546474849505152535455565758596061626364656667686970717
O2Micro, Inc.
OZ6912
2
1
1
0
9
8
1
1
1
1
1
7
6
5
4
1
1
1
1
1
1
1
3
108
1
1
0
107
0
2
1
9
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
2
A16/CCLK
A21/CDEVSEL#
WE#/CGNT#
A20/CSTOP#
A14/CPERR#
A19/CBLOCK#
CORE_VCC
A13/CPAR
A18/RFU
A8/CCBE1#
A17/CAD16
A9/CAD14
IOW#/CAD15
A11/CAD12
GND
IORD#/CAD13
OE#/CAD11
CE2#/CAD10
SOCKET_VCC
A10/CAD9
CE1#/CCBE0#
D15/CAD8
CORE_VCC
D7/CAD7
D14/RFU
D6/CAD5
D13/CAD6
D5/CAD3
D12/CAD4
D4/CAD1
GND
D11/CAD2
D3/CAD0
CD1/CCD1#
VCCD1#/SCLK
VCCD0#/SDATA
VPPD1
MF0
C/BE1#
AD15
AD14
AD13
PCI_VCC
GND
AD12
AD11
C/BE0#
AD10
AD9
PCI_VCC
AD8
AD7
AD6
AD5
AD4
AD2
AD0
AD3
AD1
MF1
GND
RI_OUT/PME#
MF3
MF2
SPKR_OUT#
MF4
GLOBAL_RST#
AUX_VCC
VPPD0/SLATCH
MF5
MF6
SUSPEND#
OZ6912-SF-1.5 Page 4
Pin List
Bold Text = Normal Default Pin Name
PCI Bus Interface Pins
Pin Name Description
AD[31:0]
C/BE[3:0]#
FRAME#
IRDY#
TRDY#
STOP#
IDSEL
DEVSEL#
PERR#
SERR#
PCI Bus Address/Data: These pins connect to
PCI bus signals AD[31:0]. A Bus transaction
consists of an address phase followed by one or
more data phases.
PCI Bus Command / Byte Enable: The
command signaling and byte enables are
multiplexed on the same pins. During the address
phase of a transaction, C/BE [3:0] # are interpreted
as the bus commands. During the data phase,
C/BE[3:0]# are interpreted as byte enables. The
byte enables are to be valid for the entirety of
each data phase, and they indicat e which bytes in
the 32-bit data path are to carry m eaningful data
for the current data phase.
Cycle Frame: This signal indicates to the OZ6912
that a bus transaction is beginning. While
FRAME# is asserted, data transfers continue.
When FRAME# is de-asserted, the trans action is
in its final phase.
Initiator Ready: This signal indicates the initiat i ng
agent’s ability to com plete the current data phas e
of the transaction. I RDY# is used in conjunction
with TRDY#.
Target Ready: This signal indicates target
Agent's the OZ6912’s ability to complete the
current data phase of the t ransaction. TRDY# is
used in conjunction with IRDY#.
Stop: This signal indicates the current target is
requesting the master to stop the current
transaction.
Initialization Device Sele c t : This input is used as
chip select during configuration read and write
transactions. This is a point-to-point signal.
IDSEL can be used as a chip select during
configuration read and write transacti ons.
Device Select: This signal i s driven active LOW
when the PCI address is recognized as
supported, thereby acting as the target for the
current PCI cycle. The Target must respond
before timeout occurs or t he cycle will terminate.
Parity Error: The output is driven active LOW
when a data parity error is detected during a write
phase.
System Error: This output is driven active LOW
to indicate an address parit y error.
OZ6912
Pin Number
LQFP BGA
3-5, 7-11, 1517, 19, 23-26,
38-41, 43, 4547, 49, 51-57
12, 27, 37, 48 E1, J3, N1, N5 TTL I/O PCI_Vcc PCI
28 J4 TTL I/O PCI_Vcc PCI
29 K1 TTL I/O PCI_Vcc PCI
31 K3 TTL I/O PCI_Vcc PCI
33 L2 TTL I/O PCI_Vcc PCI
13 F4 TTL I PCI_Vcc PCI
32 L1 TTL I/O PCI_Vcc PCI
34 L3 - TO PCI_Vcc PCI
35 M1 - TO PCI_Vcc PCI
C2, C1, D4, D2,
D1, E4, E3, E2,
F2, F1, G2, G3,
H3, H4, J1, J2,
N2, M3, N3,
K4, M4, K5, L5,
M5, K6, M6,
N6, M7, N7, L7,
K7, N8
Input Type
TTL I/O PCI_Vcc PCI
Power
Rail
Drive
Spec
Spec
Spec
Spec
Spec
Spec
Spec
Spec
Spec
Spec
OZ6912-SF-1.5 Page 5
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