NXP Semiconductors PN7462, PN7362AUHN, PN7362AUEV, PN7360AUHN, PN7360AUEV User Manual

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Document information

Info

Content

Keywords

PN7462, PN7462 family, PN7362; PN7360; NFC reader

Abstract

This document describes how to use the PN7462 family.

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Contact information

For more information, please visit:

Revision history

Rev

Date

Description

1.4

20180514

Editorial updates

1.3

20180212

Reworking the document to descri be complete PN7462 family

1.2

20170908

GPIO wakeup condition corrected

1.1

20170216

Max enhanced ESD protection changed to 12 kV

1.0

20160225

Initial version

SDA hold equation added

Pull-up and pull-down configuration for SPIM pins corrected CRC polynomial specified

Dynamic Power Control (DPC) added

http://www.nxp.com

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1. Introduction

1.1 General description

The PN7462 family is a family of 32-bit ARM Cortex-M0-based NFC microcontrollers offering high performance and low power consumption. It has a simple instruction set and memory addressing along with a reduced code size compared to existing architectures. PN7462 family offers an all in one solution, with features such as NFC, microcontroller, optional contact smart card reader, and software in a single chip. It operates at CPU frequencies of up to 20 MHz. The PN7462 family consists of six different products.

For more details on all products of the PN7462 family refer to the data sheet. Having the differences listed in the table above, all products within the PN7462 family are

equipped with 12 kB of SRAM data memory and 4 kB EEPROM. All products within the family also include one host interface with either high-speed mode I2C-bus, SPI, USB or high-speed UART, and two master interfaces, SPI and Fast-mode Plus I2C-bus. Four general-purpose counter/timers, a random number generator, one CRC coprocessor and up to 21 general-purpose I/O pins.

The PN7462 family NFC microcontroller offers a one chip solution to build contactless, or contact and contactless applications. It is equipped with a highly integrated high-power output NFC-IC for contactless communication at 13.56 MHz enabling EMV-compliance on RF level, without additional external active components.

PN7462 family supports the following operating modes:

• read/write mode supporting ISO/IEC 1443A and MIFARE ICs

• JIS X 6319-4 (comparable with FeliCa scheme)

• ISO/IEC 15693, ICODE, ISO/IEC 18000-3 mode 3

• NFC protocols - tag reader/writer, P2P

• ISO/IEC 14443- type A card emulation

• EMVCo compliance

In this document the term „MIFARE Classic card“ refers to a MIFARE Classic IC-based contactless card and the term „MIFARE Plus card“ refers to a MIFARE Plus IC-based contactless card.

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1.2 Features and benefit s

1.2.1 Integrated contact interface front-end

This chapter applies to the products with contact interface only.

• Class A, B, and C cards can work on 1.8 V, 3 V, and 5 V supply

• Specific ISO UART, variable baud rate through frequency or division ratio

programming, error management at character level for T = 0, and extra guard time register

• DC-to-DC converter for class A support starting at 3 V, and class B support starting at 2.7 V

• Thermal and short-circuit protection on contact cards

• Automatic activation and deactivation sequence, initiated by software or by

hardware in case of short-circuit, card removal, overheating, and VDD or VDD drop-out

• Enhanced ESD protection (> 12 kV)

• ISO/IEC 7816 compliant

• EMVCo 4.3 compliant

• Clock generation up to 13.56 MHz

• Synchronous card support

• Possibility to extend the number of contact interfaces, with the addition of slot

extenders such as TDA8026

1.2.2 Integrated ISO/IEC 7816-3&4 UART interface

This chapter applies to the products with Integrated ISO/IEC 7816 UART interface only.

The PN7462 family offers the possibility to extend the number of contact interfaces available. It uses an I/O auxiliary interface to connect a slot extension (TDA8035 - 1 slot, TDA8020 - 2 slots, and TDA8026 - 5 slots).

• Class A (5 V), class B (3 V), and class C (1.8 V) smart card supply

• Protection of smart card

• Three protected half-duplex bidirectional buffered I/O lines (C4, C7, and C8)

• Compliant with ISO/IEC 7816 and EMVCo 4.3 standards

1.2.3 Integrated contactless interface f r ont end

• High RF output power frontend IC for transfer speeds up to 848 kbit/s

• NFC IP1 and NPFC IP2 support

• Full NFC Tag support (Type 1, Type 2, Type 3, Type 4 A and B)

• P2P active and passive, target and initiator

• Card emulation ISO14443 type A

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• ISO/IEC 14443 Type A and B

• Support for MIFARE Classic card

• ISO/IEC 15693 and ISO/IEC 18000-3 mode 3

• iClass serial number support

• Low power card detection function

• Compliance with EMV Contactless protocol specification

• Compliance with NFC standard

1.2.4 Cortex M0 microcontroller

• Processor core

− 32-bit ARM cortex M0 processor

− Built-in Nested Vectored Interrupt Controller (NVIC)

− Non-maskable interrupt

− System Tick Timer 24 bits

− Running frequency up to 20 MHz

− Clock management to enable low power consumption

• Memory

− Flash: 160 kB

− RAM: 12 kB

− EEPROM: 4 kB

− 40 K boot ROM included, including USB mass storage primary boot loader for

code download.

• Debug Option

− Serial Wire Debug interface (SWD)

• Master Interfaces:

− SPI half-duplex, up to 6.78 Mbit/s

− I²C supporting fast mode plus, and clock stretching

• Host Interfaces

− HSUART for serial communication, supporting standards speeds from 9600 to

115200 bps, and faster speed up to 1.288 Mbit/s

− SPI half-duplex and full duplex, up to 7 Mbit/s

− I²C Host supporting standard, fast and high-speed mode with multiple addr ess

support

− USB 2.0 full speed, with USB 3.0 hub connection capability

• Up to 21 General-Purpose I/O (GPIO) with configurable pull-up/pull-down resistors

• GPIOs 1 to 12 can be used as edge and level sensitive interrupt sources

• Power

− Two reduced power modes: Sleep mode and hard power down mode

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− Suspend mode for USB host interface

− Processor wake-up from hard power down mode, stand-by mode, suspend mode

via: host interface, contact card interface, GPIOs, RF field detection

− Integrated PMU to automatically adjust internal regulators, to minimize the power

consumption during all possible power modes.

− Power-on reset

− RF supply; external, or using an integrated LDO (TXLDO configurable with 3 V,

3.3 V, 3.6 V, 4.5 V, and 4.75 V)

− Pad voltage supply: external 3.3 V or 1.8 V, or using an integrated LDO (3.3 V

supply)

− Integrated contact interface voltage regulation for 1.8 V, 3 V, and 5 V card supply,

including a DC-to-DC converter for support of Class A and Class B cards

• Timers

− Four general-purpose timers

− Programmable WatchDog Timer (WDT)

• CRC coprocessor

• Random number generator

• Clocks

− Crystal oscillator 27. 12 MHz

− Dedicated PLL 48 MHz for the USB

− Integrated HFO 20 MHz and LFO 380 kHz

• General

− HVQFN64 packaging

− Temperature range: - 40 °C to 85 °C

1.3 Derivates

1.3.1 PN7462AUEV features

Supports all PN7462AU features except ISO 7816 contact interface pins not exposed (AUX pins still available)

1.3.2 PN7362AU features

Supports all PN7462AU features except ISO 7816 interface

1.3.3 PN7360AU features

Supports all PN7462AU features except ISO 7816 interface and reduced flash size (80kB)

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Type Number Package

Name

Description

Version

PN7462AUHN

HVQFN64

160 kB memory; contact interface; ISO/ IEC 7816-3&4

leads; 64 terminals; body 9 × 9 × 0.85 mm

SOT804-4

PN7462AUEV

VFBGA64

160 kB memory; no contact interface; ISO/IEC

balls; 4.5 mm x 4.5 mm x 0.80 mm

SOT1307-2

PN7362AUHN

HVQFN64

160 kB memory; no contact interface; no ISO/IEC

leads; 64 terminals; body 9 × 9 × 0.85 mm

SOT804-4

PN7362AUEV

VFBGA64

160 kB memory; no contact interface; no ISO/IEC

balls; 4.5 mm x 4.5 mm x 0.80 mm

SOT1307-2

PN7360AUHN

HVQFN64

80 kB memory; no contact interface; no ISO/IEC

leads; 64 terminals; body 9 × 9 × 0.85 mm

SOT804-4

PN7360AUEV

VFBGA64

80 kB memory; no contact interface; no ISO/IEC

balls; 4.5 mm x 4.5 mm x 0.80 mm

SOT1307-2

1.4 Ordering information

Table 1. Ordering information

UART interface; plastic thermal enhanced very thin quad flat package; no

7816-3&4 UART interface; plastic very thin fine-pitch ball grid array package; 64

7816-3&4 UART interface; plastic thermal enhanced very thin quad flat package; no

7816-3&4 UART interface; plastic very thin fine-pitch ball grid array package; 64

7816-3&4 UART interface; plastic thermal enhanced very thin quad flat package; no

7816-3&4 UART interface; plastic very thin fine-pitch ball grid array package; 64

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Fig 1. Block diagram

1.5 Block diagram PN7462 HVQFN64

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Fig 2. Block diagram

1.6 Block diagram PN7462 VFBGA64

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Fig 3. Block diagram

1.7 Block diagram PN736X

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Fig 4. PN7462 family Memory map

2. PN7462 family memory

2.1 Memory mapping

The PN7462 family incorporates several distinct memory regions. Fig 4 shows the overall map of the entire address space from user program viewpoint following reset. The APB peripheral area is 512 K in size, and is divided to allow for up to 32 peripherals. Only peripheral from 0 to 15 are accessible, and each one is allocated 16 kB of space, in order to simplify the address decoding for each peripheral. The APB peripheral memory map is shown on the right side of

Fig 4.

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Fig 5. APB memory map

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Fig 6. Flash memory mapping

2.2 On-chip flash memory map

The PN7462 family contains 160 kB or 80 kB(PN7360) on-chip flash program memory. The flash can be programmed using In-System Programming (ISP) or In-Application Programming (IAP) via the on-chip boot-loader software.

The flash memory is divided into two instances of 80 kB, with each sector consisting of individual pages of 64 Bytes. The flash memory map is described in Fig 6

.

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Fig 7. EEPROM memory mapping

2.3 EEPROM memory map

The PN7462 family embeds 4 kB of on-chip EEPROM data memory. The EEPROM memory map is shown in Fig 7

.

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Fig 8. SRAM memory mapping

2.4 SRAM memory map

The PN7462 family contains a total of 12 kB on-chip static RAM memory. The SRAM memory map is presented in Fig 8

.

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Fig 9. Block diagram of EEPROM/FLASH controller module

3. EEPROM CTRL module

The EEPROM controller module controls the access to 4 kB EEPROM and 160 kB Onchip Flash memories. This comprises:

• Reading the content of an EEPROM or Flash word in response to a read-transfer coming from the CPU

• Writing a word (8 ,16 and 32-bit word length transfer allowed for EEPROM, only 32-bit allowed for flash) in page file upon a write-transfer coming from the CPU (Full page has to be written for flash)

• Programming the Flash, meaning copying the content of the page into the relevant EEPROM/flash

• Implementing security bits (at boot time the EEPROM first word is read. Part of those bits are controlling the Flash access and the CMB enabling. These bits are available in a register). Fig 9

shows the block diagram EEPROM/flash controller module

3.1 EEPROM/Flash controller features

• Three non-volatile memory ports: two for 80 x 2 kB of flash and one for a 4 kB of EEPROM

• 32-bit AHB-Lite slave interface with the CPU

• Read prefetching for flash memory to speed up reading from flash.

• Interrupt Request Device

• Register bank for control and status with user mode protection

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Address

Wait states FAST mode

Wait states SLOW mode

AHB

20 MHz Clock

AHB

20 MHz Clock

32-bit

5

250 ns

7

350 ns

8/16-bit

2

100 ns

3

150 ns

• 2.8 ms maximum to write a page on the EEPROM, with a max. power consumption of 2 mA

• 2.5 ms to write a page on the Flash in typical condition

• 1.03 ms to write a page on the Flash with maximum clock speed, with a max. power

consumption of 3 mA

• Test support Unit with CRC computation of the EEPROM and flash

content

3.2 AHB interface

AMBA 3 AHB Lite slave interface is implemented to connect the CPU to the EECTRL. The wait states are inserted with individual length for a read or write access.

3.3 Memory map

The memory map for the EECTRL module is divided into four parts:

• 0x0020_0000 - 0x0020_0FFF - EECTRL registers area

• 0x0020_1000 - 0x0020_1FFF - 4 kBytes DATA EEPROM Area

• 0x0020_2000 - 0x0020_2FFF - UNDEFINED area

• 0x0020_3000 - 0x0022_AFFF - 160 kBytes flash area

3.4 EEPROM controller

3.4.1 Write operation

Write operation cannot be handled within one AHB clock cycle, therefore wait states are inserted by the AHB Slave Interface during page register write phase. The following table gives an overview of minimum idle time for a write operation. The EEPROM controller programs the data page by page. A page register for write access is used to internally store the data in a quick way and then a programming cycle can start. The targeted EEPROM is 16-bit oriented so 32-bit write access need additional processing to combine two 16-bit access leading to additional wait states.

Table 2. Wait states for write access on EEPROM

width

The Write operation to the EEPROM has to be done in two steps:

1. Write the 64-Byte short term storage page register.

2. Program the page register in one row of the EEPROM matrix.

clock cycles

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Address Width

Wait states FAST mode

Wait states SLOW mode

AHB clock

20 MHz clock

AHB clock

20 MHz clock

32-bit

5

250 ns

7

350 ns

8/16-bit

2

100 ns

3

150 ns

Address Width

Wait states FAST mode

Wait states SLOW mode

AHB clock

ns (20 MHz clock)

AHB clock

ns (20 MHz clock)

32-bit access

2

100 3 150

3.4.2 Read operation

A read request cannot be handled within one AHB clock cycle, therefore wait states are inserted by the AHB Slave Interface. The targeted EEPROM is 16-bit oriented so 32-bit Read access need additional processing leading to additional wait states. Table 3 an overview of minimum idle time for a read operation.

Table 3. Wait states for read access on EEPROM

gives

cycles

3.5 Flash controller

The Flash is composed of two memory devices respectively controlled by one Flash controller integrated twice in the EECTRL module. The main difference to the EEPROM is a faster read access and a full-page program ming.

3.5.1 Write operation

Write Access is done only with 32-bit access. A write operation cannot be handled within one AHB clock cycle, therefore wait states are inserted by the AHB Slave Interface during page register write phase. The following table gives an overview of minimum idle time for a write operation. The Flash controllers program the Flash_0 and Flash_1 data page by page.

A page register for write access is used to internally store the data in a quick way and then a programming cycle is necessary to store the data.

Flash_0 stores data corresponding to «even» AHB addresses with bit [2] = ’0’ and Flash_1 stores data corresponding to «odd» AHB addresses with bit [2] = ’1’.

Table 4. Wait states for write access on EEPROM

cycles

A write operation to the Flash has to be done in two steps:

1. Write the 64-Byte short term storage page register.

2. Program the page register in one row of the Flash matrix.

3.5.2 Read Operation

Even if 32-bit, 16-bit and 8-bit Read Access are supported at system level, read access is only done with 32-bit accesses at memory level because the Flash is 32-bit oriented. The read access is similar as for the EEPROM.

The following table gives idle time with AHB wait states insertion for a read operation

cycles

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Address

Wait states FAST mode

Wait states SLOW mode

AHB

ns

AHB

ns

32- bit access

2

100 3 150

Name

Address

Width

Access

Reset value

Description

EE_CTRL

0000h

32

R/W

001F_0000h

EECTRL general control register

EE_DYN

0004h

32 W 0000_0000h

EECTRL dynamic control register

EE_STAT_DAT

0008h

32 R 0X00_0000h

EEPROM status register

EE_STAT_COD

000Ch

32 R 0000_0000h

FLASH status register

EE_CRC_DAT

0010h

32 R FFFF_FFFFh

EEPROM CRC value

EE_CRC_DAT_ADDR

0014h

32

R/W

0FFF_0000h

EEPROM CRC start/end EE_CRC_1_COD_INIT

0018h

32

R/W

FFFF_FFFFh

_1 CRC init value

EE_CRC_1_COD

001Ch

32 R FFFF_FFFFh

FLASH_1 CRC value

EE_CRC_1_COD_ADDR

0020h

32

R/W

4FFF_0000h

FLASH_1 CRC start/end address

EE_CRC_0_COD_INIT

0024h

32

R/W

FFFF_FFFFh

FLAH_0 CRC Init value

EE_CRC_0_COD

0028h

32 R FFFF_FFFFh

FLASH_0 CRC value

EE_CRC_0_COD_ADDR

002Ch

32

R/W

4FFF_0000h

FLASH_0 CRC start/end RESERVED

0030h

32

R/W

0000_0000h

Reserved

RESERVED

0034h

32

R/W

0000_0000h

Reserved

RESERVED

0038h

32

R/W

0000_0000h

Reserved

EE_TRIMM

003Ch

32

R/W

0000_0000h

EEPROM/PFLASH trimming RESERVED

0040h

32 R 6000_01ACh

Reserved

EE_ECC_PF_AHB_ERROR_ADD

0044h

32 R 0000_0000h

FLASH ECC Error address

Unused

0048h

32 - -

Unused EE_INT_CLR_ENABLE

0FD8h

32 W 0000_0000h

Interrupt CLR_ENABLE

EE_INT_SET_ENABLE

0FDCh

32 W 0000_0000h

Interrupt SET_ENABLE EE_INT_STATUS

0FE0h

32 R 0000_0000h

Interrupt STATUS commands

EE_INT_ENABLE

0FE4h

32 R 0000_0000h

Interrupt ENABLE commands

Table 5. Wait states for read access on EEPROM

Width

clock cycles

3.6 Register overview

Table 6. Clock generator register overview

offset

(bits)

(20 MHz Clock)

clock cycles

Addresses

FLASH

(20 MHz Clock)

R

Addresses

values

0FD4h

commands

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Name

Address

Width

Access

Reset value

Description

EE_INT_CLR_STATUS

0FE8h

32 W 0000_0000h

Interrupt CLR_STATUS

EE_INT_SET_STATUS

0FECh

32 W 0000_0000h

Interrupt SET_STATUS

Bit

Symbol

Access

Value

Description

31:16

RESERVED

- 0 Reserved

15

ECC_PF_AHB_ERROR_ENABLE

R/W

0

when ’1’ enables the AHB error

14

PFLASH_READ_PREFETCH_DI

R/W

0

When ’1’ disables read prefetching for the 13

BLOCK_1_COD

R/W

0

Block mode for FLASH_1

12

BNWSENS_1_COD

R/W

0

voltage drop sensor enable for FLASH_1

11

SKIPPRG_1_COD

R/W

0

skip program if erase fails for FLASH _1

10

STOP_1_COD

R/W

0

stop ramp-up at low power for FLASH_1

9

PFLASH_DOUT_SYNCHRO_DI

R/W

0

when ’0’ output PAGEFLASH data is

8

POWER_DOWN_1_COD

R/W

0

power down FLASH_1 block

7

BLOCK_0_COD

R/W

0

block mode for FLASH_0

6

BNWSENS_0_COD

R/W

0

voltage drop sensor enable for FLASH_0

5

SKIPPRG_0_COD

R/W

0

skip program if erase fails for FLASH _0

4

STOP_0_COD

R/W

0

stop ramp-up at low power for FLASH_0

3

FAST_COD

R/W

0

fast access for both FLASH_0 and

2

POWER_DOWN_0_COD

R/W

0

power down FLASH block

1

FAST_DAT

R/W

0

fast EEPROM data access

0

power_down_dat

R/W

0

power down EEPROM block

Bit

Symbol

Access

Value

Description

31:24

RESERVED

- 0 Reserved

offset

(bits)

3.7 Register description

Table 7. EE_CTRL (address offset 0x0000h)

S

commands

generation when FLASH read data cannot be corrected by the ECC mechanism and automatically set the FAST_COD bit to ’0’ to put the FLASH in slow mode.

Flash memories

S

Table 8. EE_DYN (address offset 0x0004h)

synchronized with the system clock to ensure that following ECC calculation is made on stable data. It is automatically set to ’1’ if FAST_COD = ’1’.

FLASH_1. It is automatically set to ’0’ if EE_CTRL.ECC_PF_AHB_ERROR_ENAB LE register is set to ’1’

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Bit

Symbol

Access

Value

Description

23

EE_RST_1_COD

W 0 resets the FLASH controller

22

CRC_CLEAR_1_COD

W 0 CRC clear function for FLASH

21

FULL_DUMP_READ_1_COD

W 0 performs a full or partial read of FLASH

20

PROG_1_COD

W 0 start programming data from the page 19

EE_RST_0_COD

W 0 resets the FLASH Controller

18

CRC_CLEAR_0_COD

W 0 CRC clear function for EFLASH

17

FULL_DUMP_READ_0_COD

W 0 performs a full or partial read of FLASH

16

PROG_0_COD

W

0

start programming data from the page 15:5

RESERVED

- 0 Reserved

4

RESERVED

W 0 always write 0

3

ee_rst_dat

W 0 resets the EEPROM Controller

2

crc_clear_dat

W 0 CRC Clear Function for the EEPROM

1

full_dump_read_dat

W 0 performs a full or partial read of the

0

prog_dat

W

0

start programming data from the page

Bit

Symbol

Access

Value

Description

31:23

RESERVED

- 0 Reserved

22

ALL1_DAT

R 0 Single Fault Injection (SFI) detection flag

21

ALL0_DAT

R 0 Single Fault Injection (SFI) detection flag 20

BNWDROP_DAT

R 0 BNW sensor signal for the EEPROM

19

TMANALOG_DAT

R

0

analog test mode active, analog level at

18:3

ee_edo_dat

R

0

EDO parity lines for EEPROM

2

readout_ongoing_dat

R 0 full or partial dump readout ongoing for

1

prog_dat

R

0

indicator if programming is ongoing for the

with CRC Calculation

register for FLASH_1

with CRC calculation

register for FLASH_0

Table 9. EE_STAT_DAT (address offset 0x0008h)

EEPROM with CRC calculation

register for the EEPROM

for the EEPROM

analog IO for the EEPROM

EE_EDO_DAT[15:12]: parity bits corresponding to data[31:24] EE_EDO_DAT[11:8]: parity bits corresponding to data[23:16] EE_EDO_DAT[7:4]: parity bits corresponding to data[15:8] EE_EDO_DAT[3:0]: parity bits corresponding to data[7:0]

the EEPROM

EEPROM

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Bit

Symbol

Access

Value

Description

0

hverr_dat

R 0 HV error signal for the EEPROM

Bit

Symbol

Access

Value

Description

31:26

RESERVED

- 0 Reserved

25

ECC_READ_INVALID_1_COD

R 0 1 means that read access can’t be

24

ECC_READ_CORRECT_1_CO

R 1 0 means that there is at least one bit-

23:18

EE_EDO_1_COD

R

X

EDO parity lines of the FLASH_1 32-bit

17

readout_ongoing_1_COD

R 0 full or partial dump readout ongoing for 16

DROPSENS_1_COD

R 0 drop sensor output signal for FLASH_1

15

VMPOK_1_COD

R 0 margin voltage flag for FLASH_1

14

prog_1_COD

R 0 indicator if programming is ongoing for the 13

hverr_1_COD

R 0 HV error signal for the FLASH_1

12

ECC_READ_INVALID_0_COD

R 0 1 means that read access can’t be

11

ECC_READ_CORRECT_0_CO

R 1 0 means that there is at least one bit-

10:5

EE_EDO_0_COD

R

X

EDO parity lines of the FLASH_0 32-bit

4

readout_ongoing_0_COD

R 0 full or partial dump readout ongoing for 3

DROPSENS_0_COD

R 0 drop sensor output signal for FLASH_0

2

VMPOK_0_COD

R 0 margin voltage flag for FLASH_0

1

prog_0_COD

R 0 indicator if programming is ongoing for the 0

hverr_0_COD

R 0 HV error signal for the FLASH_0

Bit

Symbol

Access

Value

Description

31:0

ee_crc_DAT

R

FFFFh

EEPROM CRC value

Bit

Symbol

Access

Value

Description

31:28

RESERVED

- 0 Reserved

Table 10. EE_STAT_COD (address offset 0x000Ch)

corrected, there is more than one bit-error

D

error, check the ECC_READ_INVALID_1_COD to confirm if it has been corrected or not 1 means that no bit error occurred

data

the entire FLASH_1

FLASH_1

corrected, there is more than one bit-error

error, check the ECC_READ_INVALID_0_COD to confirm if it has been corrected or not 1 means that no bit error occurred

data

Table 11. EE_CRC_DAT (address offset 0x0010h)

Table 12. EE_CRC_DAT_ADDR (address offset 0x0014h)

the entire FLASH_0

FLASH_0

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Bit

Symbol

Access

Value

Description

27:16

ee_CRC_DAT_ADDR_END

R/W

7FFh

EEPROM CRC calculation end address 15:12

RESERVED

- 0 Reserved

11:0

ee_CRC_DAT_ADDR_START

R/W

000h

EEPROM CRC calculation start address

Bit

Symbol

Access

Value

Description

31:0

ee_crc_1_COD_INIT

R/W

FFFFh

FLASH_1 CRC Init Value loaded as soon

Bit

Symbol

Access

Value

Description

31:0

ee_crc_1_COD

R

FFFFh

FLASH_1 CRC value

Bit

Symbol

Access

Value

Description

31:16

ee_CRC_1_COD_ADDR_END

R/W

4FFFh

FLASH_1 CRC calculation end address

15:0

ee_CRC_1_COD_ADDR_START

R/W

0000h

FLASH_1 CRC calculation start address

Bit

Symbol

Access

Value

Description

Bit

Symbol

Access

Value

Description

corresponding to a native 16-bit data access (AHB memory map divided by 2)

Table 13. EE_CRC_1_COD_INIT (address offset 0x0018h)

as CRC_CLEAR_1_COD is high, meaning that FLASH_1 CRC must be set before CRC_CLEAR_1_COD.

Table 14. EE_CRC_1_COD (address offset 0x001Ch)

Table 15. EE_CRC_1_COD_ADDR (address offset 0x0020h)

corresponding to a native 32-bit data access (AHB Memory Map divided by 8)

corresponding to a native 32-bit data access (AHB memory map divided by 8)

Table 16. EE_CRC_0_COD_INIT (address offset 0x0024h)

31:0 ee_crc_0_COD_INIT R/W FFFFh FLASH_0 CRC Init value loaded as soon

as CRC_CLEAR_0_COD is high, meaning that FLASH_0 CRC must be set before CRC_CLEAR_0_COD.

Table 17. EE_CRC_0_COD (address offset 0x0028h)

31:0 ee_crc_0_COD R FFFFh FLASH_0 CRC value

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Bit

Symbol

Access

Value

Description

Bit

Symbol

Access

Value

Description

31:16

ee_CRC_0_COD_ADDR_END

R/W

4FFFh

FLASH_0 CRC calculation end address

15:0

ee_CRC_0_COD_ADDR_START

R/W

0000h

FLASH_0 CRC calculation start address

Bit

Symbol

Access

Value

Description

31:24

RESERVED

- 0 Reserved

23:20

hvtrimw_1_COD

R/W

0

HV trimming value program for the 19:16

hvtrime_1_COD

R/W

0

HV trimming value Erase for the FLASH_1

15:12

hvtrimw_0_COD

R/W

0

HV trimming value Program for the 11:8

hvtrime_0_COD

R/W

0

HV trimming value Erase for the FLASH_0

7:4

hvtrimw_dat

R/W

0

HV trimming value Program for the 3:0

hvtrime_dat

R/W

0

HV trimming value Erase for the EEPROM

Bit

Symbol

Access

Value

Description

31:18

RESERVED

- 0 Reserved

17:0

ECC_PF_AHB_ERROR_ADDR

R

0

AHB address for which a flash read data

Bit

Symbol

Access

Value

Description

31:10

RESERVED

- 0 Reserved

9

EE_ECC_READ_NOT_CORRE

W 0 FLASH_1 not correct ECC read interrupt

8

EE_ECC_READ_INVALID_1_C

W

0

FLASH_1 Invalid ECC Read interrupt

Table 18. EE_CRC_0_COD_ADDR (address offset 0x002Ch)

31:16 ee_CRC_0_COD_ADDR_END R/W 4FFFh FLASH_ 0 CRC calculation end address

corresponding to a native 32-bit data access (AHB memory map divided by 8)

15:0 ee_CRC_0_COD_ADDR_START R/W 0000h FLASH_0 CRC Calculation start address

corresponding to a native 32-bit data access (AHB memory map divided by 8)

Table 19. EE_CRC_0_COD_ADDR (address offset 0x002Ch)

corresponding to a native 32-bit data access (AHB memory map divided by 8)

Table 20. EE_TRIMM (address offset 0x003Ch)

FLASH_1

FLASH_0

EEPROM

Table 21. EE_ECC_PF_AHB_ERROR_ADDR (address offset 0x0044h)

was detected as invalid or corrected by the ECC module.

Table 22. EE_INT_CLR_ENABLE (address offset 0x0FD8h)

CT_1_COD_INT_CLR_ENABLE

OD_INT_CLR_ENABLE

clear enable command

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Bit

Symbol

Access

Value

Description

7

EE_ECC_READ_NOT_CORRE

W 0 FLASH_0 Not Correct ECC Read interrupt

6

EE_ECC_READ_INVALID_0_C

W

0

FLASH_0 Invalid ECC Read interrupt

5

ee_hverr_1_cod_int_clr_enable

W 0 FLASH_1 High Voltage Error interrupt

4

ee_hverr_0_cod_int_clr_enable

W 0 FLASH_0 High Voltage Error interrupt

3

ee_hverr_dat_int_clr_enable

W

0

EEPROM High Voltage Error interrupt

2

ee_prog_1_cod_completed_int_c

W 0 FLASH_1 Programming Completed

1

ee_prog_0_cod_completed_int_c

W 0 FLASH_0 Programming Completed

0

ee_prog_dat_completed_int_clr_

W

0

EEPROM Programming Completed

Bit

Symbol

Access

Value

Description

31:10

Reserved

- 0 Reserved

9

EE_ECC_READ_NOT_CORRE

W 0 FLASH_1 not correct ECC read interrupt

8

EE_ECC_READ_INVALID_1_C

W 0 FLASH_1 Invalid ECC read interr upt set

7

EE_ECC_READ_NOT_CORRE

W

0

FLASH_0 not correct ECC read interrupt

6

EE_ECC_READ_INVALID_0_C

W 0 FLASH_0 invalid ECC read interrupt set

5

ee_hverr_1_cod_int_SET_enabl

W 0 FLASH_1 high voltage error interrupt set

4

ee_hverr_0_cod_int_SET_enabl

W

0

FLASH_0 high voltage error interrupt set

3

ee_hverr_dat_int_SET_enable

W 0 EEPROM high voltage error interrupt set

2

ee_prog_1_cod_completed_int_

W 0 FLASH_1 programming compl eted

1

ee_prog_0_cod_completed_int_

W

0

FLASH_0 programming compl eted

0

ee_prog_dat_completed_int_SE

W 0 EEPROM programming completed

Bit

Symbol

Access

Value

Description

31:10

Reserved

- 0 Reserved

CT_0_COD_INT_CLR_ENABLE

OD_INT_CLR_ENABLE

lr_enable

enable

Table 23. EE_INT_SET_ENABLE (address offset 0x0FDCh)

CT_1_COD_INT_SET_ENABLE

OD_INT_SET_ENABLE

clear enable command

interrupt clear enable comma nd

interrupt clear enable command

set enable command

enable command

CT_0_COD_INT_SET_ENABLE

OD_INT_SET_ENABLE

e

SET_enable

T_enable

Table 24. EE_INT_STATUS (address offset 0x0FE0h)

set enable command

enable command

interrupt set enable command

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Bit

Symbol

Access

Value

Description

9

EE_ECC_READ_NOT_CORRE

R 0 FLASH_1 not correct ECC read interrupt

8

EE_ECC_READ_INVALID_1_C

R

0

FLASH_1 Invalid ECC read interrupt

7

EE_ECC_READ_NOT_CORRE

R 0 FLASH_0 not correct ECC read interrupt

6

EE_ECC_READ_INVALID_0_C

R 0 FLASH_0 Invalid ECC read interrupt

5

ee_hverr_1_cod_int_STATUS

R

0

FLASH_1 high voltage error interrupt

4

ee_hverr_0_cod_int_STATUS

R 0 PFLASH_0 high voltage error interrupt

3

ee_hverr_dat_int_STATUS

R 0 EEPROM high voltage error interrupt

2

ee_prog_1_cod_completed_int_

R

0

FLASH_1 programming completed

1

ee_prog_0_cod_completed_int_

R 0 FLASH_0 programming completed

0

ee_prog_dat_completed_int_ST

R 0 EEPROM programming completed

Bit

Symbol

Access

Value

Description

31:10

RESERVED

- 0 Reserved

9

EE_ECC_READ_NOT_CORRE

R 0 FLASH_1 not correct ECC read interrupt

8

EE_ECC_READ_INVALID_1_C

R 0 FLASH_1 Invalid ECC read interrupt

7

EE_ECC_READ_NOT_CORRE

R

0

FLASH_0 Not Correct ECC read interrupt

6

EE_ECC_READ_INVALID_0_C

R 0 FLASH_0 invalid ECC read int err upt

5

ee_hverr_1_cod_int_SENABLE

R 0 FLASH_1 high voltage error interrupt

4

ee_hverr_0_cod_int_ENABLE

R

0

PFLASH_0 high voltage error interrupt

3

ee_hverr_dat_int_ENABLE

R 0 EEPROM high voltage error interrupt

2

ee_prog_1_cod_completed_int_

R 0 FLASH_1 programming completed

1

ee_prog_0_cod_completed_int_

R

0

FLASH_0 programming completed

0

ee_prog_dat_completed_int_EN

R 0 EEPROM programming completed

CT_1_COD_INT_STATUS

OD_INT_STATUS

CT_0_COD_INT_STATUS

OD_INT_STATUS

STATUS

ATUS

Table 25. EE_INT_ENABLE (address offset 0x0FE4h)

status variable

interrupt status variable

CT_1_COD_INT_ENABLE

OD_INT_ENABLE

CT_0_COD_INT_ENABLE

OD_INT_ENABLE

ENABLE

ABLE

enable variable

Interrupt Enable Variable

interrupt enable variable

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Bit

Symbol

Access

Value

Description

31:10

RESERVED

- 0 Reserved

9

EE_ECC_READ_NOT_CORRE

W

0

FLASH_1 not correct ECC read interrupt

8

EE_ECC_READ_INVALID_1_C

W 0 FLASH_1 Invalid ECC re ad int err upt cle ar

7

EE_ECC_READ_NOT_CORRE

W 0 FLASH_0 Not Correct ECC read interrupt

6

EE_ECC_READ_INVALID_0_C

W

0

FLASH_0 Invalid ECC read interrupt clear

5

ee_hverr_1_cod_int_CLR_STAT

W 0 FLASH_1 high voltage error interrupt clear

4

ee_hverr_0_cod_int_CLR_STAT

W 0 FLASH_0 high voltage error interrupt clear

3

ee_hverr_dat_int_CLR_STATUS

W

0

EEPROM high voltage error interrupt clear

2

ee_prog_1_cod_completed_int_

W 0 FLASH_1 programming compl eted

1

ee_prog_0_cod_completed_int_

W 0 FLASH_0 programming compl eted

0

ee_prog_dat_completed_int_CL

W

0

EEPROM programming completed

Bit

Symbol

Access

Value

Description

31:10

Reserved

- 0 Reserved

9

EE_ECC_READ_NOT_CORRE

W 0 FLASH_1 not correct ECC read interrupt

8

EE_ECC_READ_INVALID_1_C

W 0 PFLASH_1 Invalid ECC read interrupt set

7

EE_ECC_READ_NOT_CORRE

W

0

FLASH_0 not correct ECC read interrupt

6

EE_ECC_READ_INVALID_0_C

W 0 FLASH_0 invalid ECC read interrupt set

5

ee_hverr_1_cod_int_SET_STAT

W 0 FLASH_1 high voltage error in terrupt set

4

ee_hverr_0_cod_int_SET_STAT

W

0

PFLASH_0 high voltage error interrupt set

3

ee_hverr_dat_int_SET_STATUS

W 0 EEPROM high voltage error interrupt set

2

ee_prog_1_cod_completed_int_

W 0 FLASH_1 programming compl eted

1

ee_prog_0_cod_completed_int_

W

0

FLASH_0 programming compl eted

Table 26. EE_INT_CLR_STATUS (address offset 0x0FE8h)

CT_1_COD_INT_CLR_STATUS

OD_INT_CLR_STATUS

CT_0_COD_INT_CLR_STATUS

OD_INT_CLR_STATUS

US

CLR_STATUS

R_STATUS

Table 27. EE_INT_SET_STATUS (address offset 0x0FECh)

clear status command

status command

clear status command

status command

interrupt clear status command

CT_1_COD_INT_SET_STATUS

OD_INT_SET_STATUS

CT_0_COD_INT_SET_STATUS

OD_INT_SET_STATUS

US

SET_STATUS

set status command

status command

set status command

status command

interrupt set status command

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Bit

Symbol

Access

Value

Description

0

ee_prog_dat_completed_int_SE

W 0 EEPROM programming completed

EIRQ#

Source

Description

0

Timer 0/1/2/3

general-purpose timer 0/1/2/3 interrupt

1 - Reserved

2

CLIF

contactless interface module int errup t

3

EECTRL

EEPROM controller

4 - Reserved

5 - Reserved

6

Host IF

TX or RX buffer from I2C, SPI, HSU, or USB module

7

Contact IF

ISO7816 contact module interr upt

8 - Reserved

9

PMU/ TXLDO

power management unit (temperature sensor, TXLDO overcurrent detection, overload, VBUS level)

10

SPIMaster

TX or RX buffer from SPI master module

11

I2CMaster

TX or RX buffer from I2C master module

12

PCR

high temperature from temperature sensor 0 and 1,

configured as inputs.

13

PCR

interrupt common GPIO 1 to 12

T_STATUS

4. Nested Vectored Inter rupt Controller (NVIC)

4.1 NVIC features

4.2 Interrupt sources

interrupt set status command

The NVIC is an integral part of the Cortex-M0. The tight coupling to the CPU allows for a low interrupt latency and efficient processing of late arriving interrupts. The NVIC controls system exceptions and peripheral interrupts. Its control registers are accessible as memory-mapped devices.

• Controls system exceptions and peripheral interrupts

•

Supports 32 vectored interrupts

• Four interrupt priority levels, with hardware priority level masking

• Non-mask able interrupt (NMI) connected to the watchdog interrupt.

• Software interrupt generation

The following table lists the interrupt sources available in the PN7462 family microcontroller

Table 28. External interrupt sources

interrupt to CPU from PCR to indicate wakeup from suspend mode, out of standby, out of suspend, event on GPIO’s

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EIRQ#

Source

Description

14

PCR

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

15

PCR

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

16

PCR

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

17

PCR

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

18

PCR

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

19

PCR

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

20

PCR

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

21

PCR

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

22

PCR

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

23

PCR

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

24

PCR

interrupt (rise/fall/both-edge/level-high/level-low interrupt as

25

PCR

interrupt (rise/fall/both-edge/level-high/level-low interrupt as 26 - Reserved

27 - Reserved

28 - Reserved

29 - Reserved

30 - Reserved

31 - Reserved

NMI

WDT

the watchdog Interrupt is connected on the non-maskable

programmed) GPIO 1

programmed) GPIO 2

programmed) GPIO 3

programmed) GPIO 4

programmed) GPIO 5

programmed) GPIO 6

programmed) GPIO 7

programmed) GPIO 8

programmed) GPIO 9

programmed) GPIO 10

programmed) GPIO 11

programmed) GPIO 12

interrupt

4.3 NVIC register support in the SCS

The system control region includes status and configuration registers that apply to the NVIC as part of the general exception model.

All other external interrupt specific registers reside within the NVIC region of the SCS.

Table 29 summarizes the NVIC specific registers in the SCS. T able 30

NVIC_IPR bit assignments. In the table, N = 4n, where n is the NVIC_IPR register number. For example, for NVIC_IPR2, n is 2 and N is 8.

For more details, refer to DDI0419C_arm_architecture_v6m_reference_manual which can be found on the ARM webpage.

shows the

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Address

Name

Type

Reset

Description

0xE000E100

NVIC_ISER

RW

0x00000000

enables, or reads the enabled state of one or more interrupts

0xE000E104-

Reserved

0xE000E180

NVIC_ICER

RW

0x00000000

disables, or reads the enabled state

0xE000E184-

Reserved

0xE000E200

NVIC_ISPR

RW

0x00000000

on writes, sets the status of one or more interrupts to pending. On reads,

0xE000E204-

Reserved

0xE000E280

NVIC_ICPR

RW

0x00000000

On writes, clears the status of one or more interrupts to pending. On reads,

0xE000E300-

Reserved

0xE000E400-

NVIC_IPRn

RW

0x00000000

sets or reads interrupt priorities

0xE000E420-

Reserved

Bits

Name

Function

[31:30]

PRI_N3

enables, or reads the enabled state of one or more interrupts

[29:24]

-

Reserved

[23:22]

PRI_N2

disables, or reads the enabled state of one or more interrupts

[21:16]

-

Reserved

[15:14]

PRI_N1

on writes, sets the status of one or more interrupts to pending. On reads, [13:8]

-

Reserved

[7:6]

PRI_N0

on writes, clears the status of one or more interrupts to pending. On [5:0]

-

Reserved

Table 29. NVIC register overview

0xE000E17F

0xE000E1FF

0xE000E27F

of one or more interrupts

shows the pending status of the interrupts.

0xE000E3FC

0xE000E41C

0xE000E43C

Table 30. NVIC_IPRn bit assignments

shows the pending status of the interrupts.

reads, shows the pending status of the interrupts.

shows the pending status of the interrupts.

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Pin Number

Pin Name

Comment

14

SWDCLK

SWD clock

15

SWDIO

SWD I/O

Address

Name

Type

Reset

Description

0xE000E010

SYST_CSR

RW

0x000 0000

System Timer Control and status register

0xE000E014

SYST_RVR

RW 0 System Timer Reload value register

0xE000E018

SYST_CVR

RW 0 System Timer Current value register

4.4 SWD

Cortex-M0 processor-based devices use the Serial Wire ARM CoreSight™ debug technology. The Serial Wire Debug (SWD) signals are connected to the pads via the PCR (Power, Clock & Reset) described in Section 0 in order to have code (or data) read/write access protection.

4.4.1 SWD features

• Run Control of the processor allowing to start and stop programs

• Single Step one source or assembler line

• Set breakpoints while the processor is running

• Write memory contents and peripheral registers on-the-fly

• “Printf” like debug messages through the SWD.

4.4.2 SWD limitations

The PN7462 family does not allow breakpoint or single step debugging of ROM service APIs and boot code. Breakpoint or single step debugging of ROM service APIs and Boot

code results into System reset.

. The SWD interface can be disabled

Breakpoint and single step debugging is only allowed in the customer Application area.

4.4.3 Hardware connection of SWD

For using SWD it is recommended to connect an external pull-up from SWDCLK and SWDIO to PVDD_IN supply (see Table 31

Table 31. SWD pinning

5. SysTick Timer (SysTick)

The SysTick timer is a 24-bit timer that counts down to zero and ge nerates an int err upt. The SysTick timer is clocked from the system clock or from the reference clock, which is fixed to half the frequency of the system clock. In order to generate recurring interrupts at a specific interval, the SYST_RVR register must be initialized with the correct value for the desired interval. A default value is provided in the SYST_CALIB register and may be changed by software.

Table 32. SysTick timer (base address 0xE000 E000)

).

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Address

Name

Type

Reset

Description

0xE000E1C

SYST_CALIB

RW

0x4

System Timer Calibration value

register

For more details, refer to DDI0419C_arm_architecture_v6m_reference_manual which can be found on the ARM webpage.

Example timer calculation

To use the system tick timer, do the following:

a. Program the SYST_RVR register with the reload value RELOAD to

obtain the desired time interval.

b. Clear the SYST_CVR register by writing to it. This ensures that the timer

will count from the SYST_RVR value rather than an arbitrary value when the timer is enabled.

c. Program the SYST_SCR register with the value 0x7 which enables the

SysTick timer and the SysTick timer interrupt.

The following example illustrates selecting the SysTick timer reload value to obtain a 10 ms time interval with the system clock set to 20 MHz.

Example (system clock = 20 MHz) The system tick clock = system clock = 20 MHz. Bit CLKSOURCE in the SYST_CSR

register set to 1 (system clock). RELOAD = (system tick clock frequency * 10 ms) -1 = (20 MHz * 10 ms) -1 = 200000-1=

199999 = 0x00030D3F.

6. PN7462 family Power management

6.1 Power supply

The PN7462 family is using following supply voltages:

• VBUS: Main supply voltage for internal analog modules, digital logic and memories

• VBUSP: Supply voltage for the contact interface

• TVDD_IN: Supply voltage for the contactless interface

• PVDD_IN: Pad voltage reference and supply voltage for the host interfaces (HSUART,

USB, I2C and SPI) and the GPIOs

• PVDD_M_IN: Pad voltage reference and supply voltage for the master interfaces (SPI, I2C)

• DVDD: Supply voltage for the internal digital blocks

• VUP_TX: External supply voltage for the transmitter LDO (TXLDO)

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6.1.1 Microcontroller supply

In order to use the PN7462 family as microcontroller with host interface following voltages (minimum requirements) need to be supplied:

• VBUS

• PVDD_IN (if PVDD_OUT is not used, it needs to be shorted to GND)

• DVDD pin must be connected to VDD and buffered with 1 µF capacitor to GND

The SPI/ I²C master interface requires additional supply:

• PVDD_M_IN

shows the power supply of the chip (VBUS), including the supply of the digital

Fig 10

blocks (DVDD). The host interface pads are supplied using PVDD_IN and master interface pads are supplied using PVDD_M_IN. The pads can be supplied using an internal LDO, or using an external supply. The internal LDO requires that VBUS > 4 V. When PVDD_LDO is used, the maximum total current available from PVDD_OUT for the pads supply is 30 mA.

When an external source is used for PVDD_IN and PVDD_IN_M, PVDD_OUT must be connected to the ground with a ground resistance of less than 10 Ω.

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Remark: The capacitance must be chosen so that the capacitance value is correct 5 V.

Fig 10. Powering the PN7462 family microcontroller

VDD

DVDD

(1)

(

2)

1 µF

VBUSP

aaa-025630

VBUS

GND

TVSS

GNDC

GNDP

V

DDP(VBUS)

,

I

DDP(VBUS)

1 µF

PVDD_OUT

PVDD_IN PVDD_M_IN

1 µF

VBUS

V

DDP(VBUS)

,

I

DDP

(VBUS)

1 µF

(3)

PVDD_OUT

PVDD_IN PVDD_M_IN

VBUS

V

DDP(VBUS)

,

I

DDP(VBUS)

external supply

1 µF

PN7462 family

PN7462 familyPN7462 family

VBUSP

(1) Powering the microcontroller and the digital blocks (DVDD) (2) (3) 2 possibilities for powering the pad interfaces (PVDD_I N and PVDD_M_IN)

6.1.2 Contactless reader supply

In order to use the PN7462 family as contactless reader the following voltages need to be supplied:

• VBUS

• PVDD_IN (if PVDD_OUT is not used, it needs to be shorted to GND)

• TVDD_IN (If supplied by TVDD_OUT, VUP_TX needs to be supplied)

• DVDD pin must be connected to VDD and buffered with 1µF capacitor to GND

For SPI/ I²C master following supply is also needed:

• PVDD_M_IN The contactless interface is powered through TVDD_IN. This pin can be supplied either

externally or by using TVDD_OUT.

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The capacitance value must be chosen so that the capacitance value is correct at 5 V

Fig 11. Powering the contactless interface – using a single power supply

TVDD_OUT

TVDD_IN

(1)

TX2 TX1

TVSS

6.8 µF

antenna

supply

aaa-021 143

TVDD_OUT

VUP_TX

VBUS

VUP_TX

TVDD_IN

(2)

TX2 TX1

TVSS

6.8 µF

VBUS

PN7462 family

supply

antenna

supply

470 nF

PN7462 family

supply

470 nF

PN7462 family PN7462 family

In case TVDD_OUT is used

• VUP_TX needs to be supplied.

Remark: The TVDD_OUT pin must not be left floating, and needs to be at the same voltage as the TVDD_IN pin.

(1) Using the PN7462 family´s TXLDO (2) Without using PN7462 family´s TXLDO

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The capacitance value must be chosen so that the capacitance value is correct at 5 V

Fig 12. Powering the contactless interface – using an external RF transmitter supply

PN7462 family

RF transmitter supply

TVDD_OUT

VUP_TX

TVDD_IN

(1)

TX2 TX1

TVSS

6.8 µF

VBUS

PN7462 family

supply

antenna

supply

470 nF

1 µF

aaa

-021 144

PN

7462 family

RF transmitter supply

TVDD_OUT

VUP_TX

TVDD_IN

(2)

TX2 TX1

TVSS

6.8 µF

VBUS

PN7462 family

supply

antenna

supply

470 nF

PN7462 family

(1) Using the PN7462 family´s TXLDO (2) Without using PN7462 family´s TXLDO

6.1.3 Contact reader supply

In order to use the contact reader functionality of the PN7462 family, following pads need to be supplied:

• VBUS

• PVDD_IN (if PVDD_OUT is not used needs to be shorted to GND)

• VBUSP

• DVDD pin must be connected to VDD and buffered with 1 µF capacitor to GND

For SPI/ I²C master interface following supply is also needed

• PVDD_M_IN

The contact interface is powered through VBUSP which is connected to VBUS, as shown on the schematic in Fig 13

The various ISO 7816 contact card classes (A, B, or C) require different voltages:

• VBUSP > 2.7 V: support of class B and class C contact cards

• VBUSP > 3 V: support of class A contact cards

.

Remark: To support Class A cards, DC-to-DC converter has to be used. To support Class B cards with VB USP < 3.9 V, DC-to-DC converter also has to be used. The

13.shows how to connect the contact interface related pins, when no contact interface is

used.

Fig

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Fig 13. Powering the contact interface

Fig 14. Contact interface power supply connection when the contact interface is not used

aaa-021 145

SCVDD

VBUSP

VBUS

V

DDP(VBUS

)

,

I

DDP(VBUS)

GDNP

SAM

SAP

VUP

VCC

GNDC

470 nF

1 µF

470 nF

100 nF

(1)

2.7 µF

PN7462

aaa-021 146

SCVDD

VBUSP

1 µF

VBUS

connections when CTinterface

is not used

V

DDP(VBUS)

,

I

DDP(VBUS)

n.c.

GDNP

SAM

n.c.

n

.c.

SAP

VUP

VCC

GNDC

PN7462

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Fig 15. PMU Module, LDOs and power pins overview

Pin No

Pin Name

IN(I)/Out(O)

Connection

Comment

10

PVDD_IN

I

externally

pad supply for host

aaa-029420

VBUSP VCC

VUP

VBUS

VUP_TX

VDD

PVDD_OUT

TVDD_OUT

TVDD

_IN

PVDD_IN PVDD_M_IN

DVDD

DCDC

MLDO

VCC_LDOSC_LDO

PVDD_LDO

TX

_LDO

internal analog blocks

mandatory

optional

recommende

d

digital logic and memories

pad supply

master interface pads

RF transmitter

6.2 Power Management Uni t

The Integrated Power Management Unit (PMU) supplies internal analog modules, internal digital logic, memories and pads. It also provides regulated voltages for the contactless and the contact interfaces. The PMU automatically adjusts the internal regulators to minimize the power consumption during all possible power modes. The power management unit embeds also mechanisms to prevent the IC from overheat, current overconsumption and overloading the DC-to-DC converter. For the RF transmitter stage, a separated low-drop output regulator is embedded. This module also integrates a temperature sensor and Power On Reset generator. The PMU is made of analog modules and digital control unit embedding the registers

Table 33. Voltage and Supply pins connection overview

powered or PVDD_OUT

interfaces (1.8 V or 3.3 V)

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Pin No

Pin Name

IN(I)/Out(O)

Connection

Comment

11

DVDD

I

connected to

30

VMID

O

blocking

recommended 100nF

34

TVDD_IN

I

externally

37

TVDD_OUT

O

can be set in REG

38

VUP_TX

I

externally 39

VDD

O 1.8 V output for DVDD

43

VBUS

I

Externally

44

PVDD_OUT

O 3.3V output; If connected to 46

SAM

I/O

470 nF to

47

SCVDD

O

blocking

Recommended 1 µF 48

VBUSP

I

connected to

Input for contact interface

49

SAP

I/O

470 nF to

50

VUP

O

blocking

Recommended 4,7µF 51

VCC

O

contact card

55

USB_VBUS

I USB detection; If pulled

59

PVDD_M_IN

I

externally

Pad supply for master

VDD

capacitor to GND

powered or TVDD_OUT

PMU_TXLDO_CONTROL_

powered or VBUS

powered

SAP

capacitor to GND

VBUS

SAM

capacitor to GND

supply

powered or PVDD_OUT

GND, PVDD_IN is externally supplied

high USB is connected

interfaces (1.8V or 3.3V)

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Fig 16. PN7462 family basic schematic

6.2.1 Low Drop-Out regulators

The PMU embeds several Low Drop-Out regulators (LDO) in order to ensure the stability of the power supply.

6.2.1.1 Main LDO

The Main LDO (MLDO) provides 1.8 V for all internal analog, digital and memory modules. It draws its power from VBUS. It includes a current limiter to prevent damage of output transistors. The output supply is available on the VDD pin, which must be connected externally to the DVDD pin.

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6.2.1.2 PVDD_LDO

The PVDD_LDO provides 3.3 V for all digital pads. It is supplied by VBUS, and requires a minimum voltage of 4 V to be functional. It delivers a maximum current of 30 mA. The output of the PVDD_LDO is PVDD_OUT pin. This LDO is used to provide the necessary supply to PVDD_IN (pad supply for host interface) and PVDD_M_IN (pad supply for master interfaces). When an external power supply is used, the PVDD_OUT must be connected to the ground. The ROM boot detects automatically that the LDO output is connected to the ground, and switches it off. The PVDD LDO has a low power mode, which is used automatically by the PN7462 family when the chip is in Stand-by mode or Suspend mode. This enables to supply host pads and GPIOs, and to detect wake-up signals coming from these interfaces.

6.2.1.3 TXLDO Transmitter supply

The PN7462 family integrates an internal transmitter LDO. The TXLDO can be used to maintain a constant output voltage for the RF interface. The TXLDO is designed to protect the chip from voltage ripple introduced by the power supply on the VUP_TX pin. It is powered through VUP_TX pin. The programmable output voltages are: 3.0 V, 3.3 V,

3.6 V, 4.5 V, and 4.75 V. For a given output voltage, VUP_TX shall alwa ys be 0.3V

higher (i.e. to supply a 3 V output, the minimum voltage to be applied on VUP_TX is

3.3 V). If the voltage is no sufficient, then TVDD_OUT follows VUP_TX, lowered of 0.3 V.

When it is not used, TVDD_OUT shall be connected to TVDD_IN, and TX_LDO shall be turned off. The TXLDO can be used in one of the following power modes

• Full power mode

• Low power mode

• Low power 2 mode

• Shutdown mode

• Standby mode

For corresponding register settings, please refer to Section 6.7.2

6.2.1.4 VCC LDO

The VCC LDO provides contact interface supply VCC.

6.2.1.5 SCLDO

The SCLDO provides a regulated voltage to the DC-to-DC converter, to enable class B operation when 2.7 < VBUS < 3.9 V and class A operation.

6.2.1.6 DC-to-DC converter

The PN7462 family includes a DC-to-DC converter, in order to support Class A and Class B cards, when the input voltage VBUSP is not sufficient. The DC-to-DC converter is a switched capac it anc e volta ge converter. It takes its power from the SCLDO. The DCto-DC converter can be bypassed. Its output (VUP) is regulated from 3.3 to 5.5 V.

.

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LDO

Max Startup Time

PVDDLDO

1.5 ms

TXLDO

200 µs

VCC LDO

22 ms (including DC-to-DC converter, SCLDO and VCCLDO startup times) 500 µs (excluding DC-to-DC and SCLDO)

Fig 17. Block diagram of PMU

6.2.1.7 Start-up times of LDOs

Table 34. Start-up times of LDOs

6.3 PN7462 family PMU digital control unit

The PMU digital control unit of the PN7462 family is used in the system as the gateway to configure all modes of supply for the product using the control registers. Note that additional registers related to PMU control are located in the power clock and reset (PCR) Unit for they need to be always powered up. The PMU digital control unit consists of the AMBA 3.0 APB interface and the associated register bank to drive the analog part of PMU, plus additional glue logic related to controlling the temperature, overcurrent, pad voltage, interrupts and calibration of temperature sensors.

Main blocks (see Fig 17

) are:

• Register bank for PMU analog block (detailed description in Section 6.7)

• Temperature sensor controller

• 32-bit APB slave interface

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Voltage Monitor

Threshold 1

Threshold 2

Threshold 3

VBUS1

2.3 V

2.7 V

N/A

6.4 Interrupts

Interrupt signals are generated in the analog part of the PMU as a result of:

• TXLDO 5 V monitoring

• VCC current limiter

• DC-to-DC converter current overload

• SCVDD current overload

• TXLDO current overload

• Temperature sensor

All interrupts are “ORed” in the digital part of the PMU to output one unique PMU interrupt line. The software has to analyze the content of the PMU_INTERRUPT_STATUS_REG register to know which of the seven conditions caused the interrupt. All interrupts can be enabled or disabled (masked) separately using the PMU_INTERRUPT_ENABLE_REG register. Clearing the status bit field of one interrupt is performed by setting the corresponding bit field in the PMU_INTERRUPT_CLR_STATUS_REG register high. All bit fields of all PMU_INTERRU PT_CLR_STATU S_REG and PM U_ IN TERRUPT_SET_ ST ATUS_REG registers are automatically cleared if set high after two system clock cycles.

6.5 Temperature sensors

The Power Management Unit of PN7462 family comprises two temperature sensors associated with the contactless TXLDO and the contact DC-to-DC converter interfaces. The main purpose of these sensors is to monitor the temperature and prevent the overheating, which could potentially cause the damage of the chip and the customer device. The triggering levels are configurable. Following temperatures can be chosen: 135°C, 130°C, 125°C or 120°C. By default, the temperature sensor is set to 120°C. When one of the sensors detects a temperature issue, an interrupt is generated and the microcontroller will be put by software into the standby mode or the suspend mode if the USB interface is used. The registers indicate which of the two temperature sensors (contact interface, or contactless interface) generated the interrupt. When the temperature goes below the configured threshold temperature, the microcontroller wakes up automatically. For a detailed description of the corresponding registers refer to PCR_TEMP_REG.

6.6 Voltage monitoring

The voltage monitoring is used to check if the voltages are within the appropriate range

specified for a proper operation of the IC. The following power supplies are monitored:

VBUS (2 voltage monitors) and VBUSP (1 voltage monitor). T able 35 voltage monitors with the selectable thresholds values.

Table 35. Voltage monitor - possible threshold configuration

summarizes the

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Voltage Monitor

Threshold 1

Threshold 2

Threshold 3

VBUS2

2.7 V

4 V

N/A

VBUSP

2.7 V

3 V

3.9 V

6.6.1 VBUS monitor

The PN7462 family offers two selectable thresholds (2.3 V or 2.7 V) for monitoring the voltage on the VBUS pin. When VBUS voltage falls below the selected threshold and Auto Hard Power Down (HPD) feature is enabled in the Power, Clock and Reset unit (described in Section 0 monitor the signal by reading a dedicated status register and decide to put the IC into the HPD mode. The signal can be enabled for interrupt in Interrupt Enable register in the PCR to cause a CPU interrupt. By default, the VBUS monitor is disabled during the power-up.

), the IC will enter the HPD mode. Alternatively, the software can

6.6.2 PVDD LDO (VBUS2 ) monitor

The PN7462 family offers two selectable thresholds (VBUS2: 2.7 V or 4.0 V) for monitoring the voltage of the PVDD LDO supply. The status of the VBUS2 monitor is available in the status register. The software has to check whether the voltage is sufficient before enabling the LDO. The PVDD LDO can be enabled when the input supply VBUS2 > 4.0 V.

6.6.3 VBUSP monitor

VBUSP monitor is used for the Contact interface supply. Three levels (2.7, 3.0, and 3.9 V) can be selected for monitoring the voltage on the VBUSP pin. The threshold is configured by firmware depending on the card type selected. (Class A, Class B, Class C)

When VBUSP < 2.7 V, no functionality is possible. When VBUSP > 2.7 V, Class C type can be supported. When VBUSP > 3.0 V, Class A type can be supported with DC-to-DC converter

configured in the doubler mode. When VBUSP > 2.7 V and VBUSP < 3.9 V, Class B type is supported with DC-to-DC

converter configured in the doubler mode. When VBUSP > 3.9 V, Class B type of card is supported with DC-to-DC converter

configured in the follower mode. When the voltage falls below the selected threshold value and CT automatic deactivation

is enabled in the PCR System Register, the hard war e automatically de-activates the CT interface. The signal can be enabled for interrupt in Interrupt Enable register in the PCR to cause a CPU interrupt. The software must check VBUSP monitor levels by reading dedicated status registers before starting card activation sequence.

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Voltage Monitor

Latency

VBUS1

10 µs

VBUS2

10 µs

VBUSP

75 µs

PMU_STATUS_REG

0000h

R

0000_0000h

Global PMU status register.

PMU_ BG_MON_CONTROL_RE G

0004h

R/W

0000_040Eh

Used to enable comparators PMU_TXLDO_CONTROL_REG

0008h

R/W

0400_0000h

TXLDO control register

PMU_LDO_CONTR OL_REG

000Ch

R/W

0000_0000h

DC-to-DC converter control INTERNAL_USE

[1]

00010h

R/W

0000_0000h

For internal use

INTERNAL_USE

[1]

0014h

R/W

0000_0000h

For internal use

PMU_INTERRUPT_CLR_ENABLE_REG

3FD8h

W

0000_0000h

PMU interrupt clear enable

PMU_INTERRUPT_SET_ENABLE_REG

3FDCh

W

0000_0000h

PMU interrupt set enable PMU_INTERRUPT_STATUS_REG

3FE0h

R

0000_0000h

PMU interrupt status register

PMU_INTERRUPT_ENABLE_REG

3FE4h

R/W

0000_0000h

PMU interrupt enable register

PMU_INTERRUPT_CLR_STATUS_REG

3FE8h

W

0000_0000h

PMU interrupt clear status

PMU_INTERRUPT_SET_STATUS_REG

3FECh

W

0000_0000h

PMU interrupt set status

6.6.4 Latency of voltage monitors

Table 36. Latency of voltage monitors

6.7 Register overview and description

Table 37. PMU register overview (base address 0x4000 8000)

Name

Address offset

Access Reset value Description

[1] Bit-field are either set by HAL or use default value from CLIF EEPROM default settings

To be used for observing signals in system mode.

and set thresholds for the monitors

register

register with automatic clear if set by software.

register with automatic clear if set by software

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Bit

Symbol

Access

Value

Description

31:25

RESERVED

R-

0x00

Reserved

24

MLDO_LOWPOWER_VBATBUF

R-

0x00

1: Indicates that the VBAT LDO is in low 23

INTERNAL_USE

[1]

R-

0x00

For internal use

22

TXLDO_5VMON_OK

R-

0x00

TXLDO 5V monitor output

21

POK_VBUSP

R-

0x00

Output of VBUSP monitor

20

POK_VBUSMON2

R-

0x00

Output of VBUS monitor2

19

POK_PVDDOUT

R-

0x00

Output of PVDD monitor 18

RESERVED

R-

0x00

Reserved

17

RESERVED

R-

0x00

Reserved

16:12

RESERVED

R-

0x00

Reserved

11

SCVDD_OVERLOAD

R-

0x00

1: SCLDO overload error

10

DCDC_OVERLOAD

R-

0x00

1: DC-to-DC converter overload error 9:3

TXLDO_DET_OUT

R-

0x00

[6:0] - Output of State Machine detection

2

TXLDO_DET_SM_OK

R-

0x00

Signal that indicates to Digital & SW that

1

TXLDO_TVDD_OK

R-

0x00

Signal that indicates State Machine work

0

TXLDO_DET

R-

0x00

Indicates that the detection threshold for

6.7.1 Detailed register description

6.7.1.1 PMU_STATUS_REG

This register is used to observe signals in system mode.

Table 38. PMU_STATUS_REG (address offset 0x0000)

power

1: TXLDO 5V monitor output is set TVDD/VUP_TX value is greater than 5V. Source is selected in PMU_TXLDO register

1: VBUSP value is greater than threshold

1: VBUS2 value is greater than threshold

1: PVDDOUT is ok (above 3.3 V)

0: No SCLDO overload error

0: No DC-to-DC converter overload error

State Machine work is done for automatic current measurement (automatic mode) and current value is valid in TXLDO_DET_OUT

is done

current measurement is reached

[1] Bit-field are either set by HAL or use default value from CLIF EEPROM default settings

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Bit

Symbol

Access

Value

Description

31:11

RESERVED

R/W

0x00

Reserved

10

Activates 1.8 V comparator for PVDD_M

9

Sets threshold for VBUSPMON 7

Sets threshold for VBUS MON2

6

Activates VBUSP monitor

5

Activates VBUS monitor 2

4

Activates PVDDOUT monitor

3

Activates 3 V comparator for PVDD_M

2

Activates 3 V comparator for PVDD

1

RESERVED

R/W

0x01

Reserved

0

RESERVED

R/W

0x00

reserved

Bit

Symbol

Access

Value

Description

31:29

RESERVED

R/W

0x00

Reserved

28

TXLDO_ENABLE_LP2

R/W

0x00

1: Enable 2nd regulator

6.7.1.2 PMU_BG_MON_CONTROL_REG

This register is used to enable comparators and set thresholds for the monitors.

Table 39. PMU_BG_MON_CONTROL_REG (address offset 0x0004)

ENABLE_PVDD_M_1V8_COMP R/W 0x01

VBUSPMON_THRESHOLD R/W 0x00

VBUSMON2_THRESHOLD R/W 0x00

1: Enable 1.8 V comparator for PVDD_M 0: Disable 1.8 V comparator for PVDD_M

00: 2.7 V 01: 3 V 10: 3.9 V

0: 2.5 V 1: 4 V

ENABLE_VBUSPMON R/W 0x00

ENABLE_VBUSMON2 R/W 0x00

ENABLE_PVDDOUTMON R/W 0x00

ENABLE_PVDD_M_3V_COMP rw 0x01

ENABLE_PVDD_3V_COMP rw 0x01

6.7.1.3 PMU_TXLDO_CONTROL_REG

This register is used to control the TXLDO.

1: Enable VBUSP monitor 0: Disable VBUSP monitor

1: Enable VBUS monitor 2 0: Disable VBUS monitor 2

1: Enable PVDDOUT monitor 0: Disable PVDDOUT monitor

1: Enable 3 V comparator for PVDD_M 0: Disable 3 V comparator for PVDD_M

1: Enable 3 V comparator for PVDD 0: Disable 3 V comparator for PVDD

Table 40. PMU_TXLDO_CONTROL_REG (address offset 0x00 08)

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Bit

Symbol

Access

Value

Description

0: Disable 2nd regulator

27:25

RESERVED

R/W

0x02

Do not modify value

24

TXLDO_RSTN_SOURCE_SEL

R/W

0x00

Source selection bit of TXLDO_digi

23

TXLDO_OVERCURRENT_EN

R/W

0x00

1: Enable overcurrent detection

22:21

TXLDO_SELECT_ANT

R/W

0x00

Offset selection for detection range of

20

RESERVED

R/W

0x00

Always set to 0

19:15

RESERVED

R/W

0x00

Do not modify value

14:8

TXLDO_DET_IN

R/W

0x00

Selection of Current Detection value for

TXLDO_det_in[6:0]

Cur (mA)

0000000

0

0000001

0.39

0000010

0.78

0000100

1.56

0001000

3.12

0010000

6.24

0100000

12.48

1000000

24.96

1111111

50

7:5

TXLDO_SELECT

R/W

0x00

Selection of Tvdd supply

resetn. 0: resetn source = rst_pcr_system_n 1: resetn source = (~rst_pcr_system_n or

TXLDO_enable)

0: Disable overcurrent detection

the TXLDO_DET_OUT 0 20mA 1 50mA 2 70mA 3 100mA Measurement range of the 7 bit DAC with

corresponding offset 20 to 70mA, 50 to 100mA, 70 to 120mA &

100 to 150mA

manual current measurement. if value is reached TXLDO_DET is set to 1

Minimum offset in TXLDO_SELECT_ANT is 20 mA (so 0 means minimum is 20 mA for the current threshold)

0 = 3 V 1 = 3.3 V

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Bit

Symbol

Access

Value

Description

2 = 3.6 V

Activates current limiter

3

TXLDO_LOW_POWER_EN

R/W

0x00

Activates the low-power mode 2

TXLDO_EN_DAC_SM

R/W

0x00

Enables the current measurement using

1

TXLDO_DETECTOR_EN

R/W

0x00

Activates the Current Detection for DAC 0

TXLDO_ENABLE

R/W

0x00

Enable the whole TXLDO block

Bit

Symbol

Access

Value

Description

31:12

RESERVED

R/W

0x00

Reserved

11:7

RESERVED

R/W

0x00

Reserved

6

RESERVED

R/W

0x00

Reserved

5

VBUSP_HI

R/W

0x00

CT channel detects the presence and

4

RESERVED

R/W

0x00

Reserved

3

DISABLE_VCC_IPROT

R/W

0x00

If set to 1, the VCC LDO current limit is

2

CT_VCC_IPROT

R-

0x00

If set to 1 the VCC LDO c urrent limi t has 1

RESERVED

R/W

0x00

Reserved

4 TXLDO_LIMITER_EN R/W 0x00

3 = 4.5 V 4 and others=4.7 V

1: Enable current limiter 0: Disable current limiter

1: Enable low power mode 0: Disable low power mode

the state machine (automatic mode)

current measurement (manual mode) 1: Enable current detection for TXLDO 0: Disable current detection for TXLDO

6.7.1.4 PMU_LDO_CONTROL_REG

This register is used to control the DC-to-DC converter.

Table 41. PMU_LDO_CONTROL_REG (address offset 0x000C)

1: Enable TXLDO 0: Disable TXLDO

starts the CT sequence. 1: VBUSP > 3.9 V. 0: VBUSP < = 3.9 V.

disabled

been triggered

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Bit

Symbol

Access

Value

Description

31:9

RESERVED

-X

0x00

Reserved

8

VBUSMON2_LOW_IRQ_CLEAR_

-X

0x00

clears enable state of Vbus monitor 2

7

TXLDO_5V_MON_IRQ_CLEAR_

-X

0x00

clears enable state of TXLDO 5 V monitor

6

VCC_ILIM_ACT_IRQ_CLEAR_E

-X

0x00

clears enable state of VCC current limiter. 5

RESERVED

-X

0x00

Reserved

4

PVDD_IRQ_CLEAR_ENABLE

-X

0x00

clears enable state of PVDD interrupt.

3

DCDC_OVERLOAD_IRQ_CLEAR

-X

0x00

clears enable state of DC-to-DC converter

2

SCVDD_OVERLOAD_IRQ_CLEA

-X

0x00

clears enable state of SCVDD overload.

1

TXLDO_OVERCURRENT_IRQ_C

-X

0x00

clears enable state of TXLDO overcurrent

0

TEMPSENS_ERROR_IRQ_CLEA

-X

0x00

clears enable state of Temperature sen sor

Bit

Symbol

Access

Value

Description

31:9

RESERVED

-X

0x00

Reserved

VBUSMON2_LOW_IRQ_SET_EN

enables Vbus monitor 2 going low

7

TXLDO_5V_MON_IRQ_SET_EN

-X

0x00

Enables TXLDO 5 V monitor interrupt

6

VCC_ILIM_ACT_IRQ_SET_ENAB

-X

0x00

Enables VCC current limiter.

6.7.1.5 PMU_INTERRUPT_CLR_ENABLE_REG

This register is a collection of Clear Interrupt Enable commands with automatic clear if set by software.

Table 42. PMU_INTERRUPT_CLR_ENABLE_REG (address offset 0x3FD8)

ENABLE

NABLE

_ENABLE

R_ENABLE

LEAR_ENABLE

R_ENABLE

going low interrupt

interrupt

Automatically cleared after 2 cycles if set by software

overload. Automatically cleared after 2 cycles if set by software

Automatically cleared after 2 cycles if set by software

interrupt. Automatically cleared after 2 cycles if set by software

calibration interrupt. Automatically cleared after 2 cycles if set by software

6.7.1.6 PMU_INTERRUPT_SET_ENABLE_REG

This register is a collection of Set Interrupt Enable commands with automatic clear if set by software.

Table 43. PMU_INTERRUPT_SET_ENABLE_REG (address offset 0x3FDC)

8

ABLE -X 0x00

ABLE

LE

interrupt

Automatically cleared after 2 cycles if set by software

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Bit

Symbol

Access

Value

Description

5

RESERVED

-X

0x00

Reserved

4

PVDD_IRQ_SET_ENABLE

-X

0x00

Enables PVDD interrupt. Automatically

3

DCDC_OVERLOAD_IRQ_SET_E

-X

0x00

Enables DC-to-DC converter overload. 2

SCVDD_OVERLOAD_IRQ_SET_

-X

0x00

Enables SCVDD overload. Automatically

1

TXLDO_OVERCURRENT_IRQ_S

-X

0x00

Enables TXLDO overcurrent interrupt.

0

TEMPSENS_ERROR_IRQ_SET_

-X

0x00

Enables Temperature sensor calibration

Bit

Symbol

Access

Value

Description

31:9

RESERVED

R-

0x00

Reserved

0x00

Indicates Vbus monitor 2 going low

7

TXLDO_5V_MON_IRQ_STATUS

R-

0x00

Indicates TXLDO 5 V monitor interrupt is

6

VCC_ILIM_ACT_IRQ_STATUS

R-

0x00

Indicates VCC current limiter active 5

RESERVED

R-

0x00

Reserved

4

PVDD_IRQ_STATUS

R-

0x00

Indicates PVDD interrupt is set.

3

DCDC_OVERLOAD_IRQ_STATU

R-

0x00

Indicates DC-to-DC converter overload

2

SCVDD_OVERLOAD_IRQ_STAT

R-

0x00

Indicates SCVDD overload interrupt is set.

1

TXLDO_OVERCURRENT_IRQ_S

R-

0x00

Indicates TXLDO overcurrent interrupt is

0

TEMPSENS_ERROR_IRQ_STAT

R-

0x00

Indicates temperature sensor interrupt is

cleared after 2 cycles if set by software

NABLE

ENABLE

ET_ENABLE

ENABLE

6.7.1.7 PMU_INTERRUPT_STATUS_REG

This register is a collection of Interrupt Status commands.

Table 44. PMU_INTERRUPT_STATUS_REG (address offset 0x3FE0)

8 VBUSMON2_LOW_IRQ_STATUS R-

Automatically cleared after 2 cycles if set by software

cleared after 2 cycles if set by software

Automatically cleared after 2 cycles if set by software

interrupt. Automatically cleared after 2 cycles if set by software

interrupt is set

set. Automatically cleared after 2 cycles if set by software

S

US

TATUS

US

interrupt is set. Automatically cleared after 2 cycles if by software

Automatically cleared after 2 cycles if by software

interrupt is set. Automatically cleared after 2 cycles if by software

Automatically cleared after 2 cycles if by software

set. Automatically cleared after 2 cycles if by software

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Bit

Symbol

Access

Value

Description

31:9

RESERVED

R-

0x00

Reserved

8

VBUSMON2_LOW_IRQ_ENABL

R-

0x00

Indicates enabled VBUS monitor 2 going

7

TXLDO_5V_MON_IRQ_ENABL

R-

0x00

Indicates enabled TXLDO 5 V monitor

6

VCC_ILIM_ACT_IRQ_ENABLE

R-

0x00

Indicates enabled VCC current limiter 5

RESERVED

R-

0x00

Reserved

4

PVDD_IRQ_ENABLE

R-

0x00

Indicates enabled PVDD interrupt.

3

DCDC_OVERLOAD_IRQ_ENAB

R-

0x00

Indicates enabled DC-to-DC converter

2

SCVDD_OVERLOAD_IRQ_ENA

R-

0x00

Indicates enabled SCVD overload

1

TXLDO_OVERCURRENT_IRQ_

R-

0x00

Indicates enabled TXLDO overcurrent

0

TEMPSENS_ERROR_IRQ_ENA

R-

0x00

Indicates enabled temperature sensor

Bit

Symbol

Access

Value

Description

31:9

RESERVED

-X

0x00

Reserved

8

VBUSMON2_LOW_IRQ_CLEAR_S

-X

0x00

Clears status of Vbus monitor 2 going low

7

TXLDO_5V_MON_IRQ_CLEAR_S

-X

0x00

Clears status of TXLDO 5 V monitor interrupt.

6.7.1.8 PMU_INTERRUPT_ENABLE_REG

This register is a collection of Interrupt Enable commands.

Table 45. PMU_INTERRUPT_ENABLE_REG (address offset 0x3FE4)

E

LE

BLE

ENABLE

BLE

low interrupt

interrupt. Automatically cleared after 2 cycles if set by software

active interrupt. Automatically cleared after 2 cycles if by software

Automatically cleared after 2 cycles if by software

overload interrupt. Automatically cleared after 2 cycles if by software

interrupt. Automatically cleared after 2 cycles if by software

6.7.1.9 PMU_INTERRUPT_CLR_STATUS_REG

This register is a collection of Clear Interrupt Status commands with automatic clear if set by software.

Table 46. PMU_INTERRUPT_CLR_STATUS_REG (address offset 0x3FE8)

TATUS

interrupt

Automatically cleared after 2 cycles if set by software

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Bit

Symbol

Access

Value

Description

6

VCC_ILIM_ACT_IRQ_CLEAR_STA

-X

0x00

Clears status of VCC current limiter active 5

RESERVED

-X

0x00

Reserved

4

PVDD_IRQ_CLEAR_STATUS

-X

0x00

Clears status of PVDD interrupt. Automatically

3

DCDC_OVERLOAD_IRQ_CLEAR_

-X

0x00

Clears status of DC-to-DC converter overload

2

SCVDD_OVERLOAD_IRQ_CLEAR

-X

0x00

Clears status of SCVD overload interrupt.

1

TXLDO_OVERCURRENT_IRQ_CL

-X

0x00

Clears status of TXLDO overcurrent interrupt .

0

TEMPSENS_ERROR_IRQ_CLEAR

-X

0x00

Clears status of temperature sensor interrupt.

Bit

Symbol

Access

Value

Description

31:9

RESERVED

-X

0x00

Reserved

8

VBUSMON2_LOW_IRQ_SET_ST

-X

0x00

Sets status of Vbus monitor 2 going low interrupt

7

TXLDO_5V_MON_IRQ_SET_ST

-X

0x00

Sets status of TXLDO 5 V monitor interrupt.

6

VCC_ILIM_ACT_IRQ_SET_STAT

-X

0x00

Sets status of VCC current limiter active interrupt. 5

RESERVED

-X

0x00

Reserved

4

PVDD_IRQ_SET_STATUS

-X

0x00

Sets status of PVDD interrupt. Automatically

3

DCDC_OVERLOAD_IRQ_SET_S

-X

0x00

Sets status of DC-to-DC converter overload

2

SCVDD_OVERLOAD_IRQ_SET_

-X

0x00

Sets status of SCVD overload interrupt.

1

TXLDO_OVERCURRENT_IRQ_S

-X

0x00

Sets status of TXLDO overcurrent interrupt.

TUS

STATUS

_STATUS

EAR_STATUS

_STATUS

interrupt. Automatically cleared after 2 cycles if clear by software

cleared after 2 cycles if clear by software

interrupt. Automatically cleared after 2 cycles if clear by software

Automatically cleared after 2 cycles if clear by software

Automatically cleared after 2 cycles if set by software

6.7.1.10 PMU_INTERRUPT_SET_STATUS_REG

This register is a collection of Set Interrupt Status commands with automatic clear if set by software.

Table 47. PMU_INTERRUPT_SET_STATUS_REG (address offset 0x3FEC)

ATUS

US

TATUS

STATUS

ET_STATUS

Automatically cleared after 2 cycles if set by software

Automatically cleared after 2 cycles if clear by software

cleared after 2 cycles if clear by software

interrupt. Automatically cleared after 2 cycles if clear by software

Automatically cleared after 2 cycles if clear by software

Automatically cleared after 2 cycles if set by software

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Bit

Symbol

Access

Value

Description

0

TEMPSENS_ERROR_IRQ_SET_

-X

0x00

Sets status of temperature sensor interrupt.

Mode

Register

Bit Field

full power

PMU_TXLDO_CONTROL_REG

TXLDO_ENABLE =1

low Power

PMU_TXLDO_CONTROL_REG

TXLDO_ENABLE =0

low Power2

PMU_TXLDO_CONTROL_REG

TXLDO_ENABLE =0

shutdown

PMU_TXLDO_CONTROL_REG

TXLDO_ENABLE =0

standby

PCR_PMU_REG

TXLDO_ENABLE_STANDBY

STATUS

6.7.2 TXLDO Register settings

Table 48. TXLDO Register

Automatically cleared after 2 cycles if set by software

TXLDO_LOW_POWER_EN =0 TXLDO_ENABLE_LP2=0

TXLDO_LOW_POWER_EN =1 TXLDO_ENABLE_LP2=0

TXLDO_LOW_POWER_EN =0 TXLDO_ENABLE_LP2=1

TXLDO_LOW_POWER_EN =0 TXLDO_ENABLE_LP2=0

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Fig 18. Clock generator block diagram

7. Clock generator

The PN7462 family uses following clock sources:

• External 27.12 MHz crystal oscillator

• Internal 20 MHz HFO (High Frequency Oscillator)

• Internal 380 kHz LFO (Low Frequency Oscillator)

• Internal 48 MHz USB PLL (Phase Lock Loop)

• Internal CLIF PLL (Phase Lock Loop)

In addition to the clock sources, the clock generator comprises a digital control unit, which controls and monitors the signals coming from the clocks and integrated PLL. The registers are accessed using an APB register interface.

7.1 Oscillators

The PN7462 family includes three independent oscillators. Each oscillator can be used for more than one purposes. Upon reset, the PN74 62 f am il y will operate from the Internal HFO until it is switched to a different clock source. This allows systems to operate without any external crystal and the boot loader code to operate at a known frequency.

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PN7462AU

Fig 19. 27.12 MHz crystal oscillator connection

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

f

CLK frequency

ISO/ IEC and FCC compliancy

27.12

MHz

f

CLK frequency accuracy

[1]

-50 +50

Ppm

ESR

Equivalent series resistance

50

100

Ohm

C

Load capacitance

10 pF

P

Drive level

100

µW

7.1.1 27.12 MHz Crystal oscillator (XTAL)

The 27.12 MHz crystal oscillator is used as a reference for all operations requiring high stability of the clock frequency. This includes: contactless interface, contact interface, SPI and I2C master interfaces, HSUART and USB PLL for the USB interface.

To ensure the stability of the clock frequency, it is recommended to adopt the circuit with the external quartz and the trimming capacitors shown in Fig 19. Table 49 the requirements for the crystals.

summarizes

Table 49. Crystal requirements

CLK

CLK_ACC

LOAD

CLK

[1] This requirement is according FCC regulations requirements. To meet only ISO/IEC 14443 and ISO/IEC 18092 then +/-

14 kHz apply.

7.1.1.1 XTAL activation sequence

The XTAL is automatically activated by the digital control unit as soon as the system reset is released. The LFO needs to be activated to start the XTAL Oscillator.

XTAL activation sequence description:

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• Wait for system reset release

• Wait for 4 clk_lfo clock cycles (4x(1/380 KHz) ~ 10.53 us)

• Set XTAL_ENABLE_KICK to ’1’

• Wait for 4 clk_lfo clock cycles (4x(1/380 KHz) ~ 10.53 us)

• Set XTAL_ENABLE_KICK to ’1’

In case of error, the PCR can try to restart the XTAL activation sequence by activating the

system reset again or switching to another system clock source.

The XTAL can also be controlled by software when CLKGEN_HFO_XTAL_REG.XTAL_CONTROL_SW is set to ’1’. Before activating the XTAL software control, the system clock should be switched from the XTAL to another clock. The following sequence must be followed step by step in order to activate XTAL by SW.

1. Set CLKGEN_HFO_XTAL_REG.XTAL_CONTROL_SW is set to ’1’.

2. Clear CLK_HFO_XTAL_REG.XTAL_SPAR E0 to ‘0’

3. Wait for 4 clk_lfo clock cycles (4x(1/380 KHz) ~ 10.53 us)

4. Clear CLKGEN_HFO_XTAL_REG.XTALl_B YP A SS to ‘0’

5. Clear CLKGEN_HFO_XTAL_REG.XTAL_SELECT_EXTERNAL_CLOCK to ‘0’

6. Set XTAL_ENABLE_KICK to ’1’

7. Wait for 4 clk_lfo clock cycles (4x(1/380 KHz) ~ 10.53 us)

8. Set XTAL_ENABLE_KICK to ’1’

7.1.2 High Frequency Oscillator (HFO)

The PN7462 family integrates an internal low power High Frequency Oscillator (HFO), generating a 20 MHz clock without using the PLL. The HFO can be used as a system clock. The HFO is activated by default with the CLKGEN_HFO_XTAL_REG.HFO_ENABLE register bit as soon as the system reset is released.

7.1.3 Low Frequency Oscillator (LFO)

The PN7462 family integrates an internal low power Low Frequency Oscillator working at 380 kHz. The LFO is used by the EEPROM, POR sequencer, Contactless interface, timers and watchdog. The LFO needs to be activated to start the XTAL Oscillator

7.2 Phase Locked Loop (USB PLL)

The PN7462 family integrates a dedicated USB PLL to generate a low-noise 48 MHz clock signal from the 27.12 MHz input signal coming from the external crystal (XTAL). The 48 MHz clock signal is used as the main clock for the USB interface.

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Fig 20. PLL/ XTAL clock path diagram

USB PLL features:

• Low-skew, Peak-peak cycle-to-cycle jitter 48 MHz output clock (100 ps typical)

• Low Power in active more, low power-down current

• On-Chip loop filter, no external RC components needed

7.2.1 USB PLL Clock source selection

The USB PLL input can be selected between:

• Crystal oscillator output (default)

CLKGEN_HFO_X TAL_REG.XT AL_B YP A SS = ‘0 ’ CLKGEN_CLIF_PLL_GLOBAL_CONTROL_REG.PLL_INPUT_BUFFER_BYPASS = ‘0’

• External clock input CLKGEN_HFO_XTAL_REG. XTAL_BYPASS = ‘1’ CLKGEN_CLIF_PLL_GLOBAL_CONTROL_REG.PLL_INPUT_BUFFER_BYPASS = ‘0’

7.2.2 USB clock selection

The USB PLL output can be configured as:

• USB PLL Clock

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CLKGEN_USB_PLL_CONTROL_REG.USB_PLL_CLKOUT_SELECT = ’00’

• Crystal Oscillator or External clock

CLKGEN_USB_PLL_CONTROL_REG.USB_PLL_CLKOUT_SELECT = ’01’

• USB Clock Disable

CLKGEN_USB_PLL_CONTROL_REG.USB_PLL_CLKOUT_SELECT = ’10’ or ‘11’

7.2.3 USB PLL frequency calculation

The USB PLL soft decoder selects pre-defined divider ratios and corresponding bandwidth of the PLL to guarantee stability. The soft decoder can only select two sets of divider parameters in order to have a ~48 MHz output clock from a 27.12 MHz input clock (Clkout=Clkinx(M/(NxP))).

CLKGEN_USB_PLL_CONTROL_REG.usb_pll_mnp_sel = ’0’ : M=69, N=13,P=3 Clkout=Clkinx(M/N.P) = 27.12 MHz × (69/(13 × 3)) = 48 MHz

CLKGEN_USB_PLL_CONTROL_REG.usb_pll_mnp_sel = ’1’ : M=92, N=13,P=4. Clkout=Clkinx(M/N.P) = 27.12 MHz × (92/(13 × 4)) ~ 47.9815 MHz

The Soft Decoder can be bypassed in order to have the full control of the divider ratios. When CLKGEN_USB_PLL_CONTROL_REG.usb_pll_mnp_dec_selection is set to ’1’ M,N,P divider ratios are coming from CLKGEN_USB_PLL_MDEC_WO_SOFTDEC and CLKGEN_USB_PLL_NDEC_PDEC_WO_SOFTDEC registers.

7.2.4 USB PLL Activation Sequence

The Activation Sequence with default MNP parameters comprises following steps:

1. Put the PLL in Power Down Mode CLKGEN_USB_PLL_CONTROL_REG.USB_PLL_PD = ’1’

2. Enable the PLL input buffer

CLKGEN_USB_PLL_CONTROL_REG.USB_PLL_INPUT_BUFFER_ENABLE = ’1’

3. Set the expected PLL input clock frequency for the clock detector by setting the detection window length and the amount of expected detected input clock rising edges in this detection window respectively defined by the following registers CLKGEN_INPUT_CLOCK_DETECTOR_CONTROL_REG.

By default, these registers are set to detect a 27.12 MHz input clock.

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4. Enable Input Clock Detector CLKGEN_INPUT_CLOCK_DETECTOR_CONTROL_REG.USB_CLK_DETECT_EN ABLE = ’1’.

5. Poll for CLKGEN_STATUS_REG.CLK_IN_DETECT_DONE = ’1’ (after ~5.2 us by default). This will only indicate that the detection procedure is finished, not that there is clock and/or the frequency is the expected one.

6. Check that CLKGEN_STATUS_REG.CLK_IN_OK = ’1’.

This will indicate if there is a clock of a frequency higher or equals to the expected one

(27.12 MHz by default) at the input of the PLL. If this bit is 0 while CLK_IN_DETECT_DONE is high, this means either that there is no clock or that the clock has a frequency lower than the expected one (27.12 MH z), which will hamper the PLL functionality or give an unwanted PLL output frequency value.

7. Disable the Input Clock Detector

CLKGEN_USB_PLL_CONTROL_REG. USB_CLK_DETECT_ENABLE = ’0’.

8. Exit the PLL from the Power Down Mode

CLKGEN_USB_PLL_CONTROL_REG.PLL_PD = ’0’

9. Enable the PLL CLKGEN_USB_PLL_CONTROL_REG.PLL_CLKEN = ’1’

10. Poll for CLKGEN_STATUS_REG.PLL_LOCK = ’1’ to confirm the lock status of the PLL.

Software can start a new PLL input clock detection at any time by generating a low to high transition on the CLKGEN_INPUT_CLOCK_DETECTOR_CONTROL_REG.USB_CLK_DETECT_ENA BLE register.

7.3 CLIF PLL

The integrated CLIF PLL is designed to generate a low-noise 27.12 MHz clock, which is used as time reference for the Contactless Interface when PN7462 family is in reader mode or acting as ISO/IEC 18092 initiator.

The frequency value of the reference clock that is fed, can be selected using CLKGEN_CLIF_PLL_GLOBAL_CONTROL_REG register between:

1. Crystal oscillator output (default)

2. External clock input The CLIF PLL output can be configured using

CLKGEN_CLIF_PLL_GLOBAL_CONTROL_REG registers as:

1. Fractional PLL output

2. XTAL oscillator output Clock

3. Regular PLL output

4. PLL input

The clock generator module provides a PLL/XTAL clock presence indicator signal to the CLIF. This signal is active when the clock coming from the PLL or XTAL, or a

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Fin

n1

m1

p1

m2

p2

Fref1

Fcco1

Fref2

Fcco2

Fpll_clk

27.12

4

68

46

44

32.522

13.56

922.1

20.05

881.99

13.56

27.12

Name

Address

Width

Access

Reset value

Description

CLKGEN_STATUS_REG

0000h

32 R 00000000h

CLKGEN status register

CLKGEN_HFO_XTAL_REG

0004h

32

R/W

00FFF001h

HFO and XTAL control register

CLKGEN_HFO_TRIM_REG

0008h

32

R/W

00000000h

HFO trimming value register

CLKGEN_USB_PLL_CONTROL_

000Ch

32

R/W

00F90001h

PLL Global Control Register

CLKGEN_USB_PLL_MDEC_WO_

0010h

32

R/W

00000000h

PLL M decoded divider ratio

CLKGEN_USB_PLL_NDEC_PDE

0014h

32

R/W

00000000h

PLL N and P decoded divider CLKGEN_CLIF_PLL1_CONTROL_

0018h

32

R/W

02E3B190h

CLIF PLL usage configurations

CLKGEN_CLIF_PLL2_CONTROL_

001Ch

32

R/W

02E121E0h

CLF PLL usage configurations

CLKGEN_CLIF_PLL_GLOBAL_C

0020h

32

R/W

000000C8h

CLIF PLL integration

CLKGEN_INPUT_CLOCK_DETEC

0024h

32

R/W

0000100Dh

Input clock detector control RESERVED

0028h

32

R/W

0000000Fh

Reserved

CLKGEN_CLOCK_PRESENCE_B

002Ch

32

R/W

00000000h

clock presence for CLIF PLL

Unused

0030h -

32 - -

unused

combination of both (depending on the clock settings), is available. This signal can be overridden using CLIF_PLL_CLK_IN_OK_BYPASS register.

7.3.1 Op t imum divider settings for CLIF PLL

Table 50. Optimum divider settings for PLL1 and PLL2

[MHz]

(MHz)

7.4 Register overview and description

7.4.1 Clock generator register overview

Table 51. Clock generator register overview (base address 0x4001 0000)

offset

REG

SOFTDEC_REG

C_WO_SOFTDEC_REG

(bits)

(MHz)

when the soft decoder is not used

ratio when the soft decoder is not used

out (MHz)

out2

(MHz)

REG

ONTROL_REG

TOR_CONTROL_REG

YPASS_REG

3FFFh

configurations

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Bit

Symbol

Access

Value

Description

31:27

RESERVED

- 0 Reserved

26

CLIF_CLOCK_PRESENCE_OK

R

0

Indicates the status of clkgen_clif_pll_lock2_o signal. 25

XTAL_ACTIVATION_TIME

R 0 high if timeout for XTAL Activation is reached

24

XTAL_DETECT_OK

R

0

Indicates the presence of clock signal on clk_xtal if 1: Xtal detection done

23

XTAL_OSC_OK

R

0

high to indicate the clock is ready 1: Xtal osc clock is ready

22

CLIF_PLL_LOCK_OVERRIDEN

R

0

1: pll_lock2 OR pll_bypass_lock2 is set 0: pll_lock2 OR pll_bypass_lock2 is not set

21

CLIF_CLK_IN_DETECT_DONE

R

0

CLIF PLL detection status 1: CLIF PLL clk_in detection done

20

CLIF_CLK_IN_OK

R

0

PLL input clock detector ok signal. 0: clk_in not ok

19

CLIF_PLL_LOCK2

R

0

Lock detector Output for 2nd PLL 0: PLL2 lock is not set

18

CLIF_PLL_LOCK1

R

0

Lock detector Outp ut for 1st PLL. 17

XTAL_OK

R 0 1: XTAL oscillator is activated

16

XTAL_ENABLED

R 0 1: XTAL oscillator is enabled

15:8

CLK_IN_EDGES_COUNTER

R 0 input clock edges counter value when the

7

CLK_IN_DETECT_DONE

R

0

USB_PLL input clock detection status

6

CLK_IN_OK

R

0

USB_PLL input clock detector OK Sta tu s. 5

USB_PLL_FR

R 0 USB_PLL free running detector status

4

USB_PLL_PACK

R

0

USB_PLL post-divider ratio change acknowledge

3

USB_PLL_NACK

R

0

USB_PLL pre-divider ratio change acknowledge

2

USB_PLL_MACK

R 0 USB_PLL feedback divider ratio change acknowledge 1: USB_PLL feedback divider ratio change has been

7.5 Clock Status Register description

Table 52. CLKGEN_STATUS_REG (address 0000h)

1: CLIF PLL2 lock signal set 0: CLIF PLL2 lock signal not set

OUT_ERROR

1: Xtal activation has timed-out

xtal_detect_enable is set.

1: clk_in is present and correct

1: PLL2 lock is set

1: PLL1 lock is set 0: PLL1 lock is not set

0: XTAL oscillator disabled

USB_PLL_CLK_IN detection completes successfully

1: USB PLL input clock detection completed

1: CLK_IN is present and the frequency matche s expected frequency

1: USB PLL is in free running mode

1: USB_PLL post-divider ratio change has been Acknowledged 0: No post-divider ratio change

1: USB_PLL pre-divider ratio change has been Acknowledged 0: No pre-divider ratio change

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Bit

Symbol

Access

Value

Description

Acknowledged

1

USB_PLL_LOCK_OVERRIDEN

R 0 USB_PLL lock overriden status 0

USB_PLL_LOCK

R

0

USB_PLL lock status

Name

Address

Width

Access

Reset value

Description

CLKGEN_HFO_XTAL_REG

0004h

32

R/W

00FFF001h

HFO and XTAL control register

CLKGEN_HFO_TRIM_REG

0008h

32

R/W

00000000h

HFO trimming value register

Bit

Symbol

Access

Value

Description

31:24

RESERVED

R/W

0x00

Reserved

23:12

XTAL_ACTIVATION_TIMEOUT

R/W

0xFFF

Set the XTAL activation timeout value (in LFO Clock

11

XTAL_DETECT_ENABLE

R/W

0x00

Enables the XTAL output clock presence detection if

10

XTAL_SPARE3

R/W

0x00

controls XTAL Spare3

9

XTAL_SPARE2

R/W

0x00

controls XTAL Spare2

8

XTAL_SPARE1

R/W

0x00

controls XTAL Spare1

7

XTAL_SPARE0

R/W

0x00

controls XTAL Pull Down

7.5.1 Oscillators register description

Oscillators are controlled by the registers shown in Table 53. More det ai led desc r ipt ions follow. Writes to any unused bits are ignored.

0: No feedback divider ratio change

1: CLKGEN_STATUS_R EG .U SB_ P LL _lo c k or CLKGEN_USB_PLL_GLOBAL_CONTROL_REG.USB_ PLL_lock_bypass is high. 0: USB PLL Lock is not set

1: USB PLL lock set 0: USB PLL lock is not set

Table 53. Oscillators Registers

offset

(bits)

7.5.1.1 HFO and XTAL control register

The CLKGEN_HFO_XTAL_REG register contains the bits that Activate/Enable XTAL, enable HFO.

Table 54. CLKGEN_HFO_XTAL_REG (address 000 4h)

Cycles + 8); Default value > 10 ms

clk_in_detect_enable is low . 1: Enable XTAL clk detection 0: Disable XTAL clk detection

1: enable strong pull-down on clk_xtal port of clkgen_ana sub-block

0: disable pull-down on clk_xtal port of clkgen_ana subblock

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Bit

Symbol

Access

Value

Description

6

XTAL_VOLTAGE_MUX_CLOC

R/W

0x00

5

XTAL_SEL_EXTERNAL_CLOC

R/W

0x00

Controls XTAL external clock selection if 4

XTAL_ENABLE

R/W

0x00

controls XTAL Enable if XTAL_CONTROL_SW='1' 3

XTAL_ENABLE_KICK

R/W

0x00

Controls XTAL Enable Kick if XTAL_CONTROL_SW='1'

2

XTAL_BYPASS

R/W

0x00

controls XTAL Bypass if XTAL_CONTROL_SW='1'

1

XTAL_CONTROL_SW

R/W

0x00

high to control the XTAL oscillator by SW

0

HFO_ENABLE

R/W

0x01

enables the HFO (activated by default)

Bit

Symbol

Access

Value

Description

31:5

RESERVED

R/W

0x00

Reserved

4:0

HFO_TRIMM

R/W

0x00

HFO trimming values

Name

Address

Width

Access

Reset value

Description

CLKGEN_USB_PLL_CONTROL_

000Ch

32

R/W

00F90001h

PLL global control register

CLKGEN_USB_PLL_MDEC_WO_

0010h

32

R/W

00000000h

PLL M decoded divider ratio

K

7.5.1.2 HFO Trimming Value Register

Table 55. CLKGEN_HFO_TRIMM_REG (address 0008h)

controls XTAL voltage Mux

XTAL_CONTROL_SW='1' 1: Select External clock 0: Select XTAL Oscillator clock

1: Enable for XTAL oscillator 0: Disable XTAL Oscillator

1: Enable Kick of XTAL Oscillator

1: Bypass XTAL 0: XTAL not Bypassed

1: Enable software control of XTAL oscillator 0: Disable software control of XTAL oscillator

1: Enable HFO 0: Disable HFO

7.6 USB PLL register description

The USB PLL is controlled by the registers shown in Table 56. Writes to any unused bits are ignored.

Warning: Improper setting of USB PLL values may result in incorrect operation of the USB.

Table 56. USB PLL Registers

offset

REG

SOFTDEC_REG

(bits)

when the soft decoder is not used

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Name

Address

Width

Access

Reset value

Description

CLKGEN_USB_PLL_NDEC_PDE

0014h

32

R/W

00000000h

PLL N and P decoded divider

Bit

Symbol

Access

Value

Description

31

RESERVED

R/W

0x00

Reserved

30

USB_PLL_MNPSEL

R/W

0x00

M,N,P selection values for the Soft Decoder

29:28

USB_PLL_CLKOUT_SELECT

R/W

0x00

00: USB_PLL output clock 2

27:26

USB_PLL_REF_CLK_SELECT

R/W

0x00

Selects the reference clock for USB PLL

25

USB_PLL_LOCK_BYPASS

R/W

0x00

1: Bypass the USB_PLL lock output

24

USB_PLL_MNP_DEC_SELECTIO

R/W

0x00

1: M,N,P divider ratio are not coming from the soft

23:19

USB_PLL_INSELP

R/W

0x1F

select the bandwidth (don't care if

18:15

USB_PLL_INSELI

R/W

0x02

select the bandwidth (don't care if

14:11

USB_PLL_INSELR

R/W

0x00

select the bandwidth (don't care if

10

USB_PLL_BANDSEL

R/W

0x00

bandwidth adjustment (to modify externally the

offset

C_WO_SOFTDEC_REG

(bits)

7.6.1 PLL Control Register (CLKGEN_USB_PLL_CONTROL_REG - 000Ch)

The CLKGEN_USB_PLL_CONTROL_REG register contains the bits that enable and connect PLL1. Enabling USB PLL allows it to attempt to lock to the current settings of the multiplier and divider values. Connecting USB PLL causes the USB subsystem to run from the USB PLL output clock. The USB PLL must be set up, enabled, and lock established before it may be used as a clock source for the USB.

Table 57. CLKGEN_USB_PLL_CONTROL_REG (a ddress 000Ch)

0: M=600,N=113,P=3 1: M=92,N=13,P=4

01: USB_PLL_clkin 10: tie '0' 11: tie '0'

ratio when the soft decoder is not used

N

00: clk_input_buffer 01: clk_xtal 10: tie '0' 11: tie '0'

decoder but from the CLKGEN_USB_PLL_MDEC_WO_SOFTDEC and CLKGEN_USB_PLL_NDEC_PDEC_WO_SOFTDEC registers 0: M, N, P divider ratio are taken from the Soft Decoder

USB_PLL_BANDSEL='0')

bandwidth of the USB_PLL)

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Bit

Symbol

Access

Value

Description

9

USB_PLL_PREQ

R/W

0x00

USB_PLL post-divider ratio change request

8

USB_PLL_NREQ

R/W

0x00

USB_PLL pre-divider ratio change request

7

USB_PLL_MREQ

R/W

0x00

USB_PLL feedback divider ratio change request 6

USB_PLL_FRM

R/W

0x00

USB_PLL free running mode

5

USB_PLL_SKEW_EN

R/W

0x00

USB_PLL skew mode

4

USB_PLL_DIRECTO

R/W

0x00

Bypass of the USB_PLL post-divider

3

USB_PLL_DIRECTI

R/W

0x00

Bypass of the USB_PLL pre-divider

2

USB_PLL_BYPASS

R/W

0x00

Bypass of the USB_PLL (clkout=clkin)

1

USB_PLL_CLKEN

R/W

0x00

Enable the USB_PLL output clock

0

USB_PLL_PD

R/W

0x01

USB_PLL In t o power down

Bit

Symbol

Access

Value

Description

31:17

RESERVED

R/W

0x00

Reserved

16:0

USB_MDEC_WO_SOFTDEC

R/W

0x00

divider ratio code for M-divider when soft decoder is

1: Request change of USB_PLL post-divider ratio (ratio taken from register)

1: Request change of USB_PLL pre-divider ratio (ratio taken from register)

1: Request change of USB_PLL feedback divid er ratio (ratio taken from register)

1: Enable free running mode of USB PLL

1: Enable skew mode of USB_PLL

7.6.2 PLL M decoded divider ratio

The CLKGEN_USB_PLL_MDEC_WO_SOFTDEC_REG register contains the USB PLL multiplier and divider values. Changes to CLKGEN_USB_PLL_MDEC_WO_SOFTDEC_REG register do not take effect until a correct USB feed sequence has been given (see Section 7.2 PLL frequency, and multiplier and divider values are found in Section 7.2.

1: Enable Bypass of USB_PLL post-divider 0: USB_PLL post-divider Bypass disable

1: Enable Bypass of USB_PLL pre-divider 0: USB_PLL pre-divider Bypass disable

1: Enable Bypass of USB_PLL 0: USB_PLL Bypass disable

1: Enable output clock from USB PLL 0: Disable output clock from USB PLL

1: USB PLL powered down 0: USB PLL powered up

). Calculations for the USB

Table 58. CLKGEN_USB_PLL_MDEC_WO_SOFTDEC_REG (address 0010h)

not used

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Bit

Symbol

Access

Value

Description

31:16

RESERVED

R/W

0x00

Reserved

15:10

USB_PDEC_WO_SOFTDEC

R/W

0x00

divider ratio code for P-divider w hen soft decoder is not

9:0

USB_NDEC_WO_SOFTDEC

R/W

0x00

divider ratio code for N-divider w hen soft decoder is not

Name

Address

Width

Access

Reset value

Description

CLKGEN_CLIF_PLL1_CONTRO

0018h

32

R/W

02E3B190h

Clif pll usage configurations

CLKGEN_CLIF_PLL2_CONTRO

001Ch

32

R/W

02E121E0h

Clif pll usage configurations

CLKGEN_CLIF_PLL_GLOBAL_

0020h

32

R/W

000000C0h

Clif pll integration configurations

CLKGEN_INPUT_CLOCK_DETE

0024h

32

R/W

000011ADh

input clock detector control

CLKGEN_CLOCK_PRESENCE_

002Ch

32

R/W

0000000Fh

yes clock presence for clif_pll

7.6.3 PLL N and P decoded divider ratio

The CLKGEN_USB_PLL_NDEC_PDEC_WO_SOFTDEC_REG register contains the USB PLL multiplier and divider values. Changes to CLKGEN_USB_PLL_NDEC_PDEC_WO_SOFTDEC register do not take effect until a correct USB feed sequence has been given (see Section 7.2 PLL frequency, and multiplier and divider values are found in Section 7.2.

Table 59. CLKGEN_USB_PLL_NDEC_PDEC_WO_SOF TDEC_REG (address 0014h)

used

). Calculations for the USB

7.7 CLIF PLL register description

CLIF PLL is controlled by the registers shown in Table 60. More detail ed desc r ipt ions follow. Writes to any unused bits are ignored. A read of any unused bits will return a logic zero.

Warning: Improper setting of CLIF PLL value s may result in incorrect operation of the Contactless System!

Table 60. CLIF PLL register overview

offset

L_REG

CONTROL_REG

CTOR_CONTROL_REG

BYPASS_REG

7.7.1 CLIF PLL CONTROL1 REG

(bits)

The CLKGEN_CLIF_PLL1_CONTROL_REG register contains the CLIF PLL multiplier and divider values. Changes to CLKGEN_CLIF_PLL1_CONTROL_REG register do not take effect until a correct CLIF PLL feed sequence has been given. Calculations for the USB PLL frequency, and multiplier and di vi der va lues ar e found in Section 7.2

.

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Bit

Symbol

Access

Value

Description

31:28

RESERVED

R/W

0x00

Reserved

27

CLIF_PLL_LIMUP_OFF1

R/W

0x00

pulse limiter for CLIF_PLL 1

26

CLIF_PLL_FREQ_LIM1

R/W

0x00

frequency limiter for CLIF_PLL 1

25:24

CLIF_PLL_SELP1

R/W

0x02

Pins to select the BW of CLIF_PLL 1

23:22

CLIF_PLL_SELI1

R/W

0x03

Pins to select the BW of CLIF_PLL 1

21:20

CLIF_PLL_SELR1

R/W

0x02

Pins to select the BW of CLIF_PLL 1

19

CLIF_PLL_FUNC_TEST2_P1

R/W

0x00

1: Enable functional CLIF_PLL chain test of divider P1

18

CLIF_PLL_FUNC_TEST1_P1

R/W

0x00

1: Enable functional divider test of divider P1

17:12

CLIF_PLL_DIVP1

R/W

0x3B

Feedback divider ratio P1

11

CLIF_PLL_FUNC_TEST2_M1

R/W

0x00

1: Enable functional CLIF_PLL test chain of divider M1

10

CLIF_PLL_FUNC_TEST1_M1

R/W

0x00

1: Enable functional divider test of divider M1

9:3

CLIF_PLL_DIVM1

R/W

0x32

Feedback divider ratio M1

2

CLIF_PLL_BYPASS_LOCK1

R/W

0x00

Bypass of Lock1

1

CLIF_PLL_FUNC_TEST2_LOCK1

R/W

0x00

1: Enable functional CLIF_PLL test chain of lock detector 0

CLIF_PLL_FUNC_TEST1_LOCK1

R/W

0x00

1: Enable functional divider test of lock detector 1

Bit

Symbol

Access

Value

Description

31:28

RESERVED

R/W

0x00

Reserved

27

CLIF_PLL_LIMUP_OFF2

R/W

0x00

pulse limiter for CLIF_PLL 2

26

CLIF_PLL_FREQ_LIM2

R/W

0x00

frequency limiter for CLIF_PLL 2

25:24

CLIF_PLL_SELP2

R/W

0x02

Pins to select the BW of CLIF_PLL 2

23:22

CLIF_PLL_SELI2

R/W

0x03

Pins to select the BW of CLIF_PLL 2

21:20

CLIF_PLL_SELR2

R/W

0x02

Pins to select the BW of CLIF_PLL 2

19

CLIF_PLL_FUNC_TEST2_P2

R/W

0x00

1: Enable functional CLIF_PLL chain test of divider P2

18

CLIF_PLL_FUNC_TEST1_P2

R/W

0x00

1: Enable functional divider test of divider P2

17:12

CLIF_PLL_DIVP2

R/W

0x12

Feedback divider ratio P2

11

CLIF_PLL_FUNC_TEST2_M2

R/W

0x00

1: Enable functional CLIF_PLL test chain of divider M2

10

CLIF_PLL_FUNC_TEST1_M2

R/W

0x00

1: Enable functional divider test of divider M2

9:3

CLIF_PLL_DIVM2

R/W

0x3C

feedback divider ratio M2

2

CLIF_PLL_BYPASS_LOCK2

R/W

0x00

Bypass of Lock2

Table 61. CLKGEN_CLIF_PLL1_CONTROL_REG (address 0018h)

1: Bypass clif_pll_lock1

1

7.7.2 CLIF PLL CONTROL2 REG

The CLKGEN_CLIF_PLL2_CONTROL_REG register contains the CLIF PLL multiplier and divider values. Changes to CLKGEN_CLIF_PLL2_CONTROL_REG register do not take effect until a correct CLIF PLL feed sequence has been given. Calculations for the USB PLL frequency, and multiplier and di vi der va lues ar e found Section 7.2

Table 62. CLKGEN_CLIF_PLL2_CONTROL_REG (address 001Ch)

.

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Bit

Symbol

Access

Value

Description

1: Bypass clif_pll_lock2

1

CLIF_PLL_FUNC_TEST2_LOCK2

R/W

0x00

1: Enable functional CLIF_PLL test chain of lock detector 0

CLIF_PLL_FUNC_TEST1_LOCK2

R/W

0x00

1: Enable functional divider test of lock detector 2

Bit

Symbol

Access

Value

Description

31:15

RESERVED

R/W

0x00

Reserved

14

CLIF_PLL_CLK_IN_OK_BYPASS

R/W

0x00

CLIF PLL clk_in detection override

13:12

CLIF_PLL_REF_CLK_SELECT

R/W

0x00

Select the reference clock for CLIF PLL

11

RESERVED

R/W

0x00

Reserved

10

CLIF_CLK_DETECT_ENABLE

R/W

0x00

1: Enable CLIF_PLL input clock detector (clk_in).

9:7

CLIF_PLL_INPUT_FREQ_SEL

R/W

0x01

Select input frequency for the CLIF_PLL: 13, 19.2, 24,

6:5

CLIF_PLL_CLOCK_SELECT

R/W

0x02

Selects output clock from CLIF_PLL

4

PLL_INPUT_BUFFER_BYPASS

R/W

0x00

Bypass PLL input buffer (the buffer for clock going into 3

PLL_INPUT_BUFFER_ENABLE

R/W

0x01

1: Enable the PLL Input Buffer (the buffer for clock 0: Disable the PLL input Buffer

2

CLIF_PLL_FUNC_TEST_N1

R/W

0x00

1: Enable functional divider test and CLIF_PLL test

1

CLIF_PLL_DIVN1

R/W

0x00

Pre-divider selection for CLIF PLL1

0

CLIF_PLL_ENABLE

R/W

0x00

1: Enable the CLIF_PLL

2

7.7.3 CLIF PLL GLOBAL CONTROL REG

The CLIF PLL GLOBAL CONTROL REG register contains the bits that enable and connect CLIF PLL. Enabling CLIF PLL allows it to attempt to lock to the current settings of the multiplier and divider values.

Table 63. CLKGEN_CLIF_PLL_GLOBAL_C O NTR O L_RE G (address 0020h)

1: Override pll_clk_in detection

00: Clk_input_buffer 01: clk_xtal 10: tie ‘0’ 11: tie ‘0’

Higher prior than xtal_detect_enable.

26, 38.4 or 52 MHz

00: CLIF_PLL clockout2 01: clk_xtal 10: CLIF_PLL clockout 11: CLIF_PLL input clock

USB PLL and intPLL) 1: Bypass the PLL input buffer

going into USB PLL and intPLL)

chain of divider M1 0: Disable functional divider test and CLIF_PLL test

chain of divider M1

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Bit

Symbol

Access

Value

Description

0: Disable the CLIF PLL

Bit

Symbol

Access

Value

Description

31:14

RESERVED

R/W

0x0

Reserved

14

USB_PLL_CLK_IN_OK_BYPASS

R/W

0x0

usb pll clk_in detection override 13

USB_CLK_DETECT_ENABLE

R/W

0x0

Enable usb_pll_clk_in detect

12:5

INPUT_USB_CLOCK_EDGES_NUM

R/W

0x80

Defines the expected amount of input clock edges

4:0

DETECTION_WINDOW_LENGTH

R/W

0x0D

Defines the detection window length (in HFO/8

Bit

Symbol

Access

Value

Description

31:2

RESERVED

R/W

0x0

Reserved

1

CLOCK_PRESENCE_BYPASS_V

R/W

0x0

Value to apply to clif_pll_lock2_o signal when 0

CLOCK_PRESENCE_BYPASS_E

R/W

0x0

1: Enable bypass of the clif_pll_lock2_o signal to the

7.7.4 INPUT CLOCK DETEC T OR CONTROL REGISTER

Table 64. CLKGEN_INPUT_CLOCK_DETECTOR_CONTROL_REG (address 0024h)

1: usb_pll_clk_in detection overridden. Clk_in_ok set to '1'

1: Enable usb_pll_clk_in detection

BER

during the detection window length. Default value is set to detect a 27.12 MHz input clock.

clock cycles). Default value is set to detect a 27.12 MHz input

clock.

7.7.5 CLOCK PRESENCE BY PASS REG

Table 65. CLKGEN_CLOCK_PRESENCE_BYPASS_REG (address 002Ch)

AL

NABLE

corresponding enable bit is set 0: set clif_pll_lock2_o signal to 0 1: set clif_pll_lock2_o signal to 1

value stored in clock_presence_bypass_val 0: Disable Bypass of the clif_pl l_lo ck 2_o signal

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8. Power clock and reset (PCR)

The Power, Clock & Reset Unit (PCR) handles the digital startup of the PN7462 family and manages the behavior of the system in low power and active modes. The PCR unit is the only digital block that is powered in the standby mode.

The PCR unit provides following functionalities:

• Reset management

• Power on, standby, USB suspend and power off management

• Wake-up management

• Clock gating management for power consumption reduction

• I/O pad management

shows the block diagram of the PCR Unit with its main blocks:

Fig 21

• Reset Generator

• Standby Control

• Clock Box

• Pad Control

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Source

Description

Software - PCR

Software reset from the PCR peripheral; Resets the whole

Software - ARM

Software reset from the ARM processor; Resets the whole

I2C interface

I2C Standard 3.0 defines a method to reset the chip via an I2C Watchdog

Reset the chip if the watchdog threshold is not periodically reloaded; Resets the whole chip except the PCR and the ARM debug interface

VBUS - PMU

Power-on reset sequence; Resets the complete chip when the voltage

RST_N pin

External reset triggered via reset pin; Resets the complete chip when

Fig 21. Block diagram of PCR Unit

8.1 Reset sources

The PN7462 family has 6 possible rest sources. These are described in detail in Table

66.

Table 66. Reset sources

chip except the PCR and the ARM debug interface

command; This feature can be disabled; Resets the whole chip except the PCR and the ARM debug interface

is above 2.3 V

the RST_N pin is set to low

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PCR_STATUS.boot_reason

Values

Description

startup_por

0

Analog Reset Sources (Startup Por or leave Rfld 1 RF Level Detector wakeup

wuc_cnt

2

Wakeup Timer

int_aux

3

Contact uart int_aux pad gives an interrupt

Ct 4 Contact card presence is detected

i2c 5 I2C address detected

RESERVED

6

Reserved

Spi 7 SPI slave received transaction

usb_resume

8

USB Resume signaling from Host

soft_reset

9

Soft reset given by software

Wdog

10

Watch dog timer timeout or ARM reset

Tvddmon

11

5V detected by TVDD monitor

hif_reset

12

VEN from low to high back (only for test temp0

13

Neg-edge detected for Temperature error from

temp1

14

Neg-edge detected for Temperature error from no_pvdd

15

PVDD dropped

pvdd_ilim

16

Pvdd current limiter input has become 01 gpio

17

Gpio interrupt

hsu

18

HSUART transaction detected

These reset sources trigger the reset generator that generates a global reset pulse. The Reset Generator is active high-level sensitive to the reset sources. As long as one reset source is high, the global reset will be active. After releasing the reset source, the res et pulse will be prolonged to at least one cycle. The power-on reset sequence is asserted when the device is powered up. It is used to keep the system in reset state until proper supply conditions are established. This point is achieved when the internal supply voltage reaches 1.55 V.

When the internal reset is removed, the processor begins executing at address 0, which is initially the reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.

8.2 Boot reason decoding

Table 67. Boot reason decoding

reflected in register

from HPD or VEN)

purpose) Ii2c slave or smb slave requested for reset

temperature sensor 0

temperature sensor 1

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No.

Root cause description

1

A host communication is ongoing 2

If wake-up timer is enabled and its value is 0

8.3 Power modes

The PN7462 family offers four different power modes allowing customer to optimize its energy consumption. These are:

• Active mode

• Standby mode

• USB suspend mode

• Hard Power Down mode

8.3.1 Full Power Mode (Active Mode)

In the active mode, all functionalities are available and all blocks are accessible. The PN7462 family is powered from the VBUS supply.

8.3.2 Standby Mode

In this mode, only small part of the IC is powered to maintain operation of the Power Control Unit, the LFO and a small set of registers for storing data during the standby operation. The MLDO is set to the low power mode. The possible wake-up sources are still powered. Depending on the application requirements, it is possible to put PVDDL_LDO into active mode, low power mode (default) or shut down mode. The standby mode is triggered by the application firmware. Before entering the standby mode, the PN7462 family executes automatically the deactivation of the contact card. An internal mechanism prevents from entering into the standby mode either when no relevant wake up source is activated, or when conditions for a corresponding wakeup source are not present. The IC goes to power on mode again when a wake up is asserted.

8.3.2.1 Entering Standby Mode

To enter standby mode, the firmware needs to operate in an infinite while loop of:

1. Programming the standby bit in the PCR_CTRL_REG.

2. Checking if there is any standby prevention reason.

3. If any reason found, then cater to the reason preventing entry of standby Go back to step 1.

This loop will be automatically broken when PN7462 family enters standby and comes

As this will reset PN7462 family and restart the boot.

out.

8.3.2.2 Standby prevention root causes

Table below summarizes conditions preventing PN7462 family from entering the standby mode.

Table 68. Standby prevention root causes

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No.

Root cause description

3

Either RF level detector is activated as wakeup sour ce and R F level dete ctor is 4

Host Interface is selected as wakeup source and no PVDD is available

5

PVDD current limiter input has seen a 01

6

Negative-edge found on temperature error for temperature sensor 0,

7

Negative-edge found on temperature error for temperature sensor 1, 8

No host interface is selected

9

GPIO interrupt found

10

TVDD voltage has risen above 5 V

11

Card insertion or removal detected

12

Contact unart int_aux pin has given an interrupt

13

Contact deactivation is ongoing.

not enabled or RF field is already present

considering temperature sensor 0 is enabled for wakeup

considering temperature sensor 1 is enabled for wake-up

8.3.3 USB suspend mode

In this mode, only a few parts of USB are still active but not clocked. All clock sources except LFO are stopped. PN7462 family will go into suspend state if there is no activity on the USB bus for more than 3 ms.

8.3.3.1 Entering suspend mode

To enter suspend mode, the firmware needs to operate in an infinite while loop of :

1. Programming the suspend bit in the PCR_CTRL_REG

2. Wait for interrupt.

3. If the interrupt is SUSPEND_DEFAULTED then check for the standby prevention reason (same register used for standby).

4. If any reason found, then cater to the prevention reason.

5. Now go back to step 1

If the interrupt is SUSPEND, then it means P7462 family has entered and come out of suspend.

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LDO/PLL

Active

Standby

Suspend

HPD

Hardware/Software

LDOs

MLDO

full power

low power

hardware

PVDDLDO

Full/Low power/OFF

Power down by hardware

8.3.4 Wake-up from Standby/Suspend Mode

Standby/suspend mode is left if one of the following conditions is met:

• Host activity (SPI, I2C, HSU) for standby mode and USB Resume for suspend mode with following pre-conditions:

− PVDD is available

− One of interfaces is selected (hif_selection is != 0 )

− In case of SPI being selected NSS==1

• Contact card insertion/removal detection

• Wake-up timer using a 6 bit counter and a match register with programmable

standby/suspend mode duration from 50ms to 2.5s; Used to timely check for any contact or contactless card presence

• Active Reset Source: e.g. current overconsumption on the PVDD_OUT, voltage above 5V on TVDD_IN

• Disappearance of PVDD: Voltage drop below 1.8 V triggers wak e-up; Always active

• RF level detection caused by activity on the CLIF interface e.g. by bringing card near

to CLIF

• Temperature sensor threshold reached: when the temperature goes below the configured value, the microcontroller wakes-up automatically; Each temperature sensor can be configured individually

• GPIO: transition from 0 to 1 on input GPIO pads can be used to wakeup

8.3.5 Hard Power Down Mode

This is the lowest power mode allowing for the highest reduction of the power consumption. All clocks are turned off, all LDOs are turned off, except the MLDO which is set to the low power mode

The PN7462 family enters the Hard Power Down mode when RST_N is set to zero or the VBUS voltage is going below 2.3 V.

The PN7462 family exits the Hard Power Down mode, when RST_N pin is set to high level and VBUS voltage goes above 2.3 V.

8.3.6 LDOs/PLLs in different power modes

Table 69. LDOs/PLLs in power modes

Low power mode Operational mode

software

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LDO/PLL

Active

Standby

Suspend

HPD

Hardware/Software

VCCLDO

Full/Low

enabling power

TXLDO

Full/Low

PLLs and

OFF: hardware CLIF PLL

ON/OFF

OFF

software

XTAL

ON

OFF

hardware

HFO

ON

OFF

hardware

LFO

ON

OFF

hardware

DCDC/SCLDO/

power/OFF OFF OFF

Standby-LDO

oscillators

USB PLL ON/OFF OFF OFF OFF

power/OFF

mode

Standby-LDO mode software

switches.

software

ON: software

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Fig 22. Clock Box control

8.4 Clock box

The Clock Box is responsible for generating all clock signals for the system. The PCR_CLK_CFG_REG and PCR_CLK_CFG2_REG are used by firmware to gate system and IP clocks going to different modules.

The system clock source can be one among: HFO 20 MHz XTAL  27.12 MHz (internal test purpose) CLK_USB/2  24 Mh z. (only internal test purpose) System clock must be always 20 MHz

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The selection is done using the PCR_SELECT_SYSTEMCLOCK [2:0]: 001 ... 20 MHz clkHFO (default) 010 ... 24 MHz clkUSBPLL/2 (internal test purpose) 100 ... 27.12 MHz clkXtal (internal test purpose) Others ... INVALID, should not be programmed

8.5 Clock Gating

In order to reduce the overall power consumption, the PN7462 family enables adjusting the system clock and integrates clock gating mechanisms.

The clocks of the following blocks can be activated or deactivated, depending on the peripherals used (see Fig 23):

• Contactless interface

• Contact interface

• Host interfaces

2

C master interface

• I

• SPI master interface

• CRC engine

• Timers

• Random generator

• System Clock

• EEPROM

• Flash memory

To enable the clock for this part, the correspo ndi ng bit i n PCR_CL K_CF G_REG and PCR_CLK_CFG2_REG needs to be set.

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Fig 23. Clock gating

PAD Name

Power Supply

DWL_REQ

PVDD_IN

ATX_A, ATX_B, ATC_C, ATX_D

PVDD_IN

CLK_AUX, INT_AUX, IO_AUX

PVDD_IN_M

D+, D-

PVDD_IN

8.6 I/O Pad Management

I/O Pad Management allows:

• Connecting the GPIO/I2C/SPI to a peripheral IO for device pins that are not connected to a specific peripheral function

• Dynamic configuration as inputs or outputs or analog by FW

• Pull up, pull down or tri-state configuration

The GPIO read/write are made by the firmware using separate registers that allow reading, setting or clearing outputs. The value of the output register may be read back as well as the current state of the port pins. The pads controlled by the Pad Control Block are summarized in T able 7 0

Table 70. All digital controlled pads

.

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PAD Name

Power Supply

MISO_M, MOSI_M, SCLK_M, NSS_M

PVDD_IN_M

SCL_M, SDA_M

PVDD_IN_M

GPIO1 to GPIO12

PVDD_IN

SWDIO, SWDCLK

PVDD_IN

IRQ

PVDD_IN

Name

Address

Width

Access

Reset value

Description

PCR_GPREG0_REG

0x0000

32

rw-

0x00000000

General-purpose register 0 for SW

PCR_GPREG1_REG

0x0004

32

rw-

0x00000000

General-purpose register 1 for SW

PCR_GPREG2_REG

0x0008

32

rw-

0x00000000

General-purpose register 2 for SW

system configuration like Hostif selection

PMU interface. For LDO, bandgap, PCR_RFLD_REG

0x0014

32

rw-

0x00004032

CLIF configuration

temperature sensor calibration

PCR_HOSTIF_WAKEUP_CF

configuring wake-up source for standby

PCR_GPIO_WAKEUP_CFG_

configuring wake-up source for standby

8.6.1 Hard Power Down (HPD) State of Pads

In the Hard Power Down mode, all digital pad signals will be masked.

8.6.2 Pad state in absence of PVDD

In absence of PVDD all input and output drivers will be disabled with a gate and all input signals from the PAD will be clamped.

8.6.3 Selecting host interface

The PN7462 family connects to host through four pads: ATX_A/ATX_B/ATX_C/ATX_D. There are three protocols by which PN7462 family connects to host through pads: I2C/high-speed-UART/SPI. The selection of which protocol to connect with is done by using configuration of PCR_SYS_REG.hif_selection bits in PCR_SYS_REG register described in Table 75

.

8.7 Register overview

Table 71. Register overview (base addr ess 0x400 2 4000)

Offset

PCR_SYS_REG 0x000c 32 rw- 0x00000100

PCR_PMU_REG 0x0010 32 rw- 0x0217010C

(bits)

and CT enabling

DC-to-DC converter configuration and sequences

PCR_TEMP_REG 0x0018 32 rw- 0x00058888

G_REG 0x001c 32 rw- 0x00000000

PCR_WAKEUP_CFG_REG 0x0020 32 rw- 0x00000000

REG 0x0024 32 rw- 0x000000FF

information

and Suspend

and suspend

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Name

Address

Width

Access

Reset value

Description

Bootup register with important v alues to

Control register to enable Enable, gating, division value selection

Select lines for clock muxes, between different frequencies or between different

Store value on input pads into this

output value to be driven onto output

host if pad:

host if pad: PCR_PADDWL_REQ_REG

0x0050

32

rw-

0x00000001

DWL_REQ pad configuration

PCR_PAD_INT_AUX_REG

0x0054

32

rw-

0x00000001

INT_AUX pad configuration

PCR_PAD_IO_AUX_REG

0x0058

32

rw-

0x00000001

IO_AUX pad configuration

PCR_PAD_CLK_AUX_REG

0x005C

32

rw-

0x00000002

CLK_AUX pad configuration

PCR_PADIRQ_REG

0x0060

32

rw-

0x00000002

IRQ pad configuration

PCR_PADGPIO1_REG

0x0064

32

rw-

0x00000001

GPIO1 pad configuration

PCR_PADGPIO2_REG

0x0068

32

rw-

0x00000001

GPIO2 pad configuration

PCR_PADGPIO3_REG

0x006C

32

rw-

0x00000001

GPIO3 pad configuration

PCR_PADGPIO4_REG

0x0070

32

rw-

0x00000001

GPIO4 pad configuration

PCR_PADGPIO5_REG

0x0074

32

rw-

0x00000001

GPIO5 pad configuration

PCR_PADGPIO6_REG

0x0078

32

rw-

0x00000001

GPIO6 pad configuration

PCR_PADGPIO7_REG

0x007C

32

rw-

0x00000001

GPIO7 pad configuration

PCR_PADGPIO8_REG

0x0080

32

rw-

0x00000001

GPIO8 pad configuration

PCR_PADGPIO9_REG

0x0084

32

rw-

0x00000001

GPIO9 pad configuration

PCR_PADGPIO10_REG

0x0088

32

rw-

0x00000001

GPIO10 pad configuration

PCR_PADGPIO11_REG

0x008C

32

rw-

0x00000001

GPIO11 pad configuration

PCR_PADGPIO12_REG

0x0090

32

rw-

0x00000001

GPIO12 pad configuration

Offset

PCR_BOOT_REG 0x0028 32 r-- 0x00000000

PCR_CTRL_REG 0x002C 32 rw- 0x00000000

PCR_CLK_CFG_REG 0x0030 32 rw- 0x0087FE08

PCR_CLK_CFG2_REG 0x0034 32 rw- 0x00000B00

PCR_PADIN_REG 0x0038 32 r-- 0x00000000

PCR_PADOUT_REG 0x003C 32 rw- 0x00000000

PCR_PAD_ATX_A_REG 0x0040 32 rw- 0x00000000

PCR_PAD_ATX_B_REG 0x0044 32 rw- 0x00000000

PCR_PAD_ATX_C_REG 0x0048 32 rw- 0x00000000

(bits)

be checked during bootup

standby/suspend/soft-restart/clearing boot register

for clocks going to different Ips

division values

register

pads stored here

i2c_scl/spi_nss/hsu_rx/usb_dp/smb_cl

i2c_sda/spi_mosi/hsu_tx/usb_dm/smb_d a

i2c_adr0/spi_miso/hsu_rts_n/usbN.A/smbalert

PCR_PAD_ATX_D_REG 0x004C 32 rw- 0x00000000

i2cadr1/spi_sck/hsu_cts_n/usb-N.A/smbN.A

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Name

Address

Width

Access

Reset value

Description

PCR_PADSWDIO_REG

0x0094

32

rw-

0x00000006

SWDIO pad slew rate configuration

INTERNAL_USE

0x0098

32

rw-

0x00000006

For internal use

RESERVED

0x009C

32

rw-

0x0000020C

Reserved

RESERVED

0x00A0

32

rw-

0x00000008

Reserved

PCR_PADIICM_REG

0x00A4

32

rw-

0x00000280

I2C master pad configuration

PCR_ANA_TX_STANDBY_R

CLIF configuration related to power INTERNAL_USE

0x00B0

32

rw-

0x00000041

For internal use

PCR_SPIM_REG

0x00B4

32

rw-

0x00000040

SPIM master pad configuration

PCR_CTIF_REG

0x00B8

32

rw-

0x00000000

CTIF presense detection pull-up

host interface Tx/RX divider value

host interface clock value storage during PCR_TXLDO_MON_REG

0x00C4

32

rw-

0x00000008

TXLDO sequence management

PCR_BOOT2_REG

0x00C8

32

rw-

0x00000000

BOOT reason register extention.

PCR_GPREG3_REG

0x00CC

32

rw-

0x00000000

general-purpose register 3 for S W

PCR_GPREG4_REG

0x00D0

32

rw-

0x00000000

general-purpose register 4 for SW

PCR_GPREG5_REG

0x00D4

32

rw-

0x00000000

general-purpose register 5 for S W

PCR_GPREG6_REG

0x00D8

32

rw-

0x00000000

general-purpose register 6 for S W

PCR_GPREG7_REG

0x00DC

32

rw-

0x00000000

general-purpose register 7 for SW

rw-

register to program is GPIO interrupts PCR_GPIO_INT_LEVEL_SE

register to program if GPIO interrupts are

PCR_GPIO_INT_ACTIVE_B

register to program if GPIO interrupts are

PCR_SELECT_SYSTEMCLO

register to program the source for

register for configuring advanced RFLD

PCR_ADV_RFLD_TEST_RE

configuration bits for testing advanced

PCR_INT_CLR_ENABLE_RE

PCR_INT_SET_ENABLE_RE PCR_INT_STATUS_REG

0x3FE0

32

r-m

0x00000000

interrupt status

Offset

EG 0x00A8 32 rw- 0x00000000 CLIF standby GSN value selection

PCR_ANA_TXPROT_REG 0x00AC 32 rw- 0x00000001

PCR_HOSTIF_SAVE1_REG 0x00BC 32 rw- 0x00000000

PCR_HOSTIF_SAVE2_REG 0x00C0 32 rw- 0x00000000

(bits)

down

storage during standby

standby

PCR_GPIO_INT_ACTIVE_L OW_REG 0x00E0 32

NSE_REG 0x00E4 32 rw- 0x00000000

OH_EDGE_REG 0x00E8 32 rw- 0x00000000

CK 0x00EC 32 rw- 0x00000001

PCR_ADV_RFLD_REG 0x00F0 32 rw- 0x00000000

G 0x00F4 32 rw- 0x00000000

G 0x3FD8 32 -wm 0x00000000 interrupt clear enable

G 0x3FDC 32 -wm 0x00000000 interrupt set enable

0x00000000

are active low level/ falling edge sensitive

level sensitive.

both edge sensitive

system clock.

detection FSM

RFLD detection FSM

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Name

Address

Width

Access

Reset value

Description

PCR_INT_ENABLE_REG

0x3FE4

32

r-m

0x00000000

interrupt enable

PCR_INT_CLR_STATUS_RE

PCR_INT_SET_STATUS_RE

Bit

Symbol

Access

Value

Description

31:0

PCR_GPREG0

R/W

0

general-purpose register 0 for SW

Bit

Symbol

Access

Value

Description

31:0

PCR_GPREG1

R/W

0

general-purpose register 1 for SW

Bit

Symbol

Access

Value

Description

31:0

PCR_GPREG2

R/W

0

general-purpose register 2 for SW

Bit

Symbol

Access

Value

Description

31:12

RESERVED

rw

0x00

Reserved

11

1: Enables automatic initiation of CT deactivation

10

1: Enables PCR to go automatically into HPD state when

below threshold voltage

9

Indicates that PVDD is being supplied using internal 8

1: Enable the Contact interface.

7

Selects the PVDD_M voltage trigger level

6

PVDD_M_IRQ_EN

rw

0x00

Enables the PVDD_M IRQ

Offset

G 0x3FE8 32 -wm 0x00000000 interrupt clear status

G 0x3FEC 32 -wm 0x00000000 interrupt set status

(bits)

8.8 Register description

Table 72. PCR_GPREG0_REG (address offset 0x00)

Table 73. PCR_GPREG1_REG (address offset 0x04)

Table 74. PCR_GPREG2_REG (address offset 0x08)

Table 75. PCR_SYS_REG (address offset 0x0C)

AUTOMATIC_CT_DEACT rw 0x00

AUTOMATIC_HPD rw 0x00

PVDD_INT rw 0x00

ENABLE_CT rw 0x01

PVDD_M_IRQ_VAL rw 0x00

sequence when VBUSP voltage goes below programmed range.

the VBUS voltage goes below programmed voltage of

2.3 V/2.7 V 0: PCR stays in operating state even if VBUS goes

PVDD LDO 1: Enable Internal PVDD LDO

0: Disable Contact Interface

0: PVDD_M voltage trigger level 1.8 V 1: PVDD_M voltage trigger level 3.3 V

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Bit

Symbol

Access

Value

Description

1: Enable PVDD_M IRQ

5

Selects the PVDD voltage trigger level

4

Enables the PVDD IRQ 3

HOSTIF_SW_REGCONTR

2:0

Bit

Symbol

Access

Value

Description

31:29

PBF_CONST_LOAD_VA

28

Power down signal to connect/disconnect a constant

27

VBUS monitor override value

26

VBUS monitor override enable

25

PD_PBF_FIELDSENS

rw

0x01

1- Enable for pbf_pd_fieldsens

24

BG_TRIM_A

rw

0x00

bandgap trim bit

23

BG_TRIM_B

rw

0x00

bandgap trim bit

22

BG_TRIM_C

rw

0x00

bandgap trim bit

21

BG_TRIM_D

rw

0x00

bandgap trim bit

17:20

RESERVED

rw

0x00

Reserved

16

MLDO_LOWPOWER_BG_ 15

MLDO_LOWPOWER_VAL

rw

0x00

Value of mldo_low power signal

14

MLDO_LOWPOWER_EN

rw

0x00

Controls mldo low power signals

0: Disable PVDD_M IRQ

0: PVDD voltage trigger level 1.8 V

PVDD_IRQ_VAL rw 0x00

PVDD_IRQ_EN rw 0x00

OL_EN rw 0x00 1: Enabled control of USB D+,D- from ATX_A/B registers

HIF_SELECTION rw 0x00

1: PVDD voltage trigger level 3.3 V

1: Enable PVDD IRQ 0: Disable PVDD IRQ

host interface selection 000: No Host interface selected 001: I2C selected as host interface 010: SPI selected as host interface 011: HSU selected as host interface 100 -USB selected as host interface others - Invalid

Table 76. PCR_PMU_REG (address offset 0x10)

L rw 0x00 configuration bits for constant load on vdhf

PBF_EN_CONST_LOAD rw 0x00

VBATMON_OVERRIDE_VA L rw 0x00

VBATMON_OVERRIDE_EN rw 0x00

load to vdhf

0: for 2.7 V 1: for 2.3 V

1: Enable for VBUS monitor 0: Disable VBUS monitor

EN rw 0x01 Controls mldo bandgap low power signals.

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Bit

Symbol

Access

Value

Description

1: Enable low power mode of MLDO

13

To set the DC-to-DC converter in high impedance state enabling the testing of VCCLDO. VUP will be forced from

12

RESERVED

rw

0x00

Reserved

11

TXLDO clear standby mode

10

TXLDO enable standby mode

9

RESERVED

rw

0x00

Reserved

8:4

IBIAS_TRIMM

rw

0x10

IBIAS trim value

3:2

Selects pvddldo mode normal/low power/soft start/power

1:0

RESERVED

rw

0x00

Reserved

Bit

Symbol

Access

Value

Description

31:16

15

HIGHER bias current for the env-detector

14

Higher bias current for comparator

13

12

11

DCDC_OFF rw 0x00

0: Disable low power mode of MLDO

outside. 1: Bypass DC-to-DC converter if DC-to-DC_off is low

TXLDO_STANDBY_CLEAR rw 0x00

TXLDO_ENABLE_STANDB Y rw 0x00

PVDDLDO_MODE rw 0x03

Table 77. PCR_RFLD_REG (address offset 0x14)

RESERVED rw 0x00 Reserved

RFLD_ENVDET_BOOST rw 0x00

1: Disable standby mode of TXLDO

1: Enable standby mode for low power consumption during standby/suspend

down 11: power down 10: soft start 01: low power mode 00: normal mode

1: Enable Higher bias current for the env-detector

RFLD_COMP_BOOST rw 0x01

RFLD_BIAS_ADPT_ENABL E rw 0x00

RFLD_DRV_ENABLE rw 0x00

RFLD_FILTER_ENABLE rw 0x00

1: Enable Higher current for comparator Enable of automatic bias current regulation

1: Enable of automatic bias current regulation 0: Disable of automatic bias current regulation

Enable the chopper clock driver for the RF Level Detector.

1: Enable the chopper clock driver for the RF Level Detector.

0: Disable the chopper clock driver for the RF Level Detector.

Enable the chopper filter for RF Level Detector 1: Enable the chopper filter for RF Level Detector

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Bit

Symbol

Access

Value

Description

0: Disable the chopper filter for RF Level Detector

10

9

8

7:4

3:0

Bit

Symbol

Access

Value

Description

31:26

RESERVED

rw

0x00

Reserved

25

Enable calibration of temperature sensor 1

24

Enable calibration of temperature sensor 0

23

22

21

20 19:18

RFLD_COMP_ENABLE rw 0x00

RFLD_ENVDET_ENABLE rw 0x00

RFLD_VREF_ENABLE rw 0x00

Enable of RFLD comparator 0: Disable RFLD comparator 1: Enable RFLD comparator

Enable of RFLD envelope detector 1: Enable RFLD envelope detector 0: Disable RFLD envelope detector

Enable for RFLD reference voltage generator 1: Enable RFLD reference voltage generator

0: Disable RFLD reference voltage generator RFLD_REF_LO rw 0x03 RFLD_REF_HI rw 0x02

Table 78. PCR_TEMP_REG (address offset 0x18)

TEMP_ENABLE_CAL_1 rw 0x00

TEMP_ENABLE_CAL_0 rw 0x00

TEMP_ENABLE_HYST_1 rw 0x00

TEMP_ENABLE_HYST_0 rw 0x00

Higher reference value for RF level detector

Lower reference value for RF level detector

1: Enable calibration of temp erature sensor 1

0: Disable calibration of temperat ure sen sor 1

1: Enable calibration of temp erature sensor 0

0: Disable calibration of temperat ure sen sor 0

Enable Hystere of temperature sensor 1

1: Enable Hystere of temperature sensor 1

0: Disable Hystere of temperature sensor 1

Enable Hystere of temperature sensor 0

1: Enable Hystere of temperature sensor 0

0: Disable Hystere of temperature sensor 0

TEMP_ENABLE_1 rw 0x00

TEMP_ENABLE_0 rw 0x00

TEMP_DELTA_1 rw 0x01

Enable Temp Sensor 1

1: Enable Temp Sensor 1

0: Disable Temp Sensor 1

Enable Temp Sensor 0

1: Enable Temp Sensor 0

0: Disable Temp Sensor 0

Selects temperature thr esh old dete ctio n for tem perat ur e

sensor 1

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Bit

Symbol

Access

Value

Description

17:16 15:12

11:8

7:4

3:0

Bit

Symbol

Access

Value

Description

31:9

RESERVED

rw

0x00

Reserved

8:2

I2C_ADDR

rw

0x00

I2C address for wake-up

1

RESERVED

rw

0x00

Reserved

0

EN_INTERFACE

rw

0x00

1- Enable Wake-up host interface

Bit

Symbol

Access

Value

Description

31:23

RESERVED

rw

0x00

Reserved

22

EN_ADV_RFLD

rw

0x00

1: Enable advanced RFLD level detector FSM.

21

EN_VBUS_LOW

rw

0x00

1: Enable wake-up when vbus goes low

20:11

WUC_VALUE

rw

0x00

Wake-up timer value

10

EN_TVDD_MON

rw

0x00

1: Enable wake-up from TVDD 5 V monitor

9

1: Enable wake-up is TDA (CTUART) gives a level high 8

EN_CT_PR

rw

0x00

1: Enables wake-up if card is detected.

7

RESERVED

rw

0x00

Reserved

6

EN_PVDD_LIMITER

rw

0x00

1: Enables wake-up if PVDD current limiter is ris en

5

EN_GPIO_INT

rw

0x00

1: Enables wake-up if GPIO gives any input

4

EN_TEMP1

rw

0x00

1: Enable temperature 1 error Wake-up

3

EN_TEMP0

rw

0x00

1: Enable temperature 0 error Wake-up

2

EN_RFLDT

rw

0x00

1: Enable Wake-up RF level detector

1

RESERVED

rw

0x00

Set to “0”

0

EN_WUC

rw

0x00

1: Enable Wake-up timer

Bit

Symbol

Access

Value

Description

31:12

RESERVED

rw

0x00

Reserved

TEMP_DELTA_0 rw 0x01

Selects temperature thr esh old dete ctio n for temperature

sensor 0 TEMP_CAL_FINE_1 rw 0x08 TEMP_CAL_COURSE_1 rw 0x08 TEMP_CAL_FINE_0 rw 0x08 TEMP_CAL_COURSE_0 rw 0x08

Trim value fine for temperature sensor 1

Trim value course for temperature sensor 1

Trim value fine for temperature sensor 0

Trim value course for temperature sensor 0

Table 79. PCR_HOSTIF_WAKEUP_CFG_REG (address offset 0x1C)

Table 80. PCR_WAKEUP_CFG_REG (address offset 0x2 0)

EN_INT_AUX rw 0x00

Table 81. PCR_GPIO_WAKEUP_CFG_REG (address offset 0x24)

interrupt

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Bit

Symbol

Access

Value

Description

11:0

Enables wake-up by the corresponding GPIO

Bit

Symbol

Access

Value

Description

31

RESERVED

rw

0x00

Reserved

30

Indicator for USB_VBUS is ok

29

Indicator when VBUS > VBUSCritical when 28

Indicator for more than 3 V at PVDD_M pin

27

26

25:22

21:2

1

0

Bit

Symbol

Access

Value

Description

31:6

RESERVED

rw

0x00

Reserved

5

1: Enables the internal pulldown resistance to pul ldow n

4

Clearing Standby Prevention and Boot up register values

GPIO_WAKEUP_ENABLE rw 0x0FF

Table 82. PCR_BOOT_REG (address offset 0x28)

0: gpio1

1: GPIO2

e.t.c ….

USB_VBUS_OK r- 0x00

POK_VBUS r- 0x00

POK_PVDD_M_3V r- 0x00

POK_PVDD_3V r- 0x00 RESERVED r- 0x00 STBY_PREV_REASON r- 0x00 BOOT_REASON r- 0x00

POK_PVDD_M r- 0x00

POK_PVDD r- 0x00

1: USB_VBUS is available

VBUSMonitor is enabled

1: VBUS > VBUSCritical

0: VBUS < VBUSCritical

1: PVDD_M is available and over 3.3 V

0: PVDD_M is not over 3.3 V

Indicator for more than 3V at PVDD pin

1: PVDD is available and over 3.3 V

0: PVDD is not over 3.3 V

Reserved

Standby prevention reason

Boot up reason

Indicator if PVDD_m is available

1: PVDD_m is available and over 1.8 V

0: PVDD_m is not available

Indicator if PVDD is available

1: PVDD is available and over 1.8 V

0: PVDD is not available

Table 83. PCR_CTLR_REG (address offset 0x2C)

USB_VBUS_PULLDOWN rw 0x00

CLR_BOOT_REGS -x 0x00

the USB_VBUS

in the PCR_BOOT_REG register

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Bit

Symbol

Access

Value

Description

1: Clear the boot register

3

RESERVED

-x

0x00

Reserved

2

Enables entering suspend mode

1

entering standby mode

0

Bit

Symbol

Access

Value

Description

31

RESERVED

rw

0x00

Reserved

30

rw

0x00

1: EEPROM controller system clock gati ng enab le

29

rw

0x00

1: EEPROM controller page flash clock gating enab le

28

rw

0x00

1: EEPROM controller automatic clock gati ng enab le

27

IPCLOCK_CTIF_ENABLE

rw

0x00

1: Enable contact interfa ce IP clock

26

IPCLOCK_HSUART_ENAB

rw

0x00

1- Enable high speed UART IP clock

25

IPCLOCK_SPIM_ENABLE

rw

0x00

1: Enable SPI master UART IP clock

24

IPCLOCK_I2CM_ENABLE

rw

0x00

1: Enable I2C master UART IP clock

23

CLOCK_CTIF_ENABLE

rw

1: Enable contact source for Contact interface

22

I2CM_CLOCK_GATING_EN

rw

1: Enable clock source for I2C master

21

CPU_CLKREQ_ENABLE

rw

1: Enable the automatic clock request for ROM and RAM

20

AUTOMATIC_CLOCKSTOP

rw

1: Enable automatic clock gating for CRC, EECT R L,

19

CLOCK_SPIM_ENABLE

rw

1: Enable clock source for SPIM 18

RESERVED

rw

0x00

Reserved

17

CLOCK_HOSTIF_ENABLE

rw

1: Enable clock source for HOSTIF

SUSPEND -x 0x00

STANDBY -x 0x00

SOFT_RESET -x 0x00

Table 84. PCR_CLK_CFG_REG (address offset 0x30)

EECTRL_SYS_GATING_E NABLE

EECTRL_PF_GATING_EN ABLE

EECTRL_EEPROM_GATIN G_ENABLE

LE

1: Enter suspend mode

1: Enter standby mode

Trigger Soft Reset Source

1: Provide soft reset to the device

0: EEPROM controller system clock gati ng disable

0: EEPROM controller page flash clock gating disable

0: EEPROM controller automatic clock gati ng dis abl e

0: Disable contact interface IP clock

0: Disable high speed UART IP clock

ABLE

_AT_IDLE_ENABLE

0x01

0x00

0x01

0: Disable SPI master UART IP clock

0: Disable I2C master UART IP clock

0: Disable contact source for Contact interface

0: Disable clock source for I2C master

via the CPU

RNG and ROM when cpu is in idle mode

0: Disable clock source for SPIM

0: Disable clock source for HOSTIF

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Bit

Symbol

Access

Value

Description

16

CLOCK_TIMER_ENABLE

rw

1: Enable clock source for TIMER

15

CLOCK_CRC_ENABLE

rw

1: Enable clock source for CRC

14

CLOCK_CLKGEN_ENABLE

rw

1: Enable clock source for CLKGEN 13

RESERVED

rw

0x01

Set to “0”

12

CLOCK_RNG_ENABLE

rw

1: Enable clock source for RNG

11

CLOCK_CLIF_ENABLE

rw

1: Enable clock source for CLIF

10

LFO_EN

rw

1: Enable LFO 9:4

LFO_TRIMM

rw

0x20

Trim value for LFO

3

EN_SWIO_CLK

rw

2

SELECT_SCR_CTSEQ

rw

1:0

RESERVED

rw

0x01

0x00 0x00

0: Disable clock source for TIMER

0: Disable clock source for CRC

0: Disable clock source for CLKGEN

0: Disable clock source for RNG

0: Disable clock source for CLIF

0 -Disable LFO

1: Enables the SWIO clock

Selects the clock source for the system clock generati on

0 - clkXTAL (27.12 MHz)

1 - clkPLL/2 (24 MHz)

Reserved

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Bit

Symbol

Access

Value

Description

31:18

RESERVED

rw

0x00

Reserved

19

CTRL_TXLDO_CLK

rw

0x00

TXLDO clock division select. 0->LFO/2 , 1-> LFO

18

rw

Selects between XTAL clock and external clock.

17:16

rw

Selects ip clock divider value for hsuart.

15:14

rw

Selects ip clock divider value for spim.

13:12

rw

Selects ip clock divider value for spim.

11

CTSEQ_CLKSEL

rw

0x01

0: +10

10

EE_EEPROM_CLKSEL

rw

0x01

Selects the divider value for the lfo clock for the 9

EE_PF_FIX_CLKSEL

rw

0x01

Selects between divided xtal value

8:6

EE_PF_VAR_CLKSEL

rw

0x04

Selects between and xtal divided clocks for p age flash

5:4

SPARE_CELL_CLK_CFGL

rw

0x00

Spare cells to be used for clock config .

3:2

RESERVED

rw

0x00

Reserved

1:0

SYSTEM_CLOCK_SEL

rw

0x00

Selects the divider for the system clock.

Table 85. PCR_CLK_CFG2_REG (address offset 0x34)

EXT_CLK_SEL

HSUART_IP_CLKSEL

SPIM_IP_CLKSEL

0x00

0 - XTAL

1: external clock

00: xtal/1

01: xtal/2

10: xtal/4

11: RESERVED

00: xtal/1

01: xtal/2

10: xtal/4

11: RESERVED

I2CM_IP_CLKSEL

0x00

00: xtal/1

01 -.xtal/2

10: xtal/4

11: RESERVED

1: +82

EEPROM module

0: LFO/1

1: lfo/4

0: No clock

1: xtal-clk/32

module.

0: No clock

1: Xtal-clk/4

2: Xtal-clk/8

3: Xtal-c lk/16

4: Xtal-c lk/32

5: 7 RESERVED

00: Divby1

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Bit

Symbol

Access

Value

Description

01: DIVby2

Bit

Symbol

Access

Value

Description

31:28

RESERVED

-

0x00

Reserved

27

RESERVED

r-

0x00

Reserved

26

PADIN_CLK_AUX

r-

0x00

input value for CLK_AUX

25

PADIN_IO_AUX

r-

0x00

input value for IO_AUX

24

PADIN_INT_AUX

r-

0x00

input value for INT_AUX

23

PADIN_GPIO12

r-

0x00

input value for GPIO12

22

PADIN_GPIO11

r-

0x00

input value for GPIO11

21

PADIN_GPIO10

r-

0x00

input value for GPIO10

20

PADIN_GPIO9

r-

0x00

input value for GPIO9

19

PADIN_GPIO8

r-

0x00

input value for GPIO8

18

PADIN_GPIO7

r-

0x00

input value for GPIO7

17

PADIN_GPIO6

r-

0x00

input value for GPIO6

16

PADIN_GPIO5

r-

0x00

input value for GPIO5

15

PADIN_GPIO4

r-

0x00

input value for GPIO4

14

PADIN_GPIO3

r-

0x00

input value for GPIO3

13

PADIN_GPIO2

r-

0x00

input value for GPIO2

12

PADIN_GPIO1

r-

0x00

input value for GPIO1

11

PADIN_DWL_REQ

r-

0x00

input value for DWL_REQ

10

PADIN_MISO_M

r-

0x00

input value for MISO_M

9

PADIN_MOSI_M

r-

0x00

input value for MOSI_M

8

PADIN_SCLK_M

r-

0x00

input value for SCLK_M

7

PADIN_NSS_M

r-

0x00

input value for NSS_M

6

PADIN_SDA_M

r-

0x00

input Value SDA_M

5

PADIN_SCL_M

r-

0x00

input Value SCL_M

4

PADIN_IRQ

r-

0x00

input value for IRQ

3

PADIN_ATX_D

r-

0x00

input Value ATX_D

2

PADIN_ATX_C

r-

0x00

input Value ATX_C

1

PADIN_ATX_B

r-

0x00

input Value ATX_B

0

PADIN_ATX_A

r-

0x00

input Value ATX_A

Table 86. PCR_PADIN_REG (address offset 0x38)

10: DIVby4

11: Reserved

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Bit

Symbol

Access

Value

Description

31:29

RESERVED

-

0x00

Reserved

28

RESERVED

rw

0x00

Reserved

27

RESERVED

rw

0x00

Reserved

26

PADOUT_CLK_AUX

rw

0x00

output value for CLK_AUX

25

PADOUT_IO_AUX

rw

0x00

output value for IO_AUX

24

PADOUT_INT_AUX

rw

0x00

output value for INT_AUX

23

PADOUT_GPIO12

rw

0x00

output value for GPIO12

22

PADOUT_GPIO11

rw

0x00

output value for GPIO11

21

PADOUT_GPIO10

rw

0x00

output value for GPIO10

20

PADOUT_GPIO9

rw

0x00

output value for GPIO9

19

PADOUT_GPIO8

rw

0x00

output value for GPIO8

18

PADOUT_GPIO7

rw

0x00

output value for GPIO7

17

PADOUT_GPIO6

rw

0x00

output value for GPIO6

16

PADOUT_GPIO5

rw

0x00

output value for GPIO5

15

PADOUT_GPIO4

rw

0x00

output value for GPIO4

14

PADOUT_GPIO3

rw

0x00

output value for GPIO3

13

PADOUT_GPIO2

rw

0x00

output value for GPIO2

12

PADOUT_GPIO1

rw

0x00

output value for GPIO1

11

PADOUT_DWL_REQ

rw

0x00

output value for DWL_REQ

10

PADOUT_MISO_M

rw

0x00

output value for MISO_M

9

PADOUT_MOSI_M

rw

0x00

output value for MOSI_M

8

PADOUT_SCLK_M

rw

0x00

output value for SCLK_M

7

PADOUT_NSS_M

rw

0x00

output value for NSS_M

6

PADOUT_SDA_M

rw

0x00

output Value SDA_M

5

PADOUT_SCL_M

rw

0x00

output Value SCL_M

4

PADOUT_IRQ

rw

0x00

output value for IRQ

3

PADOUT_ATX_D

rw

0x00

output Value ATX_D

2

PADOUT_ATX_C

rw

0x00

output Value ATX_C

1

PADOUT_ATX_B

rw

0x00

output Value ATX_B

0

PADOUT_ATX_A

rw

0x00

output Value ATX_A

Bit

Symbol

Access

Value

Description

31:5

RESERVED

rw

0x00

Reserved

4

Select driver strength for ATX_A 3:2

ATX_A_PUPD

rw

0x00

Enable PullUp/Down on ATX_A

Table 87. PCR_PADOUT_REG (address offset 0x3C)

Table 88. PCR_PAD_ATX_A_REG (address offset 0x40)

ATX_A_SLEW_RATE rw 0x00

1: Enable slew for ATX_A

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Bit

Symbol

Access

Value

Description

10: Enable pull up 1

ATX_A_EN_OUT

rw

0x00

1: Enables output driver for ATX_A

0

ATX_A_EN_IN

rw

0x00

1: Enables input driver for ATX_A

Bit

Symbol

Access

Value

Description

31:5

RESERVED

rw

0x00

Reserved

4

Select driver strength for ATX_B

3:2

Enable Pull Up/Down on ATX_B

1

ATX_B_EN_OUT

rw

0x00

1: Enables output driver for ATX_B

0

ATX_B_EN_IN

rw

0x00

1: Enables input driver for ATX_B

Bit

Symbol

Access

Value

Description

31:5

RESERVED

rw

0x00

Reserved

4

Select driver strength for ATX_C

3:2

Enable pull Up/Down on ATX_C

1

ATX_C_EN_OUT

rw

0x00

1: Enables output driver for ATX_C

0

ATX_C_EN_IN

rw

0x00

1: Enables input driver for ATX_C

Bit

Symbol

Access

Value

Description

31:5

RESERVED

rw

0x00

Reserved

4

ATX_D_SLEW_RATE

rw

0x00

Select driver strength for ATX_D

3:2

Enable pull Up/Down on ATX_D

1

ATX_D_EN_OUT

rw

0x00

1: Enables output driver for ATX_D

0

ATX_D_EN_IN

rw

0x00

1: Enables input driver for ATX_D

Table 89. PCR_PAD_ATX_B_REG (address offset 0x44)

11: Enable pull down

ATX_B_SLEW_RATE rw 0x00

ATX_B_PUPD rw 0x00

Table 90. PCR_PAD_ATX_C_REG (address offset 0x48)

ATX_C_SLEW_RATE rw 0x00

ATX_C_PUPD rw 0x00

1: Enable slew for ATX_B

10: Enable pull up

11: Enable pull down

1: Enable slew for ATX_C

10: Enable pull up

11: Enable pull down

Table 91. PCR_PAD_ATX_D_REG (address offset 0x4C)

ATX_D_PUPD rw 0x00

10: Enable pull up

11: Enable pull down

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Bit

Symbol

Access

Value

Description

31:5

RESERVED

rw

0x00

Reserved

4

Select driver strength for DWLREQ

3:2

Enable pull Up/Down on DWLREQ

1

DWLREQ_EN_OUT

rw

0x00

1: Enables output driver for DWLREQ

0

DWLREQ_EN_IN

rw

0x01

1: Enables input driver for DWLREQ

Bit

Symbol

Access

Value

Description

31:8

RESERVED

rw

0x00

Reserved

7

Configures INT_AUX to be interpreted as active low

6

Puts the INT_AUX PAD in GPIO mode (By default in I2C

5

Enabling software register control for INT_AUX

4

Select Driver Strength for INT_AUX

3:2

Enable PullUp/Down on INT_AUX

1

INT_AUX_EN_OUT

rw

0x00

1: Enables output driver for INT_AUX

0

INT_AUX_EN_IN

rw

0x01

1: Enables input driver for INT_AUX

Bit

Symbol

Access

Value

Description

31:7

RESERVED

rw

0x00

Reserved

6

Puts the IO_AUX PAD in GPIO mode (By default in I2C

5

IO_AUX_SW_ENABLE

rw

0x00

1: Enabling software register control for IO_AUX

4

IO_AUX_SLEW_RATE

rw

0x00

Select Driver Strength for IO_AUX

Table 92. PCR_PADDWL_REQ_REG (address offset 0x5 0)

DWLREQ_SLEW_RATE rw 0x00

DWLREQ_PUPD rw 0x00

Table 93. PCR_PAD_INT_AUX_REG (address offset 0x54)

INT_AUX_ACTIVE_LOW_E N rw 0x00

INT_AUX_GPIOMODE_EN rw 0x00

INT_AUX_SW_ENABLE rw 0x00

1: Enable slew for DWL_REQ

10: Enable pull up

11: Enable pull down

signal

1: INT_AUX is active low

0: INT_AUX active high

mode)

1: Enable GPIO mode for INT_AUX pads

0: INT_AUX pad in functional mode

1: Enable software control for INT_AUX pad

INT_AUX_SLEW_RATE rw 0x00

INT_AUX_PUPD rw 0x00

Table 94. PCR_PAD_IO_AUX_REG (address offset 0x58)

IO_AUX_GPIOMODE_EN rw 0x00

1: Enable slew for INT_AUX pad

10: Enable Pull up

11: Enable Pull down

mode)

1: IO_AUX pad in GPIO mode

0: IO_AUX pad in functional mode

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Bit

Symbol

Access

Value

Description

1: Enable Slew for IO_AUX

3:2

Enable pull Up/Down on IO_AUX

1

IO_AUX_EN_OUT

rw

0x00

1: Enables output driver for IO_AUX

0

IO_AUX_EN_IN

rw

0x01

1: Enables input driver for IO_AUX

Bit

Symbol

Access

Value

Description

31:7

RESERVED

rw

0x00

Reserved

6

Enabling CLK_AUX pad in GPIO mode (By default in I2C

5

CLK_AUX_SW_ENABLE

rw

0x00

1: Enabling software register control for CLK_AUX

4

Select driver strength for CLK_AUX

3:2

Enable pull Up/Down on CLK_AUX

1

CLK_AUX_EN_OUT

rw

0x01

1: Enables output driver for CLK_AUX

0

CLK_AUX_EN_IN

rw

0x00

1: Enables input driver for CLK_AUX

Bit

Symbol

Access

Value

Description

31:5

RESERVED

rw

0x00

Reserved

4

Select driver strength for IRQ

3:2

Enable Pull Up/Down on IRQ

1

IRQ_EN_OUT

rw

0x01

1: Enables output driver for IRQ

0

IRQ_EN_IN

Rw

0x00

1: Enables input driver for IRQ

Bit

Symbol

Access

Value

Description

31:6

RESERVED

Rw

0x00

Reserved

5

RESERVED

Rw

0x00

Always set to “0”

IO_AUX_PUPD rw 0x00

Table 95. PCR_PAD_CLK_AUX_REG (address of fset 0x5C )

CLK_AUX_GPIOMODE_EN rw 0x00

10: Enable pull up

11: Enable pull down

mode)

1: CLK_AUX pad in GPIO mode

0: CLK_AUX pad in functional mode

CLK_AUX_SLEW_RATE rw 0x00

CLK_AUX_PUPD rw 0x00

Table 96. PCR_PADIRQ_REG (address offset 0x60)

IRQ_SLEW_RATE rw 0x00

IRQ_PUPD rw 0x00

1: Enable Slew for CLK_AUX

10: Enable pull up

11: Enable pull down

1: Enable slew for IRQ

10: Enable pull up

11: Enable pull down

Table 97. PCR_PADGPIO1_REG (address offset 0x64)

NXP Semiconductors

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Bit

Symbol

Access

Value

Description

4

Select driver strength for GPIO1

3:2

Enable pull Up/Down on GPIO1

1

GPIO1_EN_OUT

Rw

0x00

1: Enables output driver for GPIO1

0

GPIO1_EN_IN

Rw

0x01

1: Enables input driver for GPIO1

Bit

Symbol

Access

Value

Description

31:6

RESERVED

Rw

0x00

Reserved

5

RESERVED

Rw

0x00

Always set to “0”

4

Select driver strength for GPIO2

3:2

Enable pull Up/Down on GPIO2

1

GPIO2_EN_OUT

Rw

0x00

1: Enables output driver for GPIO2

0

GPIO2_EN_IN

Rw

0x01

1: Enables input driver for GPIO2

Bit

Symbol

Access

Value

Description

31:6

RESERVED

Rw

0x00

Reserved

5

RESERVED

Rw

0x00

Always set to “0”

4

Select Driver Strength for GPIO3

3:2

Enable pull Up/Down on GPIO3

1

GPIO3_EN_OUT

Rw

0x00

1: Enables output driver for GPIO3

0

GPIO3_EN_IN

Rw

0x01

1: Enables input driver for GPIO3

Bit

Symbol

Access

Value

Description

31:6

RESERVED

Rw

0x00

Reserved

5

RESERVED

Rw

0x00

Always set to “0”

4

Select driver strength for GPIO4

GPIO1_SLEW_RATE Rw 0x00

GPIO1_PUPD Rw 0x00

Table 98. PCR_PADGPIO2_REG (address offset 0x68)

GPIO2_SLEW_RATE Rw 0x00

GPIO2_PUPD Rw 0x00

1: Enable Slew for GPIO1

01: Enable pull up

11: Enable pull down

1: Enable slew for GPIO2

10: Enable pull up

11: Enable pull down

Table 99. PCR_PADGPIO3_REG (address offset 0x6C)

GPIO3_SLEW_RATE Rw 0x00

GPIO3_PUPD Rw 0x00

Table 100. PCR_PADGPIO4_REG (address offset 0x70)

GPIO4_SLEW_RATE Rw 0x00

1: Enable slew for GPIO3

10: Enable pull up

11: Enable pull down

1: Enable slew for GPIO4

NXP Semiconductors

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PN7462 family HW user manual

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User manual COMPANY PUBLIC

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Bit

Symbol

Access

Value

Description

3:2

Enable pull Up/Down on GPIO4

1

GPIO4_EN_OUT

rw

0x00

1: Enables output driver for GPIO4

0

GPIO4_EN_IN

rw

0x01

1: Enables input driver for GPIO4

Bit

Symbol

Access

Value

Description

31:5

RESERVED

Rw

0x00

Reserved

4

Select driver strength for GPIO5

3:2

Enable pull Up/Down on GPIO5

1

GPIO5_EN_OUT

rw

0x00

1: Enables output driver for GPIO5

0

GPIO5_EN_IN

rw

0x01

1: Enables input driver for GPIO5

Bit

Symbol

Access

Value

Description

31:5

RESERVED

rw

0x00

Reserved

4

Select driver strength for GPIO6

3:2

Enable Pull Up/Down on GPIO6

1

GPIO6_EN_OUT

rw

0x00

1: Enables output driver for GPIO6

0

GPIO6_EN_IN

rw

0x01

1: Enables input driver for GPIO6

Bit

Symbol

Access

Value

Description

31:5

RESERVED

rw

0x00

Reserved

4

Select driver strength for GPIO7

3:2

Enable Pull Up/Down on GPIO7

1

GPIO7_EN_OUT

rw

0x00

1: Enables output DRIVER for GPIO7

0

GPIO7_EN_IN

rw

0x01

1: Enables input driver for GPIO7

GPIO4_PUPD rw 0x00

Table 101. PCR_PADGPIO5_REG (address offset 0x74)

10: Enable pull up

11: Enable pull down

GPIO5_SLEW_RATE Rw 0x00

GPIO5_PUPD rw 0x00

Table 102. PCR_PADGPIO6_REG (address offset 0x78)

GPIO6_SLEW_RATE rw 0x00

GPIO6_PUPD rw 0x00

1: Enable slew for GPIO5

10: Enable pull up

11: Enable pull down

1: Enable slew for GPIO6

10: Enable pull up

11: Enable pull down

Table 103. PCR_PADGPIO7_REG (address offset 0x7C)

GPIO7_SLEW_RATE rw 0x00

GPIO7_PUPD rw 0x00

1: Enable Slew for GPIO7

10: Enable Pull up

11: Enable Pull down

NXP Semiconductors

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PN7462 family HW user manual

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User manual COMPANY PUBLIC

Rev. 1.4 — 14 May 2018

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100 of 345

Bit

Symbol

Access

Value

Description

31:5

RESERVED

rw

0x00

Reserved

4

Select driver strength for GPIO8

3:2

Enable pull Up/Down on GPIO8

1

GPIO8_EN_OUT

rw

0x00

1: Enables output driver for GPIO8

0

GPIO8_EN_IN

rw

0x01

1: Enables input driver for GPIO8

Bit

Symbol

Access

Value

Description

31:5

RESERVED

rw

0x00

Reserved

4

Select driver strength for GPIO9

3:2

Enable pull Up/Down on GPIO9

1

GPIO9_EN_OUT

rw

0x00

1: Enables output driver for GPIO9

0

GPIO9_EN_IN

rw

0x01

1: Enables input driver for GP IO9

Bit

Symbol

Access

Value

Description

31:5

RESERVED

rw

0x00

Reserved

4

Select driver strength for GPIO10

3:2

Enable pull Up/Down on GPIO10

1

GPIO10_EN_OUT

rw

0x00

1: Enables output driver for GPIO10

0

GPIO10_EN_IN

rw

0x01

1: Enables input driver for GPIO10

Bit

Symbol

Access

Value

Description

31:5

RESERVED

rw

0x00

Reserved

4

GPIO11_SLEW_RATE

rw

0x00

Select driver strength for GPIO11

Table 104. PCR_PADGPIO8_REG (address offset 0x80)

GPIO8_SLEW_RATE rw 0x00

GPIO8_PUPD rw 0x00

Table 105. PCR_PADGPIO9_REG (address offset 0x84)

GPIO9_SLEW_RATE rw 0x00

GPIO9_PUPD rw 0x00

1: Enable slew for GPIO8

10: Enable pull up

11: Enable pull down

1: Enable slew for GPIO9

10: Enable pull up

11: Enable pull down

Table 106. PCR_PADGPIO10_REG (address offset 0x88)

GPIO10_SLEW_RATE rw 0x00

GPIO10_PUPD rw 0x00

Table 107. PCR_PADGPIO11_REG (address offset 0x8C)

1: Enable slew for GPIO1 0

10: Enable pull up

11: Enable pull down

NXP Semiconductors PN7462, PN7362AUHN, PN7362AUEV, PN7360AUHN, PN7360AUEV User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. Introduction

1.1 General description

1.2 Features and benefit s

1.2.1 Integrated contact interface front-end

1.2.2 Integrated ISO/IEC 7816-3&4 UART interface

1.2.3 Integrated contactless interface f r ont end

1.2.4 Cortex M0 microcontroller

1.3 Derivates

1.3.1 PN7462AUEV features

1.3.2 PN7362AU features

1.3.3 PN7360AU features

1.4 Ordering information

1.5 Block diagram PN7462 HVQFN64

1.6 Block diagram PN7462 VFBGA64

1.7 Block diagram PN736X

2. PN7462 family memory

2.1 Memory mapping

2.2 On-chip flash memory map

2.3 EEPROM memory map

2.4 SRAM memory map

3. EEPROM CTRL module

3.1 EEPROM/Flash controller features

3.2 AHB interface

3.3 Memory map

3.4 EEPROM controller

3.4.1 Write operation

3.4.2 Read operation

3.5 Flash controller

3.5.1 Write operation

3.5.2 Read Operation

3.6 Register overview

3.7 Register description

4. Nested Vectored Inter rupt Controller (NVIC)

4.1 NVIC features

4.2 Interrupt sources

4.3 NVIC register support in the SCS

4.4 SWD

4.4.1 SWD features

4.4.2 SWD limitations

4.4.3 Hardware connection of SWD

5. SysTick Timer (SysTick)

6. PN7462 family Power management

6.1 Power supply

6.1.1 Microcontroller supply

6.1.2 Contactless reader supply

6.1.3 Contact reader supply

6.2 Power Management Uni t

6.2.1 Low Drop-Out regulators

6.2.1.1 Main LDO

6.2.1.2 PVDD_LDO

6.2.1.3 TXLDO Transmitter supply

6.2.1.4 VCC LDO

6.2.1.5 SCLDO

6.2.1.6 DC-to-DC converter

6.2.1.7 Start-up times of LDOs

6.3 PN7462 family PMU digital control unit

6.4 Interrupts

6.5 Temperature sensors

6.6 Voltage monitoring

6.6.1 VBUS monitor

6.6.2 PVDD LDO (VBUS2 ) monitor

6.6.3 VBUSP monitor

6.6.4 Latency of voltage monitors

6.7 Register overview and description

6.7.1 Detailed register description

6.7.1.1 PMU_STATUS_REG

6.7.1.2 PMU_BG_MON_CONTROL_REG

6.7.1.3 PMU_TXLDO_CONTROL_REG

6.7.1.4 PMU_LDO_CONTROL_REG

6.7.1.5 PMU_INTERRUPT_CLR_ENABLE_REG

6.7.1.6 PMU_INTERRUPT_SET_ENABLE_REG

6.7.1.7 PMU_INTERRUPT_STATUS_REG

6.7.1.8 PMU_INTERRUPT_ENABLE_REG

6.7.1.9 PMU_INTERRUPT_CLR_STATUS_REG

6.7.1.10 PMU_INTERRUPT_SET_STATUS_REG

6.7.2 TXLDO Register settings