NXP Semiconductors P89LPC952, P89LPC954 User Manual

UM10147

P89LPC952/954 User manual

Rev. 02 — 28 April 2008 User manual

Document information

Info Content Keywords P89LPC952, P89LPC954 Abstract Technical information for the P89LPC952/954 devices.

NXP Semiconductors

UM10147

P89LPC952/954 User manual

Revision history

Rev Date Description

02 20080428 Added LQFP48 package information 01 20070917 Initial version

Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

User manual Rev. 02 — 28 April 2008 2 of 134

NXP Semiconductors

1. Introduction

1.1 Pin configuration

UM10147

P89LPC952/954 User manual

P1.4/INT1

P5.7

P5.6

P5.5

P5.4

181920212223242526

P5.3

P1.3/INT0/SDA

P1.2/T0/SCL

P1.1/RXD0

P1.0/TXD0

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

Fig 1. PLCC44 pin configuration

P1.5/RST

P1.6

P89LPC952FA P89LPC954FA

P5.2

P5.1

P5.0

P1.7/AD04

P2.0/AD07

P4.6 P2.1/AD06

P4.7/TCLK

424140

002aab307

P4.4 P0.1/CIN2B/KBI1/AD00

P4.5/TDI P0.0/CMP2/KBI0/AD05

P4.2/TXD1 P0.3/CIN1B/KBI3/AD02

P4.3/RXD1 P0.2/CIN2A/KBI2/AD01

P0.4/CIN1A/KBI4/AD03

P0.5/CMPREF/KBI5

P0.6/CMP1/KBI6

P0.7/T1/KBI7

P2.2/MOSI

P2.3/MISO

P2.4/SS

P2.5/SPICLK

P4.0

P4.1/TRIG

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P1.4/INT1

P1.5/RST

P1.6

VSSP1.7/AD04

P2.0/AD07

P2.1/AD06

P0.0/CMP2/KBI0/AD05

P0.1/CIN2B/KBI1/AD00

P0.2/CIN2A/KBI2/AD01

4443424140393837363534

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P89LPC952/954 User manual

P0.3/CIN1B/KBI3/AD02

P5.7

P5.6

P5.5

P5.4

1213141516171819202122

P5.3

P1.3/INT0/SDA

P1.2/T0/SCL

P1.1/RXD0

P1.0/TXD0

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

Fig 2. LQFP44 pin configuration

P89LPC952FBD P89LPC954FBD

P5.1

P5.0

P5.2

P4.7/TCLK

P4.6

P4.4

P4.5/TDI

002aab306

P4.2/TXD1

P4.3/RXD1

P0.4/CIN1A/KBI4/AD03

P0.5/CMPREF/KBI5

P0.6/CMP1/KBI6

P0.7/T1/KBI7

P2.2/MOSI

P2.3/MISO

P2.4/SS

P2.5/SPICLK

P4.0

P4.1/TRIG

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P89LPC952/954 User manual

VREFN

P1.6

VSSP1.7/AD04

P2.0/AD07

P89LPC954FBD48

P5.1

P5.0

P4.6

P4.7/TCLK

P2.1/AD06

P0.0/CMP2/KBI0/AD05

P0.1/CIN2B/KBI1/AD00

P0.2/CIN2A/KBI2/AD01

P0.3/CIN1B/KBI3/AD02

P4.4

P4.5/TDI

P4.1/TRIG

P4.2/TXD1

P4.3/RXD1

P0.4/CIN1A/KBI4/AD03

P0.5/CMPREF/KBI5

P0.6/CMP1/KBI6

VREFP

P0.7/T1/KBI7

P2.2/MOSI

P2.3/MISO

P2.4/SS

P2.5/SPICLK

P2.6

P4.0

002aad095

P1.3/INT0/SDA

P1.2/T0/SCL

P1.1/RXD0

P1.0/TXD0

P2.7

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P5.7

P5.6

P5.5

P5.4

P1.4/INT1

P1.5/RST

4847464544434241403938

1314151617181920212223

P5.3

P5.2

Fig 3. LQFP48 pin configuration

1.2 Pin description

Table 1. Pin description

Symbol Pin Type Description

P0.0 to P0.7 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable

P0.0/CMP2/ KBI0/AD05

LQFP48 PLCC44 LQFP44

output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 5.1 “

The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described

below:

40 43 37 I/O P0.0 — Port 0 bit 0.

O CMP2 — Comparator 2 output. I KBI0 — Keyboard input 0. I AD05 — ADC0 channel 5 analog input.

Port configurations” .

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Table 1. Pin description

Symbol Pin Type Description

LQFP48 PLCC44 LQFP44

P0.1/CIN2B/ KBI1/AD00

P0.2/CIN2A/ KBI2/AD01

P0.3/CIN1B/ KBI3/AD02

P0.4/CIN1A/ KBI4/AD03

P0.5/CMPREF/ KBI5

P0.6/CMP1/ KBI6

P0.7/T1/KBI7313529I/OP0.7 — Port 0 bit 7.

P1.0 to P1.7 I/O, I

P1.0/TXD0 4 10 4 I/O P1.0 — Port 1 bit 0.

P1.1/RXD0393I/OP1.1 — Port 1 bit 1.

39 42 36 I/O P0.1 — Port 0 bit 1.

38 41 35 I/O P0.2 — Port 0 bit 2.

37 40 34 I/O P0.3 — Port 0 bit 3.

36 39 33 I/O P0.4 — Port 0 bit 4.

35 38 32 I/O P0.5 — Port 0 bit 5.

34 37 31 I/O P0.6 — Port 0 bit 6.

…continued

I CIN2B — Comparator 2 positive input B. I KBI1 — Keyboard input 1. I AD00 — ADC0 channel 0 analog input.

I CIN2A — Comparator 2 positive input A. I KBI2 — Keyboard input 2. I AD01 — ADC0 channel 1 analog input.

I CIN1B — Comparator 1 positive input B. I KBI3 — Keyboard input 3. I AD02 — ADC0 channel 2 analog input.

I CIN1A — Comparator 1 positive input A. I KBI4 — Keyboard input 4. I AD03 — ADC0 channel 3 analog input.

I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5.

O CMP1 — Comparator 1 output. I KBI6 — Keyboard input 6.

I/O T1 — Timer/counter 1 external count input or overflow

output.

I KBI7 — Keyboard input 7.

Port 1: Port 1 is an 8-bit I/O port with a user-configurable

[1]

output type, except for three pins as noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 5.1

“Port configurations”. P1.2 to P1.3 are open drain when used

as outputs. P1.5 is input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described

below:

O TXD0 — Transmitter output for serial port 0.

I RXD0 — Receiver input for serial port 0.

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Table 1. Pin description

…continued

Symbol Pin Type Description

LQFP48 PLCC44 LQFP44

P1.2/T0/SCL282I/OP1.2 — Port 1 bit 2 (open-drain when used as output).

I/O T0 — Timer/counter 0 external count input or overflow output

(open-drain when used as output).

C-bus serial clock input/output.

— External interrupt 0 input.

C-bus serial data input/output.

— External interrupt 1 input.

— External Reset input during power-on or maybe a

P1.3/INT0

P1.4/INT1

P1.5/RST

I/O SCL — I

/SDA171I/OP1.3 — Port 1 bit 3 (open-drain when used as output).

I INT0 I/O SDA — I

48 6 44 I/O P1.4 — Port 1 bit 4.

I INT1

47 5 43 I P1.5 — Port 1 bit 5 (input only).

I RST

reset input/output if selected via UCFG1 and UCFG2. When functioning as a reset input or input/output, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. When functioning as a reset output or input/output an internal reset source will drive this pin LOW. Also used during a power-on sequence to force ISP mode. When using an oscillator frequency above

12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until V

has reached its

specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V

falls below the minimum specified operating voltage.

P1.6 46 4 42 I/O P1.6 — Port 1 bit 6. P1.7/AD04 43 2 40 I/O P1.7 — Port 1 bit 7.

I AD04 — ADC0 channel 4 analog input.

P2.0 to P2.5 I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable

output type. During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 5.1 “

Port configurations”.

All pins have Schmitt triggered inputs. Port 2 also provides various special functions as described

below:

P2.0/AD07 42 1 39 I/O P2.0 — Port 2 bit 0.

I AD07 — ADC0 channel 7 analog input.

P2.1/AD06414438I/OP2.1 — Port 2 bit 1.

I AD06 — ADC0 channel 6 analog input.

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P89LPC952/954 User manual

Table 1. Pin description

Symbol Pin Type Description

LQFP48 PLCC44 LQFP44

P2.2/MOSI303428I/OP2.2 — Port 2 bit 2.

P2.3/MISO293327I/OP2.3 — Port 2 bit 3.

P2.4/SS

P2.5/SPICLK273125I/OP2.5 — Port 2 bit 5.

P2.6 26 - - I/O P2.6 — Port 2 bit 6. P2.7 5 - - I/O P2.7 — Port 2 bit 7. P3.0 to P3.1 I/O Port 3: Port 3 is a 2-bit I/O port with a user-co n fi g urable

P3.0/XTAL2/ CLKOUT

P3.1/XTAL1 6 1 1 5 I/O P3.1 — Port 3 bit 1.

P4.0 to P4.7 I/O Port 4: Port 4 is an 8-bit I/O port with a user-configurable

28 32 26 I/O P2.4 — Port 2 bit 4.

7126I/OP3.0 — Port 3 bit 0.

…continued

I/O MOSI — SPI master out slave in. When configured as

master, this pin is output; when configured as slave, this pin is input.

I/O MISO — When configured as master, this pin is input, when

configured as slave, this pin is output.

I/O SS

I/O SPICLK — SPI clock. When configured as master, this pin is

O XTAL2 — Output from the oscillator amplifier (when a crystal

O CLKOUT — CPU clock divided by 2 when enabled via SFR

I XTAL1 — Input to the oscillator circuit and internal clock

— SPI Slave select.

output; when configured as slave, this pin is input.

output type. During reset Port 3 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 5.1 “

All pins have Schmitt triggered inputs. Port 3 also provides various special functions as described

below:

oscillator option is selected via the flash configuration.

bit (ENCLK -TRIM.6). It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XT AL2 are used to generate clock source for the RTC/system timer.

generator circuits (when selected via the flash configuration). It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL 2 a re no t used to generate the clock for the RTC/system timer.

output type. During reset Port 4 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 4 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 5.1 “

All pins have Schmitt triggered inputs. Port 4 also provides various special functions as described

below:

Port configurations”.

User manual Rev. 02 — 28 April 2008 8 of 134

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P89LPC952/954 User manual

Table 1. Pin description

…continued

Symbol Pin Type Description

LQFP48 PLCC44 LQFP44

P4.0 25 30 24 I/O P4.0 — Port 4 bit 0. P4.1/TRIG242923I/OP4.1 — Port 4 bit 1.

O TRIG — Debugger trigger output.

P4.2/TXD1232822I/OP4.2 — Port 4 bit 2.

O TXD1 — Transmitter output for serial port 1.

P4.3/RXD1222721I/OP4.3 — Port 4 bit 3.

I RXD1 — Receiver input for serial port 1. P4.4 21 26 20 I/O P4.4 — Port 4 bit 4. P4.5/TDI 20 25 19 I/O P4.5 — Port 4 bit 5.

I/O TDI — Serial data input/output for debugger interface. P4.6 19 24 18 I/O P4.6 — Port 4 bit 6. P4.7/TCLK182317I/OP4.7 — Port 4 bit 7.

I TCLK — Serial clock input for debugger interface. P5.0 to P5.7 I/O Port 5: Port 5 is an 8-bit I/O port with a user-configurable

output type. During reset Port 5 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 5 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 5.1 “

Port configurations”.

All pins have Schmitt triggered inputs. Port 5 also provides various special functions as described

below:

P5.0 16 21 15 I/O P5.0 — Port 5 bit 0. High current output. P5.1 15 20 14 I/O P5.1 — Port 5 bit 1. High current output. P5.2 14 19 13 I/O P5.2 — Port 5 bit 2. High current output. P5.3 13 18 12 I/O P5.3 — Port 5 bit 3. High current output. P5.4 12 17 1 1 I/O P5.4 — Port 5 bit 4. High current output. P5.5 1 1 16 10 I/O P5.5 — Port 5 bit 5. High current output. P5.6 10 15 9 I/O P5.6 — Port 5 bit 6. High current output. P5.7 9 14 8 I/O P5.7 — Port 5 bit 7. High current output. V

17, 45 3, 22 16, 41 I Ground: 0 V reference. VREFN 44 - - negative ADC reference voltage V

8, 32 13, 36 7, 30 I Power supply: This is the power supply voltage for normal

operation as well as Idle and Power-down modes.

VREFP 33 - - positive ADC refe rence voltage

[1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.

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P89LPC952/954

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P89LPC952/954 User manual

ACCELERATED 2-CLOCK 80C51 CPU

P5[7:0]

P4[7:0]

P3[1:0]

P2[5:0]

P2[7:0]

P1[7:0]

P0[7:0]

8 kB/16 kB

CODE FLASH

256-BYTE

DATA RAM

256-BYTE

AUXILIARY RAM

PORT 5

CONFIGURABLE I/Os

PORT 4

CONFIGURABLE I/Os

PORT 3

CONFIGURABLE I/Os

(1)

(2)

PORT 2

CONFIGURABLE I/Os

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

WATCHDOG TIMER

AND OSCILLATOR

internal

bus

UART0

UART1

I2C-BUS

ADC0

SPI

REAL-TIME CLOCK/

SYSTEM TIMER

TIMER 0 TIMER 1

ANALOG

COMPARATORS

DEBUGGER INTERFACE

TXD0 RXD0

TXD1 RXD1

SCL SDA

AD00

AD02

AD04

AD06

SPICLK MOSI MISO SS

T0 T1

CMP2

CIN2A

CIN1A

TRIG TCLK TDI

AD01

AD03

AD05

AD07

CIN2B

CMP1

CIN1B

CRYSTAL

RESONATOR

XTAL1

XTAL2

PROGRAMMABLE

OSCILLATOR DIVIDER

CONFIGURABLE

OSCILLATOR

CPU clock

ON-CHIP RC

OSCILLATOR WITH

CLOCK DOUBLER

POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)

002aab305

(1) 44-pin package. (2) 48-pin package.

Fig 4. Block diagram

User manual Rev. 02 — 28 April 2008 10 of 134

NXP Semiconductors

1.3 Special function registers

Remark: SFR accesses are restricted in the following ways:

• User must not attempt to access any SFR locations not defined.

• Accesses to any defined SFR locations m ust be strictly for the functions for the SFRs.

• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

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P89LPC952/954 User manual

– ‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value

when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives.

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read. – ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

User manual Rev. 02 — 28 April 2008 11 of 134

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

User manual Rev. 02 — 28 April 2008 12 of 134

Table 2. Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

ACC* Accumulator E0H 00 0000 0000 AD0CON ADC0 control

AD0INS ADC0 input

AD0MODA ADC0 mode

AD0MODB ADC0 mode

AUXR1 Auxiliary

B* B register F0H 00 0000 0000 BRGR0_0 Baud rate

BRGR1_0 Baud rate

BRGCON_0 Baud rate

CMP1 Comparator 1

CMP2 Comparator 2

DIVM CPU clock

DPTR Data pointer

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

addr.

MSB LSB Hex Binary

Bit addressE7E6E5E4E3E2E1E0

97H ENBI0 ENADCI0 TMM0 EDGE0 ADCI0 ENADC0 ADCS01 ADCS00 00 0000 0000

A3H ADI07 ADI06 ADI05 ADI04 ADI03 ADI02 ADI01 ADI00 00 0000 0000

select

C0HBNDI0BURST0SCC0SCAN0----0000000000

A1HCLK2CLK1CLK0-----00000x0000

A2H CLKLP EBRR ENT1 ENT0 SRST 0 - DPS 00 0000 00x0 function register

Bit addressF7F6F5F4F3F2F1F0

BEH 00 0000 0000 generator 0 rate low

BFH 00 0000 0000 generator 0 rate high

BDH------SBRGS_0BRGEN_000 generator 0 control

ACH - - CE1 CP1 CN1 OE1 CO1 CMF1 00 control register

ADH - - CE2 CP2 CN2 OE2 CO2 CMF2 00 control register

95H 00 0000 0000 divide-by-M control

(2 bytes)

[2]

[1]

xxxx xx00

xx00 0000

NXP Semiconductors

P89LPC952/954 User manual

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User manual Rev. 02 — 28 April 2008 13 of 134

Table 2. Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

DPH Data pointer

DPL Data poi n te r

FMADRH Program flash

FMADRL Program flash

FMCON Program flash

FMDATA Program flash

I2ADR I

I2CON* I

I2DAT I

I2SCLH Serial clock

I2SCLL Serial clock

I2STAT I

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

high

low

address high

address low

control (Read) Program flash

control (Write)

data

C-bus slave address register

Bit address DF DE DD DC DB DA D9 D8

C-bus control register

C-bus data register

generator/SCL duty cycle register high

generator/SCL duty cycle register low

C-bus status register

Bit address AF AE AD AC AB AA A9 A8

…continued

Bit functions and addresses Reset value

addr.

83H 00 0000 0000

82H 00 0000 0000

E7H 00 0000 0000

E6H 00 0000 0000

E4H BUSY - - - HVA HVE SV OI 70 0111 0000

E4H FMCMD.7 FMCMD.6 FMCMD.5 FMCMD.4 FMCMD.3 FMCMD.2 FMCMD.1 FMCMD.0

E5H 00 0000 0000

DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC 00 0000 0000

D8H - I2EN STA STO SI AA - CRSEL 00 x000 00x0

DAH

DDH 00 0000 0000

DCH 00 0000 0000

D9H STA.4 STA.3 STA.2 STA.1 STA.0 0 0 0 F8 11111000

MSB LSB Hex Binary

NXP Semiconductors

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User manual Rev. 02 — 28 April 2008 14 of 134

Table 2. Special function registers …continued

* indicates SFRs that are bit addressable.

Name Description SFR

IEN0* Interrupt

IEN1* Interrupt

IEN2 Interrupt

IP0* Interrupt

IP0H Interrupt

IP1* Interrupt

IP1H Interrupt

IP2 Interrupt

IP2H Interrupt

KBCON Keypad control

KBMASK Keypad

KBPA TN Keypad pattern

P0* Port 0 80H T1/KB7 CMP1

P1* Port 1 90H - - RST

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Bit functions and addresses Reset value

addr.

A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0 EX0 00 0000 0000

enable 0

Bit address EF EE ED EC EB EA E9 E8

E8H - EST - - ESPI EC EKBI EI2C 00

enable 1

D5H - - - - EST1 ES1/ESR1 EADC - 00

enable 2

Bit address BF BE BD BC BB BA B9 B8

B8H - PWDRT PBO PS/PSR PT1 PX1 PT0 PX0 00

priority 0

B7H - PWDRTH PBOH PSH/

priority 0 high

Bit address FF FE FD FC FB FA F9 F8

F8H - PST - - PSPI PC PKBI PI2C 00

priority 1

F7H - PSTH - - PSPIH PCH PKBIH PI2CH 00

priority 1 high

D6H - - - - PEST1 PES1/

priority 2

D7H - - - - PEST1H PES1H/

priority 2 high

94H------PATN

86H 00 0000 0000 interrupt mask register

93H FF 1111 1111 register

Bit address8786858483828180

Bit address9796959493929190

MSB LSB Hex Binary

/KB6

CMPREF

/KB5

PT1H PX1H PT0H PX0H 00

PSRH

PADC - 00

PESR1

PADCH - 00

PESR1H

KBIF 00

_SEL

CIN1A

/KB4

CIN1B

/KB3

CIN2A

/KB2

CIN2B

/KB1

CMP2

/KB0

INT1 INT0/SDA T0/SCL RXD0 TXD0

NXP Semiconductors

[1]

00x0 0000

[1]

00x0 0000

[1]

x000 0000

[1]

x000 0000

[1]

00x0 0000

[1]

00x0 0000

[1]

00x0 0000

[1]

00x0 0000

[1]

xxxx xx00

P89LPC952/954 User manual

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[1]

User manual Rev. 02 — 28 April 2008 15 of 134

Table 2. Special function registers …continued

* indicates SFRs that are bit addressable.

Name Description SFR

P2* Port 2 A0H - - SPICLK SS

P3*Port3B0H------XTAL1XTAL2 P4 Port 4 B3H - TMS - - RXD1 TXD1 TRIG T3EX P5Port5B4HT3------P0M1 Port 0 output

P0M2 Port 0 output

P1M1 Port 1 output

P1M2 Port 1 output

P2M1 Port 2 output

P2M2 Port 2 output

P3M1 Port 3 output

P3M2 Port 3 output

PCON Power control

PCONA Power control

PSW* Program status

PT0AD Port 0 digital

RSTSRC Reset source

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Bit functions and addresses Reset value

addr.

Bit address9796959493929190

Bit addressB7B6B5B4B3B2B1B0

84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF mode 1

85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00 mode 2

91H (P1M1.7) (P1M1.6) - (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3 mode 1

92H (P1M2.7) (P1M2.6) - (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00 mode 2

A4H - - (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0) FF

mode 1

A5H - - (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0) 00

mode 2

B1H------(P3M1.1)(P3M1.0)03xxxx xx11

mode 1

B2H------(P3M2.1)(P3M2.0)00

mode 2

87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 0000 0000 register

B5H RTCPD - VCPD ADPD I2PD SPPD SPD - 00

Bit addressD7D6D5D4D3D2D1D0

D0H CY AC F0 RS1 RS0 OV F1 P 00 0000 0000

word

F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 xx00 000x

input disable

DFH - - BOF POF R_BK R_WD R_SF R_EX

MSB LSB Hex Binary

MISO MOSI - -

NXP Semiconductors

[1]

[1] [1] [1]

[1]

1111 1111

[1]

0000 0000

[1]

11x1 xx11

[1]

00x0 xx00

[1]

1111 1111

[1]

0000 0000

[1]

xxxx xx00

P89LPC952/954 User manual

[1]

0000 0000

UM10147

[3]

User manual Rev. 02 — 28 April 2008 16 of 134

Table 2. Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

RTCCON RTC control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60 RTCH RTC register

RTCL RTC register

S0ADDR Serial port

S0ADEN Serial port

S0BUF Serial Port data

S0CON* Serial port

S0STAT Serial port

SP Stack pointer 81H 07 0000 0111 SPCTL SPI control

SPSTAT SPI status

SPDAT SPI data

S1CON Serial port 1

S1STAT Serial port 1

TAMOD Timer 0 and 1

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

…continued

Bit functions and addresses Reset value

addr.

D2H 00

high

D3H 00

low

A9H 00 0000 0000 address register

B9H 00 0000 0000 address enable

99H xx xxxx xxxx

buffer register

Bit address 9F 9E 9D 9C 9B 9A 99 98

98H SM0_0/FE_0SM1_00 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00 0000 0000

control

BAH DBMOD_0 INTLO_0 CIDIS_0 DBISEL_0 FE_0 BR_0 OE_0 STINT_0 00 0000 0000 extended status register

E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 04 0000 0100

E1HSPIFWCOL------0000xxxxxx

E3H 00 0000 0000

B6H SM0_1/FE_1SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00 0000 0000

control

D4H DBMOD_1 INTLO_1 CIDIS_1 DBISEL_1 FE_1 BR_1 OE_1 STINT_1 00 0000 0000 extended status register

8FH - - - T1M2 - - - T0M2 00 xxx0 xxx0 auxiliary mode

Bit address 8F 8E 8D 8C 8B 8A 89 88

MSB LSB Hex Binary

[1][6] [6]

[6]

NXP Semiconductors

011x xx00 0000 0000

0000 0000

P89LPC952/954 User manual

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User manual Rev. 02 — 28 April 2008 17 of 134

Table 2. Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

TCON* Timer 0 and 1

TH0 Timer 0 high 8CH 00 0000 0000 TH1 Timer 1 high 8DH 00 0000 0000 TL0 Timer 0 low 8AH 00 0000 0000 TL1 Timer 1 low 8BH 00 0000 0000 TMOD Timer 0 and 1

TRIM Internal

WDCON Watchdog

WDL Watchdog load C1H FF 1111 1111 WFEED1 Watchdog

WFEED2 Watchdog

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

…continued

Bit functions and addresses Reset value

addr.

88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 0000 0000

control

89H T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 0000 0000

mode

96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 oscillator trim register

A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK

control register

C2H

feed 1

C3H

feed 2

MSB LSB Hex Binary

[5] [6]

[4] [6]

NXP Semiconductors

[1] All ports are in input only (high-impedance) state after power-up. [2] BRGR1_0 and BRGR0_0 must only be written if BRGEN_0 in BRGCON_0 SFR is logic 0. If any are written while BRGEN_0 = 1, the result is unpredictable. [3] The RSTSRC register reflects the cause of the UM10147 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is

xx110000.

[4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

Other resets will not affect WDTOF. [5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [6] The only reset source that affects these SFRs is power-on reset.

P89LPC952/954 User manual

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User manual Rev. 02 — 28 April 2008 18 of 134

Table 3. Extended special function registers

Name Description SFR

ADC0HBND ADC0 high_boundary register,

ADC0LBND ADC0 low_boundary register

AD0DAT0R ADC0 data register 0, right

AD0DAT0L ADC0 data register 0, left

AD0DAT1R ADC0 data register 1, right

AD0DAT1L ADC0 data register 1, left

AD0DAT2R ADC0 data register 2, right

AD0DAT2L ADC0 data register 2, left

AD0DAT3R ADC0 data register 3, right

AD0DAT3L ADC0 data register 3, left

AD0DAT4R ADC0 data register 4, right

AD0DAT4L ADC0 data register 4, left

AD0DAT5R ADC0 data register 5, right

AD0DAT5L ADC0 data register 5, left

AD0DAT6R ADC0 data register 6, right

AD0DAT6L ADC0 data register 6, left

AD0DAT7R ADC0 data register 7, right

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

left (MSB)

(MSB)

(LSB)

(MSB)

(LSB)

(MSB)

(LSB)

(MSB)

(LSB)

(MSB)

(LSB)

(MSB)

(LSB)

(MSB)

(LSB)

(MSB)

(LSB)

Bit functions and addresses Reset value

addr.

FFEFH FF 1111 1111

FFEEH 00 0000 0000

FFFEH AD0DAT0[7:0] 00 0000 0000

FFFFH AD0DAT0[9:2] 00 0000 0000

FFFCH AD0DAT1[7:0] 00 0000 0000

FFFDH AD0DAT1[9:2] 00 0000 0000

FFFAH AD0DAT2[7:0] 00 0000 0000

FFFBH AD0DAT2[9:2] 00 0000 0000

FFF8H AD0DAT3[7:0] 00 0000 0000

FFF9H AD0DAT3[9:2] 00 0000 0000

FFF6H AD0DAT4[7:0] 00 0000 0000

FFF7H AD0DAT4[9:2] 00 0000 0000

FFF4H AD0DAT5[7:0] 00 0000 0000

FFF5H AD0DAT5[9:2] 00 0000 0000

FFF2H AD0DAT6[7:0] 00 0000 0000

FFF3H AD0DAT6[9:2] 00 0000 0000

FFF0H AD0DAT7[7:0]

MSB LSB Hex Binary

NXP Semiconductors

P89LPC952/954 User manual

UM10147

User manual Rev. 02 — 28 April 2008 19 of 134

Table 3. Extended special function registers

Name Description SFR

AD0DAT7L ADC0 data register 7, left

BNDSTA0 ADC0 boundary status register FFEDH BRGCON_1 Baud rate generator 1 control FFB3H - - - - - - SBRGS_1BRGEN_100

BRG0_1 Baud rate generator 1 rate low FFB4H BRG1_1 Baud rate generator 1 rate high FFB5H FREEZE Peripheral clock freeze FFD0H - - - RTC_F - WDT_F T1_F T0_F 00 xxx0 0000 P4M1 Port 4 output mode 1 FFB8H (P4M1.7) (P4M1.6) (P4M1.5) (P4M1.4) (P4M1.3) (P4M1.2) (P4M1.1) (P4M1.0) FF P4M2 Port 4 output mode 2 FFB9H (P4M2.7) (P4M2.6) (P4M2.5) (P4M2.4) (P4M2.3) (P4M2.2) (P4M2.1) (P4M2.0) 00 P5M1 Port 5 output mode 1 FFBAH (P5M1.7) (P5M1.6) (P5M1.5) (P5M1.4) (P5M1.3) (P5M1.2) (P5M1.1) (P5M1.0) FF P5M2 Port 5 output mode 3 FFBBH (P5M2.7) (P5M2.6) (P5M2.5) (P5M2.4) (P5M2.3) (P5M2.2) (P5M2.1) (P5M2.0) 00 S1ADDR Serial port 1 address register FFB2H 00 0000 0000 S1ADEN Serial port 1 address enable FFB1H 00 0000 0000 S1BUF Serial port 1 data buffer

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

…continued

Bit functions and addresses Reset value

addr.

FFF1H AD0DAT7[9:2]

(MSB)

FFB0H xx xxxx xxxx

MSB LSB Hex Binary

[2]

xxxx xx00

[1]

1111 1111

[1]

0000 0000

[1]

1111 1111

[1]

0000 0000

NXP Semiconductors

[1] Extended SFRs are physically located on-chip but logically located in external data memory address space (XDATA). The MOVX A,@DPTR and MOVX @DPTR,A instructions are

used to access these extended SFRs. [2] BRGR1_1 and BRGR0_1 must only be written if BRGEN_1 in BRGCON_1 SFR is logic 0. If any are written while BRGEN_1 = 1, the result is unpredictable.

P89LPC952/954 User manual

UM10147

NXP Semiconductors

1.4 Memory organization

FF00h

FFEFh

1FFFh

1E00h

1C00h

1BFFh

1800h

17FFh

1400h

13FFh

1000h

0FFFh

0C00h

0BFFh

0800h

07FFh

0400h

03FFh

0000h

IAP entry-

points

ISP CODE

(512B)*

SECTOR 7

SECTOR 6

SECTOR 5

SECTOR 4

SECTOR 3

SECTOR 2

SECTOR 1

SECTOR 0

Read-protected

IAP calls only

IDATA routines

entry points for:

-51 ASM. code

-C code

ISP serial loader

entry points for:

-UART (auto-baud)

-I2C, SPI, etc.*

Flexible choices:

-as supplied (UART)

-Philips libraries*

-user-defined

FFEFh

FF1Fh

FF00h

1FFFh

1E00h

entry points

SPECIAL FUNCTION

REGISTERS

(DIRECTLY ADDRESSABLE)

UM10147

P89LPC952/954 User manual

IDATA (incl. DATA)

128 BYTES ON-CHIP

DATA MEMORY (STACK

AND INDIR. ADDR.)

DATA

128 BYTES ON-CHIP

DATA MEMORY (STACK,

DIRECT AND INDIR. ADDR.)

4 REG. BANKS R[7:0]

data memory

(DATA, IDATA)

002aaa948

Fig 5. P89LPC952 memory map - P89LPC954 is similar

The various P89LPC952/954 memory spaces are as follows: DATA — 128 bytes of internal data memory space (00h:7Fh) accessed via direct or

indirect addressing, using instruction other than MOVX and MOVC. All or part of the Stack may be in this area.

IDATA — Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.

SFR — Special Function Registers. Sele cted CPU registers and peripheral control and status registers, accessible only via direct addressing.

XDATA — ‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the DPTR, R0, or R1. All or part of this space could be implemented on-chip. The P89LPC952/954 has 256 bytes of on-chip XDATA memory.

CODE — 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC952/954 has 8 kB/ 16 kB of on-chip Code memory.

Table 4. Data RAM arrangement

Type Data RAM Size (bytes)

DATA Directl y an d indirectly addressable memory 128 IDATA Indirectly addressable memory 256 XDATA Indirectly addressable using MOVX, MOVC, DPTR, R0, R1 256

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NXP Semiconductors

The P89LPC952/954 is a single-chip microcontroller designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC952/954 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC952/954 in order to reduce component count, board space, and system cost

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P89LPC952/954 User manual

User manual Rev. 02 — 28 April 2008 21 of 134

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2. Clocks

2.1 Enhanced CPU

The P89LPC952/954 uses an enhanced 80C51 CPU which ru ns at six times the spee d of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

2.2 Clock definitions

The P89LPC952/954 device has several internal clocks as defined below: OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock

sources and can also be optionally divided to a slower frequency (see Figure 6

Section 2.8 “

OSCCLK frequency. CCLK — CPU clock; output of the DIVM clock divider. There are two CCLK cycles per

machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output. PCLK — Clock for the various peripheral devices and is

P89LPC952/954 User manual

CPU Clock (CCLK) modification: DIVM register”). Note: f

CCLK

⁄

UM10147

and

is defined as the

osc

2.2.1 Oscillator Clock (OSCCLK)

The P89LPC952/954 provides several user-selectable oscillator options. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the FLASH is programmed and include an on -chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source. The crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 18 MHz.

2.2.2 Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration.

2.2.3 Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.

2.2.4 High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this configuration. When using a clock frequency

above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until V specified level. When system power is removed V specified operating voltage. When using a clock frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V requirements for clock frequencies above 12 MHz do not apply when using the internal RC oscillator in clock doubler mode.

falls below the minimum specified operating voltage. These

has reached its

will fall below the minimum

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NXP Semiconductors

2.3 Clock output

The P89LPC952/954 supports a user-selectable clock output function on the XTAL2 / CLKOUT pin when the crystal oscillator is not being used. This condition occurs if a different clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on X1) and if the Real-time Clock is not using the crystal oscillator as its clock source. This allows external devices to synchronize to the P89LPC9 52/954 . This output is enabled by the ENCLK bit in the TRIM register

UM10147

P89LPC952/954 User manual

The frequency of this clock output is

⁄

that of the CCLK. If the clock output is not needed

in Idle mode, it may be turned off prior to entering Idle, saving additional power. Note: on reset, the TRIM SFR is initialized with a factory preprogrammed value. Therefore when setting or clearing the ENCLK bit, the user should retain the contents of other bits of the TRIM register. This can be done by reading the contents of the TRIM register (into the ACC for example), modifying bit 6, and writing this result back into the TRIM register. Alternatively, the ‘ANL direct’ or ‘ORL direct’ instructions can be used to clear or set bit 6 of the TRIM register.

2.4 On-chip RC oscillator option

The P89LPC952 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz ± 1 % at room temperature. (Note: the initial value is better than 1 %; please refer to the P89LPC952/954 data sheet for behavior over temperature). End user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. Increasing the TRIM value will decrease the oscillator frequency. When the clock doubler option is enabled (UCFG1.3 = 1), the output frequency is doubled. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing highest performance access. This bit can then be se t in software if CCLK is runni ng at 8 MHz or slower.

The requirements in Section 2.2.4 “ an external reset input and using an external reset circuit when the clock freq uency is greater than 12 MHz do not apply when using the internal RC oscillator’s clock doubler option.

Table 5. On-chip RC oscillator trim register (TRIM - address 96h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 Reset 0 0 Bits 5:0 loaded with factory stored value during reset.

High speed oscillator option” for configuring P1.5 as

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P89LPC952/954 User manual

Table 6. On-chip RC oscillator trim register (TRIM - address 96h) bit description

Bit Symbol Description

0 TRIM.0 Trim value. Determines the frequency of the internal RC oscillator. During reset, 1TRIM.1 2TRIM.2 3TRIM.3 4TRIM.4 5TRIM.5 6 ENCLK when = 1,

7 RCCLK when = 1, selects the RC Oscillator output as the CPU clock (CCLK). This allows for

these bits are loaded with a stored factory calibration value. When writing to either bit 6 or bit 7 of this register, care should be taken to preserve the current TRIM value by reading this register, modifying bits 6 or 7 as required, and writing the result to this register.

CCLK

⁄

is output on the XTAL2 pin provided the crystal oscillator is not

being used.

fast switching between any clock source and the internal RC oscillator without needing to go through a reset cycle.

2.5 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.

2.6 External clock input option

In this configuration, the processor clock is derived from an external source driving the XT AL1 / P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2 / P3.0 pin may be used as a standard port pin or a clock output.

When using an external clock input frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until V removed V

will fall below the minimum specified operating voltage. When using

has reached its specified level. When syst em power is

an external clock input frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V

falls below the minimum specified operating voltage. These requirements for clock frequencies above 12 MHz do not apply when using the internal RC oscillator in clock doubler mode.

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NXP Semiconductors

Fig 6. Using the crystal oscillator.

UM10147

P89LPC952/954 User manual

quartz crystal or

ceramic resonator

P89LPC952/954

XTAL1

(1)

XTAL2

002aad364

Note: The oscillator must be configured in one of the following modes: Low frequency crystal, medium frequency crystal, or high frequency crystal.

(1) A series resistor may be required to limit crystal drive levels. This is especially important for low

frequency crystals (see text).

XTAL1

XTAL2

RC OSCILLATOR

WITH CLOCK DOUBLER

(7.3728 MHz/14.7456 MHz ± 1 %)

(400 kHz +30 % −20 %)

HIGH FREQUENCY

MEDIUM FREQUENCY

LOW FREQUENCY

WATCHDOG

OSCILLATOR

RCCLK

OSCCLK

TIMER 0 AND

DIVM

TIMER 1

RCCLK

PCLK

RTC

ADC0

CCLK

÷2

PCLK

SPI

CPU

WDT

UARTSI2C-BUS

002aab409

Note: The oscillator must be configured in one of the following modes: Low frequency crystal, medium frequency crystal, or high frequency crystal.

(1) A series resistor may be required to limit crystal drive levels. This is especially important for low frequency crystals (see text).

Fig 7. Block diagram of oscillator control.

2.7 Oscillator Clock (OSCCLK) wake-up delay

The P89LPC952/954 has an internal wake-up timer that delays the clock until it stabilizes depending to the clock source used. If the clock source is any of the three crystal selections, the delay is 992 OSCCLK cycles plus 60 μs to 100 μs. If the clock source is either the internal RC oscillator or the Watchdog oscillator, the delay is 224 OSCCLK cycles plus 60 μs to 100 μs.

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NXP Semiconductors

2.8 CPU Clock (CCLK) modification: DIVM register

The OSCCLK frequency can be divided down, by an integer, up to 510 times by configuring a dividing register, DIVM, to provide CCLK. This produces the CCLK frequency using the following formula:

UM10147

P89LPC952/954 User manual

Where: f Since N ranges from 0 to 255, the CCLK frequency can be in the range of f

(for N = 0, CCLK = f This feature makes it possible to temporarily run the CPU at a lower rate, reducing power

consumption. By dividing the clock, the CPU can retain the ability to respond to events other than those that can cause interrupts (i.e. events that allow exiting the Idle mode) by executing its normal program at a lower rate. This can often result in lower power consumption than in Idle mode. This can allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.

2.9 Low power select

The P89LPC952/954 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance. This bit can then be set in software if CCLK is running at 8 MHz or slower.

3. A/D converter

CCLK frequency = f

is the frequency of OSCCLK, N is the value of DIVM.

osc

/ (2N)

osc

to f

osc

/510.

3.1 General description

The P89LPC952/954 has a 10-bit, 8-channel multiplexed successive approximation analog-to-digital converter module. A block diagram of the A/D converter is shown in

Figure 8

providing an input signal to one of two comp arator inpu ts. The contro l logic in combinati on with the SAR drives a digital-to-analog converter which provides the other input to the comparator. The output of the comparator is fed to the SAR.

. The A/D consists of an 8-input multiplexer which feeds a sample-and-hold circuit

3.2 A/D features

• 10-bit, 8-channel multiplexed input, successive approximation A/D converter.

• Eight result register pairs.

• Six operating modes

– Fixed channel, single conversion mode – Fixed channel, continuous conversion mode – Auto scan, single conversion mode – Auto scan, continuous conversion mode – Dual channel, continuous conversion mode – Single step mode

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NXP Semiconductors

• Three conversion start modes

• 10-bit conversion time of 4μs at an A/D clock of 9 MHz

• Interrupt or polled operation

• High and low boundary limits interrupt

• Clock divider

• Power down mode

– Timer triggered start – Start immediately – Edge triggered

INPUT

MUX

comp

–

DAC0

UM10147

P89LPC952/954 User manual

SAR

CONTROL

LOGIC

Fig 8. ADC block diagram.

3.2.1 A/D operating modes

3.2.1.1 Fixed channel, single conversion mode

A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register pair which corresponds to the selected input channel (see Table 7 conversion completes. The input channel is selected in the ADINS register. This mode is selected by setting the SCAN0 bit in the ADMODA register.

T able 7. Input channels and result registers for fixed channel single, auto scan single, and

auto scan continuous conversion modes

Result register Input channel Result register Input channel

AD0DAT0R/L AD00 AD0DAT4R/L AD04 AD0DAT1R/L AD01 AD0DAT5R/L AD05 AD0DAT2R/L AD02 AD0DAT6R/L AD06 AD0DAT3R/L AD03 AD0DAT7R/L AD07

3.2.1.2 Fixed channel, continuous conversion mode

A single input channel can be selected for continuous conversion. The results of the conversions will be sequentially placed in the eight result register pairs (see Table 8 user may select whether an interrupt can be generated after every four or every eight

). An interrupt, if enabled, will be generated after the

CCLK

002aab10

). The

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NXP Semiconductors

conversions. Additional conversion results will again cycle through the result register pairs, overwriting the previous results. Continuous conversions continue until terminated by the user. This mode is selected by setting the SCC0 bit in the ADMODA register.

T able 8. Result registers and conversion results for fixed channel, continuous conversion

Result register Contains

AD0DAT0R/L Selected channel, first conversion result AD0DAT1R/L Selected channel, second conversion result AD0DAT2R/L Selected channel, third conversion result AD0DAT3R/L Selected channel, fourth conversion result AD0DAT4R/L Selected channel, fifth conversion result AD0DAT5R/L Selected channel, sixth conversion result AD0DAT6R/L Selected channel, seventh conversion result AD0DAT7R/L Selected channel, eighth conversion result

3.2.1.3 Auto scan, single conversion mode

Any combination of the eight input channels can be selected for conversion by setting a channel’s respective bit in the ADINS register. A single conversion of each selected input will be performed and the result placed in the result register pair which corresponds to the selected input channel (see Table 7 enabled, will be generated after either the first four conversions have occurred or all selected channels have been converted. If the user selects to generate an interrupt after the first four input channels have been converted, a second interrupt will be generated after the remaining input channels have been converted. If only a single channel is selected this is equivalent to single channel, single conversion mode. The channels are converted from LSB to MSB order (in ADINS). This mode is selected by setting the SCAN0 bit in the ADMODA register.

UM10147

P89LPC952/954 User manual

mode

). The user may select whether an interrupt, if

3.2.1.4 Auto scan, continuous conversion mode

Any combination of the eight input channels can be selected for conversion by setting a channel’s respective bit in the ADINS register. A conversion of each selected input will be performed and the result placed in the result register pair which corresponds to the selected input channel (See Table 7

). The user may select whether an interrupt, if enabled, will be generated after either the first four conversions have occurred or all selected channels have been converted. If the user selects to generate an interrupt after the four input channels have been converted, a second interrupt will be generated after the remaining input channels have been converted. Afte r all selected channels have been converted, the process will repeat starting with the first selected channel. Additional conversion results will again cycle through the eight result register pairs, overwriting the previous results. Continuous conversions continue until terminated by the user. The channels are converted from LSB to MSB order (in ADINS). This mode is selected by setting the BURST0 bit in the ADMODA register.

3.2.1.5 Dual channel, continuous conversion mode

This is a variation of the auto scan continuous conversion mode where conversio n occurs on two user-selectable inputs. Any combination of two of the eight input channels can be selected for conversion. The result of the conversion of the first channel is placed in the result register pair, AD0DAT0R and AD0DAT0L. The result of the conversion of the

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second channel is placed in result register pair, AD0DAT1R and AD0DAT1L. The first channel is again converted and its result stored in AD0DAT2R and AD0DAT2L. The second channel is again converted and its result placed in AD0DAT3R and AD0DAT3L, etc. (see Table 9 conversions (user selectable). This mode is selected by setting the SCC0 bit in the ADMODA register.

Table 9. Result registers and conversion results for dual channel, continuous conversion

Result register Contains

AD0DAT0R/L First channel, first conversion result AD0DAT1R/L Second channel, first conversion result AD0DAT2R/L First channel, second conversion result AD0DAT3R/L Second channel, second conversion result AD0DAT4R/L First channel, third conversion result AD0DAT5R/L Second channel, third conversion result AD0DAT6R/L First channel, fourth conversion result AD0DAT7R/L Second channel, fourth conversion result

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). An interrupt is generated, if enabled, after every set of four or eight

mode

3.2.1.6 Single step mode

This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any combination of the eight input channels can be selected for conversion. After each channel is converted, an interrupt is generated, if enabled, and the A/D waits for the next start condition. The result of each channel is placed in the result register which corresponds to the selected input channel (See Table 7 start modes. This mode is selected by clearing the BURST0, SCC0, and SCAN0 bits in the ADMODA register.

3.2.2 Conversion mode selection bits

The A/D uses three bits in ADMODA to select the conversio n mode . T hese mod e bits are summarized in Table 10 combinations shown, are undefined.

Table 10. Conversion mode bits

Burst0 SCC0 Scan0 ADC0 conversion mode

0 0 0 Single step 0 0 1 Fixed channel, single

0 1 0 Fixed channel, continuous

1 0 0 Auto scan, continuous

,below. Combinations of the three bits, other than the

). May be used with any of the

Auto scan, single

Dual channel, continuous

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3.2.3 Conversion start modes

3.2.3.1 Timer triggered start

An A/D conversion is started by the overflow of Timer 0. Once a conversion has started, additional Timer 0 triggers are ignored until the conversion has completed. The Timer triggered start mode is available in all A/D operating modes.This mode is selected by the TMMx bit and the ADCS01 and ADCS00 bits (see Table 12

3.2.3.2 Start immediately

Programming this mode immediately start s a conversion.Th is start mode is avai lable in all A/D operating modes.This mode is selected by setting the ADCS01 and ADCS00 bits in the ADCON0 register (See Table 12

3.2.3.3 Edge triggered

An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has started, additional edge triggers are ignored until th e conversion has completed. The edge triggered start mode is available in all A/D operating modes.This mode is selected by setting the ADCS01 and ADCS00 bits in the ADCON0 register (See Table 12

Table 14

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and Table 14).

and

3.2.4 Stopping and restarting conversions

An A/D conversion or set of conversions can be stopped by clearing the ADCS01 and ADCS00 bits in ADCON0 (and also theTMM0 bit in ADCON0 if the conversion was started in Timer triggered mode). Prior to resuming conversions, the user will need to reset the input multiplexer to the first user specified channel. This can be accomplished by writing the ADINS register with the desired channels.

3.2.5 Boundary limits interrupt

The A/D converter has both a high and low boundary limit register. The user may select whether an interrupt is generated when the conversion result is within (or equal to) the high and low boundary limits or when the conversion result is out side the boun da ry limits. An interrupt will be generated, if enabled, if the result meets the selected interrupt criteria. The boundary limit may be disabled by clearing the boundary limit interrupt enable.

An early detection mechanism exists when the interrupt criteria has been selected to be outside the boundary limits. In this case, after the four MSBs have been converted, these four bits are compared with the fo ur MSBs of the boundary high and low registers. If the four MSBs of the conversion meet the interrupt criteria (i.e.- outside the boundary limits) an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt criteria, the boundary limits will again be comp ared af ter all 8MSBs have been converted. The boundary status register (BNDSTA0) flags the channels which caused a boundary interrupt.

3.2.6 Clock divider

The A/D converter requires that its internal clock source be in the range of 320 kHz to 9 MHz to maintain accuracy . A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose (See Table 16

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NXP Semiconductors P89LPC952, P89LPC954 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. Introduction

1.1 Pin configuration

1.2 Pin description

1.3 Special function registers

1.4 Memory organization

2. Clocks

2.1 Enhanced CPU

2.2 Clock definitions

2.2.1 Oscillator Clock (OSCCLK)

2.2.2 Low speed oscillator option

2.2.3 Medium speed oscillator option

2.2.4 High speed oscillator option

2.3 Clock output

2.4 On-chip RC oscillator option

2.5 Watchdog oscillator option

2.6 External clock input option

2.7 Oscillator Clock (OSCCLK) wake-up delay

2.8 CPU Clock (CCLK) modification: DIVM register

2.9 Low power select

3. A/D converter

3.1 General description

3.2 A/D features

3.2.1 A/D operating modes

3.2.1.1 Fixed channel, single conversion mode

3.2.1.2 Fixed channel, continuous conversion mode

3.2.1.3 Auto scan, single conversion mode

3.2.1.4 Auto scan, continuous conversion mode

3.2.1.5 Dual channel, continuous conversion mode

3.2.1.6 Single step mode

3.2.2 Conversion mode selection bits

3.2.3 Conversion start modes

3.2.3.1 Timer triggered start

3.2.3.2 Start immediately

3.2.3.3 Edge triggered

3.2.4 Stopping and restarting conversions

3.2.5 Boundary limits interrupt

3.2.6 Clock divider