NXP Semiconductors MSC8158E Reference Manual

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MSC8158E Reference Manual

Broadband Wireless Access Six Core DSP With Security

MSC8158ERM

Rev 2, January 2012

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How to Reach Us:

Home Page:

www.freescale.com

Web Support:

http://www.freescale.com/support

North America:

Freescale Semiconductor, Inc. Technical Sales and Commercial Support Periferico Sur #8110 Col. El Mante Tlaquepaque Jalisco 45609 Mexico 1-800-521-6274 (US/Canada) 001 800 514 3392 (Mexico) www.freescale.com/support

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support

Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com

Asia/Pacific:

Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 010 5879 8000 support.asia@freescale.com

Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. The re are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semico ndu cto r make s no warran ty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.

Freescale, the Freescale logo, StarCore, and CodeWarrior are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. QUICC Engine is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.

MSC8158RME Rev. 2 1/2012

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Overview

SC3850 Core Overview

External Signals

Chip-Level Arbitration and Switching System (CLASS)

Reset

Boot Program

Clocks

General Configuration Registers

Memory Map

MSC8158 SC3850 DSP Subsystem

Internal Memory Subsystem

DDR-SDRAM Controller

Interrupt Handling

Direct Memory Access (DMA) Controller

High Speed Serial Interface (HSS I)

Serial RapidIO Controller and Enhance Message Complex

Common Public Radio Interface (CPRI)

QUICC Engine Subsystem

UART

Timers

GPIO

Hardware Semaphores

I2C

Debugging, Profiling, and Performance Monitoring

Multi Accelerator Platform Engine, Baseband 2 (MAPLE-B2)

Security Engine (SEC)

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Overview

SC3850 Core Overview External Signals Chip-Level Arbitration and Switching System (CLASS) Reset Boot Program Clocks General Configuration Registers Memory Map MSC8158 SC3850 DSP Subsystem Internal Memory Subsystem DDR-SDRAM Controller

Interrupt Handling Direct Memory Access (DMA) Controller High Speed Serial Interface (HSSI) Serial RapidIO Controller and Enhance Message Complex Common Public Radio Interface (CPRI) QUICC Engine Subsystem UART Timers GPIO Hardware Semaphores

I2C

Debugging, Profiling, and Performance Monitoring

Multi Accelerator Platform Engine, Baseband 2 (MAPLE-B2) Security Eng in e (SEC)

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Before Using This Manual—Important Note . . . . . . . . . . . . . . . . . . . . . . . . . .lxviii

Audience and Helpful Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .lxviii

Notational Conventions and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lxix

Conventions for Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lxx

Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lxx

Other MSC8158E Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .lxxiii

Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .lxxiii

Document Change History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lxxiv

1 Overview

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

1.3 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

1.4 StarCore SC3850 DSP Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18

1.4.1 StarCore SC3850 DSP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19

1.4.2 L1 Instruction Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20

1.4.3 L1 Data Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20

1.4.4 L2 Unified Cache/M2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

1.4.5 Memory Management Unit (MMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

1.4.6 Debug and Profiling Unit (DPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

1.4.7 Extended Programmable Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . 1-22

1.4.8 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22

1.5 MAPLE-B2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23

1.6 Security Engine (SEC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23

1.7 Chip-Level Arbitration and Switching System (CLASS) . . . . . . . . . . . . . . . . . 1-24

1.8 M3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24

1.9 Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25

1.10 DDR Controller (DDRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25

1.11 DMA Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26

1.12 High Speed System Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27

1.12.1 CLASS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27

1.12.2 OCN Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

1.12.3 OCN-to-MBus (O2M) Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

1.12.4 DMA Controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

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1.12.5 Serial RapidIO Complex. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

1.12.6 Protocol Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29

1.12.7 SerDes PHY Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29

1.13 QUICC Engine Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29

1.13.1 Ethernet Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30

1.13.2 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30

1.14 Global Interrupt Controller (GIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31

1.15 UART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31

1.16 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31

1.17 Hardware Semaphores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31

1.18 Virtual Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31

1.19 I

1.20 GPIOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32

1.21 Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32

1.22 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32

1.23 Developer Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32

1.23.1 Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33

1.23.2 Application Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34

C Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32

2 SC3850 Core Overview

2.1 Core Architecture Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2 StarCore SC3850 Core Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

3 External Signals

3.1 Power Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.2 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.3 Reset and Configuration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.4 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

3.5 SerDes Multiplexed Signals for the Serial RapidIO, CPRI, and

SGMII Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

3.6 CPRI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

3.7 Ethernet Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

3.8 Serial Peripheral Interface (SPI) Signal Summary . . . . . . . . . . . . . . . . . . . . . . 3-18

3.9 GPIO/Maskable Interrupt Signal Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19

3.10 Timer Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24

3.11 UART Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26

3.12 I

3.13 External DMA Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27

3.14 Other Interrupt Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28

3.15 OCE Event and JTAG Test Access Port Signals . . . . . . . . . . . . . . . . . . . . . . . . 3-29

C Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27

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Contents

4 Chip-Level Arbitration and Switching System (CLASS)

4.1 CLASS Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.2 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2.1 Expander Module and Transaction Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.2.2 Multiplexer and Arbiter Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.2.2.1 CLASS Arbiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.2.2.1.1 Weighted Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.2.2.1.2 Late Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.2.2.1.3 Priority Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.2.2.1.4 Auto Priority Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.2.2.2 CLASS Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.2.3 Normalizer Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.2.4 CLASS Control Interface (CCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.3 CLASS Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.4 CLASS Debug Profiling Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4.4.1 Profiling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4.4.2 Watch Point Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

4.4.3 Event Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

4.4.4 Debug and Profiling Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

4.5 CLASS Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

4.5.1 Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

4.5.2 Hard Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

4.6 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

4.7 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14

4.7.1 CLASS Priority Mapping Registers (C0PMRx) . . . . . . . . . . . . . . . . . . . . . . . 4-15

4.7.2 CLASS Priority Auto Upgrade Value Registers (C0PAVRx) . . . . . . . . . . . . 4-16

4.7.3 CLASS Priority Auto Upgrade Control Registers (C0PACRx) . . . . . . . . . . . 4-17

4.7.4 CLASS Error Address Registers (C0EARx) . . . . . . . . . . . . . . . . . . . . . . . . . 4-18

4.7.5 CLASS Error Extended Address Registers (C0EEARx) . . . . . . . . . . . . . . . . 4-19

4.7.6 CLASS Initiator Profiling Configuration Registers (C0IPCRx) . . . . . . . . . . 4-20

4.7.7 CLASS Initiator Watch Point Control Registers (C0IWPCRx) . . . . . . . . . . . 4-22

4.7.8 CLASS Arbitration Weight Registers (C0AWRx) . . . . . . . . . . . . . . . . . . . . . 4-23

4.7.9 CLASS Start Address Decoder x (C0SADx) . . . . . . . . . . . . . . . . . . . . . . . . . 4-24

4.7.10 CLASS End Address Decoder x (C0EADx). . . . . . . . . . . . . . . . . . . . . . . . . . 4-25

4.7.11 CLASS Attributes Decoder 1 (C0ATD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26

4.7.12 CLASS Attributes Decoder x (C0ATDx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28

4.7.13 CLASS IRQ Status Register (C0ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29

4.7.14 CLASS IRQ Enable Register (C0IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30

4.7.15 CLASS Target Profiling Configuration Register (C0TPCR) . . . . . . . . . . . . . 4-30

4.7.16 CLASS Profiling Control Register (C0PCR) . . . . . . . . . . . . . . . . . . . . . . . . . 4-32

4.7.17 CLASS Watch Point Control Registers (C0WPCR) . . . . . . . . . . . . . . . . . . . 4-33

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4.7.18 CLASS Watch Point Access Configuration Register (C0WPACR) . . . . . . . 4-34

4.7.19 CLASS Watch Point Extended Access Configuration Register

(C0WPEACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35

4.7.20 CLASS Watch Point Address Mask Registers (C0WPAMR) . . . . . . . . . . . . 4-36

4.7.21 CLASS Profiling Time-Out Registers (C0PTOR) . . . . . . . . . . . . . . . . . . . . . 4-37

4.7.22 CLASS Target Watch Point Control Registers (C0TWPCR) . . . . . . . . . . . . 4-38

4.7.23 CLASS Profiling IRQ Status Register (C0PISR) . . . . . . . . . . . . . . . . . . . . . . 4-39

4.7.24 CLASS Profiling IRQ Enable Register (C0PIER) . . . . . . . . . . . . . . . . . . . . . 4-40

4.7.25 CLASS Profiling Reference Counter Register (C0PRCR) . . . . . . . . . . . . . . . 4-40

4.7.26 CLASS Profiling General Counter Registers (C0PGCRx). . . . . . . . . . . . . . . 4-41

4.7.27 CLASS Arbitration Control Register (C0ACR) . . . . . . . . . . . . . . . . . . . . . . . 4-42

5 Reset

5.1 Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.1.1 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.1.2 Reset Actions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.1.3 Power-On Reset Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.1.4 Detailed Power-On Reset Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.1.5 HRESET

5.2 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5.2.1 Reset Configuration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5.2.2 Reset Configuration Words Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5.2.3 Reset Configuration Input Signal Selection and Reset Sequence Duration . . . 5-8

5.2.4 Reset Configuration Words. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

5.2.5 Loading The Reset Configuration Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

5.2.5.1 Loading From an I2C EEPROM (RCW_SRC[0–2] = 010). . . . . . . . . . . . . . 5-9

5.2.5.1.1 Using The Boot Sequencer For Reset Configuration . . . . . . . . . . . . . . . . . 5-9

5.2.5.1.2 EEPROM Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

5.2.5.1.3 EEPROM Data Format In Reset Configuration Mode . . . . . . . . . . . . . . . . 5-9

5.2.5.1.4 Single Device Loading From I2C EEPROM. . . . . . . . . . . . . . . . . . . . . . . 5-10

5.2.5.1.5 Loading Multiple Devices From a Single I

5.2.5.2 Loading Multiplexed RCW from External Pins (RCW_SRC[0–2] = 000) . 5-12

5.2.5.3 Loading Reduced RCW From External Pins (RCW_SRC[0–2] = 011) . . . 5-13

5.2.5.3.1 Reduced External Reset Configuration Word Low Field Values . . . . . . . 5-13

5.2.5.3.2 Reduced External Reset Configuration Word High Field Values . . . . . . . 5-14

5.2.5.4 Default Reset Configuration Words (RCW_SRC[0–2] = 100 or 101). . . . . 5-14

5.2.5.4.1 Hard Coded Reset Configuration Word Low Field Values. . . . . . . . . . . . 5-14

5.2.5.4.2 Hard Coded Reset Configuration Word High Field Values . . . . . . . . . . . 5-15

5.3 Reset Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16

5.3.1 Reset Configuration Word Low Register (RCWLR) . . . . . . . . . . . . . . . . . . . 5-16

5.3.2 Reset Configuration Word High Register (RCWHR). . . . . . . . . . . . . . . . . . . 5-20

Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

C EEPROM . . . . . . . . . . . . . 5-10

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5.3.3 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22

5.3.4 Reset Protection Register (RPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24

5.3.5 Reset Control Register (RCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25

5.3.6 Reset Control Enable Register (RCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26

6 Boot Program

6.1 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.1.1 Private Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.1.2 Shared Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.1.3 Patch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

6.1.4 Multi Device Support for the I

6.1.5 Example Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

6.2 Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9

6.2.1 I

6.2.2 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

6.2.2.1 DHCP Client. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15

6.2.2.2 TFTP Client . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16

6.2.2.3 Boot File Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16

6.2.3 Simple Ethernet Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18

6.2.3.1 Simple Ethernet Boot Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18

6.2.3.2 Simple Ethernet Boot Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19

6.2.3.3 Boot File Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20

6.2.4 Serial RapidIO Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21

6.2.4.1 Serial RapidIO Interface Without I

6.2.4.2 Serial RapidIO Interface with I2C Support . . . . . . . . . . . . . . . . . . . . . . . . . 6-22

6.2.5 SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22

6.3 Jump to User Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23

6.4 System after Boot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23

6.5 Boot Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24

C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9

C Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

C Support . . . . . . . . . . . . . . . . . . . . . . 6-21

7 Clocks

7.1 Clock Generation Components and Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

7.2 System Clock Control Register (SCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

8 General Configuration Registers

8.1 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.2 Detailed Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.2.1 General Configuration Register 1 (GCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.2.2 General Configuration Register 2 (GCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

8.2.3 General Status Register 1 (GSR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

8.2.4 High Speed Serial Interface Status Register (HSSI_SR) . . . . . . . . . . . . . . . . . 8-8

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8.2.5 DDR General Control Register (DDR_GCR). . . . . . . . . . . . . . . . . . . . . . . . . 8-11

8.2.6 High Speed Serial Interface Control Register 1 (HSSI_CR1) . . . . . . . . . . . . 8-12

8.2.7 High Speed Serial Interface Control Register 2 (HSSI_CR2) . . . . . . . . . . . . 8-15

8.2.8 QUICC Engine Control Register (QECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16

8.2.9 GPIO Pull-Up Enable Register (GPUER). . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17

8.2.10 GPIO Input Enable Register (GIER). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18

8.2.11 System Part and Revision ID Register (SPRIDR) . . . . . . . . . . . . . . . . . . . . . 8-19

8.2.12 General Control Register 4 (GCR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20

8.2.13 General Control Register 5 (GCR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22

8.2.14 General Status Register 2 (GSR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24

8.2.15 Core Subsystem Slave Port Priority Control Register (TSPPCR) . . . . . . . . . 8-26

8.2.16 General Status Register 3 (GSR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27

8.2.17 General Control Register 6 (GCR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29

8.2.18 General Control Register 7 (GCR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30

8.2.19 General Control Register 8 (GCR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33

8.2.20 General Control Register 10 (GCR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34

8.2.21 General Interrupt Register 1 (GIR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35

8.2.22 General Interrupt Enable Register 1 (GIER1_x). . . . . . . . . . . . . . . . . . . . . . . 8-37

8.2.23 General Interrupt Register 3 (GIR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-38

8.2.24 General Interrupt Enable Register 3 for Cores 0–3 (GIER3_x) . . . . . . . . . . . 8-40

8.2.25 General Interrupt Register 5 (GIR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-42

8.2.26 General Interrupt Enable Register 5 (GIER5_x). . . . . . . . . . . . . . . . . . . . . . . 8-44

8.2.27 General Control Register 11 (GCR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-46

8.2.28 General Control Register 13 (GCR13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-47

8.2.29 General Status Register 8 (GSR8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-48

8.2.30 DMA Request0 Control Register (GCR_DREQ0) . . . . . . . . . . . . . . . . . . . . . 8-49

8.2.31 DMA Request1 Control Register (GCR_DREQ1) . . . . . . . . . . . . . . . . . . . . . 8-53

8.2.32 DMA Done Control Register (GCR_DDONE) . . . . . . . . . . . . . . . . . . . . . . . 8-57

8.2.33 DDR Controller General Configuration Register (DDRC_GCR). . . . . . . . . . 8-60

8.2.34 Core Subsystem Slave Port General Configuration Register

(CORE_SLV_GCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-62

8.2.35 QUICC Engine Input General Control Register (QE_PIO_IN_GCR) . . . . . . 8-63

8.2.36 QUICC Engine Output General Status Register (QE_PIO_OUT_GSR) . . . . 8-64

8.2.37 L2Q Arbitration Control for Core Subsystems 0 and 1

(MEX_T2_0_1_ARB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-65

8.2.38 L2Q Arbitration Control for Core Subsystems 2 and 3

(MEX_T2_2_3_ARB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-66

8.2.39 L2Q Arbitration Control for Core Subsystems 4 and 5

(MEX_T2_4_5_ARB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-67

8.2.40 General Interrupt Register 6 (GIR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-68

8.2.41 General Interrupt Enable Register 6 (GIER6_x). . . . . . . . . . . . . . . . . . . . . . . 8-71

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8.2.42 General Interrupt Register 7 (GIR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-74

8.2.43 General Interrupt Enable Register 7 (GIER7_x). . . . . . . . . . . . . . . . . . . . . . . 8-76

8.2.44 DDR View Through L2 Memory Core Subsystems 0–3 (L2MAP_0_3) . . . . 8-79

8.2.45 DDR View Through L2 Memory Core Subsystems 4–5 (L2MAP_4_5) . . . . 8-80

8.2.46 eMSG to QUICC Engine External Request Enable (CPCEER) . . . . . . . . . . . 8-81

8.2.47 RGMII1 High Resolution Delay Register (UCC1_DELAY_HR) . . . . . . . . . 8-84

8.2.48 RGMII2 High Resolution Delay Register (UCC3_DELAY_HR) . . . . . . . . . 8-86

8.2.49 General Interrupt Register 8 (GIR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-88

8.2.50 CPRI to MAPLE External Request Enable (MAPLE_EXT_REQ_EN_1) . . 8-89

9 Memory Map

9.1 Shared Memory Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

9.2 Shared SC3850 DSP Core Subsystem M2/L2 Memories . . . . . . . . . . . . . . . . . . 9-2

9.3 SC3850 DSP Core Subsystem Internal Address Space . . . . . . . . . . . . . . . . . . . . 9-5

9.4 CCSR Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

9.5 Initiators Views of the System Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

9.5.1 SC3850 (Data) View of the System Address Space . . . . . . . . . . . . . . . . . . . . . 9-7

9.5.2 Peripherals View of the System Address Space . . . . . . . . . . . . . . . . . . . . . . . . 9-8

9.5.3 Security Engine View of the System Address Space . . . . . . . . . . . . . . . . . . . . 9-8

9.6 Detailed System Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

10 SC3850 DSP Subsystem

10.1 SC3850 DSP Core Subsystem Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.2 SC3850 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

10.3 Instruction Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

10.3.1 Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4

10.3.2 Instruction Fetch Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

10.4 Data Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

10.4.1 Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5

10.4.2 Data Fetch Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6

10.4.3 Write-Back Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

10.4.4 Write-Through Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

10.4.5 Data Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7

10.4.6 Write Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8

10.5 Memory Management Unit (MMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8

10.6 L2 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

10.7 On-Chip Emulator and Debug and Profiling Unit . . . . . . . . . . . . . . . . . . . . . 10-10

10.8 Extended Programmable Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . 10-11

10.9 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11

10.10 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11

10.10.1 QBus to MBus Interface Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11

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10.10.2 MBus to DMA Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11

10.11 Entering and Exiting Wait and Stop States Safely. . . . . . . . . . . . . . . . . . . . . . 10-12

10.11.1 Wait State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12

10.11.2 Stop State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12

10.11.2.1 Procedure for Entering DSP Subsystem Stop State Safely . . . . . . . . . . . . 10-12

10.11.2.2 Procedure for Exiting the Stop State Safely. . . . . . . . . . . . . . . . . . . . . . . . 10-13

10.12 Programming Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13

11 Internal Memory Subsystem

11.1 Memory Management Unit (MMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.2 Instruction Channel (ICache and IFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

11.3 Data Channel and Write Queue (DCache). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

11.4 L2 Unified Cache/M2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8

11.5 M3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12

11.6 Internal Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12

12 DDR SDRAM Memory Controller

12.1 DDR Memory Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

12.2 DDR Memory Controller Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . 12-2

12.3 DDR Controller Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3

12.3.1 DDR SDRAM Interface Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7

12.3.2 Supported DDR SDRAM Organizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8

12.3.3 DDR SDRAM Address Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8

12.3.4 JEDEC Standard DDR SDRAM Interface Commands. . . . . . . . . . . . . . . . . 12-11

12.3.5 DDR SDRAM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13

12.3.6 Clock Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16

12.3.7 DDR SDRAM Mode-Set Command Timing . . . . . . . . . . . . . . . . . . . . . . . . 12-17

12.3.8 DDR SDRAM Registered DIMM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18

12.3.9 DDR SDRAM Write Timing Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19

12.3.10 DDR SDRAM Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20

12.3.10.1 DDR SDRAM Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21

12.3.10.2 DDR SDRAM Refresh and Power-Saving Modes. . . . . . . . . . . . . . . . . . . 12-22

12.3.10.3 Self-Refresh in Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23

12.3.11 DDR Data Beat Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24

12.3.12 Page Mode and Logical Bank Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24

12.3.13 Error Checking and Correcting (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24

12.3.14 Error Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26

12.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27

12.4.1 Programming Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30

12.4.2 DDR SDRAM Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32

12.4.3 Self-Refresh Mode Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32

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12.4.3.1 Software Based Self-Refresh Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32

12.4.3.2 Bypassing Re-initialization During Battery-Backed Operation . . . . . . . . . 12-33

12.5 Memory Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-33

12.5.1 Chip-Select x Bounds Register (CSx_BNDS) . . . . . . . . . . . . . . . . . . . . . . . 12-35

12.5.2 Chip-Select x Configuration Register (CSx_CONFIG) . . . . . . . . . . . . . . . . 12-36

12.5.3 Chip-Select x Configuration Register 2 (CSx_CONFIG_2). . . . . . . . . . . . . 12-38

12.5.4 DDR SDRAM Timing Configuration 3 Register (TIMING_CFG_3) . . . . . 12-39

12.5.5 DDR SDRAM Timing Configuration Register 0 (TIMING_CFG_0) . . . . . 12-42

12.5.6 DDR SDRAM Timing Configuration Register 1 (TIMING_CFG_1) . . . . . 12-45

12.5.7 DDR SDRAM Timing Configuration Register 2 (TIMING_CFG_2) . . . . . 12-48

12.5.8 DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG) . . . 12-51

12.5.9 DDR SDRAM Control Configuration Register 2 (DDR_SDRAM_CFG_2) 12-54

12.5.10 DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE). . . 12-57

12.5.11 DDR SDRAM Mode Configuration 2 Register (DDR_SDRAM_MODE_2)12-58

12.5.12 DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL) . . . . 12-58

12.5.13 DDR SDRAM Interval Configuration Register

(DDR_SDRAM_INTERVAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-61

12.5.14 DDR SDRAM Data Initialization Register (DDR_DATA_INIT) . . . . . . . . 12-62

12.5.15 DDR SDRAM Clock Control Configuration Register

(DDR_SDRAM_CLK_CNTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-63

12.5.16 DDR SDRAM Initialization Address Register (DDR_INIT_ADDR) . . . . . 12-64

12.5.17 DDR Initialization Enable Register (DDR_INIT_EN) . . . . . . . . . . . . . . . . . 12-65

12.5.18 DDR SDRAM Timing Configuration 4 Register (TIMING_CFG_4) . . . . . 12-66

12.5.19 DDR SDRAM Timing Configuration 5 Register (TIMING_CFG_5) . . . . . 12-68

12.5.20 DDR ZQ Calibration Control Register (DDR_ZQ_CNTL) . . . . . . . . . . . . . 12-70

12.5.21 DDR Write Leveling Control Register (DDR_WRLVL_CNTL). . . . . . . . . 12-72

12.5.22 DDR Write Leveling Control 2 Register (DDR_WRLVL_CNTL_2) . . . . . 12-75

12.5.23 DDR Write Leveling Control 3 Register (DDR_WRLVL_CNTL_3) . . . . . 12-78

12.5.24 DDR Self Refresh Counter Register (DDR_SR_CNTR) . . . . . . . . . . . . . . . 12-81

12.5.25 DDR SDRAM Register Control Words 1 Register

(DDR_SDRAM_RCW_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-82

12.5.26 DDR SDRAM Register Control Words 2 Register

(DDR_SDRAM_RCW_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-83

12.5.27 DDR SDRAM Mode 3 Configuration Register (DDR_SDRAM_MODE_3)12-84

12.5.28 DDR SDRAM Mode Configuration 4 Register (DDR_SDRAM_MODE_4)12-85

12.5.29 DDR Debug Status Register 1 (DDRDSR_1). . . . . . . . . . . . . . . . . . . . . . . . 12-86

12.5.30 DDR Debug Status Register 2 (DDRDSR_2). . . . . . . . . . . . . . . . . . . . . . . . 12-87

12.5.31 DDR Control Driver Register 1 (DDRCDR_1) . . . . . . . . . . . . . . . . . . . . . . 12-87

12.5.32 DDR Control Driver Register 2 (DDRCDR_2) . . . . . . . . . . . . . . . . . . . . . . 12-91

12.5.33 DDR SDRAM IP Block Revision 1 Register (DDR_IP_REV1) . . . . . . . . . 12-92

12.5.34 DDR SDRAM IP Block Revision 2 Register (DDR_IP_REV2) . . . . . . . . . 12-92

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12.5.35 DDR Memory Test Control Register (DDR_MTCR). . . . . . . . . . . . . . . . . . 12-93

12.5.36 DDR Data Memory Test Pattern x Register (DDR_MTPx) . . . . . . . . . . . . . 12-94

12.5.37 DDR SDRAM Memory Data Path Error Injection Mask High Register

(DATA_ERR_INJECT_HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-95

12.5.38 DDR SDRAM Memory Data Path Error Injection Mask Low Register

(DATA_ERR_INJECT_LO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-96

12.5.39 DDR SDRAM Memory Data Path Error Injection Mask ECC Register

(ERR_INJECT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-97

12.5.40 DDR SDRAM Memory Data Path Read Capture Data High Register

(CAPTURE_DATA_HI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-98

12.5.41 DDR SDRAM Memory Data Path Read Capture Data Low Register

(CAPTURE_DATA_LO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-98

12.5.42 DDR SDRAM Memory Data Path Read Capture ECC Register

(CAPTURE_ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-99

12.5.43 DDR SDRAM Memory Error Detect Register (ERR_DETECT) . . . . . . . . 12-99

12.5.44 DDR SDRAM Memory Error Disable Register (ERR_DISABLE) . . . . . . 12-101

12.5.45 DDR SDRAM Memory Error Interrupt Enable Register (ERR_INT_EN) 12-102

12.5.46 DDR SDRAM Memory Error Attributes Capture Register

(CAPTURE_ATTRIBUTES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-103

12.5.47 DDR SDRAM Memory Error Address Capture Register

(CAPTURE_ADDRESS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-104

12.5.48 DDR SDRAM Single-Bit ECC Memory Error Management Register

(ERR_SBE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-105

13 Interrupt Handling

13.1 Global Interrupt Controller (GIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3

13.2 General Configuration Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4

13.2.1 Interrupt Groups Toward the SC3850 Cores. . . . . . . . . . . . . . . . . . . . . . . . . . 13-5

13.2.2 Interrupt Groups Toward QUICC Engine Processors. . . . . . . . . . . . . . . . . . . 13-6

13.2.3 External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6

13.2.4 Interrupt Groups Directed Toward MAPLE-B2 . . . . . . . . . . . . . . . . . . . . . . . 13-7

13.2.5 Interrupt Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8

13.3 Interrupt Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9

13.4 Core Interrupt Mesh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25

13.5 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26

13.5.1 Global Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26

13.5.1.1 Virtual Interrupt Generation Register (VIGR) . . . . . . . . . . . . . . . . . . . . . . 13-26

13.5.1.2 Virtual Interrupt Status Register (VISR) . . . . . . . . . . . . . . . . . . . . . . . . . . 13-27

13.5.2 General Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-29

13.5.3 Programming Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-30

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14 Direct Memory Access (DMA) Controller

14.1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2

14.2 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3

14.2.1 One-Dimensional Simple Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4

14.2.2 One-Dimensional Cyclic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5

14.2.3 One-Dimensional Chained Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6

14.2.4 One-Dimensional Incremental Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7

14.2.5 One-Dimensional Complex Buffers With Dual Cyclic Buffers . . . . . . . . . . . 14-8

14.2.6 Two-Dimensional Simple Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9

14.2.7 Three-Dimensional Simple Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11

14.2.8 Four-Dimensional Simple Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12

14.2.9 Multi-Dimensional Chained Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15

14.2.10 Two-Dimensional Cyclic Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17

14.2.11 Three-Dimensional Cyclic Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18

14.3 Arbitration Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19

14.3.1 Round-Robin Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19

14.3.2 EDF Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-20

14.3.2.1 Issuing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21

14.3.2.2 Counter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21

14.3.2.3 Clock Source to the Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22

14.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22

14.4.1 Maskable Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22

14.4.2 Nonmaskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22

14.5 DMA Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23

14.5.1 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23

14.5.2 Configuration and Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24

14.5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25

14.5.3.1 Request Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25

14.5.3.2 Done Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25

14.5.3.3 Signal Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25

14.5.4 Using the DMA Peripheral Interface Block . . . . . . . . . . . . . . . . . . . . . . . . . 14-26

14.6 DMA Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27

14.6.1 DMA Buffer Descriptor Base Registers x (DMABDBRx). . . . . . . . . . . . . . 14-28

14.6.2 DMA Controller Channel Configuration Registers x (DMACHCRx) . . . . . 14-29

14.6.3 DMA Controller Global Configuration Register (DMAGCR) . . . . . . . . . . . 14-31

14.6.4 DMA Channel Enable Register (DMACHER) . . . . . . . . . . . . . . . . . . . . . . . 14-31

14.6.5 DMA Channel Disable Register (DMACHDR) . . . . . . . . . . . . . . . . . . . . . . 14-32

14.6.6 DMA Channel Freeze Register (DMACHFR) . . . . . . . . . . . . . . . . . . . . . . . 14-33

14.6.7 DMA Channel Defrost Register (DMACHDFR).. . . . . . . . . . . . . . . . . . . . . 14-33

14.6.8 DMA Time-To-Dead Line Registers x (DMAEDFTDLx). . . . . . . . . . . . . . 14-34

14.6.9 DMA EDF Control Register (DMAEDFCTRL). . . . . . . . . . . . . . . . . . . . . . 14-35

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14.6.10 DMA EDF Mask Register (DMAEDFMR) . . . . . . . . . . . . . . . . . . . . . . . . . 14-35

14.6.11 DMA EDF Mask Update Register (DMAEDFMUR). . . . . . . . . . . . . . . . . . 14-36

14.6.12 DMA EDF Status Register (DMAEDFSTR) . . . . . . . . . . . . . . . . . . . . . . . . 14-38

14.6.13 DMA Mask Register (DMAMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-38

14.6.14 DMA Mask Update Register (DMAMUR). . . . . . . . . . . . . . . . . . . . . . . . . . 14-39

14.6.15 DMA Status Register (DMASTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-40

14.6.16 DMA Error Register (DMAERR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-41

14.6.17 DMA Debug Event Status Register (DMADESR) . . . . . . . . . . . . . . . . . . . . 14-43

14.6.18 DMA Round-Robin Priority Group Update Register (DMARRPGUR) . . . 14-43

14.6.19 DMA Channel Active Status Register (DMACHASTR) . . . . . . . . . . . . . . . 14-44

14.6.20 DMA Channel Freeze Status Register (DMACHFSTR) . . . . . . . . . . . . . . . 14-44

14.6.21 DMA Channel Buffer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-45

14.6.21.1 Buffer Attributes (BD_ATTR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-48

14.6.21.2 Multi-Dimensional Buffer Attributes (BD_MD_ATTR). . . . . . . . . . . . . . 14-51

15 High Speed Serial Interface (HSSI) Subsystem

15.1 HSSI Subsystem Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2

15.2 CLASS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3

15.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4

15.2.1.1 Expander Module and Transaction Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4

15.2.1.2 Multiplexer and Arbiter Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4

15.2.1.2.1 CLASS Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5

15.2.1.2.2 CLASS Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6

15.2.1.2.3 Normalizer Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6

15.2.1.3 CLASS1 Control Interface (C1CI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6

15.2.2 CLASS Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6

15.2.3 CLASS Debug Profiling Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7

15.2.3.1 Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7

15.2.3.2 Watch Point Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8

15.2.3.3 Event Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9

15.2.3.4 Debug and Profiling Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12

15.2.4 CLASS Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12

15.2.5 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12

15.3 OCN Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12

15.4 OCN-to-MBus (O2M) Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13

15.5 DMA Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13

15.5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14

15.5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14

15.5.3 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14

15.5.4 DMA Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16

15.5.4.1 Basic DMA Mode Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16

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15.5.4.1.1 Basic Direct Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17

15.5.4.1.2 Basic Direct Single-Write Start Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17

15.5.4.1.3 Basic Chaining Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18

15.5.4.1.4 Basic Chaining Single-Write Start Mode . . . . . . . . . . . . . . . . . . . . . . . . 15-19

15.5.4.1.5 Extended DMA Mode Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19

15.5.4.1.5.1 Extended Direct Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19

15.5.4.1.5.2 Extended Direct Single-Write Start Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20

15.5.4.1.5.3 Extended Chaining Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20

15.5.4.1.5.4 Extended Chaining Single-Write Start Mode . . . . . . . . . . . . . . . . . . . . . . . . 15-20

15.5.4.2 Channel Continue Mode for Cascading Transfer Chains. . . . . . . . . . . . . . 15-21

15.5.4.2.1 Basic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22

15.5.4.2.2 Extended Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22

15.5.4.3 Channel Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22

15.5.4.4 Bandwidth Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22

15.5.4.5 Channel State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23

15.5.4.6 Illustration of Stride Size and Stride Distance . . . . . . . . . . . . . . . . . . . . . . 15-23

15.5.5 DMA Transfer Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24

15.5.6 DMA Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24

15.5.7 DMA Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24

15.5.8 Local Access ATMU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-27

15.5.9 Limitations and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-27

15.6 Serial RapidIO Complex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-28

15.7 Protocol Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-28

15.8 SerDes PHY Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-28

15.8.1 Serdes Banks and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-29

15.8.2 SerDes PLL Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-29

15.8.3 SerDes PLL Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-30

15.8.4 SerDes Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-31

15.9 HSSI Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-32

15.9.1 CLASS1 Priority Mapping Registers (C1PMRx) . . . . . . . . . . . . . . . . . . . . . 15-35

15.9.2 CLASS1 Priority Auto Upgrade Value Registers (C1PAVRx) . . . . . . . . . . 15-36

15.9.3 CLASS1 Priority Auto Upgrade Control Registers (C1PACRx) . . . . . . . . . 15-37

15.9.4 CLASS1 Error Address Registers (C1EARx) . . . . . . . . . . . . . . . . . . . . . . . 15-38

15.9.5 CLASS1 Error Extended Address Registers (C1EEARx) . . . . . . . . . . . . . . 15-39

15.9.6 CLASS1 Initiator Profiling Configuration Registers (C1IPCRx) . . . . . . . . 15-40

15.9.7 CLASS1 Initiator Watch Point Control Registers (C1IWPCRx) . . . . . . . . . 15-41

15.9.8 CLASS1 Arbitration Weight Registers (C1AWRx) . . . . . . . . . . . . . . . . . . . 15-42

15.9.9 CLASS1 Start Address Decoder 1 (C1SAD1) . . . . . . . . . . . . . . . . . . . . . . . 15-43

15.9.10 CLASS1 Start Address Decoder 2(C1SAD2). . . . . . . . . . . . . . . . . . . . . . . . 15-44

15.9.11 CLASS1 End Address Decoder 1 (C1EAD1). . . . . . . . . . . . . . . . . . . . . . . . 15-45

15.9.12 CLASS1 End Address Decoder 1 (C1EAD2). . . . . . . . . . . . . . . . . . . . . . . . 15-46

15.9.13 CLASS1 Attributes Decoder 1 (C1ATD1) . . . . . . . . . . . . . . . . . . . . . . . . . . 15-47

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15.9.14 CLASS1 Attributes Decoder 1 (C1ATD2) . . . . . . . . . . . . . . . . . . . . . . . . . . 15-49

15.9.15 CLASS1 IRQ Status Register (C1ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-50

15.9.16 CLASS1 IRQ Enable Register (C1IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-52

15.9.17 CLASS1 Target Profiling Configuration Register (C1TPCR) . . . . . . . . . . . 15-53

15.9.18 CLASS1 Profiling Control Register (C1PCR) . . . . . . . . . . . . . . . . . . . . . . . 15-54

15.9.19 CLASS1 Watch Point Control Registers (C1WPCR) . . . . . . . . . . . . . . . . . 15-55

15.9.20 CLASS1 Watch Point Access Configuration Register (C1WPACR) . . . . . 15-57

15.9.21 CLASS1 Watch Point Extended Access Configuration Register

(C1WPEACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-58

15.9.22 CLASS1 Watch Point Address Mask Registers (C1WPAMR) . . . . . . . . . . 15-59

15.9.23 CLASS1 Profiling Time-Out Registers (C1PTOR) . . . . . . . . . . . . . . . . . . . 15-60

15.9.24 CLASS1 Target Watch Point Control Registers (C1TWPCR) . . . . . . . . . . 15-61

15.9.25 CLASS1 Profiling IRQ Status Register (C1PISR) . . . . . . . . . . . . . . . . . . . . 15-62

15.9.26 CLASS1 Profiling IRQ Enable Register (C1PIER) . . . . . . . . . . . . . . . . . . . 15-63

15.9.27 CLASS1 Profiling Reference Counter Register (C1PRCR) . . . . . . . . . . . . . 15-64

15.9.28 CLASS1 Profiling General Counter Registers (C1PGCRx). . . . . . . . . . . . . 15-65

15.9.29 CLASS1 Arbitration Control Register (C1ACR) . . . . . . . . . . . . . . . . . . . . . 15-66

15.9.30 Mode Registers 0–3 (DnMR[0–3]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-67

15.9.31 Status Registers (DnSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-70

15.9.32 Current Link Descriptor Extended Address Registers (DnECLNDARn). . . 15-72

15.9.33 Current Link Descriptor Address Registers (DnCLNDARn): . . . . . . . . . . . 15-73

15.9.34 Source Attributes Registers (DnSATRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-74

15.9.35 Source Address Registers (DnSARn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-75

15.9.36 Destination Attributes Registers (DnDATRn). . . . . . . . . . . . . . . . . . . . . . . . 15-76

15.9.37 Destination Address Registers (DnDARn) . . . . . . . . . . . . . . . . . . . . . . . . . . 15-77

15.9.38 Byte Count Registers (DnBCRn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-78

15.9.39 Extended Next Link Descriptor Address Registers (DnENLNDARn). . . . . 15-79

15.9.40 Next Link Descriptor Address Registers (DnNLNDARn) . . . . . . . . . . . . . . 15-80

15.9.41 Extended Current List Descriptor Address Registers (DnECLSDARn). . . . 15-81

15.9.42 Current List Descriptor Address Registers (DnCLSDARn) . . . . . . . . . . . . . 15-82

15.9.43 Extended Next List Descriptor Address Registers (DnENLSDARn). . . . . . 15-83

15.9.44 Next List Descriptor Address Registers (DnNLSDARn) . . . . . . . . . . . . . . . 15-84

15.9.45 Source Stride Registers (DnSSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-85

15.9.46 Destination Stride Registers (DnDSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-86

15.9.47 DMA General Status Register (DnDGSR)) . . . . . . . . . . . . . . . . . . . . . . . . . 15-87

15.9.48 Local Access Window Base Address Registers 0–9 (DnLAWBAR[0–9]) . 15-89

15.9.49 Local Access Window Attributes Registers 0–9 (DnLAWAR[0–9]). . . . . . 15-90

15.9.50 CPRIn PCVTR Control Register 0(PCVTRCPRInCR0) . . . . . . . . . . . . . . . 15-92

15.9.51 CPRIn PCVTR Control Register 1(PCVTRCPRInCR1) . . . . . . . . . . . . . . . 15-93

15.9.52 SRDS Bank 1 Reset Control Register (SRDSB1RSTCTL) . . . . . . . . . . . . . 15-94

15.9.53 SRDS Bank 2 Reset Control Register (SRDSB2RSTCTL) . . . . . . . . . . . . . 15-95

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15.9.54 SRDS Bank 1–2 PLL Control Register 0 (SRDSB[1–2]PLLCR0) . . . . . . . 15-96

15.9.55 SRDS Bank 1–2 PLL Control Register 1 (SRDSB[1–2]PLLCR1) . . . . . . . 15-97

15.9.56 Lane C–J General Control Register 0 (L[C–J]GCR0) . . . . . . . . . . . . . . . . . 15-98

15.9.57 Lane C–J General Control Register 1 (L[C–J]GCR1) . . . . . . . . . . . . . . . . . 15-99

15.9.58 Lane C–J Receive Equalization Control Register 0 (L[C–J]RECR0). . . . . 15-100

15.9.59 Lane C–J Transmit Equalization Control Register 0 (L[C–J]TECR0) . . . . 15-102

15.9.60 Lane C–J Test Control/Status Register 3 (L[C–J]TCSR3) . . . . . . . . . . . . . 15-104

16 Serial RapidIO Controller and Enhanced Message Complex

16.1 Serial RapidIO and eMSG Complex Overview. . . . . . . . . . . . . . . . . . . . . . . . . 16-4

16.1.1 Serial RapidIO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4

16.1.2 eMSG Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5

16.1.3 Internal Processing Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7

16.1.4 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8

16.1.5 x1/x2/x4 LP-Serial Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8

16.1.6 RapidIO Interface Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9

16.1.6.1 Initialization for Booting the MSC8158E DSP . . . . . . . . . . . . . . . . . . . . . . 16-9

16.1.6.2 Initialization for Non-Boot Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9

16.1.7 Link Training. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9

16.1.7.1 Initialize Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10

16.1.7.2 Reset Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10

16.1.7.3 Software Retraining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11

16.1.8 Special Case of x2/x1 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11

16.2 RapidIO Interface Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12

16.2.1 RapidIO Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12

16.2.2 Message Passing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14

16.2.3 RapidIO Data Streaming (Type9) Transactions . . . . . . . . . . . . . . . . . . . . . . 16-14

16.2.4 RapidIO GSM Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15

16.2.5 RapidIO Packet Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15

16.2.6 RapidIO Control Symbol Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17

16.2.7 Accessing Configuration Registers via RapidIO Packets . . . . . . . . . . . . . . . 16-18

16.2.7.1 Inbound Maintenance Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18

16.2.7.2 Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19

16.2.7.3 Outbound Maintenance Accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19

16.2.8 Interaction with the Message Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19

16.2.8.1 Inbound (Rx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20

16.2.8.2 Outbound (Tx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20

16.2.8.3 Buffer Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20

16.2.8.3.1 Tx Message Unit Request Packets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21

16.2.8.3.2 Tx Message Unit Response/Flow Control Packets . . . . . . . . . . . . . . . . . 16-22

16.2.8.3.3 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23

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16.2.8.3.3.1 Arbitration Point 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23

16.2.8.3.3.2 Arbitration Point 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24

16.2.8.3.3.3 Arbitration Point 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24

16.2.9 RapidIO ATMU Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24

16.2.9.1 RapidIO Outbound ATMU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-25

16.2.9.2 Outbound Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-27

16.2.9.3 Window Size and Segmented Windows. . . . . . . . . . . . . . . . . . . . . . . . . . . 16-27

16.2.9.3.1 Valid Hits to Multiple ATMU Windows. . . . . . . . . . . . . . . . . . . . . . . . . 16-52

16.2.9.3.2 Window Boundary Crossing Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-53

16.2.9.4 RapidIO Inbound ATMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-54

16.2.9.4.1 Hits to Multiple ATMU Windows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-56

16.2.9.4.2 Window Boundary Crossing Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-56

16.2.10 Generating Link-Request/Reset-Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-57

16.2.11 Outbound Drain Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-58

16.2.12 Input Port Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-59

16.2.13 Software Assisted Error Recovery Register Support . . . . . . . . . . . . . . . . . . 16-59

16.2.14 Errors and Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-60

16.2.14.1 RapidIO Error Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-60

16.2.14.2 Physical Layer RapidIO Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-61

16.2.14.3 Logical Layer RapidIO Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-64

16.3 RapidIO Enhanced Message Unit (eMSG) Communication . . . . . . . . . . . . . . 16-90

16.3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-90

16.3.2 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-92

16.3.2.1 Outbound Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-92

16.3.2.2 Inbound Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-92

16.3.3 Command Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-93

16.3.3.1 Inbound Command Descriptor Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-93

16.3.3.2 Outbound Command Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . 16-95

16.3.3.3 Outbound Completion Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-96

16.3.4 Scatter/Gather Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-97

16.3.5 Type5 NWrite Unit Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 16-99

16.3.5.1 Type5 Outbound NWrite Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . 16-99

16.3.5.2 Type5 Outbound NWrite Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-102

16.3.5.2.1 Work Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-102

16.3.5.2.2 Adding NWrites to a Message Queue . . . . . . . . . . . . . . . . . . . . . . . . . . 16-102

16.3.5.2.3 NWrite Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-103

16.3.5.2.4 Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-103

16.3.5.2.4.1 Descriptor Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-104

16.3.5.2.4.2 Transaction Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-104

16.3.6 Type6 Streaming Write Functional Description . . . . . . . . . . . . . . . . . . . . . 16-105

16.3.6.1 Type6 Outbound SWrite Descriptor Format . . . . . . . . . . . . . . . . . . . . . . 16-105

16.3.6.2 Type6 Outbound SWrite Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-107

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16.3.6.2.1 Work Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-108

16.3.6.2.2 Adding NWrites To A Message Queue. . . . . . . . . . . . . . . . . . . . . . . . . 16-108

16.3.6.2.3 SWrite Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-108

16.3.6.2.4 Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-108

16.3.6.2.4.1 Descriptor Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-109

16.3.6.2.4.2 Transaction Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-109

16.3.7 Type8 Port-Write Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . 16-110

16.3.7.1 Type8 Outbound Port-Write Descriptor Format . . . . . . . . . . . . . . . . . . . 16-110

16.3.7.2 Type8 Inbound Port-Write Descriptor Format. . . . . . . . . . . . . . . . . . . . . 16-112

16.3.7.3 Type8 Outbound Port-Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 16-113

16.3.7.3.1 Work Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-113

16.3.7.3.2 Adding Port-Writes To A Message Queue . . . . . . . . . . . . . . . . . . . . . . 16-113

16.3.7.3.3 Port-Write Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-114

16.3.7.3.4 Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-114

16.3.7.3.4.1 Descriptor Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-115

16.3.7.3.4.2 Transaction Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-115

16.3.7.4 Type8 Inbound Port-Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-116

16.3.7.4.1 Inbound Port-Write Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-116

16.3.7.4.2 Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-116

16.3.7.4.2.1 Buffer Size Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-117

16.3.7.4.2.2 Transaction Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-117

16.3.8 Type9 Data Streaming Functional Description. . . . . . . . . . . . . . . . . . . . . . 16-117

16.3.8.1 Type9 Segmentation Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . 16-117

16.3.8.2 Type9 Reassembly Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-120

16.3.8.3 Type9 Outbound Segmentation Operation. . . . . . . . . . . . . . . . . . . . . . . . 16-123

16.3.8.3.1 Work Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-123

16.3.8.3.2 Adding PDUs To A Message Queue. . . . . . . . . . . . . . . . . . . . . . . . . . . 16-123

16.3.8.3.3 Segmentation Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-124

16.3.8.3.4 Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-124

16.3.8.3.4.1 Descriptor Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-125

16.3.8.3.4.2 Transaction Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-125

16.3.8.4 Type9 Reassembly Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-126

16.3.8.4.1 Reassembly Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-126

16.3.8.4.2 Packet Steering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-126

16.3.8.4.3 Packet Drop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-126

16.3.8.4.4 Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-126

16.3.8.4.4.1 Single/Start Segment Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-128

16.3.8.4.4.2 Continuation Segment Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-128

16.3.8.4.4.3 End Segment Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-128

16.3.8.4.4.4 Segment Request Timeout Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-129

16.3.8.4.4.5 MTU Violation Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-129

16.3.8.4.4.6 Source Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-129

16.3.8.4.4.7 Size Mismatch Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-129

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16.3.8.4.4.8 Transaction Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-129

16.3.8.5 Flow Control Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-130

16.3.8.5.1 Receiving Flow Control Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-130

16.3.8.5.2 Sending Flow Control Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-131

16.3.9 Type10 Doorbell Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . 16-132

16.3.9.1 Type10 Outbound Doorbell Descriptor Format . . . . . . . . . . . . . . . . . . . . 16-132

16.3.9.2 Type10 Inbound Doorbell Descriptor Format . . . . . . . . . . . . . . . . . . . . . 16-135

16.3.9.3 Type10 Outbound Doorbell Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . 16-137

16.3.9.3.1 Work Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-137

16.3.9.3.2 Adding Doorbells To A Message Queue. . . . . . . . . . . . . . . . . . . . . . . . 16-137

16.3.9.3.3 Doorbell Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-138

16.3.9.3.4 Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-138

16.3.9.3.4.1 Descriptor Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-139

16.3.9.3.4.2 Doorbell Error Response Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-140

16.3.9.3.4.3 Doorbell Response Time-out Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-140

16.3.9.3.4.4 Retry Threshold Exceeded Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-140

16.3.9.3.4.5 Transaction Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-140

16.3.9.4 Type10 Inbound Doorbell Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-141

16.3.9.4.1 Doorbell Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-141

16.3.9.4.2 Doorbell Steering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-141

16.3.9.4.3 Retry Response Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-141

16.3.9.4.4 Error Response Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-141

16.3.9.4.5 Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-142

16.3.9.4.5.1 Buffer Size Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-142

16.3.9.4.5.2 Transaction Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-143

16.3.10 Type11 Message Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . 16-143

16.3.10.1 Type11 Outbound Message Descriptor Format . . . . . . . . . . . . . . . . . . . . 16-143

16.3.10.2 Type11 Inbound Message Descriptor Format . . . . . . . . . . . . . . . . . . . . . 16-147

16.3.10.3 Type11 Outbound Message Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . 16-149

16.3.10.3.1 Work Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-149

16.3.10.3.2 Adding Messages to a Message Queue . . . . . . . . . . . . . . . . . . . . . . . . . 16-150

16.3.10.3.3 Message Unit Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-150

16.3.10.3.4 Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-150

16.3.10.3.4.1 Descriptor Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-152

16.3.10.3.4.2 Message Error Response Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-152

16.3.10.3.4.3 Segment Response Time-Out Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-152

16.3.10.3.4.4 Retry Threshold Exceeded Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-152

16.3.10.3.4.5 Multicast Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-153

16.3.10.3.4.6 Transaction Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-153

16.3.10.4 Type11 Inbound Message Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-154

16.3.10.4.1 Inbound Message Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-154

16.3.10.4.2 Message Steering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-154

16.3.10.4.3 Retry Response Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-154

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16.3.10.4.4 Error Response Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-154

16.3.10.4.5 Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-155

16.3.10.4.5.1 Segment Request Time-Out Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-156

16.3.10.4.5.2 Buffer Size Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-157

16.3.10.4.5.3 Message Format Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-157

16.3.10.4.5.4 Transaction Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-157

16.3.11 Session Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-157

16.3.11.1 Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-158

16.3.12 Hardware Context Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-158

16.3.12.1 Segmentation and Reassembly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-159

16.3.12.2 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-162

16.3.13 Address Alignment Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-166

16.3.14 Ordering Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-166

16.3.14.1 Inbound Ordering Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-166

16.3.14.2 Outbound Ordering Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-166

16.3.14.3 Outbound Segmentation Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . 16-167

16.3.14.4 Transaction Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-168

16.3.15 Congestion Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-168

16.3.15.1 Critical Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-168

16.3.16 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-169

16.3.17 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-169

16.3.17.1 Initializing the Global Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-169

16.3.17.2 Classification Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-169

16.3.17.3 Dynamically Changing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-171

16.3.17.4 Mixing Classification Rule Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-171

16.3.17.5 Initializing Inbound Message Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-171

16.3.17.6 Initializing Outbound Message Queues . . . . . . . . . . . . . . . . . . . . . . . . . . 16-172

16.4 RapidIO/eMSG Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-172

16.4.1 RapidIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-181

16.4.1.1 Device Identity Capability Register (DIDCAR) . . . . . . . . . . . . . . . . . . . 16-181

16.4.1.2 Device Information Capability Register (DICAR). . . . . . . . . . . . . . . . . . 16-182

16.4.1.3 Assembly Identity Capability Register (AIDCAR) . . . . . . . . . . . . . . . . . 16-182

16.4.1.4 Assembly Information Capability Register (AICAR) . . . . . . . . . . . . . . . 16-183

16.4.1.5 Processing Element Features Capability Register (PEFCAR) . . . . . . . . . 16-184

16.4.1.6 Source Operations Capability Register (SOCAR) . . . . . . . . . . . . . . . . . . 16-185

16.4.1.7 Destination Operations Capability Register (DOCAR) . . . . . . . . . . . . . . 16-186

16.4.1.8 Data Streaming Information Capability Register (DSICAR). . . . . . . . . . 16-188

16.4.1.9 Data Streaming Logical Layer Control Command and Status Register

(DSLLCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-189

16.4.1.10 Processing Element Logical Layer Control Command and Status Register

(PELLCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-190

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16.4.1.11 Local Configuration Space Base Address 1 Command and Status Register

(LCSBA1CSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-190

16.4.1.12 Base Device ID Command and Status Register (BDIDCSR) . . . . . . . . . 16-191

16.4.1.13 Host Base Device ID Lock Command and Status Register

(HBDIDLCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-192

16.4.1.14 Component Tag Command and Status Register (CTCSR) . . . . . . . . . . . 16-192

16.4.1.15 Port Maintenance Block Header 0 (PMBH0). . . . . . . . . . . . . . . . . . . . . . 16-193

16.4.1.16 Port Link Time-Out Control Command and Status Register

(PLTOCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-194

16.4.1.17 Port Response Time-Out Control Command and Status Register

(PRTOCCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-194

16.4.1.18 Port General Control Command and Status Register (PGCCSR) . . . . . . 16-195

16.4.1.19 Port 1–2 Link Maintenance Request Command and Status Register

(PnLMREQCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-196

16.4.1.20 Port 1–2 Link Maintenance Response Command and Status Register

(PnLMRESPCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-197

16.4.1.21 Port 1–2 Local ackID Command and Status Register (PnLASCR) . . . . . 16-198

16.4.1.22 Port 1–2 Error and Status Command and Status Register (PnESCSR) . . 16-199

16.4.1.23 Port 1–2 Control Command and Status Register (PnCCSR) . . . . . . . . . . 16-200

16.4.1.24 Error Reporting Block Header (ERBH) . . . . . . . . . . . . . . . . . . . . . . . . . . 16-203

16.4.1.25 Logical/Transport Layer Error Detect Command and Status Register

(LTLEDCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-203

16.4.1.26 Logical/Transport Layer Error Enable Command and Status Register

(LTLEECSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-205

16.4.1.27 Logical/Transport Layer Address Capture Command and Status Register

(LTLACCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-207

16.4.1.28 Logical/Transport Layer Device ID Capture Command and Status Register

(LTLDIDCCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-208

16.4.1.29 Logical/Transport Layer Control Capture Command and Status Register

(LTLCCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-209

16.4.1.30 Port 1–2 Error Detect Command and Status Register (PnEDCSR) . . . . . 16-210

16.4.1.31 Port 1–2 Error Rate Enable Command and Status Register (PnERECSR)16-211

16.4.1.32 Port 1–2 Error Capture Attributes Command and Status Register

(PnECACSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-212

16.4.1.33 Port 1–2 Packet/Control Symbol Error Capture Command and Status Register

(PnPCSECCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-213

16.4.1.34 Port 1–2 Packet Error Capture Command and Status Register 1

(PnPECCSR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-214

16.4.1.35 Port 1–2 Packet Error Capture Command and Status Register 2

(PnPECCSR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-215

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16.4.1.36 Port 1–2 Packet Error Capture Command and Status Register 3

(PnPECCSR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-215

16.4.1.37 Port 1–2 Error Rate Command and Status Register (PnERCSR). . . . . . . 16-216

16.4.1.38 Port 1–2 Error Rate Threshold Command and Status Register

(PnERTCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-217

16.4.1.39 Logical Layer Configuration Register (LLCR) . . . . . . . . . . . . . . . . . . . . 16-218

16.4.1.40 Error/Port-Write Status Register (EPWISR):. . . . . . . . . . . . . . . . . . . . . . 16-218

16.4.1.41 Logical Retry Error Threshold Configuration Register (LRETCR). . . . . 16-219

16.4.1.42 Physical Retry Error Threshold Configuration Register (PRETCR) . . . . 16-220

16.4.1.43 Port 1–2 Alternate Device ID Command and Status Register

(PnADIDCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-220

16.4.1.44 Port 1–2 Pass-Through Accept-All Configuration Register

(PnPTAACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-222

16.4.1.45 Port 1–2 Logical Outbound Packet Time-to-Live Configuration Register

(PnLOPTTLCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-223

16.4.1.46 Port 1–2 Implementation Error Command and Status Register

(PnIECSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-224

16.4.1.47 Port 1–2 Physical Configuration Register (PnPCR). . . . . . . . . . . . . . . . . 16-225

16.4.1.48 Port 1–2 Serial Link Command and Status Register (PnSLCSR) . . . . . . 16-226

16.4.1.49 Port 1–2 Serial Link Error Injection Configuration Register

(PnSLEICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-226

16.4.1.50 Port n Arbitration 0 Tx Configuration Register (PnA0TxCR). . . . . . . . . 16-227

16.4.1.51 Port n Arbitration 1 Tx Configuration Register (PnA1TxCR). . . . . . . . . 16-229

16.4.1.52 Port n Arbitration 2 Tx Configuration Register (PnA2TxCR). . . . . . . . . 16-230

16.4.1.53 Port n Message Request Tx Buffer Allocation Configuration Register 0

(PnMReqTxBACR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-232

16.4.1.54 Port n Message Request Tx Buffer Allocation Configuration Register 1

(PnMReqTxBACR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-233

16.4.1.55 Port n Message Request Tx Buffer Allocation Configuration Register 2

(PnMReqTxBACR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-235

16.4.1.56 Port n Message Response/Flow Control Tx Buffer Allocation

Configuration Register (PnMRspFcTxBACR) . . . . . . . . . . . . . . . . . . . . 16-236

16.4.1.57 IP Block Revision Register 1 (IPBRR1) . . . . . . . . . . . . . . . . . . . . . . . . . 16-237

16.4.1.58 IP Block Revision Register 2 (IPBRR2) . . . . . . . . . . . . . . . . . . . . . . . . . 16-238

16.4.1.59 Port 1–2 RapidIO Outbound Window Translation Address

Registers x (PnROWTARx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-238

16.4.1.60 Port 1–2 RapidIO Outbound Window Translation Extended Address

Registers x (PnROWTEARx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-239

16.4.1.61 Port 1–2 RapidIO Outbound Window Base Address Registers x

(PnROWBARx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-240

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16.4.1.62 Port 1–2 RapidIO Outbound Window Attributes Registers x

(PnROWARx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-241

16.4.1.63 Port 1–2 RapidIO Outbound Window Segment 1–3 Registers 1–8

(PnROWSxRy). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-243

16.4.1.64 Port 1–2 RapidIO Inbound Window Translation Address Registers x

(PnRIWTARx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-244

16.4.1.65 Port 1–2 RapidIO Inbound Window Base Address Registers x

(PnRIWBARx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-244

16.4.1.66 Port 1–2 RapidIO Inbound Window Attributes Registers x

(PnRIWARx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-245

16.4.2 eMSG, BMLite, and QMLite Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-247

16.4.2.1 Inbound Block m Type8 Classification Unit n Mode Register

(IBmT8CnMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-247

16.4.2.2 Inbound Block m Type8 Classification n Status Register (IBmT8CnSR) 16-248

16.4.2.3 Inbound Block m Type8 Classification n Message Queue Register . . . . 16-248

16.4.2.4 Inbound Block m Type8 Classification n Rule Value Register 0

(IBmT8CnRVR0) and Inbound Block m Type8 Classification n Rule Value

16.4.2.5 Inbound Block m Type8 Classification n Rule Mask Register 0

(IBmT8CnRMR0) and Inbound Block m Type8 Classification n Rule Mask

16.4.2.6 Inbound Block m Type8 Classification n Data Buffer Pool Register

(IBmT8CnDBPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-253

16.4.2.7 Inbound Block m Type8 Classification n Data Offset Register

(IBmT8CnDOR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-255

16.4.2.8 Inbound Block m Type9 Classification n Mode Registers

(IBmT9CnMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-255

16.4.2.9 Inbound Block m Type9 Classification n Status Register (IBmT9CnSR) 16-256

16.4.2.10 Inbound Block m Type9 Classification n Message Queue Register . . . . 16-257

16.4.2.11 Inbound Block m Type9 Classification n Rule Value Register 0

(IBmT9CnRVR0) and Inbound Block m Type9 Classification n Rule Value

16.4.2.12 Inbound Block m Type9 Classification n Rule Mask Register 0 (IBmT9CnRMR)

and Inbound Block m Type9 Classification n Rule Mask Register 1

(IBmT9CnRMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-259

16.4.2.13 Inbound Block m Type9 Classification n Flow Control Destination Register

(IBmT9CnFCDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-261

16.4.2.14 Inbound Block m Type9 Classification n Data Buffer Pool Register

(IBmT9CnDBPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-262

16.4.2.15 Inbound Block m Type9 Classification n Data Offset Register

(IBmT9CnDOR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-263

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16.4.2.16 Inbound Block m Type9 Classification n Scatter/Gather Buffer Pool Register

(IBmT9CnSGBPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-264

16.4.2.17 Inbound Block m Type10 Classification n Mode Register

(IBmT10CnMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-265

16.4.2.18 Inbound Block m Type10 Classification n Status Register

(IBmT10CnSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-266

16.4.2.19 Inbound Block m Type10 Classification n Message Queue Register . . . 16-267

16.4.2.20 Inbound Block m Type10 Classification n Rule Value Register 0

(IBmT10CnRVR0) and Inbound Block m Type10 Classification n Rule Value

16.4.2.21 Inbound Block m Type10 Classification n Rule Mask Register 0

(IBmT10CnRMR0) and Inbound Block m Type10 Classification n Rule Mask

16.4.2.22 Inbound Block m Type10 Classification n Data Buffer Pool Register

(IBmT10CnDBPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-271

16.4.2.23 Inbound Block m Type10 Classification n Data Offset Register

(IBmT10CnDOR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-272

16.4.2.24 Inbound Block m Type11 Classification n Mode Registers

(IBmT11CnMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-273

16.4.2.25 Inbound Block m Type11 Classification n Status Register

(IBmT11CnSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-275

16.4.2.26 Inbound Block m Type11 Classification n Message Queue Register

(IBmT11CnMQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-275

16.4.2.27 Inbound Block m Type11 Classification n Rule Value Register 0

(IBmT11CnRVR0) and Inbound Block m Type11 Classification n Rule Value

16.4.2.28 Inbound Block m Type11 Classification n Rule Mask Register 0

(IBmT11CnRMR0) and Inbound Block m Type11 Classification n Rule Mask Register 1

(IBmT11CnRMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-278

16.4.2.29 Inbound Block m Type11 Classification Unit n Data Buffer Pool Register

(IBmT11CnDBPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-280

16.4.2.30 Inbound Block m Type11 Classification Unit n Data Offset Register

(IBmT11CnDOR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-281

16.4.2.31 Inbound Block m Message Queue n Mode Registers (IBmMQnMR) . . . 16-281

16.4.2.32 Inbound Block m Message Queue n Status Registers (IBmMQnSR) . . . 16-282

16.4.2.33 Inbound Block m Message Queue n Dequeue Pointer Address Registers

(IBmMQnDPAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-283

16.4.2.34 Inbound Block m Message Queue n Enqueue Pointer Address Registers

(IBmMQnEPAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-284

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16.4.2.35 Inbound Block m Message Queue n Congestion Management Register

(IBmMQnCMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-285

16.4.2.36 Inbound Block m Message Queue Interrupt Enable Registers

(IBmMQIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-286

16.4.2.37 Inbound Block m Message Queue Interrupt Detect Registers

(IBmMQIDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-288

16.4.2.38 Inbound Block m Message Queue n Interrupt Coalescing Registers

(IBmMQnICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-289

16.4.2.39 Outbound Block m Message Queue n Mode Registers (OBmMQnMR). 16-290

16.4.2.40 Outbound Block m Message Queue n Status Registers (OBmMQnSR) . 16-292

16.4.2.41 Outbound Block m Message Queue n Dequeue Pointer Address Registers

(OBmMQnDPAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-292

16.4.2.42 Outbound Block m Message Queue n Enqueue Pointer Address Registers

(OBmMQnEPAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-293

16.4.2.43 Outbound Block m Message Queue Interrupt Enable Registers

(OBmMQIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-294

16.4.2.44 Outbound Block m Message Queue Interrupt Detect Registers

(OBmMQIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-296

16.4.2.45 Outbound Block m Completion Queue Mode Registers (OBmCQMR) . 16-297

16.4.2.46 Outbound Block m Completion Queue Status Registers (OBmCQSR). . 16-298

16.4.2.47 Outbound Block m Completion Queue Dequeue Pointer Address Registers

(OBmMQnDPAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-298

16.4.2.48 Outbound Block m Completion Queue Enqueue Pointer Address Registers

(OBmCQEPAR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-299

16.4.2.49 Outbound Block m Completion Queue Interrupt Coalescing Registers

(OBmCQICR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-300

16.4.2.50 Software Portal Interrupt Status Register (SWPn_ISR). . . . . . . . . . . . . . 16-301

16.4.2.51 Software Portal Interrupt Enable Register (SWPn_IER) . . . . . . . . . . . . . 16-302

16.4.2.52 Software Portal Interrupt Status Disable Register (SWPn_ISDR). . . . . . 16-303

16.4.2.53 Software Portal Interrupt Inhibit Register (SWPn_IIR). . . . . . . . . . . . . . 16-304

16.4.2.54 Software Portal Interrupt Force Register (SWPn_IFR) . . . . . . . . . . . . . . 16-304

16.4.2.55 Software Portal Configuration/Assign, Enable, and Base Address

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-305

16.4.2.56 Software Portal Acquire Consumer Index (SWPn_ACQ_CI_RINGk) . . 16-309

16.4.2.57 Software Portal Release Producer Index (SWPn_REL_PI_RINGk) . . . . 16-310

16.4.2.58 Software Portal Acquire Producer Index (SWPn_ACQ_PI_RINGk) . . . 16-311

16.4.2.59 Software Portal Release Consumer Index (SWPn_REL_CI_RINGk). . . 16-313

16.4.2.60 Message Queue Mode Register (MQMR) . . . . . . . . . . . . . . . . . . . . . . . . 16-314

16.4.2.61 Outbound Message Queue Dequeue Scheduler Configuration Register 1

(OMQDSCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-314

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16.4.2.62 Outbound Message Queue Dequeue Scheduler Configuration Register 2

(OMQDSCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-315

16.4.2.63 Message Queue Interrupt Enable Register (MQIER). . . . . . . . . . . . . . . . 16-316

16.4.2.64 Message Queue Error Detect Registers (MQEDR) . . . . . . . . . . . . . . . . . 16-316

16.4.2.65 Message Queue Error Capture Address Register (MQECAR) . . . . . . . . 16-317

16.4.2.66 S/W Portal Depletion Entry Threshold Register (POOLk_SWDET) . . . 16-318

16.4.2.67 S/W Portal Depletion Exit Threshold Register (POOLk_SWDXT) . . . . 16-318

16.4.2.68 S/W Portal Depletion Count Register (POOLk_SDCNT) . . . . . . . . . . . . 16-319

16.4.2.69 Pool Content Register (POOLk_CONTENT) . . . . . . . . . . . . . . . . . . . . . 16-319

16.4.2.70 H/W Portal Depletion Entry Threshold Register (POOLk_HWDET). . . 16-320

16.4.2.71 H/W Portal Depletion Exit Threshold Register (POOLk_HWDXT). . . . 16-321

16.4.2.72 H/W Portal Depletion Count Register (POOLk_HDCNT) . . . . . . . . . . . 16-321

16.4.2.73 Free List Head Pointer Register (POOLk_HDPTR) . . . . . . . . . . . . . . . . 16-322

16.4.2.74 AXI Configuration Registers (AXI_CFG_[1–2]) . . . . . . . . . . . . . . . . . . 16-322

16.4.2.75 Buffer Pointer Range Release Registers (BPRR_{CFG,START,END}) 16-325

16.4.2.76 Free Buffer Proxy Record Free Pool Count (FBPR_FPC). . . . . . . . . . . . 16-327

16.4.2.77 Free Buffer Proxy Record List Head Pointer Register (FBPR_HDPTR) 16-328

16.4.2.78 FBPR Free Pool Depletion Interrupt Threshold (FBPR_FP_THRES) . . 16-328

16.4.2.79 Dynamic Power Management Configuration (DPM_CFG). . . . . . . . . . . 16-328

16.4.2.80 Error Interrupt Status Register (ERR_ISR) . . . . . . . . . . . . . . . . . . . . . . . 16-329

16.4.2.81 Error Interrupt Enable Register (ERR_IER) . . . . . . . . . . . . . . . . . . . . . . 16-330

16.4.2.82 Interrupt Status Disable Register (ERR_ISDR) . . . . . . . . . . . . . . . . . . . . 16-331

16.4.2.83 Error Interrupt Inhibit Register (ERR_IIR) . . . . . . . . . . . . . . . . . . . . . . . 16-332

16.4.2.84 Error Interrupt Force Register (ERR_IFR). . . . . . . . . . . . . . . . . . . . . . . . 16-332

16.4.2.85 Single Bit ECC Error Threshold Register (SBET). . . . . . . . . . . . . . . . . . 16-333

16.4.2.86 Single Bit ECC Error Count Registers (SBEC) . . . . . . . . . . . . . . . . . . . . 16-333

16.4.2.87 External Memory Access Interrupt Capture Register (EMAI_ECR). . . . 16-334

16.4.2.88 External Memory Access Interrupt Address Register (EMAI_EADR) . . 16-335

16.4.2.89 External Memory Corruption Interrupt Capture Register (EMCI_ECR). 16-336

16.4.2.90 External Memory Corruption Interrupt Address Register

(EMCI_EADR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-337

16.4.2.91 IP Block Revision 1 Register (IP_REV_1) . . . . . . . . . . . . . . . . . . . . . . . 16-337

16.4.2.92 IP Block Revision 2 Register (IP_REV_2) . . . . . . . . . . . . . . . . . . . . . . . 16-338

16.4.2.93 Message Unit Mode Register (MUMR). . . . . . . . . . . . . . . . . . . . . . . . . . 16-339

16.4.2.94 Message Unit Status Register (MUSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 16-339

16.4.2.95 Message Unit Interrupt Enable Registers (MUIER) . . . . . . . . . . . . . . . . 16-340

16.4.2.96 Message Unit Error Detect Registers (MUEDR). . . . . . . . . . . . . . . . . . . 16-341

16.4.2.97 Message Unit Interrupt Coalescing Registers (MUICR) . . . . . . . . . . . . . 16-342

16.4.2.98 Message Unit T8 Drop Counter Registers (MUT8DCR). . . . . . . . . . . . . 16-343

16.4.2.99 Message Unit T9 Drop Counter Registers (MUT9DCR). . . . . . . . . . . . . 16-343

16.4.2.100 Message Unit Error Capture MQ Register (MUECMQR). . . . . . . . . . . . 16-344

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16.4.2.101 Message Unit Error Capture CD Register 0 (MUECCDR0) . . . . . . . . . . 16-344

16.4.2.102 Message Unit Error Capture CD Register 1 (MUECCDR1) . . . . . . . . . . 16-345

16.4.2.103 Message Unit Error Capture CD Register 2 (MUECCDR2) . . . . . . . . . . 16-345

16.4.2.104 Message Unit Error Capture CD Register 3 (MUECCDR3) . . . . . . . . . . 16-346

16.4.2.105 Message Unit Error Capture Address Register (MUECAR). . . . . . . . . . 16-346

16.4.2.106 Message Unit Arbitration Weight Register (MUAWR). . . . . . . . . . . . . . 16-347

16.4.2.107 Message Unit Outbound Interleaving Mask Register (MUOIMR) . . . . . 16-348

16.4.2.108 Message Unit Segmentation Execution Privilege Register 0 (MUSEPR0)

and Message Unit Segmentation Execution Privilege Register 1

(MUSEPR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-348

16.4.2.109 Message Unit Reassembly Context Assignment Registers 0–2

(MURCAR0–2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-350

16.4.2.110 IP Block Revision Register 0 (IPBRR0) for eMSG . . . . . . . . . . . . . . . . . 16-352

16.4.2.111 IP Block Revision Register 1 (IPBRR1) for eMSG . . . . . . . . . . . . . . . . . 16-352

16.5 Programming Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-353

17 Common Public Radio Interface (CPRI) Complex

17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2

17.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

17.3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

17.3.1 CPRI Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

17.3.1.1 CPRI Framer Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6

17.3.1.2 CPRI Framer Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7

17.3.1.3 Auto Negotiation (Setup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9

17.3.1.3.1 Autonegotiation (Setup) Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10

17.3.1.3.2 Protocol Setup (State C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11

17.3.1.3.3 C&M Channel Rate Setup (State D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12

17.3.1.3.4 DMA Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13

17.3.1.3.5 State E—Interface and Vendor Specific Negotiation . . . . . . . . . . . . . . . 17-13

17.3.1.4 CPRI AxC Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13

17.3.1.4.1 Basic AxC Mapping Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13

17.3.1.4.2 Advanced AxC Mapping Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17

17.3.1.4.3 CPRI IQ MAP Interface Synchronization . . . . . . . . . . . . . . . . . . . . . . . . 17-22

17.3.1.5 Control Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23

17.3.1.5.1 Control Words Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23

17.3.1.5.2 Control Words Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25

17.3.1.5.3 Fast C&M Channel (Ethernet). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25

17.3.1.5.4 Slow C&M Channel (HDLC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27

17.3.2 The CPRI Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27

17.3.3 CPRI DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-28

17.3.3.1 Receive DMA and Transmit DMA Memories . . . . . . . . . . . . . . . . . . . . . . 17-29

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17.3.3.2 Receive IQ Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30

17.3.3.3 Transmit IQ Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-33

17.3.3.4 Receive VSS (Vendor Specific Data) Data Flow. . . . . . . . . . . . . . . . . . . . 17-34

17.3.3.5 Transmit VSS (Vendor Specific Data) Data Flow . . . . . . . . . . . . . . . . . . . 17-35

17.3.3.6 Receive Ethernet Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-36

17.3.3.7 Receive Ethernet Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-38

17.3.3.8 Transmit Ethernet Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-38

17.3.3.9 Ethernet Transmit Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-39

17.3.3.10 Receive HDLC Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-39

17.3.3.11 Receive HDLC Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-40

17.3.3.12 Transmit HDLC Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-40

17.3.3.13 HDLC Transmit Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-41

17.3.4 Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-41

17.3.5 Chip Rate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-42

17.3.5.1 Uplink Functional Description in Chip Rate Mode . . . . . . . . . . . . . . . . . . 17-42

17.3.5.2 AxC Data Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-43

17.3.5.3 Uplink Delay in Chip Rate Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-46

17.3.5.4 Downlink Functional Description in Chip Rate Mode. . . . . . . . . . . . . . . . 17-46

17.3.5.5 Down Link Latency.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-47

17.3.6 External Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-47

17.3.6.1 Star Topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-48

17.3.6.2 Chain Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-48

17.3.7 CPRI Double Sampling Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-50

17.3.8 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-51

17.3.8.1 Timer Sync State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-53

17.3.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-54

17.3.10 L1 Inband Protocol Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-56

17.3.11 CP_LOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-57

17.3.12 Delay Measurement and Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-57

17.3.12.1 CPRI Transmission Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-59

17.3.12.2 CPRI Reception Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-60

17.3.12.3 Delay Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-62

17.4 CPRI Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-62

17.4.1 CPRI Framer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-66

17.4.1.1 CPRI Status Register (CPRIn_STATUS) . . . . . . . . . . . . . . . . . . . . . . . . . 17-66

17.4.1.2 CPRI Configuration (CPRIn_CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-67

17.4.1.3 CPRI Receive Line Coding Violation Counter (CPRIn_LCV) . . . . . . . . . 17-68

17.4.1.4 CPRI Recovered BFN Counter (CPRIn_BFN) . . . . . . . . . . . . . . . . . . . . . 17-69

17.4.1.5 CPRI Recovered HFN Counter (CPRIn_HFN) . . . . . . . . . . . . . . . . . . . . . 17-69

17.4.1.6 CPRI Hardware Reset from Control Word (CPRIn_HW_RESET) . . . . . . 17-70

17.4.1.7 CPRI Control and Management Configuration (CPRIn_CM_CONFIG) . 17-71

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17.4.1.8 CPRI Control and Management Status (CPRIn_CM_STATUS). . . . . . . . 17-72

17.4.1.9 CPRI Receive Delay (CPRIn_RX_DELAY) . . . . . . . . . . . . . . . . . . . . . . . 17-73

17.4.1.10 CPRI Round Trip Delay (CPRIn_ROUND_DELAY). . . . . . . . . . . . . . . . 17-73

17.4.1.11 CPRI Extended Delay Measurement Configuration

(CPRIn_EX_DELAY_CONFIG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-74

17.4.1.12 CPRI Extended Delay Measurement Status

(CPRIn_EX_DELAY_STATUS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-75

17.4.1.13 CPRI Transmit Protocol Version (CPRIn_TX_PROT_VER) . . . . . . . . . . 17-75

17.4.1.14 CPRI Transmit Scrambler Seed (CPRIn_TX_SCR_SEED) . . . . . . . . . . . 17-76

17.4.1.15 CPRI Receive Scrambler Seed (CPRIn_RX_SCR_SEED) . . . . . . . . . . . . 17-77

17.4.1.16 CPRI SerDes Interface Configuration (CPRIn_SERDES_CONFIG) . . . . 17-77

17.4.1.17 CPRI Mapping Configuration (CPRIn_MAP_CONFIG) . . . . . . . . . . . . . 17-78

17.4.1.18 CPRI Mapping Counter Configuration (CPRIn_MAP_CNT_CONFIG) . 17-79

17.4.1.19 CPRI Mapping Table Configuration (CPRIn_MAP_TBL_CONFIG). . . . 17-79

17.4.1.20 CPRI RX AxC Container Mapping Block Offset

(CPRIn_MAP_OFFSET_RX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-80

17.4.1.21 CPRI TX AxC Container Mapping Block Offset

(CPRIn_MAP_OFFSET_TX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-81

17.4.1.22 CPRI Offset for TX Start Synchronization Output

(CPRIn_START_OFFSET_TX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-81

17.4.1.23 CPRI Mapping Buffer RX Status register <y>

(CPRIn_IQ_RX_BUF_STATUS<y>) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-82

17.4.1.24 CPRI Mapping Buffer TX Status Register<y>

(CPRIn_IQ_TX_BUF_STATUS<y>) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-83

17.4.1.25 Ethernet Receive Status (CPRIn_ETH_RX_STATUS). . . . . . . . . . . . . . . 17-84

17.4.1.26 Ethernet Feature Enable/Disable and Trigger Enable Bits

(CPRIn_ETH_CONFIG_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-85

17.4.1.27 Ethernet Miscellaneous Configuration (CPRIn_ETH_CONFIG_2) . . . . . 17-86

17.4.1.28 Ethernet RX Packet Discard (CPRIn_ETH_RX_CONTROL) . . . . . . . . . 17-87

17.4.1.29 Ethernet RX External Status (CPRIn_ETH_RX_EX_STATUS) . . . . . . . 17-87

17.4.1.30 Ethernet 16 MSB of MAC Address (CPRIn_ETH_ADDR_MSB) . . . . . . 17-88

17.4.1.31 Ethernet 32 LSB of MAC Address (CPRIn_ETH_ADDR_LSB) . . . . . . . 17-89

17.4.1.32 Ethernet Small 32-Entries Hash Table to Filter Multicast Traffic

(CPRIn_ETH_HASH_TABLE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-89

17.4.1.33 Ethernet Configuration 3 (CPRIn_ETH_CONFIG_3). . . . . . . . . . . . . . . . 17-90

17.4.1.34 Ethernet Receive Frame Counter (CPRIn_ETH_CNT_RX_FRAME) . . . 17-91

17.4.1.35 HDLC Receive Status (CPRIn_HDLC_RX_STATUS) . . . . . . . . . . . . . . 17-91

17.4.1.36 HDLC Different Feature Enable/Disable and Trigger Enable

(CPRIn_HDLC_CONFIG_1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-92

17.4.1.37 HDLC Miscellaneous Configuration (CPRIn_HDLC_CONFIG_2) . . . . . 17-93

17.4.1.38 HDLC RX Packet Discard (CPRIn_HDLC_RX_CONTROL) . . . . . . . . . 17-94

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17.4.1.39 HDLC RX External Status (CPRIn_HDLC_RX_EX_STATUS) . . . . . . . 17-94

17.4.1.40 HDLC Configuration 3 (CPRIn_HDLC_CONFIG_3) . . . . . . . . . . . . . . . 17-95

17.4.1.41 HDLC Receive Frame Counter (CPRIn_HDLC_CNT_RX_FRAME) . . . 17-96

17.4.2 CPRI Complex Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-97

17.4.2.1 Receive IQ MBus Transaction Size (CPRInRIQMTS) . . . . . . . . . . . . . . . 17-97

17.4.2.2 Receive IQ Second Destination Mbus Transaction Size

(CPRInRIQSDMTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-98

17.4.2.3 Transmit IQ MBus Transaction Size (CPRInTIQMTS) . . . . . . . . . . . . . . 17-99

17.4.2.4 Receive VSS MBus Transaction Size (CPRInRVSSMTS) . . . . . . . . . . . 17-100

17.4.2.5 Transmit VSS MBus Transaction Size (CPRInTVSSMTS) . . . . . . . . . . 17-100

17.4.2.6 Receive IQ Second Destination Base Address (CPRInRIQSDBA). . . . . 17-101

17.4.2.7 Receive IQ Buffer Size (CPRInRIQBS) . . . . . . . . . . . . . . . . . . . . . . . . . 17-102

17.4.2.8 Receive IQ Second Destination Buffer Size (CPRInRIQSDBS) . . . . . . 17-102

17.4.2.9 Transmit IQ Buffer Size (CPRInTIQBS). . . . . . . . . . . . . . . . . . . . . . . . . 17-103

17.4.2.10 Receive VSS Buffer Size (CPRInRVSSBS) . . . . . . . . . . . . . . . . . . . . . . 17-103

17.4.2.11 Transmit VSS Buffer Size (CPRInTVSSBS). . . . . . . . . . . . . . . . . . . . . . 17-104

17.4.2.12 Receive Ethernet Buffer Size (CPRInRETHBS) . . . . . . . . . . . . . . . . . . . 17-104

17.4.2.13 Receive HDLC Buffer Size (CPRInRHDLCBS). . . . . . . . . . . . . . . . . . . 17-105

17.4.2.14 Receive VSS Base Address (CPRInRVSSBA) . . . . . . . . . . . . . . . . . . . . 17-105

17.4.2.15 Transmit VSS Base Address (CPRInTVSSBA) . . . . . . . . . . . . . . . . . . . 17-106

17.4.2.16 Receive Ethernet BD Ring Base Address (CPRInREBDRBA) . . . . . . . 17-106

17.4.2.17 Transmit Ethernet BD Ring Base Address (CPRInTEBDRBA) . . . . . . . 17-107

17.4.2.18 Receive HDLC BD Ring Base Address (CPRInRHBDRBA) . . . . . . . . 17-107

17.4.2.19 Transmit HDLC BD Ring Base Address (CPRInTHBDRBA) . . . . . . . . 17-108

17.4.2.20 Receive Ethernet BD Ring Size (CPRInREBDRS) . . . . . . . . . . . . . . . . . 17-108

17.4.2.21 Transmit Ethernet BD Ring Size (CPRInTEBDRS) . . . . . . . . . . . . . . . . 17-109

17.4.2.22 Receive HDLC BD Ring Size (CPRInRHBDRS) . . . . . . . . . . . . . . . . . . 17-109

17.4.2.23 Transmit HDLC BD Ring Size (CPRInTHBDRS) . . . . . . . . . . . . . . . . . 17-110

17.4.2.24 Receive General CPRI Mode (CPRInRGCM). . . . . . . . . . . . . . . . . . . . . 17-110

17.4.2.25 Transmit General CPRI Mode (CPRInTGCM) . . . . . . . . . . . . . . . . . . . . 17-111

17.4.2.26 Transmit Synchronization Configuration Register (CPRInTSCR) . . . . . 17-112

17.4.2.27 Transmit CPRI Framer Buffer Size (CPRInTCFBS) . . . . . . . . . . . . . . . . 17-113

17.4.2.28 Transmit Control Table Insert Enable 1(CPRInTCTIE1) . . . . . . . . . . . . 17-114

17.4.2.29 Transmit Control Table Insert Enable 2(CPRInTCTIE2) . . . . . . . . . . . . 17-115

17.4.2.30 Timer Configuration (CPRInTMRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-116

17.4.2.31 Receive Frame Pulse Width (CPRInRFPW) . . . . . . . . . . . . . . . . . . . . . . 17-118

17.4.2.32 Transmit Frame Pulse Width (CPRInTFPW). . . . . . . . . . . . . . . . . . . . . . 17-119

17.4.3 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-120

17.4.3.1 Receive Control Register (CPRInRCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-120

17.4.3.2 Transmit Control Register (CPRInTCR) . . . . . . . . . . . . . . . . . . . . . . . . . 17-121

17.4.3.3 Receive AxC Control Register (CPRInRACCR). . . . . . . . . . . . . . . . . . . 17-122

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17.4.3.4 Transmit AxC Control Register (CPRInTACCR) . . . . . . . . . . . . . . . . . . 17-124

17.4.3.5 Receive Control Attribute Register (CPRInRCA) . . . . . . . . . . . . . . . . . . 17-125

17.4.3.6 Receive Control Data register 0 (CPRInRCD0). . . . . . . . . . . . . . . . . . . . 17-126

17.4.3.7 Receive Control Data Register 1 (CPRInRCD1) . . . . . . . . . . . . . . . . . . . 17-126

17.4.3.8 Receive Control Data Register 2 (CPRInRCD2) . . . . . . . . . . . . . . . . . . . 17-127

17.4.3.9 Transmit Control Attribute Register (CPRInTCA) . . . . . . . . . . . . . . . . . 17-128

17.4.3.10 Transmit Control Data Register 0 (CPRInTCD0) . . . . . . . . . . . . . . . . . . 17-129

17.4.3.11 Transmit Control Data register 1(CPRInTCD1) . . . . . . . . . . . . . . . . . . . 17-130

17.4.3.12 Transmit Control Data Register 2 (CPRInTCD2) . . . . . . . . . . . . . . . . . . 17-130

17.4.3.13 Receive IQ First Threshold (CPRInRIQFT) . . . . . . . . . . . . . . . . . . . . . . 17-131

17.4.3.14 Receive IQ Second Threshold (CPRInRIQST) . . . . . . . . . . . . . . . . . . . . 17-132

17.4.3.15 Receive IQ Threshold (CPRInRIQT). . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-133

17.4.3.16 Transmit IQ First Threshold (CPRInTIQFT). . . . . . . . . . . . . . . . . . . . . . 17-134

17.4.3.17 Transmit IQ Second Threshold (CPRInTIQST). . . . . . . . . . . . . . . . . . . . 17-135

17.4.3.18 Transmit IQ Threshold (CPRInTIQT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-136

17.4.3.19 Receive VSS Threshold (CPRInRVSST) . . . . . . . . . . . . . . . . . . . . . . . . 17-136

17.4.3.20 Transmit VSS Threshold (CPRInTVSST) . . . . . . . . . . . . . . . . . . . . . . . 17-137

17.4.3.21 Receive Ethernet Coalescing Threshold (CPRInRETHCT) . . . . . . . . . . 17-138

17.4.3.22 Transmit Ethernet Coalescing Threshold (CPRInTETHCT) . . . . . . . . . 17-139

17.4.3.23 CPRI Receive Control & Timing Interrupts Enable Register

(CPRInRCIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-140

17.4.3.24 CPRI Transmit Control & Timing Interrupts Enable Register

(CPRInTCIER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-141

17.4.3.25 Receive IQ Threshold Second Destination (CPRInRIQTSD) . . . . . . . . . 17-142

17.4.3.26 CPRI Error Interrupt Enable Register (CPRInEIER) . . . . . . . . . . . . . . . 17-142

17.4.3.27 Timer Enable Register (CPRInTMRE) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-144

17.4.3.28 Receive Ethernet Write Pointer Ring (CPRInREWPR). . . . . . . . . . . . . . 17-145

17.4.3.29 Transmit Ethernet Write Pointer Ring (CPRInTEWPR) . . . . . . . . . . . . . 17-146

17.4.3.30 Receive HDLC Write Pointer Ring (CPRInRHWPR) . . . . . . . . . . . . . . . 17-147

17.4.3.31 Transmit HDLC Write Pointer Ring (CPRInTHWPR) . . . . . . . . . . . . . . 17-148

17.4.3.32 Receive Antenna Carrier Parameter Register <y> (CPRInRACPR<y>) . 17-149

17.4.3.33 Transmit Antenna Carrier Parameter Register <y> (CPRInTACPR<y>) 17-150

17.4.3.34 CPRI Auxiliary Interface Mask Registers <y> (CPRInMASKR<y>) . . . 17-151

17.4.3.35 CPRI Auxiliary Control Register (CPRInAUXCR). . . . . . . . . . . . . . . . . 17-152

17.4.4 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-153

17.4.4.1 Receive IQ Buffer Displacement Register (CPRInRIQBDR) . . . . . . . . . 17-153

17.4.4.2 Receive IQ Second Destination Buffer Displacement Register

(CPRInRIQSDBDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-154

17.4.4.3 Transmit IQ Buffer Displacement Register (CPRInTIQBDR) . . . . . . . . 17-154

17.4.4.4 Receive Chips Counter Register (CPRInRCCR) . . . . . . . . . . . . . . . . . . . 17-155

17.4.4.5 Receive VSS Buffer Displacement Register (CPRInRVSSBDR) . . . . . . 17-156

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17.4.4.6 Transmit VSS Buffer Displacement Register (CPRInTVSSBDR) . . . . . 17-157

17.4.4.7 Receive Ethernet Buffer Descriptor (CPRInRETHBD). . . . . . . . . . . . . . 17-158

17.4.4.8 Transmit Ethernet Buffer Descriptor (CPRInTETHBD) . . . . . . . . . . . . . 17-159

17.4.4.9 Receive Ethernet Read Pointer Ring (CPRInRERPR) . . . . . . . . . . . . . . 17-160

17.4.4.10 Transmit Ethernet Read Pointer Ring (CPRInTERPR) . . . . . . . . . . . . . . 17-161

17.4.4.11 Receive HDLC Buffer Descriptor (CPRInRHDLCBD) . . . . . . . . . . . . . 17-162

17.4.4.12 Transmit HDLC Buffer Descriptor (CPRInTHDLCBD). . . . . . . . . . . . . 17-163

17.4.4.13 Receive HDLC Read Pointer Ring (CPRInRHRPR) . . . . . . . . . . . . . . . 17-164

17.4.4.14 Transmit HDLC Read Pointer Ring (CPRInTHRPR) . . . . . . . . . . . . . . . 17-165

17.4.4.15 Receive Event Register (CPRInRER) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-166

17.4.4.16 Transmit Event Register (CPRInTER). . . . . . . . . . . . . . . . . . . . . . . . . . . 17-167

17.4.4.17 Error Event Register (CPRInEER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-169

17.4.4.18 Receive Ethernet Coalescing Status (CPRInRETHCS) . . . . . . . . . . . . . 17-171

17.4.4.19 Transmit Ethernet Coalescing Status (CPRInTETHCS) . . . . . . . . . . . . . 17-172

17.4.4.20 TIMERn Status Register (CPRInTMRSR) . . . . . . . . . . . . . . . . . . . . . . . 17-172

17.4.4.21 Receive Status Register (CPRInRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-173

17.4.4.22 Transmit Status Register (CPRInTSR). . . . . . . . . . . . . . . . . . . . . . . . . . . 17-174

17.4.4.23 Receive Configuration Memory (CPRInRCM_<i>) . . . . . . . . . . . . . . . . 17-174

17.4.4.24 Transmit Configuration Memory (CPRInTCM_<i>). . . . . . . . . . . . . . . . 17-176

17.4.4.25 CPRI Control Clocks Register (CPRICCR). . . . . . . . . . . . . . . . . . . . . . . 17-178

17.4.4.26 CPRI Interrupt Control Register y (CPRIICR<y>) . . . . . . . . . . . . . . . . . 17-179

17.4.4.27 CPRI Receive CPU Control Interrupt Enable Register (CPRIRCCIER) 17-181

17.4.4.28 CPRI Transmit CPU Control Interrupt Enable Register (CPRITCCIER) 17-183

17.4.4.29 General Receive Synchronization Register (CPRIGRSR) . . . . . . . . . . . 17-185

17.4.4.30 General Transmit Synchronization Register (CPRIGTSR) . . . . . . . . . . . 17-186

17.4.4.31 CPRI Error Status Register (CPRIESR). . . . . . . . . . . . . . . . . . . . . . . . . . 17-187

18 QUICC Engine Subsystem

18.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2

18.2 RISC Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3

18.2.1 SC3850 Core Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3

18.2.2 Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4

18.2.3 Parameter RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4

18.2.4 Buffer Descriptors (BDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5

18.2.5 Multithreading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6

18.2.6 Serial Numbers (SNUMs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7

18.2.7 IRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8

18.3 Serial DMA Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8

18.3.1 Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8

18.3.2 SDMA and Bus Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9

18.3.2.1 Simple Recovery from Bus Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9

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18.3.2.2 Selective Peripheral Recovery Procedure . . . . . . . . . . . . . . . . . . . . . . . . . 18-10

18.3.3 SDMA and Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10

18.3.4 MBus Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10

18.3.5 SDMA Internal Resource . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11

18.4 Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11

18.4.1 Multiplexer Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11

18.4.2 Baud-Rate Generators (BRGs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13

18.5 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14

18.6 UCCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14

18.6.1 UCC Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15

18.6.2 UCC Programming Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15

18.6.2.1 Tx Virtual FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15

18.6.2.2 Multi-Threading Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-17

18.7 Ethernet Controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-17

18.7.1 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19

18.7.1.1 RGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19

18.7.1.2 SGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19

18.7.2 Ethernet Physical Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19

18.7.2.1 Reduced Gigabit Media-Independent Interface (RGMII) Signals . . . . . . . 18-20

18.7.2.1.1 RGMII Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20

18.7.2.1.2 RGMII Signal Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21

18.7.2.2 Serial Gigabit Media-Independent Interface (SGMII) Signals . . . . . . . . . 18-21

18.7.2.2.1 SGMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21

18.7.2.2.2 SGMII Signal Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-22

18.7.3 Controlling PHY Links (Management Interface) . . . . . . . . . . . . . . . . . . . . . 18-22

18.7.4 Ethernet Controller Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-23

18.7.5 Ethernet Programming Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-24

18.7.5.1 RMON Statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-24

18.7.5.2 Unreported Overrun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-24

18.7.5.3 Broadcast Status after an In-Band CRS Event . . . . . . . . . . . . . . . . . . . . . . 18-24

18.7.5.4 Pause Frame End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-24

18.7.5.5 Pause Frame Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-25

18.7.5.6 Transmit During Pause Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-25

18.7.5.7 Magic Packet Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-26

18.7.5.7.1 Failure to Exit Magic Packet Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-26

18.7.5.7.2 Malformed Magic Packet Mode Triggers Exit . . . . . . . . . . . . . . . . . . . . 18-27

18.7.5.8 Ethernet Transmit Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27

18.7.5.9 Initialization of SGMII Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27

18.8 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-29

18.8.1 SPI Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-30

18.8.1.1 SPI as a Master Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-30

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18.8.1.2 SPI as a Slave Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-32

18.8.2 SPI in Multi-Master Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-32

18.8.3 External Signal Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-34

18.8.4 SPI Transmission and Reception Process . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-34

18.9 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-35

19 UART

19.1 Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6

19.1.1 Character Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7

19.1.2 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9

19.1.3 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10

19.1.4 Parity Bit Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10

19.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10

19.2.1 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11

19.2.2 Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12

19.2.3 Framing Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17

19.2.4 Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18

19.2.5 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18

19.2.6 Baud-Rate Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18

19.2.6.1 Slow Data Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19

19.2.6.2 Fast Data Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20

19.2.7 Receiver Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20

19.2.7.1 Idle Input Line Wake-Up (WAKE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21

19.2.7.2 Address Mark Wake-Up (WAKE = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21

19.3 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21

19.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-22

19.4.1 Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-22

19.4.2 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-22

19.4.3 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23

19.4.4 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23

19.4.5 Receiver Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23

19.5 Interrupt Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24

19.6 UART Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24

19.6.1 SCI Baud-Rate Register (SCIBR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25

19.6.2 SCI Control Register (SCICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26

19.6.3 SCI Status Register (SCISR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-29

19.6.4 SCI Data Register (SCIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31

19.6.5 SCI Data Direction Register (SCIDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-32

20 Timers

20.1 Device-Level Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1

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20.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3

20.1.2 Timer Module Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3

20.1.3 Setting Up Counters for Cascaded Operation . . . . . . . . . . . . . . . . . . . . . . . . . 20-4

20.1.3.1 Operation of the Cascaded Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5

20.1.3.2 Cascading Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5

20.1.4 Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5

20.1.4.1 One-Shot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7

20.1.4.2 Pulse Output Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8

20.1.4.3 Fixed Frequency PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8

20.1.4.4 Variable Frequency PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9

20.1.5 Timer Compare Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11

20.1.5.1 Compare Preload Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12

20.1.5.2 Capture Register Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13

20.1.5.3 Broadcast from an Initiator Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13

20.1.6 System Global Timer Register (32b timers only) . . . . . . . . . . . . . . . . . . . . . 20-13

20.1.7 Resets and Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14

20.1.7.1 Timer Compare Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14

20.1.7.2 Timer Overflow Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-15

20.1.7.3 Timer Input Edge Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-15

20.1.8 Special CPRI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16

20.2 SC3850 DSP Core Subsystem Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17

20.3 Software Watchdog Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17

20.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17

20.3.2 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18

20.3.3 Software WDT Servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18

20.4 Timers Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-20

20.4.1 Device-Level Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-20

20.4.1.1 Timer Channel Control Registers (TMRnCTLx). . . . . . . . . . . . . . . . . . . . 20-22

20.4.1.2 Timer Channel Status and Control Registers (TMRnSCTLx) . . . . . . . . . . 20-24

20.4.1.3 Timer Channel Compare 1 Registers (TMRnCMP1x). . . . . . . . . . . . . . . . 20-26

20.4.1.4 Timer Channel Compare 2 Registers (TMRnCMP2x). . . . . . . . . . . . . . . . 20-26

20.4.1.5 Timer Channel Compare Load 1 Registers (TMRnCMPLD1x) . . . . . . . . 20-26

20.4.1.6 Timer Channel Compare Load 2 Registers (TMRnCMPLD2x) . . . . . . . . 20-26

20.4.1.7 Timer Channel Comparator Status and Control Registers

(TMRnCOMSCx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-27

20.4.1.8 Timer Channel Capture Registers (TMRnCAPx) . . . . . . . . . . . . . . . . . . . 20-28

20.4.1.9 Timer Channel Load Registers (TMRnLOADx) . . . . . . . . . . . . . . . . . . . . 20-28

20.4.1.10 Timer Channel Hold Registers (TMRnHOLDx) . . . . . . . . . . . . . . . . . . . . 20-28

20.4.1.11 Timer Channel Counter Registers (TMRnCNTRx) . . . . . . . . . . . . . . . . . . 20-28

20.4.1.12 Timer_32b Channel x Compare 1 Registers (TMR_32b_n_CMP1_x) . . . 20-29

20.4.1.13 Timer_32b Channel x Compare 2 Registers (TMR_32b_n_CMP2_x) . . . 20-29

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20.4.1.14 Timer_32b Channel Capture Registers (TMR_32b_nCAPx) . . . . . . . . . . 20-30

20.4.1.15 Timer_32b Channel Load Registers (TMR_32b_n_LOADx) . . . . . . . . . . 20-30

20.4.1.16 Timer_32b Channel Hold Registers (TMR_32b_n_HOLDx) . . . . . . . . . . 20-31

20.4.1.17 Timer_32b Channel Counter Registers (TMR_32b_n_CNTRx) . . . . . . . . 20-31

20.4.1.18 Timer_32b Channel Control Registers (TMR_32b_n_CTLx) . . . . . . . . . . 20-32

20.4.1.19 Timer_32b Channel Status and Control Registers (TMR_32b_n_SCRx) . 20-35

20.4.1.20 Timer_32b Channel Compare Load 1 Registers

(TMR_32b_n_CMPLD1x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-37

20.4.1.21 Timer_32b Channel Compare Load 2 Registers

(TMR_32b_n_CMPLD2x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-37

20.4.1.22 Timer_32b Channel Comparator Status and Control Registers

(TMR_32b_n_COMSCx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-38

20.4.1.23 Timer_32b Global System Timer Register (TMR_32b_n_GLB) . . . . . . . 20-39

20.4.1.24 Timer_32b Global System Timer Control Register

(TMR_32b_n_GLBCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-40

20.4.1.25 Timer_32b Timer Set and Forget Register (TMR_32b_n_SAF) . . . . . . . . 20-42

20.4.1.26 Timer_32b Timer Clear Lock Register (TMR_32b_n_CLRL) . . . . . . . . . 20-43

20.4.2 SC3850 DSP Core Subsystem Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-44

20.4.3 Software Watchdog Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-44

20.4.3.1 System Watchdog Control Register 0–7 (SWCRR[0–7]) . . . . . . . . . . . . . 20-45

20.4.3.2 System Watchdog Count Register 0–7 (SWCNR[0–7]) . . . . . . . . . . . . . . 20-46

20.4.3.3 System Watchdog Service Register 0–7 (SWSRR[0–7]). . . . . . . . . . . . . . 20-46

21 GPIO

21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1

21.2 GPIO Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2

21.3 GPIO Connection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3

21.4 GPIO Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5

21.4.1 Pin Open-Drain Register (PODR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6

21.4.2 Pin Data Register (PDAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7

21.4.3 Pin Data Direction Register (PDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8

21.4.4 Pin Assignment Register (PAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9

21.4.5 Pin Special Options Register (PSOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10

22 Hardware Semaphores 23 I

23.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2

23.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2

23.3 I

23.3.1 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3

C Module Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3

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23.3.2 Input Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3

23.3.3 Digital Input Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3

23.3.4 Transaction Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4

23.3.5 Arbitration Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4

23.3.6 Transfer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4

23.3.7 In/Out Data Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5

23.3.8 Address Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5

23.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6

23.4.1 START Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6

23.4.2 Target Address Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7

23.4.3 Repeated START Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7

23.4.4 STOP Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8

23.4.5 Arbitration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8

23.4.6 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9

23.4.7 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9

23.4.8 Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9

23.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9

23.5.1 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10

23.5.2 Generation of START. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10

23.5.3 Post-Transfer Software Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10

23.5.4 Generation of STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11

23.5.5 Generation of Repeated START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11

23.5.6 Generation of I2C_SCL When I2C_SDA Low. . . . . . . . . . . . . . . . . . . . . . . 23-11

23.5.7 Target Mode Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12

23.5.8 Target Transmitter and Received Acknowledge. . . . . . . . . . . . . . . . . . . . . . 23-12

23.5.9 Loss of Arbitration and Forcing of Target Mode . . . . . . . . . . . . . . . . . . . . . 23-12

23.5.10 Interrupt Service Routine Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12

23.6 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14

23.6.1 I2C Address Register (I2CADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14

23.6.2 I2C Frequency Divider Register (I2CFDR) . . . . . . . . . . . . . . . . . . . . . . . . . 23-15

23.6.3 I2C Control Register (I2CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-16

23.6.4 I2C Status Register (I2CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-17

23.6.5 I2C Data Register (I2CDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-19

23.6.6 Digital Filter Sampling Rate Register (I2CDFSRR). . . . . . . . . . . . . . . . . . . 23-19

24 Debugging, Profiling, and Performance Monitoring

24.1 TAP, Boundary Scan, and OCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1

24.1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2

24.1.2 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4

24.1.3 Instruction Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5

24.1.4 Multi-Core JTAG and OCE Module Concept. . . . . . . . . . . . . . . . . . . . . . . . . 24-9

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24.1.5 Enabling the OCE Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9

24.1.6 DEBUG_REQUEST and ENABLE_ONCE Commands . . . . . . . . . . . . . . . 24-10

24.1.7 RD_STATUS Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11

24.1.8 Reading/Writing OCE Registers Through JTAG . . . . . . . . . . . . . . . . . . . . . 24-11

24.1.9 Signalling a Debug Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12

24.1.10 EE_CTRL Modifications for the MSC8158E. . . . . . . . . . . . . . . . . . . . . . . . 24-13

24.1.11 ESEL_DM and EDCA_CTRL Register Programming. . . . . . . . . . . . . . . . . 24-14

24.1.12 Real-Time Debug Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14

24.1.13 Exiting Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15

24.1.14 General JTAG Mode Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16

24.1.15 JTAG and OCE Module Programming Model . . . . . . . . . . . . . . . . . . . . . . . 24-16

24.1.15.1 Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16

24.1.15.2 Boundary Scan Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-17

24.1.15.3 Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-19

24.1.15.4 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-19

24.1.15.5 Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-20

24.2 Debug and Profiling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-21

24.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-21

24.2.2 Entering Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-22

24.2.3 Exiting Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-22

24.2.4 SC3850 Debug and Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-23

24.2.5 L1 ICache and DCache Debug and Profiling . . . . . . . . . . . . . . . . . . . . . . . . 24-23

24.2.6 DMA Controller Debug and Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-23

24.2.6.1 Debug Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-23

24.2.6.2 Profiling Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-24

24.2.7 CLASS Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-24

24.2.7.1 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-24

24.2.7.2 CLASS Debug Profiling Unit (CDPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-24

24.2.8 QUICC Engine Debug and Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26

24.2.8.1 Trace Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26

24.2.8.2 Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26

24.2.9 Serial RapidIO and eMSG Debug and Profiling. . . . . . . . . . . . . . . . . . . . . . 24-26

24.2.9.1 Debug Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26

24.2.9.2 Profiling Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-27

24.2.10 CPRI Debug and Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-27

24.2.10.1 Debug Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-27

24.2.10.2 Profiling Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-28

24.2.11 Software Watchdog (SWT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-28

24.2.12 Profiling Unit Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-28

24.3 Performance Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-28

24.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-29

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24.3.1.1 Performance Monitor Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-30

24.3.1.2 Event Counting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-30

24.3.1.3 Threshold Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-30

24.3.1.4 Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-31

24.3.1.5 Performance Monitor Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-31

24.3.1.6 Performance Monitor Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-45

24.3.2 Performance Monitor Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . 24-47

24.3.2.1 Performance Monitor Global Control Register (PMGC) . . . . . . . . . . . . . . 24-48

24.3.2.2 Performance Monitor Local Control A0 Register (PMLCA0). . . . . . . . . . 24-49

24.3.2.3 Performance Monitor Local Control A[1–8] (PMLCA[1–8]) . . . . . . . . . . 24-50

24.3.2.4 Performance Monitor Counter 0 (PMC0). . . . . . . . . . . . . . . . . . . . . . . . . . 24-51

24.3.2.5 Performance Monitor Counter 1–8 (PMC[1–8]) . . . . . . . . . . . . . . . . . . . . 24-52

25 Multi Accelerator Platform Engine, Baseband 2 (MAPLE-B2)

25.1 Information Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2

25.2 MAPLE-B2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4

25.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11

25.3.1 3G Technologies Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11

25.3.2 3GLTE and WiMAX Technologies Operation Mode. . . . . . . . . . . . . . . . . . 25-11

25.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11

25.4.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12

25.4.1.1 MAPLE-B2 API. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12

25.4.1.2 Initialization Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13

25.4.2 MAPLE-B2 Configuration and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13

25.4.2.1 PE Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13

25.4.2.2 PE Arbitration Between Different Clients . . . . . . . . . . . . . . . . . . . . . . . . . 25-14

25.4.2.2.1 Arbitration Between the Three eFTPE Engines . . . . . . . . . . . . . . . . . . . 25-14

25.4.2.2.2 Internal eFTPE Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14

25.4.2.3 Buffer Descriptor (BD) Ring Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15

25.4.2.3.1 BD Rings Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15

25.4.2.3.2 BD Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16

25.4.2.3.3 BDs Data Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-19

25.4.2.4 MBus Priority Scheme Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20

25.4.2.4.1 MBus Fixed Priority Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20

25.4.2.4.2 MBus Dynamic Priority Accesses Scheme . . . . . . . . . . . . . . . . . . . . . . . 25-20

25.4.2.4.3 MBus Dynamic Priority Accesses with DMA Queue Upgrade . . . . . . . 25-21

25.4.3 Internal Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-21

25.4.3.1 MAPLE-B2 Second Generation Programmable System Interface (PSIF2) 25-22

25.4.3.1.1 Memory Error Correction/Detection Support . . . . . . . . . . . . . . . . . . . . . 25-23

25.4.3.1.2 MAPLE-B2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-25

25.4.3.1.2.1 BD Rings Done Indication Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-25

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25.4.3.1.2.2 General Error Event Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-25

25.4.3.1.2.3 General ECC Error Event Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-26

25.4.3.1.2.3.1 Detecting the Error Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-26

25.4.3.1.2.3.2 Handling a General ECC Error Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-27

25.4.3.2 eTVPE HARQ, Rate De-Matching, and Turbo/Viterbi Decoding Flow . . 25-27

25.4.3.2.1 eTVPE Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-27

25.4.3.2.2 Turbo Standard Parameter Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . 25-28

25.4.3.2.3 eTVPE Initialization Parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-28

25.4.3.2.4 eTVPE Buffer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-28

25.4.3.2.5 eTVPE Input Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-28

25.4.3.2.5.1 Input Samples Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-31

25.4.3.2.5.2 LTE HARQ Input Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-31

25.4.3.2.5.3 WiMAX HARQ Input Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-32

25.4.3.2.5.4 E-DCH HARQ with Mixed Vector Input Data Structure . . . . . . . . . . . . . . . 25-33

25.4.3.2.5.5 E-DCH HARQ with Separate Vectors Input Data Structure . . . . . . . . . . . . . 25-34

25.4.3.2.5.6 Sub-Block Interleaved Input Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . 25-36

25.4.3.2.5.7 UMTS Mixed Input Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-36

25.4.3.2.5.8 Separate Vectors Input Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-37

25.4.3.2.5.9 Viterbi Periodically Punctured Stream Input Data Structure . . . . . . . . . . . . . 25-39

25.4.3.2.5.10 eTVPE Input Data Structures Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-41

25.4.3.2.6 eTVPE Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-41

25.4.3.2.6.1 E-DCH Rate De-Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-41

25.4.3.2.6.1.1 Rate Matched Code Block Size Calculation . . . . . . . . . . . . . . . . . . . . . . . . 25-43

25.4.3.2.6.1.2 Skip Count Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-43

25.4.3.2.6.1.3 Buffer Size Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-44

25.4.3.2.6.1.4 Code Block e_ini Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-45

25.4.3.2.6.1.5 Parameters Calculation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-45

25.4.3.2.6.2 HARQ Combining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-46

25.4.3.2.6.2.1 eTVPE BD Parameter Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-46

25.4.3.2.6.2.2 Setting the HARQ Combining Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 25-48

25.4.3.2.6.2.3 Calculating the IHBSA Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-49

25.4.3.2.6.3 Sub-Block De-interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-50

25.4.3.2.6.4 Turbo Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-51

25.4.3.2.6.4.1 Turbo Channel Data Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-51

25.4.3.2.6.4.2 Turbo Processing Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-51

25.4.3.2.6.4.3 Number of Turbo Processing Elements (DREs) . . . . . . . . . . . . . . . . . . . . . 25-53

25.4.3.2.6.4.4 Turbo Stopping Criteria Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-54

25.4.3.2.6.4.5 Aposteriori Output Quality Based Stopping Criteria . . . . . . . . . . . . . . . . . 25-54

25.4.3.2.6.4.6 CRC Check Based Stopping Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-55

25.4.3.2.6.4.7 Steady CRC Based Stopping Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-55

25.4.3.2.6.4.8 Stopping Criteria Configuration Limitations . . . . . . . . . . . . . . . . . . . . . . . 25-56

25.4.3.2.6.4.9 Stopping Criteria Status Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-56

25.4.3.2.6.5 Viterbi Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-57

25.4.3.2.6.5.1 Viterbi Periodic Depuncturing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-57

25.4.3.2.6.5.2 Viterbi Decoding Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-58

25.4.3.2.6.5.3 Feed Forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-59

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25.4.3.2.6.5.4 Maximum Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-62

25.4.3.2.6.5.5 Trace-Back Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-62

25.4.3.2.6.6 Zero Tail Viterbi Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-62

25.4.3.2.6.7 Tail Biting Viterbi Processing (WAVA*) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-63

25.4.3.2.6.8 Viterbi Large Blocks Partitioning Support . . . . . . . . . . . . . . . . . . . . . . . . . . 25-64

25.4.3.2.6.9 De-Randomization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-68

25.4.3.2.6.10 CRC Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-68

25.4.3.2.7 eTVPE Output Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-69

25.4.3.2.8 Output Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-69

25.4.3.2.8.1 Aposteriori/Extrinsic Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-69

25.4.3.2.8.1.1 Aposteriori Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-69

25.4.3.2.8.1.2 Extrinsic Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-71

25.4.3.2.8.2 Soft Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-72

25.4.3.2.8.3 Hard Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-73

25.4.3.2.8.3.1 Hard Output Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-74

25.4.3.2.8.3.2 Hard Output Byte and Bit Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-74

25.4.3.2.8.3.3 Byte/Bit Ordering Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-76

25.4.3.2.9 eTVPE Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-76

25.4.3.3 eFTPE FFT/iFFT/DFT/iDFT Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . 25-77

25.4.3.3.1 eFTPE Buffer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-77

25.4.3.3.2 BD Repeat Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-77

25.4.3.3.3 Identical Output Scale Alignment for BD Repeat . . . . . . . . . . . . . . . . . . 25-79

25.4.3.3.4 eFTPE Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-80

25.4.3.3.4.1 Input Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-80

25.4.3.3.4.1.1 Guard Band Insertion for iFFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-82

25.4.3.3.4.1.2 Zero Padding Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-84

25.4.3.3.4.1.3 Cyclic Prefix Removal for FFT BD Repeat . . . . . . . . . . . . . . . . . . . . . . . . 25-84

25.4.3.3.4.1.4 Input Buffers Offset (in KBs) for FFT BD Repeat . . . . . . . . . . . . . . . . . . . 25-85

25.4.3.3.4.1.5 Input Buffers Offset (in 16 Bytes multiplication) for DFT/iDFT BD

Repeat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-86

25.4.3.3.4.2 Output Data Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-87

25.4.3.3.4.2.1 Guard Band Removal for FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-87

25.4.3.3.4.2.2 Cyclic Prefix Insertion for iFFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-89

25.4.3.3.5 Pre and Post Vector Multiplication Support . . . . . . . . . . . . . . . . . . . . . . 25-89

25.4.3.3.5.1 Pre-Multiplication Processing Support in the eFTPE . . . . . . . . . . . . . . . . . . 25-90

25.4.3.3.5.2 Post-Multiplication processing support in the eFTPE . . . . . . . . . . . . . . . . . . 25-93

25.4.3.3.5.3 ‘One-Shot’ Initialization of the Pre/Post Multiplication buffers . . . . . . . . . . 25-95

25.4.3.3.6 Scalar Post Multiplication in eFTPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-96

25.4.3.3.7 Frequency Correction Support in eFTPE . . . . . . . . . . . . . . . . . . . . . . . . 25-96

25.4.3.3.7.1 Frequency Correction Support during BD Repeat . . . . . . . . . . . . . . . . . . . . . 25-98

25.4.3.3.8 WCDMA Scrambled Pilot Code Generation. . . . . . . . . . . . . . . . . . . . . . 25-98

25.4.3.3.8.1 Pilot Symbols Generation and Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-99

25.4.3.3.8.2 Scrambling Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-100

25.4.3.3.8.3 Combining Pilot Symbols and Scrambling Code . . . . . . . . . . . . . . . . . . . . 25-100

25.4.3.3.8.4 Code Generation with BD Repeat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-101

25.4.3.3.8.5 Code Generation with Zero Padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-101

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25.4.3.3.8.6 Code Generation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-102

25.4.3.3.9 eFTPE Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-102

25.4.3.3.9.1 eFTPE Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-102

25.4.3.3.9.2 Inverse Transform Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-106

25.4.3.3.9.3 Transform Length Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-106

25.4.3.3.9.4 eFTPE Internal Scaling Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-107

25.4.3.3.9.4.1 Scaling During Internal Radix Calculations. . . . . . . . . . . . . . . . . . . . . . . 25-108

25.4.3.3.9.4.2 User Defined Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-109

25.4.3.3.9.4.3 Adaptive Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-109

25.4.3.3.9.4.4 Overall Scaling Amount Programming . . . . . . . . . . . . . . . . . . . . . . . . . . 25-110

25.4.3.3.9.4.5 Input Exponent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-111

25.4.3.3.9.4.6 User Defined Input Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-111

25.4.3.3.9.4.7 Adaptive Input Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-112

25.4.3.3.9.4.8 Extra Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-113

25.4.3.3.9.4.9 Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-113

25.4.3.3.10 eFTPE Initialization Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-113

25.4.3.3.10.1 eFTPE Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-114

25.4.3.3.10.2 Data Size Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-115

25.4.3.3.11 eFTPE Status Indications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-115

25.4.3.3.12 eFTPE ECC Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-116

25.4.3.4 DEPE Downlink Turbo Encoding Operation. . . . . . . . . . . . . . . . . . . . . . 25-116

25.4.3.4.1 DEPE Buffer Descriptors and Header Structures . . . . . . . . . . . . . . . . . 25-117

25.4.3.4.2 DEPE Multiple Headers (tasks) in single BD support. . . . . . . . . . . . . . 25-117

25.4.3.4.3 [LH] Indication in DEPE Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-118

25.4.3.4.4 DEPE Input Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-118

25.4.3.4.4.1 Input Buffer Offset Support (3GLTE and UMTS only) . . . . . . . . . . . . . . . 25-119

25.4.3.4.4.2 Input Data Structure for Multiple Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-119

25.4.3.4.5 DEPE Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-120

25.4.3.4.5.1 3GLTE Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-120

25.4.3.4.5.1.1 Add Filler Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-121

25.4.3.4.5.1.2 CRC Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-121

25.4.3.4.5.1.3 Turbo Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-121

25.4.3.4.5.1.4 Rate Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-121

25.4.3.4.5.2 WiMAX Processing (802.16e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-124

25.4.3.4.5.2.1 CRC Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-124

25.4.3.4.5.2.2 Randomization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-125

25.4.3.4.5.2.3 Turbo Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-125

25.4.3.4.5.2.4 Rate Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-125

25.4.3.4.5.3 WiMAX Processing (802.16m) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-127

25.4.3.4.5.3.1 Turbo Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-127

25.4.3.4.5.3.2 Bit Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-128

25.4.3.4.5.4 UMTS Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-129

25.4.3.4.5.4.1 CRC Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-130

25.4.3.4.5.4.2 Scrambling (FDD Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-130

25.4.3.4.5.4.3 Turbo Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-130

25.4.3.4.5.4.4 Rate Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-131

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25.4.3.4.5.4.5 Bit Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-133

25.4.3.4.5.4.6 UMTS Transport Block (TB) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-133

25.4.3.4.5.4.7 UMTS Processing Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-135

25.4.3.4.5.4.8 Code Blocks Encoding Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-135

25.4.3.4.6 DEPE Output Data Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-137

25.4.3.4.6.1 Output Buffer Offset and Concatenate Output Support

(3GLTE and UMTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-138

25.4.3.4.6.2 Output Data Structure for Multiple Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . 25-140

25.4.3.4.6.3 Separate Vectors Output Data Structure for UMTS . . . . . . . . . . . . . . . . . . 25-141

25.4.3.4.7 BD Status Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-142

25.4.3.5 CRPE Uplink/Downlink UMTS Chip Rate Processing Operation . . . . . 25-143

25.4.3.5.1 Chip Rate Uplink Batch Processing Element . . . . . . . . . . . . . . . . . . . . 25-143

25.4.3.5.1.1 CRPE-ULB Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-143

25.4.3.5.1.1.1 CRPE-ULB API Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-143

25.4.3.5.1.1.2 CRPE-ULB Parameters Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-144

25.4.3.5.1.1.3 CRPE-ULB Core Descriptors Initialization . . . . . . . . . . . . . . . . . . . . . . . 25-145

25.4.3.5.1.1.4 CRPE-ULB Registers Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-145

25.4.3.5.1.1.5 Maple_crpe_ulb_init Routine Activation . . . . . . . . . . . . . . . . . . . . . . . . . 25-145

25.4.3.5.1.2 CRPE-ULB Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-145

25.4.3.5.1.2.1 Interpolation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-146

25.4.3.5.1.2.2 Delay Spread Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-146

25.4.3.5.1.2.3 Finger Combining Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-146

25.4.3.5.1.2.4 One Output Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-148

25.4.3.5.1.3 CRPE-ULB General Processing Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-148

25.4.3.5.1.4 CRPE-ULB Data Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-150

25.4.3.5.1.5 CRPE-ULB Command Processing Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-150

25.4.3.5.1.5.1 Core Descriptors and Command List Size Table . . . . . . . . . . . . . . . . . . . 25-152

25.4.3.5.1.5.2 Finger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-153

n 16 Bytes Finger Command size . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-154

25-87 8 Bytes Finger Command size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-154

25.4.3.5.1.5.3 PCH Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-154

25.4.3.5.1.6 Interpolation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-155

25.4.3.5.1.6.1 Internal Interpolation Antenna Input Data Structure (INT_MODE = 1) . 25-156

25.4.3.5.1.6.2 External Interpolation 2x Antenna Input Data Structure

(INT_MODE=0, IIL=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-156

25.4.3.5.1.6.3 External Interpolation 4x Antenna Input Data Structure

(INT_MODE=0, IIL=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-157

25.4.3.5.1.6.4 External Interpolation 8x Antenna Input Data Structure

(INT_MODE=0, IIL=2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-158

25.4.3.5.1.6.5 External Interpolation 16x Antenna Input Data Structure

(INT_MODE=0, IIL=3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-159

25.4.3.5.1.7 Antenna Input Sub Slot Data Structure (All modes) . . . . . . . . . . . . . . . . . . 25-159

25.4.3.5.1.8 Internal Interpolation Processing implementation . . . . . . . . . . . . . . . . . . . . 25-160

25.4.3.5.1.8.1 Interpolation x16: INT_MODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-161

25.4.3.5.1.8.2 Interpolation x8: INT_MODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-161

25.4.3.5.1.8.3 Interpolation x4: INT_MODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-162

25.4.3.5.1.8.4 Interpolation x2: INT_MODE = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-162

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25.4.3.5.1.8.5 Internal Interpolation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-162

25.4.3.5.1.8.6 Interpolation Saturation During Internal Interpolation . . . . . . . . . . . . . . . 25-163

25.4.3.5.1.9 Descrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-163

25.4.3.5.1.9.1 Scrambling Data Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-164

25.4.3.5.1.9.2 Descrambling Using Long Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-165

25.4.3.5.1.9.3 Descrambling Using Short Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-166

25.4.3.5.1.10 Despreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-167

25.4.3.5.1.11 Combining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-167

25.4.3.5.1.12 Finger Combining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-167

25.4.3.5.1.12.1 FC Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-169

25.4.3.5.1.12.2 Frequency Correction Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-169

25.4.3.5.1.13 Output Buffer Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-170

25.4.3.5.1.14 Output Buffer Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-172

25.4.3.5.1.14.1 Finger Combining Bypass (FC_MODE = 0) . . . . . . . . . . . . . . . . . . . . . . 25-172

25.4.3.5.1.14.2 Finger Combining Enabled 16 bits Fixed Point Outputs

(FC_MODE = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-174

25.4.3.5.1.14.3 Finger Combining Enabled 32 bits Floating Point Outputs

(FC_MODE = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-174

25.4.3.5.1.14.4 System Output Buffers Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-175

25.4.3.5.1.14.5 Compressed Mode (ODT = 0x3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-176

25.4.3.5.1.15 Output Interrupt and Finished Channels Buffer Maintenance. . . . . . . . . . . 25-176

25.4.3.5.1.15.1 Finished Channel Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-176

25.4.3.5.1.15.2 Finished Channel Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-176

25.4.3.5.1.15.3 Finished Channel Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-177

25.4.3.5.1.15.4 Finished Channel Search Limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-178

25.4.3.5.1.16 CRPE-ULB Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-178

25.4.3.5.2 Chip Rate Uplink Fast Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-180

25.4.3.5.2.1 CRPE-ULF Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-180

25.4.3.5.2.1.1 CRPE-ULF Parameters Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-180

25.4.3.5.2.1.2 CRPE-ULF Configuration Registers Initialization . . . . . . . . . . . . . . . . . . 25-181

25.4.3.5.2.2 CRPE-ULF Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-181

25.4.3.5.2.2.1 CRPE-ULF Interpolation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-181

25.4.3.5.2.2.2 CRPE-ULF Delay Spread Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-182

25.4.3.5.2.2.3 CRPE-ULF Pilot Correlation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-182

25.4.3.5.2.2.4 CRPE-ULF Early/Late Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-182

25.4.3.5.2.3 CRPE-ULF Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-183

25.4.3.5.2.4 CRPE-ULF Data Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-183

25.4.3.5.2.5 Time Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-185

25.4.3.5.2.6 Input Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-185

25.4.3.5.2.6.1 Input Data Structure—Interpolation Enabled . . . . . . . . . . . . . . . . . . . . . . 25-185

25-112 Direct Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-186

25-113 Window Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-186

25.4.3.5.2.6.2 Input Data Structure—interpolation Bypass Mode . . . . . . . . . . . . . . . . . 25-186

25.4.3.5.2.6.3 Input Data interface—Interpolation Bypass Mode . . . . . . . . . . . . . . . . . . 25-187

2 Interpolation Bypass initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 25-189

25.4.3.5.2.7 Interpolation Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-189

25.4.3.5.2.8 Despreading and Descrambling (DD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-190

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25.4.3.5.2.8.1 Antenna Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-190

25.4.3.5.2.8.2 Chip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-190

25.4.3.5.2.8.3 Physical Channel (PCH) and Slot Format (SLF) Selection . . . . . . . . . . . 25-191

25.4.3.5.2.8.4 Scrambling Sequence Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-192

25.4.3.5.2.8.5 OVSF Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-193

25.4.3.5.2.8.6 Pilot Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-193

25.4.3.5.2.8.7 DPCCH/PRACH PILOT Correlation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-196

25.4.3.5.2.8.8 E-DPCCH and HS-DPCCH Data Correlation. . . . . . . . . . . . . . . . . . . . . . 25-197

25.4.3.5.2.8.9 Early/On-time/Late (EOL) Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-197

25.4.3.5.2.8.10 Updating Finger Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-199

25.4.3.5.2.9 Compressed PCHs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-201

25.4.3.5.2.10 CRPE-ULF Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-201

25.4.3.5.2.10.1 Soft Symbol Packet Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-201

25.4.3.5.2.10.2 Soft Symbol Packet Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-202

25.4.3.5.2.10.3 System Memory Output Buffers Structure . . . . . . . . . . . . . . . . . . . . . . . . 25-203

25.4.3.5.2.10.4 Writing the Output Data Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-204

25.4.3.5.2.11 CRPE-ULF Command Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-204

25.4.3.5.2.11.1 Finger Command (FIC) Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-205

25.4.3.5.2.11.2 Physical Channel Command Structure (PCHC) . . . . . . . . . . . . . . . . . . . . 25-206

25.4.3.5.2.11.3 Command Fetching Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-209

25.4.3.5.2.11.4 Command Generation Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-210

25.4.3.5.2.11.5 Command Setting Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-210

25.4.3.5.2.12 CRPE-ULF Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-211

25.4.3.5.2.13 CRPE-ULF Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-212

25.4.3.5.3 Chip Rate Downlink Processing Operation. . . . . . . . . . . . . . . . . . . . . . 25-212

25.4.3.5.3.1 CRPE-DL Initialization Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-212

25.4.3.5.3.2 CRPE Chip-Rate Downlink Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-212

25.4.3.5.3.3 CRPE Downlink Operation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-213

25.4.3.5.3.4 Channels Activation and Maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-213

25.4.3.5.3.5 CRPE-DL Input Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-217

25.4.3.5.3.6 Internal CRPE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-218

25.4.3.5.3.6.1 TPC Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-218

25.4.3.5.3.6.2 Slot Format Look Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-218

25.4.3.5.3.6.3 TPC Value Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-219

25.4.3.5.3.6.4 STTD Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-220

25.4.3.5.3.6.5 Spreading Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-220

25.4.3.5.3.6.6 Scrambling Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-221

25.4.3.5.3.6.7 Gain Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-221

25.4.3.5.3.6.7 Gains Usage synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-222

25.4.3.5.3.6.8 Combine Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-223

25.4.3.5.3.6.9 Beam Forming Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-224

25.4.3.5.3.6.10 Virtual Antennas Idle Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-226

25.4.3.5.3.7 Output Modes Of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-226

25.4.3.5.3.7.1 MAPLE-B2 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-226

25.4.3.5.3.7.2 CPRI Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-227

25.4.3.5.3.7.3 Output Buffer Accesses Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-228

25.4.3.5.3.8 Initialization of CPRI Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-229

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25.4.3.5.3.9 CRPE-DL Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-230

25.4.3.5.3.9.1 Output Chip Override Prevention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-230

25.4.3.5.3.9.2 Controlled Processing Task Per Processing Period . . . . . . . . . . . . . . . . . 25-230

25.4.3.5.4 CRPE Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-230

25.4.3.6 CRC Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-231

25.4.3.6.1 CRCPE Buffer Descriptor Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-231

25.4.3.6.2 CRC Input Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-231

25.4.3.6.3 Byte Reverse CRC Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-233

25.4.3.6.4 CRC Initial Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-233

25.4.3.6.5 CRC Polynomials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-234

25.4.3.6.6 CRC Processing Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-234

25.4.3.6.6.1 Reverse Output Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-234

25.4.3.6.6.2 Inverse Output Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-235

25.4.3.6.6.3 CRC Result Check/Calculate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-235

25.4.3.7 Code Generation Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-236

25.4.3.7.1 CGPE Buffer Descriptor Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-236

25.4.3.7.2 CGPE Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-236

25.4.3.7.2.1 OVSF Codes Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-236

25.4.3.7.2.2 Uplink Scrambling Codes Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-237

25.4.3.7.2.2.1 Long Complex Scrambling Codes Generation . . . . . . . . . . . . . . . . . . . . . 25-237

25.4.3.7.2.2.2 Short Complex Scrambling Codes Generation . . . . . . . . . . . . . . . . . . . . . 25-239

25.4.3.7.2.3 Downlink Scrambling Codes Generation . . . . . . . . . . . . . . . . . . . . . . . . . . 25-241

25.4.3.7.2.4 Code Generation Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-243

25.4.3.7.3 Output Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-243

25.4.3.8 CONVPE Convolution and Correlation Processing Operation . . . . . . . . 25-244

25.4.3.8.1 CONVPE Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-245

25.4.3.8.1.1 CONVPE Buffer Descriptor Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-245

25.4.3.8.1.2 CONVPE Detailed Tasks Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-245

25.4.3.8.1.3 RACH Preamble Correlations Task Description . . . . . . . . . . . . . . . . . . . . . 25-245

25.4.3.8.1.3.1 RACH Preamble Task Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-246

25.4.3.8.1.3.2 RACH Preamble Input Data Structure - Antenna data . . . . . . . . . . . . . . . 25-247

25.4.3.8.1.3.3 RACH Preamble Input Data Structure - Signatures . . . . . . . . . . . . . . . . . 25-248

25.4.3.8.1.3.4 RACH Preamble Output Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 25-248

25.4.3.8.1.4 Path Searcher Correlations Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-249

25.4.3.8.1.4.1 CONVPE Path Search Task limitations . . . . . . . . . . . . . . . . . . . . . . . . . . 25-250

25.4.3.8.2 FDU Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-251

25.4.3.8.2.1 FDU Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-252

25.4.3.8.2.2 FDU Arithmetic Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-253

25.4.3.8.2.3 FDU Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-254

25.4.4 External Masters Support Using Serial RapidIO Doorbell . . . . . . . . . . . . . 25-254

25.4.4.1 Serial RapidIO Doorbell Parameters Configuration. . . . . . . . . . . . . . . . . 25-254

25.4.4.2 Operation Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-256

25.4.5 MAPLE-B2 Internal Task Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-258

25.4.6 MAPLE-B2 Power Gating Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-259

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25.4.6.1 Dynamic Power gating Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-259

25.4.6.2 Per Processing Element Static Clock Gating Scheme . . . . . . . . . . . . . . . 25-259

25.4.7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-261

25.5 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-261

25.5.1 MAPLE-B2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-265

25.5.1.1 General Programming Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-266

25.5.2 Initialization Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-266

25.5.2.1 MAPLE Mode Configuration 0 Parameter (MMC0P). . . . . . . . . . . . . . . 25-266

25.5.2.2 MAPLE Mode Configuration 1 Parameter (MMC1P). . . . . . . . . . . . . . . 25-268

25.5.2.3 MAPLE eTVPE Configuration Parameter (MTVCP) . . . . . . . . . . . . . . . 25-271

25.5.2.4 CRPE-DL Output Mode Configuration Parameter (CDOMCP) . . . . . . . 25-272

25.5.2.5 CRPE-ULB Mode Configuration Parameter (CRUBMCP). . . . . . . . . . . 25-274

25.5.3 Parameter RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-275

25.5.3.1 General Parameter RAM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-275

25.5.3.1.1 MAPLE UCode Version Parameter (MUCVP). . . . . . . . . . . . . . . . . . . 25-277

25.5.3.1.2 MAPLE Timer Period Parameter (MP_TPP) . . . . . . . . . . . . . . . . . . . . 25-278

25.5.3.1.3 MAPLE Clock Gating Control Parameter (MCGCP) . . . . . . . . . . . . . . 25-279

25.5.3.2 eTVPE Parameter RAM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-280

25.5.3.2.1 MAPLE Turbo Viterbi Puncturing Vector x High Configuration

Parameter (MTVPVxHCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-281

25.5.3.2.2 MAPLE Turbo Viterbi Puncturing Vector x Low Configuration

Parameter (MTVPVxLCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-282

25.5.3.2.3 MAPLE Turbo Viterbi Puncturing Period Configuration y

Parameter (MTVPPCyP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-283

25.5.3.2.4 MAPLE Turbo Viterbi Polynomial Vector Set x Configuration 0

Parameter (MTVPVSxC0P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-284

25.5.3.2.5 MAPLE Turbo Viterbi Polynomial Vector Set x Configuration 1

Parameter (MTVPVSxC1P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-285

25.5.3.3 eFTPE Parameter RAM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-286

25.5.3.3.1 eFTPE Data Size Set x Parameter 0 (FTPEDSSxP0) . . . . . . . . . . . . . . 25-287

25.5.3.3.2 eFTPE Data Size Set x Parameter 1 (FTPEDSSxP1) . . . . . . . . . . . . . . 25-288

25.5.3.3.3 eFTPE Data Size Set x Parameter 2(FTPEDSSxP2). . . . . . . . . . . . . . . 25-289

25.5.3.3.4 eFTPE x Update Pre-Multiplication Buffer Pointer

Parameter (FTPExUPRMBPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-290

25.5.3.3.5 eFTPE x Update Post-Multiplication Buffer Pointer

Parameter (FTPExUPSMBPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-291

25.5.3.3.6 eFTPE x Update Buffers Size Parameter (FTPExUBSP) . . . . . . . . . . . 25-292

25.5.3.3.7 eFTPE Complete Update Buffers Routine Parameter (FTPECUBRP). 25-293

25.5.3.4 CRPE Parameter RAM Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-294

25.5.3.4.1 CRPE General Parameter Description. . . . . . . . . . . . . . . . . . . . . . . . . . 25-294

25.5.3.4.1.1 MAPLE CRPE Reset Completion Indication Parameter (MCRRCIP) . . . . 25-294

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25.5.3.4.2 CRPE-ULB Parameters Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-295

25.5.3.4.2.1 MAPLE CRPE-ULB Physical Channel <x> Base Address Parameter

(MCUBPCHxBAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-296

25.5.3.4.2.2 MAPLE CRPE-ULB Physical Channel <x> Size Parameter

(MCUBPCHxSZP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-297

25.5.3.4.2.3 MAPLE CRPE-ULB Physical Channel <x> Write Pointer Parameter

(MCUBPCHxWPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-298

25.5.3.4.2.4 MAPLE CRPE-ULB Physical Channel <x> Output Buffer Interrupt

Configuration Parameter (MCUBPCHxOBICP) . . . . . . . . . . . . . . . . . . . . . 25-299

25.5.3.4.2.5 MAPLE CRPE-ULB Group <x> Configuration 1 Parameter

(MCUBGxC1P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-300

25.5.3.4.2.6 MAPLE CRPE-ULB Group <x> Configuration 2 Parameter

(MCUBGxC2P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-301

25.5.3.4.2.7 MAPLE CRPE-ULB Group <x> Configuration 3 Parameter

(MCUBGxC3P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-302

25.5.3.4.2.8 MAPLE CRPE-ULB Group <x> Configuration 4 Parameter

(MCUBGxC4P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-303

25.5.3.4.2.9 MAPLE CRPE-ULB Antenna <x> Descriptor Parameter

(MCUBANTxDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-304

25.5.3.4.2.10 MAPLE CRPE-ULB Configuration Parameter (MCUBCP) . . . . . . . . . . . . 25-305

25.5.3.4.2.11 MAPLE CRPE-ULB Output Buffer Interrupt Configuration Parameter

(MCUBOBICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-306

25.5.3.4.2.12 MAPLE CRPE-ULB Finished Channels Buffer <x> Parameter

(MCUBFCBxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-307

25.5.3.4.3 CRPE-ULF Parameters Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-308

25.5.3.4.3.1 MAPLE CRPE-ULF Command Input Buffer Address <x> Parameter

(MCUFCIBAxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-309

25.5.3.4.3.2 MAPLE CRPE-ULF Command Input Buffer Write Pointer <x> Parameter

(MCUFCIBWPxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-310

25.5.3.4.3.3 MAPLE CRPE-ULF Command Input Buffer Read Pointer <x> Parameter

(MCUFCIBRPxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-311

25.5.3.4.3.4 MAPLE CRPE-ULF Interpolation Bypass General Configuration Parameter

(MCUFIBGCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-312

25.5.3.4.3.5 MAPLE CRPE-ULF General Configuration Parameter (MCUFGCP) . . . . 25-313

25.5.3.4.3.6 MAPLE CRPE-ULF Interpolation Bypass Group Attributes <x> Parameter

(MCUFIBGAxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-314

25.5.3.4.3.7 MAPLE CRPE-ULF Interpolation Bypass Antenna Address <x> Parameter

(MCUFIBAAxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-315

25.5.3.4.4 CRPE-DL Parameters Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-316

25.5.3.4.4.1 MAPLE CRPE-DL Slot Channel <x> Parameter 0 (MCDLSCxP0) . . . . . 25-317

25.5.3.4.4.2 MAPLE CRPE-DL Slot Channel <x> Parameter 1 (MCDLSCxP1) . . . . . 25-318

25.5.3.4.4.3 MAPLE CRPE-DL Slot Channel <x> Parameter 2 (MCDLSCxP2) . . . . . 25-319

25.5.3.4.4.4 MAPLE CRPE-DL Slot Channel <x> Read Pointer Parameter

(MCDLSCxRPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-320

25.5.3.4.4.5 MAPLE CRPE-D1L Fast Channel <x> Parameter 0 (MCDLFCxP0) . . . . 25-321

25.5.3.4.4.6 MAPLE CRPE-DL Fast Channel <x> Parameter 1 (MCDLFCxP1) . . . . . 25-322

25.5.3.4.4.7 MAPLE CRPE-DL Slot Channel <x> Parameter 2 (MCDLSCxP2) . . . . . 25-324

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25.5.3.4.4.8 MAPLE CRPE-DL Fast Channel <x> Read Pointer Parameter

(MCDLFCxRPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-325

25.5.3.4.4.9 MAPLE CRPE-DL Output Buffer <x> Base Address Parameter

(MCDLOBxBAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-326

25.5.3.4.4.10 MAPLE CRPE-DL Output Buffer <x> Size Parameter (MCDLOBxSP) . . 25-327

25.5.3.4.4.11 MAPLE CRPE-DL Output Buffer <x> Write Pointer Parameter

(MCDLOBxWPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-328

25.5.3.4.4.12 MAPLE CRPE-DL Number Of Channels Limit Parameter

(MCDLNOCLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-329

25.5.3.4.4.13 MAPLE CRPE-DL General Configuration Parameter (MCDLGCP) . . . . . 25-330

25.5.3.5 Serial RapidIO Doorbell Support Attributes Parameters . . . . . . . . . . . . . 25-331

25.5.3.5.1 Serial RapidIO Outbound RapidIO Doorbell Port 1 Base Address Parameter

(SORDP0BAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-331

25.5.3.5.2 Serial RapidIO Outbound RapidIO Doorbell Port 2 Base Address Parameter

(SORDP1BAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-332

25.5.3.5.3 Hardware Semaphore Port 1 Base Address Parameter (HSP0BAP) . . . 25-333

25.5.3.5.4 Hardware Semaphore Port 2 Base Address Parameter (HSP1BAP) . . . 25-334

25.5.3.5.5 MAPLE-B Doorbell Hardware Semaphore ID Configuration Parameter

(MDHSIDCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-335

25.5.3.5.6 MAPLE-B Doorbell General Configuration Parameter (MDGCP) . . . 25-336

25.5.4 Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-336

25.5.4.1 General BD Ring and BD Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-336

25.5.4.1.1 MAPLE BD Rings Configuration Parameter 0 (MBDRCP0). . . . . . . . 25-339

25.5.4.1.2 MAPLE BD Rings Configuration Parameter 1 (MBDRCP1). . . . . . . . 25-342

25.5.4.1.3 MAPLE BD Rings Configuration Parameter 2 (MBDRCP2). . . . . . . . 25-344

25.5.4.1.4 MAPLE <yy>PE BD Ring High Priority A <x> Parameter

(M<yy>BRHPAxP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-345

25.5.4.1.5 MAPLE <yy>PE BD Ring High Priority B <x> Parameter

(M<yy>BRHPBxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-348

25.5.4.1.6 MAPLE <yy>PE BD Ring Low Priority A <x> Parameter

(M<yy>BRLPAxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-351

25.5.4.1.7 MAPLE <yy>PE BD Ring Low Priority B <x> Parameter

(M<yy>BRLPBxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-354

25.5.4.2 eTVPE Buffer-Descriptor Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-357

25.5.4.3 eFTPE Buffer Descriptor Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-368

25.5.4.3.1 Buffer Descriptor Special Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-377

25.5.4.3.2 eFTPE Buffer Descriptor’s Extension. . . . . . . . . . . . . . . . . . . . . . . . . . 25-378

25.5.4.3.3 Transform Length Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-383

25.5.4.4 DEPE BD and Header Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-384

25.5.4.4.1 DEPE Buffer Descriptor Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-384

25.5.4.4.2 Buffer Descriptors Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-392

25.5.4.4.3 DEPE Headers Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-393

25.5.4.4.3.1 DEPE Header Structure for 3GLTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-393

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25.5.4.4.3.2 DEPE Header Structure for WiMAX (802.16e) . . . . . . . . . . . . . . . . . . . . . 25-395

25.5.4.4.3.3 DEPE Header Structure for WiMAX (802.16m) . . . . . . . . . . . . . . . . . . . . . 25-397

25.5.4.4.3.4 DEPE Header Structure for UMTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-399

25.5.4.5 CRPE-ULB Core Descriptor, Finger and PCH Commands Structures . . 25-402

25.5.4.5.1 CRPE-ULB Core Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-403

25.5.4.5.2 CRPE-ULB Finger Command Structure . . . . . . . . . . . . . . . . . . . . . . . . 25-404

25.5.4.5.3 CRPE-ULB PCH Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . 25-406

25.5.4.6 CRCPE Buffer Descriptor Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-409

25.5.4.7 CGPE Buffer Descriptor Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-414

25.5.4.8 CONVPE Buffer Descriptor Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-418

25.5.4.9 CONVPE RACH Preamble Correlations Task Descriptor . . . . . . . . . . . 25-419

25.5.4.10 CONVPE Path Searcher Task Descriptor . . . . . . . . . . . . . . . . . . . . . . . . 25-423

25.5.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-429

25.5.5.1 PSIF2 Registers (SBus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-429

25.5.5.1.1 PSIF Command Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-429

25.5.5.1.2 PSIF PIC Event Register 0 (PSPICER0). . . . . . . . . . . . . . . . . . . . . . . . 25-431

25.5.5.1.3 PSIF PIC Event Register 1 (PSPICER1). . . . . . . . . . . . . . . . . . . . . . . . 25-432

25.5.5.1.4 PSIF PIC Event Register 2 (PSPICER2). . . . . . . . . . . . . . . . . . . . . . . . 25-433

25.5.5.1.5 PSIF PIC Edge/Level Register 0 (PSPICELR0) . . . . . . . . . . . . . . . . . . 25-435

25.5.5.1.6 PSIF PIC Mask Register 0 (PSPICMR0) . . . . . . . . . . . . . . . . . . . . . . . 25-436

25.5.5.1.7 PSIF PIC Mask Register 1 (PSPICMR1) . . . . . . . . . . . . . . . . . . . . . . . 25-437

25.5.5.1.8 PSIF PIC Mask Register 2 (PSPICMR2) . . . . . . . . . . . . . . . . . . . . . . . 25-438

25.5.5.1.9 PSIF PIC Interrupts Assertion Clocks Register (PSPICIACR). . . . . . . 25-440

25.5.5.2 eTVPE Registers Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-441

25.5.5.2.1 eTVPE Configuration 0 Register (TVPEC0R) . . . . . . . . . . . . . . . . . . . 25-441

25.5.5.2.2 eTVPE Aposteriori Quality Configuration Register (TVAQCR) . . . . . 25-442

25.5.5.3 eFTPE_x Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-443

25.5.5.3.1 EFTPE_<x> Data Size Register 0 (FTPE<x>DSR0) . . . . . . . . . . . . . . 25-444

25.5.5.3.2 EFTPE_<x> Data Size Register 1 (FTPE<x>DSR1) . . . . . . . . . . . . . . 25-445

25.5.5.3.3 EFTPE_<x> Data Size Register 2 (FTPE<x>DSR2) . . . . . . . . . . . . . . 25-446

25.5.5.3.4 EFTPE_<x> Configuration Register (FTPE<x>CR) . . . . . . . . . . . . . . 25-447

25.5.5.3.5 EFTPE_<x> ECC Interrupt Status Register (FTPE<x>ECCISR). . . . . 25-448

25.5.5.4 CRPE-ULB Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-450

25.5.5.4.1 CRPE-ULB Interpolation Weights 1 Sample <x> Configuration Register

(CRUBIW1SxCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-450

25.5.5.4.2 CRPE-ULB Interpolation Weights 2 Sample <x> Configuration Register

(CRUBIW2SxCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-451

25.5.5.4.3 CRPE-ULB Group First Antenna <x> Configuration Register

(CRUBGFAxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-452

25.5.5.4.4 CRPE-ULB Group Number Of Antenna <x> Configuration Register

(CRUBGNOAxCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-453

25.5.5.4.5 CRPE-ULB Event Status Register (CRUBESR). . . . . . . . . . . . . . . . . . 25-454

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25.5.5.4.6 CRPE-ULB Output Saturation Counter Status Register

(CRUBOSCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-455

25.5.5.4.7 CRPE-ULB Interpolation Saturation Counter Status Register

(CRUBISCSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-456

25.5.5.5 CRPE-ULF Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-456

25.5.5.5.1 ULF General Configuration Register (ULFGCR). . . . . . . . . . . . . . . . . 25-457

25.5.5.5.2 ULF Secondary Configuration Register (ULFSCR) . . . . . . . . . . . . . . . 25-459

25.5.5.5.3 ULF Interpolation Configuration Register <x> (ULFICRx). . . . . . . . . 25-459

25.5.5.5.4 ULF Output Buffer <x> Base Configuration Register (ULFOBxBCR) 25-461

25.5.5.5.5 ULF Output Buffer <x> Attributes Configuration Register

(ULFOBxACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-462

25.5.5.5.6 ULF Event Status Register (ULFESR) . . . . . . . . . . . . . . . . . . . . . . . . . 25-463

25.5.5.5.7 ULF Command FIFO Status Register (ULFCFSR) . . . . . . . . . . . . . . . 25-464

25.5.5.5.8 ULF Input Buffer Status Register (ULFIBSR) . . . . . . . . . . . . . . . . . . . 25-465

25.5.5.5.9 ULF Time Status Register (ULFTSR). . . . . . . . . . . . . . . . . . . . . . . . . . 25-465

25.5.5.5.10 ULF ECC Status Register (ULFECCSR) . . . . . . . . . . . . . . . . . . . . . . . 25-466

25.5.5.6 CRPE-DL Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-467

25.5.5.6.1 CRPE-DL Chips Output Data Table (CDCODT) . . . . . . . . . . . . . . . . . 25-468

25.5.5.6.2 CRPE-DL Slot Format Look-Up Table (SFLUT). . . . . . . . . . . . . . . . . 25-470

25.5.5.6.3 CRPE-DL Scrambling Initialization Look-Up Table (SCRILUT) . . . . 25-473

25.5.5.6.4 CRPE-DL Normalization Value Configuration Register (CDNVCR) . 25-475

25.5.5.6.5 CRPE-DL Virtual Antenna Gains Control Register 0 (CDVAGLR0) . 25-476

25.5.5.6.6 CRPE-DL Virtual Antenna Gains Control Register 1 (CDVAGLR1) . 25-477

25.5.5.6.7 CRPE-DL Beam Forming Coefficients Values Control Register 0

(CDBFCVLR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-478

25.5.5.6.8 CRPE-DL Beam Forming Coefficients Values Control Register 1

(CDBFCVLR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-480

25.5.5.6.9 CRPE-DL Beam Forming Coefficients Values Control Register 2

(CDBFCVLR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-482

25.5.5.6.10 CRPE-DL Beam Forming Coefficients Values Control Register 3

(CDBFCVLR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-484

25.5.5.6.11 CRPE-DL Beam Forming Coefficients Values Control Register 4

(CDBFCVLR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-486

25.5.5.6.12 CRPE-DL Beam Forming Coefficients Values Control Register 5

(CDBFCVLR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-488

25.5.5.6.13 CRPE-DL Beam Forming Coefficients Values Control Register 6

(CDBFCVLR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-490

25.5.5.6.14 CRPE-DL Beam Forming Coefficients Values Control Register 7

(CDBFCVLR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-492

25.5.5.6.15 CRPE-DL Start Control Register (CDSLR) . . . . . . . . . . . . . . . . . . . . . 25-494

25.5.5.6.16 CRPE-DL TPC Command Control Register (CDTCLR) . . . . . . . . . . . 25-495

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25.5.5.6.17 CRPE-DL Virtual Antennas Gain Command Control Regis

(ter (CDVAGCLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-496

25.5.5.6.18 CRPE-DL General Command Control Register (CDGCLR) . . . . . . . . 25-497

25.5.5.6.19 CRPE-DL Idle Period Control Register <x> (CDIPLRx) . . . . . . . . . . . 25-499

25.5.5.6.20 CRPE-DL Beam Forming Coefficients Timing Command Control

25.5.5.6.21 CRPE-DL Combined Chips Shift Command Control Register <x>

(CDCCSCLRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-501

25.5.5.6.22 CRPE-DL Rate Control Register (CDRLR) . . . . . . . . . . . . . . . . . . . . . 25-502

25.5.5.6.23 CRPE-DL Event Status Register (CDESR). . . . . . . . . . . . . . . . . . . . . . 25-503

25.5.5.6.24 CRPE-DL Processing Stage Status Register (CDPSSR). . . . . . . . . . . . 25-504

25.5.5.6.25 CRPE-DL ECC Status Register (CDECCSR). . . . . . . . . . . . . . . . . . . . 25-505

26 Security Engine (SEC)

26.1 Architecture Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2

26.1.1 Functional Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4

26.1.2 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5

26.1.2.1 Controller Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5

26.1.2.1.1 Channel-Controlled Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6

26.1.2.1.2 Core Processor-Controlled Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6

26.1.2.2 Descriptors and Link Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6

26.1.3 Polychannel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7

26.1.4 Virtual Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8

26.1.4.1 Channel Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8

26.1.4.2 Channel Completion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-9

26.1.4.3 Integrity Check Value (ICV) Generation and Checking . . . . . . . . . . . . . . . 26-9

26.1.4.4 Encryption and Hashing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-9

26.1.4.5 Snooping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-9

26.1.5 Common EU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-10

26.2 SEC Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-10

26.2.1 Bus Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-11

26.2.1.1 System Bus Master Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-12

26.2.1.2 System Bus Master Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-12

26.2.2 Controller Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-13

26.2.2.1 Controller Primary Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-13

26.2.2.2 Controller Secondary Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-14

26.2.3 Controller Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-14

26.3 Polychannel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-15

26.4 Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-16

26.4.1 Channel Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-16

26.4.2 Arbitration Among Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-17

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26.4.2.1 Arbitration for Use of the Polychannel . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-17

26.4.2.2 Arbitration for Use of the Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-18

26.4.2.3 Arbitration for Use of Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-18

26.4.2.4 Arbitration Algorithms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-19

26.4.2.4.1 Round-Robin Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-19

26.4.2.4.2 Priority Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-19

26.4.3 Channel Registers and Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-20

26.4.4 Channel Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-20

26.4.4.1 Channel Done Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-21

26.4.4.2 Channel Error Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-21

26.4.4.3 Channel Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-21

26.5 Descriptors and Link Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-22

26.6 Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-24

26.6.1 Public Key Execution Unit (PKEU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-26

26.6.1.1 PKEU Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-26

26.6.1.2 PKEU Key Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-26

26.6.1.3 PKEU AB Size Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-26

26.6.1.4 PKEU Data Size Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-26

26.6.1.5 PKEU Reset Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-27

26.6.1.6 PKEU Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-27

26.6.1.7 PKEU Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-27

26.6.1.8 PKEU Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-27

26.6.1.9 PKEU End_of_Message Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-28

26.6.1.10 PKEU Parameter Memories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-28

26.6.1.11 PKEU Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-28

26.6.1.11.1 CLEARMEMORY: Clear Memory (0x01). . . . . . . . . . . . . . . . . . . . . . . 26-30

26.6.1.11.2 MOD_EXP: Prime field (Fp) Exponential mod N and Deconvert From

Montgomery Format (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-30

26.6.1.11.3 MOD_EXP_TEQ: Exponentiate mod N and Deconvert From

Montgomery Format with Timing Equalization (0x1d) . . . . . . . . . . . . . 26-31

26.6.1.11.4 MOD_R2MODN: Prime Field (Fp) Compute Montgomery

Converter Constant (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-31

26.6.1.11.5 MOD_RRMODP: Prime Field (Fp) Compute Montgomery

Converter Constant for Chinese Remainder Theorem (0x04). . . . . . . . . 26-31

26.6.1.11.6 EC_FP_AFF_PTMULT: Prime Field Elliptic Curve Scalar

Point Multiply in Affine Coordinates (0x05) . . . . . . . . . . . . . . . . . . . . . 26-32

26.6.1.11.7 EC_F2M_AFF_PTMULT: Polynomial Field Elliptic Curve

Scalar Point Multiply in Affine Coordinates (0x06) . . . . . . . . . . . . . . . . 26-32

26.6.1.11.8 EC_FP_PROJ_PTMULT: Prime Field Elliptic Curve Scalar

Point Multiply in Projective Coordinates (0x07). . . . . . . . . . . . . . . . . . . 26-33

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26.6.1.11.9 EC_F2M_PROJ_PTMULT: Polynomial Field Elliptic Curve Scalar

Point Multiply in Projective Coordinates (0x08). . . . . . . . . . . . . . . . . . . 26-34

26.6.1.11.10 EC_FP_ADD: Prime Field Elliptic Curve Point Add in Projective

Coordinates (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-35

26.6.1.11.11 EC_FP_DOUBLE: Prime Field Elliptic Curve Point Double in

Projective Coordinates (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-35

26.6.1.11.12 EC_F2M_ADD: Polynomial Field Elliptic Curve Point Add in

Projective Coordinates (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-36

26.6.1.11.13 EC_F2M_DOUBLE: Polynomial Field Elliptic Curve Point

Double in Projective Coordinates (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . 26-36

26.6.1.11.14 F2M_R2: Polynomial Field (F2m) Compute Montgomery

Converter Constant (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-37

26.6.1.11.15 F2M_INV: Polynomial Field (F2m) Modular Inversion (0x0E). . . . . . . 26-37

26.6.1.11.16 MOD_INV: Prime Field (Fp) Modular Inversion (0x0F) . . . . . . . . . . . . 26-37

26.6.1.11.17 MOD_ADD: Prime Field (Fp) Modular Addition (0x10). . . . . . . . . . . . 26-38

26.6.1.11.18 MOD_RED: Prime Field (Fp) Modulo Reduction (0x12) . . . . . . . . . . . 26-38

26.6.1.11.19 MOD_SUB: Prime Field (Fp) Modular Subtraction (0x20) . . . . . . . . . . 26-38

26.6.1.11.20 MOD_MULT1_MONT: Prime Field (Fp) Montgomery

Modular Multiplication (0x30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-39

26.6.1.11.21 MOD_MULT2_DECONV: Prime Field (Fp) Montgomery Modular

Multiplication and Deconvert From Montgomery Format (0x40) . . . . . 26-39

26.6.1.11.22 F2M_ADD: Polynomial Field (F2m) Modular Addition (0x50) . . . . . . 26-39

26.6.1.11.23 F2M_MULT1_MONT: Polynomial Field (F2m) Montgomery

Modular Multiplication (0x60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-40

26.6.1.11.24 F2M_MULT2_DECONV: Polynomial Field (F2m) Montgomery Modular

Multiplication and Deconvert From Montgomery Format (0x70) . . . . . 26-40

26.6.1.11.25 RSA_SSTEP: RSA Single Step Modular Exponentiation (0x80). . . . . . 26-40

26.6.1.11.26 RSA_SSTEP_TEQ: RSA Single Step Modular Exponentiation with

Timing Equalization (0x1e). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-41

26.6.1.11.27 SPK_BUILD: Build PK Data Structure (0xFF) . . . . . . . . . . . . . . . . . . . 26-41

26.6.2 Data Encryption Standard Execution Unit (DEU) . . . . . . . . . . . . . . . . . . . . 26-42

26.6.2.1 DEU Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-42

26.6.2.2 DEU Key Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-42

26.6.2.3 DEU Data Size Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-42

26.6.2.4 DEU Reset Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-42

26.6.2.5 DEU Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-43

26.6.2.6 DEU Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-43

26.6.2.7 DEU Interrupt Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-43

26.6.2.8 DEU End_of_Message Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-43

26.6.2.9 DEU IV Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-44

26.6.2.10 DEU Key Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-44

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26.6.2.11 DEU FIFOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-44

26.6.3 Advanced Encryption Standard Execution Unit (AESU) . . . . . . . . . . . . . . . 26-45

26.6.3.1 AESU Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-45

26.6.3.2 AESU Key Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-45

26.6.3.3 AESU Data Size Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-46

26.6.3.4 AESU Reset Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-46

26.6.3.5 AESU Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-46

26.6.3.6 AESU Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-46

26.6.3.7 AESU Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-47

26.6.3.8 AESU End_of_Message Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-47

26.6.3.9 AESU Context Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-47

26.6.3.9.1 Context for CBC, CBC-RBP, OFB, and CFB128 Cipher Modes . . . . . . 26-49

26.6.3.9.2 Context for Counter (CTR) Cipher Mode . . . . . . . . . . . . . . . . . . . . . . . . 26-50

26.6.3.9.3 Context for SRT Cipher Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-50

26.6.3.9.4 Context and Operation for XTS Cipher Mode . . . . . . . . . . . . . . . . . . . . 26-50

26.6.3.9.5 Context and Operation for XCBC-MAC Cipher Mode. . . . . . . . . . . . . . 26-52

26.6.3.9.6 Context and Operation for GCM-GHAS Cipher Mode. . . . . . . . . . . . . . 26-53

26.6.3.9.7 Context and Operation for CMAC (OMAC1) Cipher Mode. . . . . . . . . . 26-54

26.6.3.9.8 Context for CCM Cipher Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-56

26.6.3.9.9 Context and Operation for GCM Cipher Mode. . . . . . . . . . . . . . . . . . . . 26-58

26.6.3.10 AESU Key Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-66

26.6.3.11 AESU FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-66

26.6.4 Message Digest Execution Unit (MDEU). . . . . . . . . . . . . . . . . . . . . . . . . . . 26-67

26.6.4.1 ICV Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-67

26.6.4.2 MDEU Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-68

26.6.4.3 MDEU Key Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-69

26.6.4.4 MDEU Data Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-69

26.6.4.5 MDEU Reset Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-70

26.6.4.6 MDEU Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-70

26.6.4.7 MDEU Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-70

26.6.4.8 MDEU Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-71

26.6.4.9 MDEU ICV Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-71

26.6.4.10 MDEU End_of_Message Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-71

26.6.4.11 MDEU Context Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-71

26.6.4.12 MDEU Key Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-72

26.6.4.13 MDEU FIFOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-72

26.6.5 ARC Four Execution Unit (AFEU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-73

26.6.5.1 AFEU Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-73

26.6.5.1.1 Core Processor-Provided Context via Prevent Permute . . . . . . . . . . . . . 26-73

26.6.5.1.2 Dump Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-73

26.6.5.2 AFEU Key Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-74

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26.6.5.3 AFEU Context/Data Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-74

26.6.5.4 AFEU Reset Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-75

26.6.5.5 AFEU Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-75

26.6.5.6 AFEU Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-75

26.6.5.7 AFEU Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-75

26.6.5.8 AFEU End_of_Message Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-75

26.6.5.9 AFEU Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-76

26.6.5.9.1 AFEU Context Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-76

26.6.5.9.2 AFEU Context Memory Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . 26-76

26.6.5.10 AFEU Key Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-77

26.6.5.11 AFEU FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-77

26.6.6 Kasumi Execution Unit (KEU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-77

26.6.6.1 KEU Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-78

26.6.6.2 KEU Key Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-78

26.6.6.3 KEU Data Size Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-78

26.6.6.4 KEU Reset Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-79

26.6.6.5 KEU Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-79

26.6.6.6 KEU Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-79

26.6.6.7 KEU Interrupt Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-80

26.6.6.8 KEU Data Out Register (F9 MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-80

26.6.6.9 KEU End_of_Message Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-80

26.6.6.10 KEU IV_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-80

26.6.6.11 KEU ICV_In Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-81

26.6.6.12 KEU IV_2 Register (Fresh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-81

26.6.6.13 KEU Context Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-81

26.6.6.14 KEU Key Data Registers_[1–2] (Confidentiality Key) . . . . . . . . . . . . . . . 26-81

26.6.6.15 KEU Key Data Registers _[3–4] (Integrity Key). . . . . . . . . . . . . . . . . . . . 26-82

26.6.6.16 KEU FIFOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-82

26.6.7 Cyclic Redundancy Check Unit (CRCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-83

26.6.7.1 ICV Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-83

26.6.7.2 CRCU Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-84

26.6.7.3 CRCU Key Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-84

26.6.7.4 CRCU Data Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-84

26.6.7.5 CRCU Reset Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-84

26.6.7.6 CRCU Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-84

26.6.7.7 CRCU Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-84

26.6.7.8 CRCU Interrupt/Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-85

26.6.7.9 CRCU Interrupt/Error Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-85

26.6.7.10 CRCU ICV Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-85

26.6.7.11 CRCU End of Message Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-85

26.6.7.12 CRCU Context Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-85

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26.6.7.13 CRCU Key Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-86

26.6.7.14 CRCU FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-87

26.6.8 SNOW3G Execution Unit (STEU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-87

26.6.8.1 ICV Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-87

26.6.8.2 STEU Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-88

26.6.8.3 STEU Key Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-88

26.6.8.4 STEU Data Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-88

26.6.8.5 STEU Reset Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-88

26.6.8.6 STEU Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-88

26.6.8.7 STEU Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-89

26.6.8.8 STEU Interrupt Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-89

26.6.8.9 STEU Data Out Register (F9 MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-89

26.6.8.10 STEU End of Message Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-89

26.6.8.11 STEU IV_1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-89

26.6.8.12 STEU ICV_In Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-91

26.6.8.13 STEU IV_2 Register (FRESH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-91

26.6.8.14 STEU Context Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-92

26.6.8.15 STEU LFSR State Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-92

26.6.8.16 STEU FSM State Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-92

26.6.8.17 STEU Key Data Registers (Confidentiality Key) . . . . . . . . . . . . . . . . . . . 26-92

26.6.8.18 STEU FIFOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-92

26.6.9 Random Number Generator (RNGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-93

26.6.9.1 RNGU Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-94

26.6.9.2 RNGU Data Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-94

26.6.9.3 RNGU Reset Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-94

26.6.9.4 RNGU Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-94

26.6.9.5 RNGU Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-94

26.6.9.6 RNGU Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-95

26.6.9.7 RNGU End_of_Message Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-95

26.6.9.8 RNGU Entropy Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-95

26.6.9.9 RNGU FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-95

26.7 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-96

26.7.1 Descriptors and Link Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-100

26.7.1.1 Descriptor Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-100

26.7.1.2 Descriptor Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-102

26.7.1.2.1 Descriptor Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-104

26.7.1.2.2 Descriptor Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-106

26.7.1.2.3 Descriptor Operations During Cryptographic Processing . . . . . . . . . . . 26-108

26.7.1.2.4 Descriptor Types 0000_0: aesu_ctr_nonsnoop . . . . . . . . . . . . . . . . . . . 26-111

26.7.1.2.5 Descriptor Type 0001_0: common_nonsnoop. . . . . . . . . . . . . . . . . . . . 26-112

26.7.1.2.6 Descriptor Type 0010_0: hmac_snoop_no_afeu. . . . . . . . . . . . . . . . . . 26-117

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26.7.1.2.7 Descriptor Type 0101_0: common_nonsnoop_afeu. . . . . . . . . . . . . . . 26-123

26.7.1.2.8 Descriptor Type 1000_0: pkeu_mm . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-124

26.7.1.2.9 Descriptor Type 1100_0: hmac_snoop_aesu_ctr . . . . . . . . . . . . . . . . . 26-126

26.7.1.2.10 Descriptor Type 0000_1: IPsec_ESP. . . . . . . . . . . . . . . . . . . . . . . . . . . 26-128

26.7.1.2.11 IPsec-ESP Outbound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-128

26.7.1.2.12 IPsec-ESP Inbound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-130

26.7.1.2.13 Descriptor Type 0001_1: IEEE 802.11i_aes_ccmp. . . . . . . . . . . . . . . . 26-132

26.7.1.2.14 IEEE 802.11i Outbound. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-133

26.7.1.2.15 IEEE 802.11i Inbound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-136

26.7.1.2.16 Descriptor Type 0010_1: SRTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-138

26.7.1.2.17 SRTP Outbound. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-139

26.7.1.2.18 SRTP Inbound without ICV Compare. . . . . . . . . . . . . . . . . . . . . . . . . . 26-141

26.7.1.2.19 SRTP Inbound with ICV Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-143

26.7.1.2.20 Descriptor Types 0011_1: pkeu_build, 0100_1: pkeu_ptmul, and

0101_1: pkeu_ptadd_dbl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-144

26.7.1.2.21 Descriptor Type 1000_1: tls_ssl_block . . . . . . . . . . . . . . . . . . . . . . . . . 26-148

26.7.1.2.22 TLS / SSL Block Cipher Outbound. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-149

26.7.1.2.23 TLS / SSL Block Cipher Inbound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-151

26.7.1.2.24 Descriptor Type 1001_1: tls_ssl_stream . . . . . . . . . . . . . . . . . . . . . . . . 26-154

26.7.1.2.25 TLS / SSL Stream Cipher Outbound. . . . . . . . . . . . . . . . . . . . . . . . . . . 26-155

26.7.1.2.26 TLS / SSL Stream Cipher Inbound . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-157

26.7.1.2.27 Descriptor Type 1010_1: raid_xor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-159

26.7.1.2.28 Descriptor Type 1011_1: aes_gcm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-161

26.7.1.2.29 AES_GCM Outbound for MACSec . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-165

26.7.1.2.30 AES_GCM Inbound for MACSec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-167

26.7.1.2.31 AES_GCM Outbound for IPsec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-169

26.7.1.2.32 AES_GCM Inbound for IPsec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-171

26.7.1.2.33 Descriptor Type 1100_1: dbl_crc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-172

26.7.1.2.34 iSCSI dbl_crc Outbound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-172

26.7.1.2.35 iSCSI dbl_crc Inbound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-174

26.7.2 Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-175

26.7.3 Link Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-177

26.7.4 SEC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-179

26.7.4.1 Master Control Register (MCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-179

26.7.4.2 Controller Identification Register (CIDR) . . . . . . . . . . . . . . . . . . . . . . . . 26-182

26.7.4.3 Controller IP Block Revision Register (CIPBRR) . . . . . . . . . . . . . . . . . . 26-182

26.7.4.4 EU Assignment Status (EUASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-183

26.7.4.5 Controller Interrupt Enable Register (CIER) . . . . . . . . . . . . . . . . . . . . . . 26-185

26.7.4.6 Controller Interrupt Status Register (CISR). . . . . . . . . . . . . . . . . . . . . . . 26-189

26.7.4.7 Controller Interrupt Clear Register (CICR) . . . . . . . . . . . . . . . . . . . . . . . 26-192

26.7.5 Polychannel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-194

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26.7.5.1 Fetch FIFO Enqueue Counter (FFEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-195

26.7.5.2 Descriptor Finished Counter (DFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-196

26.7.5.3 Data Bytes In Counter (DBIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-197

26.7.5.4 Data Bytes Out Counter (DBOC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-198

26.7.6 Channel Registers and Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-198

26.7.6.1 Channel Configuration Registers for Channels 1–4 (CCR[1–4]). . . . . . . 26-199

26.7.6.2 Channel Status Registers (CSR[1–4]) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-202

26.7.6.3 Current Descriptor Pointer Register (CDPR). . . . . . . . . . . . . . . . . . . . . . 26-207

26.7.6.4 Channel Fetch FIFO (CFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-209

26.7.6.5 Channel Descriptor Buffer (DB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-210

26.7.7 PKEU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-211

26.7.7.1 PKEU Mode Register (PKEUMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-211

26.7.7.2 PKEU Key Size Register (PKEUKSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 26-213

26.7.7.3 PKEU AB Size Register (PKEUABSR) . . . . . . . . . . . . . . . . . . . . . . . . . 26-214

26.7.7.4 PKEU Data Size Register (PKEUDSR). . . . . . . . . . . . . . . . . . . . . . . . . . 26-215

26.7.7.5 PKEU Reset Control Register (PKEURCR) . . . . . . . . . . . . . . . . . . . . . . 26-216

26.7.7.6 PKEU Status Register (PKEUSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-217

26.7.7.7 PKEU Interrupt Status Register (PKEUISR) . . . . . . . . . . . . . . . . . . . . . . 26-218

26.7.7.8 PKEU Interrupt Mask Register (PKEUIMR). . . . . . . . . . . . . . . . . . . . . . 26-220

26.7.7.9 PKEU End_of_Message Register (PKEUEOMR). . . . . . . . . . . . . . . . . . 26-221

26.7.7.10 PKEU Parameter Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-221

26.7.7.10.1 PKEU Parameter Memory A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-221

26.7.7.10.2 PKEU Parameter Memory B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-222

26.7.7.10.3 PKEU Parameter Memory E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-222

26.7.7.10.4 PKEU Parameter Memory N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-222

26.7.8 DEU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-223

26.7.8.1 DEU Mode Register (DEUMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-223

26.7.8.2 DEU Key Size Register (DEUKSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-224

26.7.8.3 DEU Data Size Register (DEUDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-225

26.7.8.4 DEU Reset Control Register (DEURCR). . . . . . . . . . . . . . . . . . . . . . . . . 26-226

26.7.8.5 DEU Status Register (DEUSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-227

26.7.8.6 DEU Interrupt Status Register (DEUISR) . . . . . . . . . . . . . . . . . . . . . . . . 26-228

26.7.8.7 DEU Interrupt Mask Register (DEUIMR) . . . . . . . . . . . . . . . . . . . . . . . . 26-230

26.7.8.8 DEU End_of_Message Register (DEUEOMR) . . . . . . . . . . . . . . . . . . . . 26-232

26.7.8.9 DEU IV Register (DEUIVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-232

26.7.8.10 DEU Key Registers (DEUKR[1–3]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-233

26.7.8.11 DEU FIFOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-233

26.7.9 AESU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-234

26.7.9.1 AESU Mode Register (AESUMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-234

26.7.9.2 AESU Key Size Register (AESUKSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 26-237

26.7.9.3 AESU Data Size Register (AESUDSR). . . . . . . . . . . . . . . . . . . . . . . . . . 26-238

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26.7.9.4 AESU Reset Control Register (AESURCR) . . . . . . . . . . . . . . . . . . . . . . 26-239

26.7.9.5 AESU Status Register (AESUSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-240

26.7.9.6 AESU Interrupt Status Register (AESUISR) . . . . . . . . . . . . . . . . . . . . . . 26-241

26.7.9.7 AESU Interrupt Mask Register (AESUIMR). . . . . . . . . . . . . . . . . . . . . . 26-243

26.7.9.8 AESU ICV Size Register (AESUICVSR) . . . . . . . . . . . . . . . . . . . . . . . . 26-245

26.7.9.9 AESU End_of_Message Register (AESUEOMR). . . . . . . . . . . . . . . . . . 26-246

26.7.9.10 AESU Context Registers (AESUCR[1–12]) . . . . . . . . . . . . . . . . . . . . . . 26-247

26.7.9.11 AESU Key Registers (AESUK[U/L]R[1–3]). . . . . . . . . . . . . . . . . . . . . . 26-250

26.7.9.12 AESU FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-251

26.7.10 MDEU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-252

26.7.10.1 MDEU Mode Register (MDEUMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-252

26.7.10.2 MDEU Key Size Register (MDEUKSR) . . . . . . . . . . . . . . . . . . . . . . . . . 26-254

26.7.10.3 MDEU Data Size Register (MDEUDSR) . . . . . . . . . . . . . . . . . . . . . . . . 26-255

26.7.10.4 MDEU Reset Control Register (MDEURCR) . . . . . . . . . . . . . . . . . . . . . 26-256

26.7.10.5 MDEU Status Register (MDEUSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-257

26.7.10.6 MDEU Interrupt Status Register (MDEUISR). . . . . . . . . . . . . . . . . . . . . 26-258

26.7.10.7 MDEU Interrupt Mask Register (MDEUIMR) . . . . . . . . . . . . . . . . . . . . 26-260

26.7.10.8 MDEU ICV Size Register (MDEUICVSR). . . . . . . . . . . . . . . . . . . . . . . 26-262

26.7.10.9 MDEU End_of_Message Register (MDEUEOMR) . . . . . . . . . . . . . . . . 26-263

26.7.10.10 MDEU Context Registers (MDEUCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 26-264

26.7.10.11 MDEU Key Registers (MDEUKR[1–8]) . . . . . . . . . . . . . . . . . . . . . . . . . 26-266

26.7.10.12 MDEU Input FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-266

26.7.11 AFEU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-267

26.7.11.1 AFEU Mode Register (AFEUMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-267

26.7.11.2 AFEU Key Size Register (AFEUKSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 26-268

26.7.11.3 AFEU Context/Data Size Register (AFEUCDSR). . . . . . . . . . . . . . . . . . 26-269

26.7.11.4 AFEU Reset Control Register (AFEURCR) . . . . . . . . . . . . . . . . . . . . . . 26-270

26.7.11.5 AFEU Status Register (AFEUSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-271

26.7.11.6 AFEU Interrupt Status Register (AFEUISR) . . . . . . . . . . . . . . . . . . . . . . 26-272

26.7.11.7 AFEU Interrupt Mask Register (AFEUIMR). . . . . . . . . . . . . . . . . . . . . . 26-274

26.7.11.8 AFEU End_of_Message Register (AFEUEOMR). . . . . . . . . . . . . . . . . . 26-276

26.7.11.9 AFEU Context Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-276

26.7.11.10 AFEU Context Memory Pointer Register (AFEUCMPR) . . . . . . . . . . . . 26-277

26.7.11.11 AFEU Key Registers (AFEUKR[1–2]) . . . . . . . . . . . . . . . . . . . . . . . . . . 26-277

26.7.11.12 AFEU FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-277

26.7.12 KEU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-278

26.7.12.1 KEU Mode Register (KEUMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-278

26.7.12.2 KEU Key Size Register (KEUKSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-280

26.7.12.3 KEU Data Size Register (KEUDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-281

26.7.12.4 KEU Reset Control Register (KEURCR). . . . . . . . . . . . . . . . . . . . . . . . . 26-282

26.7.12.5 KEU Status Register (KEUSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-283

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26.7.12.6 KEU Interrupt Status Register (KEUISR) . . . . . . . . . . . . . . . . . . . . . . . . 26-284

26.7.12.7 KEU Interrupt Mask Register (KEUIMR) . . . . . . . . . . . . . . . . . . . . . . . . 26-286

26.7.12.8 KEU Data Out Register (KEUDOR) for F9 MAC. . . . . . . . . . . . . . . . . . 26-288

26.7.12.9 KEU End_of_Message Register (KEUEOMR) . . . . . . . . . . . . . . . . . . . . 26-289

26.7.12.10 KEU IV1 Register (KEUIV1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-290

26.7.12.11 KEU ICV_In Register (KEUICVIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-291

26.7.12.12 KEU IV2 Register (KEUIV2R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-292

26.7.12.13 KEU Context 1–6 Registers (KEUCR[1–6]) . . . . . . . . . . . . . . . . . . . . . . 26-293

26.7.12.14 KEU Key Data Registers 1–2 (KEUKDR[1–2]) . . . . . . . . . . . . . . . . . . . 26-294

26.7.12.15 KEU Key Data Registers 3–4 (KEUKDR[3–4]) . . . . . . . . . . . . . . . . . . . 26-295

26.7.12.16 KEU Input FIFO/Output FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-295

26.7.13 CRCU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-296

26.7.13.1 CRCU Mode Register (CRCUMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-296

26.7.13.2 CRCU Key Size Register (CRCUKSR). . . . . . . . . . . . . . . . . . . . . . . . . . 26-298

26.7.13.3 CRCU Data Size Register (CRCUDSR) . . . . . . . . . . . . . . . . . . . . . . . . . 26-299

26.7.13.4 CRCU Reset Control Register (CRCURCR) . . . . . . . . . . . . . . . . . . . . . . 26-300

26.7.13.5 CRCU Control Register (CRCUCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-301

26.7.13.6 CRCU Status Register (CRCUSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-302

26.7.13.7 CRCU Interrupt/Error Status Register (CRCUISR). . . . . . . . . . . . . . . . . 26-303

26.7.13.8 CRCU Interrupt/Error Mask Register (CRCUIMR) . . . . . . . . . . . . . . . . 26-305

26.7.13.9 CRCU ICV Size Register (CRCUICVSR). . . . . . . . . . . . . . . . . . . . . . . . 26-307

26.7.13.10 CRCU End_of_Message Register (CRCUEOMR) . . . . . . . . . . . . . . . . . 26-308

26.7.13.11 CRCU Context Register (CRCUCXR) . . . . . . . . . . . . . . . . . . . . . . . . . . 26-309

26.7.13.12 CRCU Key Register (CRCUKR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-310

26.7.13.13 CRCU Input FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-310

26.7.14 STEU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-311

26.7.14.1 STEU Mode Register (STEUMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-311

26.7.14.2 STEU Key Size Register (STEUKSR). . . . . . . . . . . . . . . . . . . . . . . . . . . 26-312

26.7.14.3 STEU Data Size Register (STEUDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 26-313

26.7.14.4 STEU Reset Control Register (STEURCR). . . . . . . . . . . . . . . . . . . . . . . 26-314

26.7.14.5 STEU Status Register (STEUSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-315

26.7.14.6 STEU Interrupt Status Register (STEUISR) . . . . . . . . . . . . . . . . . . . . . . 26-316

26.7.14.7 STEU Interrupt Mask Register (STEUIMR) . . . . . . . . . . . . . . . . . . . . . . 26-318

26.7.14.8 STEU Data Out Register (STEUDOR) for F9 MAC . . . . . . . . . . . . . . . . 26-320

26.7.14.9 STEU End_of_Message Register (STEUEOMR) . . . . . . . . . . . . . . . . . . 26-321

26.7.14.10 STEU IV1 Register (STEUIV1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-322

26.7.14.11 STEU ICV_In Register (STEUICVIR) . . . . . . . . . . . . . . . . . . . . . . . . . . 26-323

26.7.14.12 STEU IV2 Register (STEUIV2R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-324

26.7.14.13 STEU Context Register 1 (STEUCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 26-325

26.7.14.14 STEU Context Register 2 (STEUCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 26-326

26.7.14.15 STEU Context Register 3 (STEUCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . 26-327

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Contents

26.7.14.16 STEU Context Register 4 (STEUCR4) . . . . . . . . . . . . . . . . . . . . . . . . . . 26-328

26.7.14.17 STEU LFSR State Registers 0–7 (STEULFSRSR[0–7]). . . . . . . . . . . . . 26-329

26.7.14.18 STEU FSM State Registers 1 (STEUFSMSR1). . . . . . . . . . . . . . . . . . . . 26-330

26.7.14.19 STEU FSM State Register 2 (STEUFSMSR2) . . . . . . . . . . . . . . . . . . . . 26-331

26.7.14.20 STEU Key Data Registers 1–2 (STEUKDR[1–2]) . . . . . . . . . . . . . . . . . 26-332

26.7.14.21 STEU Input FIFO/Output FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-332

26.7.15 RNGU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-333

26.7.15.1 RNGU Mode Register (RNGMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-333

26.7.15.2 RNGU Data Size Register (RNGDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 26-334

26.7.15.3 RNGU Reset Control Register (RNGRCR) . . . . . . . . . . . . . . . . . . . . . . . 26-335

26.7.15.4 RNGU Status Register (RNGSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-336

26.7.15.5 RNGU Interrupt Status Register (RNGISR) . . . . . . . . . . . . . . . . . . . . . . 26-337

26.7.15.6 RNGU Interrupt Mask Register (RNGIMR) . . . . . . . . . . . . . . . . . . . . . . 26-338

26.7.15.7 RNGU End_of_Message Register (RNGEOMR) . . . . . . . . . . . . . . . . . . 26-340

26.7.15.8 RNGU Entropy Registers 0–7 (RNGER[0–7]) . . . . . . . . . . . . . . . . . . . . 26-340

26.7.15.9 RNGU Output FIFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-341

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About This Book

E S 1 D c m p w l t d t p I a l (

The MSC8158E device is the fourth generation of Freescale high-end multicore DSP devices. It

builds upon the proven success of the previous multicore DSPs and is designed to support the 3G-LTE (FDD and TDD), HSPA+, LTE-Advanced, and WiMAX markets. Its tool suite provides a full-featured

development environment for C/C++ and assembly languages as well as ease of integration with third-party software, such as off-the-shelf libraries and a real-time operating system. The MSC8158E device includes six DSP core subsystems, a large internal memory subsystem and DDR memory controller for external memory, and a variety of communication processors and interfaces.

One SRIO

UART I2C Timers

3072 KB M3

Memory

Six DSP Core Subsystems

ach DSP core s ubsystem includes an C3850 DSP core, a 32 KB 8-way level

ICache, a 32 KB 8-way level 1

Cache, 512 KB level 2 cache

onfigurable as M2 memory, a memory

anagement unit, an embedded

rogrammable interrupt controller (EPIC)

ith up to 256 interrupts and 32 priority evels, two general-purpose 32-bit imers, an on-chip emulator (OCE), a

ebug and profiling unit (DPU), a JTAG

est access port (TAP), and two low-

ower operating modes (Wai t and Stop).

nterface from the cores to the m emories

nd external interfaces is thr oug h a ch ip-

evel arbitration and switching system

CLASS).

Freescale Semicond uc tor lxvii

StarCore

SC3850

Core Subsystem

512 KB

L2 Cache/

M2 Memory

Per Core Subsystem

Memory Subsystem

The memory subsystem includes 3072 KB of shared M3 memory, one DDRSDRAM controller to access up to 2 GB of DDR3/3L external memory, and a 32channel direct memory access (DMA) controller optimized for DDR-SDRAM.

The second-generatio n multi-accelerato r platform engine (MAPLE-B2) provides Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE, IRC and ML equalization schemes, m atrix operations, CRC insertion and check, DFT/iDFT and FFT/iFFT calculations, and Chip Rate acceleration.

MSC8158E Reference Manual, Rev. 2

SEC

MAPLE

32 KB

ICache

MAPLE-B2

QUICC Engine Module

32 KB

DCache

HSSI

Six CPRI

Two SGMII

Ethernet Ethernet

DDR

Memory

Controller

SerDes Interfaces

SPI

DDR Interface

Communications

Processors and Interfaces

Includes one serial RapidIO interface, six CPRI lanes, a UART interface, an I interface, eight timer input/outputs, and QUICC Engine module with two 1000Base-T Ethernet controllers and a SPI. In addition, the global interrupt controller (GIC) consolidates all chipmaskable and non-maskable interrupts and routes them to NMI_OUT, INT_OUT, and to the cores. The hardware semaphores allow initiators to protect and reserve the system hardware resources.

Security Engine (SEC)

The optional SEC has an internal bus controller, 4 data channels, 6 execution units, and a shared random number generator for communications security applications encryption/ decryption

Page 68

Before Using This Manual—Important Note

This manual describes the structure and function of the MSC8158E device. The information in this manual is subject to change without notice, as described in the disclaimers on the title page of this manual. As with any technical documentation, it is your responsibility as the reader to ensure that you are using the most recent version of the documentation. For more information, contact your sales representative.

Before using this manual, determine whether it is the latest revision and whether there are errata or addenda. To locate any published errata or updates associated with this manual or this product, refer to the Freescale web site. The address for the web site is listed on the back cover of this manual.

Audience and Helpful Hints

This manual is intended for software and hardware developers and applications programmers who want to develop products with the MSC8158E. It is assumed that you have a working knowledge of DSP technology and that you may be familiar with Freescale products based on StarCore technology.

For your convenience, the chapters of this manual are organized to make the information flow as predictably as possible. When feasible, the information in each chapter follows this general sequence:

 General description, block diagram, features, and architecture  Functional description with operating modes and example applications and programming  Programming Model (registers)

In chapters that include a Programming Model section, this section is the last one in the chapter, or module subsection for those chapters that include multiple modules, and describes all registers for the module discussed. The Programming Model section begins with a bulleted overview of the registers that includes the page number where the description of each register begins.

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Notational Conventions and Definitions

This manual uses the following notational conventions:

mnemonics Instruction mnemonics appear in lowercase bold.

COMMAND

names

Command names are set in small caps, as follows: GRACEFUL STOP TRANSMIT

ENTER HUNT MODE.

italics Book titles in text are set in italics, as are cross-referenced section titles. Also,

italics are used for emphasis and to highlight the main items in bulleted lists. 0x Prefix to denote a hexadecimal number. 0b Prefix to denote a binary number. REG[FIELD] Abbreviations or acronyms for registers or buffer descriptors appear in

uppercase text. Specific bits, fields, or numeric ranges appear in brackets. For

example, ICR[INIT] refers to the Force Initialization bit in the host Interface

Control Register.

ACTIVE HIGH SIGNALS

ACTIVE LOW SIGNALS

Names of active high signals appear in sans serif capital letters, as follows:

TT[04], TSIZ[0–3], and DP[0–7].

Signal names of active low signals appear in sans serif capital letters with an

overbar, as follows:

DBG, AACK, and EXT_BG[2].

x A lowercase italicized x in a register or signal name indicates that there are

multiple registers or signals with this name. For example, BRCGx refers to

BRCG[1–8], and MxMR refers to the MAMR/MBMR/MCMR registers.

On the MSC8158E device, the SC3850 cores are 16-bit DSP processors. The following table shows the SC3850 assembly language data types. For details, see the StarCore SC3850 DSP Core Reference Manual.

Name SC3850

Byte/Octet 8 bits

Half Word 8 bits

Word 16 bits

Long/Long Word/2 Words 32 bits

Quad Word/4 Words 64 bits

The following table lists the SC3850 C language data types recognized by the StarCore C compiler. For details, see the StarCore SC100 C Compiler User’s Manual (MNSC100CC/D).

Name Size

char/unsigned char 8 bits short/unsigned short 16 bits int/unsigned int 16 bits

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Name Size

fractional short 16 bits long/unsigned long 32 bits fractional long 32 bits pointer 32 bits

Conventions for Registers

The Programming Model section of each chapter includes a register bit table for each register in that module, as well as a table describing each bit in the register. The register bit table not only shows the names and positions of the bits/bit fields but also their reset value, value after boot, and their type (Read/Write). For registers that are not changed by the system boot, no boot line is listed. The register address is shown with the register name and mnemonic. Reserved bits/fields are indicated with a long dash (—). In the RSR shown below, all of the bits are read/write (R/W). Other registers may include read-only (R) and write-only (W) bits. Notice that the least significant bit (LSB) is 0, or big-endian order.

RSR Reset Status Register Offset 0x10

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RCWSRC — SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7

Type R/W

Reset RCW_SRC[0–2] 1 0 0 0 0 0 0 0 0 0 0 0 0

Bit1514131211109876543210

— BSF — SWHR RM JPO JH — RIO2 RIO1 RS —

Type R/W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Organization

Following is a summary and a brief description of the chapters of this manual:

 Chapter 1, Overview. Features, descriptive overview of main modules, configurations,

and application examples.

 Chapter 2, SC3850 Core Overview. Target markets, features, overview of development

tools, descriptive overview of main modules.

 Chapter 3, External Signals. Identifies the external signals, lists signal groupings,

including the number of signal connections in each group, and describes each signal within a functional group.

 Chapter 4, Chip-Level Arbitration and Switching System (CLASS). Describes the

system switch fabric that allows multi-initiator access to the internal memory and devices and enables high-bandwidth internal data transfers with few bottlenecks.

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 Chapter 5, Reset. Covers reset sources, causes, and configurations; gives examples of

different reset configuration scenarios, including systems with multiple MSC8158E devices.

 Chapter 6, Boot Program. Describes the bootloader program that loads and executes

source code to initialize the MSC8158E after it completes a reset sequence and programs its registers for the required mode of operation. This chapter covers selection of bootloader modes, normal sequence of events for bootloading a source program, and booting in a multi-processor environment.

 Chapter 7, Clocks. Contains an overview of the MSC8158E clock modules.  Chapter 8, General Configuration Registers. Contains a detailed description of the

general configuration registers.

 Chapter 9, Memory Map. Defines the address spaces for all MSC8158E modules;

includes cross references to all registers discussed.

 Chapter 10, SC3850 DSP Subsystem. Describes the structure of the DSP core

subsystem, which includes the SC3850 core, the instruction cache (ICache), the data cache (DCache), L2/M2 memory, memory management unit (MMU), two 32-bit timers, the embedded programmable interrupt controller (EPIC), and the on-chip emulator (OCE).

 Chapter 11, Internal Memory Subsystem. Describes the structure and operation of the

L1 ICache, L1 DCache, L2/M2 memory, and M3 memory.

 Chapter 12, DDR SDRAM Memory Controller. Describes the how the memory

controller interface works and how to program it. This interface increases the efficiency of accesses through the DDR memory controller to external DDR memory.

 Chapter 13, Interrupt Handling. Discusses the interrupt controllers that provide

maximum flexibility in handling MSC8158E interrupts, enabling interrupts to be handled by the SC3850 cores internally, by an external host, or by a combination of the two; also discusses source priority schemes.

 Chapter 14, Direct Memory Access (DMA) Controller. Describes the different DMA

operating modes, transfer types, and buffer types. The chapter also gives procedures for programming different types of transfers. The multi-channel DMA controller includes hardware support for up to 16 time-multiplexed channels including buffer alignment. The DMA controller supports flyby transactions on either bus. and enables hot swaps between channels, by using time-multiplexed channels that impose no cost in clock cycles.

 Chapter 15, High Speed Serial Interface (HSSI) Subsystem. Describes subsystem that

supports and multiplexes the Serial RapidIO, CPRI, and SGMII signals across the SerDes PHY port and how the dedicated DMA controllers support the serial RapidIO interfaces and how to program them.

 Chapter 16, Serial RapidIO Controller and Enhanced Message Complex. Describes the

how the serial RapidIO interfaces and eMSG complex work and how to program them.

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 Chapter 17, Common Public Radio Interface (CPRI) Complex. Describes how the

CPRI complex works and how to program it.

 Chapter 18, QUICC Engine Subsystem. Describes the QUICC Engine module, the

Ethernet controllers, and the serial peripheral interface (SPI). Detailed information is referenced in the QUICC Engine Block Reference Manual with Protocol Interworking (QEIWRM).

 Chapter 19, UART. Describes the UART interface, which is a full-duplex serial port

used to communicate with other devices.

 Chapter 21, Timers. Discusses the 32 identical 16-bit general-purpose timers residing in

four timer modules, 16 identical 32-bit general purpose timers residing in two timer modules, and the 8 system watchdog timers and their sets of configuration registers.

 Chapter 20, GPIO. Discusses the thirty-two GPIO signals. Sixteen of the signals can be

configured as external interrupt inputs. Each pin is multiplexed with other signals and can be configured as a general-purpose input, general-purpose output, or a dedicated peripheral pin.

 Chapter 22, Hardware Semaphores. Describes the function and programming of the

hardware semaphores, which control resource sharing.

 Chapter 23, I2C. Describes the I

C interface. which allows the MSC8158E to boot from

a serial EEPROM device.

 Chapter 24, Debugging, Profiling, and Performance Monitoring. Includes aspects of

the JTAG implementation that are specific to the SC3850 core and should be used with the supporting IEEE Std. 1149.6 documentation. The discussion covers the items that the standard requires to be defined and provides additional information specific to the MSC8158E implementation. Also includes debugging resources available in the SC3850 DSP core subsystem, including the OCE modules, and L2 ICache module.

 Chapter 25, Multi Accelerator Platform Engine, Baseband 2 (MAPLE-B2). Describes

the architecture, function, and register and memory structures used by the secondgeneration multi-accelerator platform engine (MAPLE-B2) for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, OFDMA and SCFDMA equalization and CRC algorithms. The MAPLE-B2 includes a quad-RISC programmable control processor, a second generation Programmable-System-Interface (PSIF2) that is a programmable controller with DMA capabilities, and nine accelerators.

 Chapter 26, Security Engine (SEC). Describes the architecture, function, and register

and memory structures used for security algorithm processing.

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Document Change History

Revision Date Change Description

0 Oct 2011 Initial public release 1 Dec 2011 • Chapter 5, Reset.

– Removed the row for mode 22 in Table 5-11.

• Chapter 10, SC3850 DSP Subsystem

– Added new Section 10.12.

• Chapter 12, DDR SDRAM Memory Controller

– Added RC10 modification procedure after Figure 12-11Figure 12-11.

• Chapter 15, High Speed Serial Interface (HSSI) Subsystem

– Added note to Section 15.4. – Added note after Table 15-57.

• Chapter 16, Serial RapidIO Controller and Enhanced Message Complex

– Added note after the second bullet in Section 16.1.4. – Added Section 16.1.7 and subsections. – Added Section 16.1.8. – Added note to Section 16.3.1 about PDU segmentation. – Updated Section 16.3.4. – Updated Section 16.3.8.2. – Added note to Section 16.3.8.3. – Added note after Table 16-116. – Updated PWO and OPE rows in Table 16-72. – Updated SIZE row in Table 16-134, Table 16-136, and Table 16-153. – Added Section 16.5.

• Chapter 17, Common Public Radio Interface (CPRI) Complex

– Updated scrambling feature in Section 17.1. – Updated Section 17.3.1.1. – Updated Section 17.3.1.3. – Updated Section 17.3.1.5.3. – Updated Section 17.3.3.6. – Updated Section 17.3.3.10 – Updated Section 17.3.6.2. – Updated Section 17.4.1.13. – Updated Section 17.4.1.14. – Updated RETHB S row in Table 17-65 – Updated Section 17.4.2.25. – Updated ABO RT row in Table 17-127 – Updated Section 17.4.3.35. – Updated Section 17.4.4.7. – Updated Section 17.4.4.11.

• Chapter 18, QUICC Engine Subsystem

– Added Section 18.6.1 and subsections. – Added Section 18.7.5 and subsections.

• Chapter 20, Timers

– Removed all references to special CPRI support. – Updated Section 20.1.5 to add detailed procedure. – Added note to Section 20.1.5.1.

• Chapter 26, Security Engine (SEC)

– Updated Section 26.6.8 and Section 26.7.4.4.

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Revision Date Change Description

2 Jan 2012 • Chapter 5, Reset

– Updated rows for bit 17 and bit 16 in Table 5-5, Table 5-7, and Table 5-9.

• Chapter 8, General Configuration Registers

– Updated SerDes PLL designat ors in the descriptions for bits 19 and 18 in Table 8-7.

• Chapter 15, High Speed Serial Interface (HSSI) Subsystem

– Add EATT R settings in Table 15-29. – Updated the description of the LA[2–1] row in Table 15-37. – Split old Section 15.10.52 into two: Secti o n 15.10.52 and Section 15.10.53 to describe

SRDB1RSTCTL and SRDB2RSTCTL individually.

– Updated FRAT E_S EL settings description in Table 15-62.

• Chapter 21, Timers

– Added an updated version of Section 21.1.8, Special CPRI Support which had been removed

in Rev. 1.

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1 Overview

The MSC8158E device is the fourth generation of Freescale high-end multicore DSP devices that target the communications infrastructure and delivers the industry’s highest level of performance and integration. It builds upon the proven success of the previous multicore DSPs and is designed to support the rapidly changing and expanding broadband wireless markets, with special support for UMTS and TD-SCDMA application processing. minimal cost, power, and area per channel. The highly flexible, fully-programmable and powerful MSC8158E broadband wireless access DSP offers tremendous processing power while maintaining a competitive price and high performance.

The highly integrated MSC8158E DSP device includes the following:

 Six StarCore SC3850 DSP subsystems each running at up to 1 GHz with an architecture

optimized for wireless applications.

 One high-speed industry-standard DDR3 memory interface.  Multi-Accelerator Platform Engine for Baseband 2 (MAPLE-B2) supports hardware

acceleration for Turbo or Viterbi decoding, Turbo encoding and rate matching, CRC insertion and check, DFT/iDFT and FFT/iFFT calculations, and Chip Rate acceleration.

The MSC8158E is carefully optimized for

 High-Speed Serial Interface (HSSI) subsystem (8-lane) that supports

— Two serial RapidIO interfaces (one 1x/2x/4x and the other 1x/2x) — Two Gigabit serial Ethernet interfaces — Six CPRI channels

 QUICC Engine dual RISC-based subsystem to guarantee reliable data transport over

packet networks while significantly off loading such processing from the DSP cores that supports:

— Two gigabit Ethernet controllers with RGMII and SGMII support — One SPI

 16 bidirectional channels DMA controller  UART interface

 I

C interface

 Security Engine Core (SEC) to support multiple security algorithms and networking

protocols, including IPSec and accelerates data plane encryption/decryption and code protection with minimal DSP cores intervention.

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Overview

1.1 Features

The MSC8158E includes the following features:

 StarCore DSP subsystem. The DSP subsystem includes:

— StarCore SC3850 core

• Running at up to 1 GHz

• Up to 8000 16-bit MMACS. A MAC operation includes a multiply-accumulate command with the associated data moves and a pointer update.

• Backwards binary compatible with the SC140 and SC3400 architectures.

• Data Arithmetic and Logic Unit (DALU) containing 4 ALUs, each capable of performing 2 16 × 16 multiply accumulate operations, effectively doubling the performance of convolution-based kernels relative to the SC3400 core

• New instructions double the performance of complex and extended precision multiplication.

• Address Generating Unit (AGU) containing 2 Address Arithmetic Units (AAU)

• Up to six instructions executed in a single clock cycle: 4 DALU and 2 AGU instructions

• Variable-length Execution Set (VLES) execution model.

• 16 data registers, 40 bits each; 27 address registers, 32 bits each.

• Hardware support for fractional and integer data types.

• Four hardware loops with near-zero cycle overhead

• Very rich 16-bit wide orthogonal instruction set.

• Application specific instructions for Viterbi and Multimedia.

• Special SIMD (Single instruction, multiple data) instructions working on 2-word or 4-byte operands packed in a register, enabling to perform 2 to 4 operations per instruction (8 to 16 operations per VLES)

• New dedicated instructions accelerate FFTs enabling a 40% cycle count reduction and improved SNR

• User and Supervisor privilege levels, supporting a protected SW model

• New instructions and features to improve control code performance

• Precise exceptions for memory accesses enabling good RTOS support and Soft Error corrections

• Branch Target Buffer (BTB) for acceleration of change of flow operations

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— L1 ICache:

• 32 Kbytes

• 8 ways with 16 lines of 256 bytes per line

• Multi-task support

• Real-time support through locking flexible boundaries

• Line pre-fetch capability

• Software coherency support

• Software pre-fetch support by core instructions

— L1 DCache:

• 32 Kbytes

• 8 ways with 16 lines of 256 bytes per line

• Capable of serving two data accesses in parallel (XA, XB)

• Multi-task support

• Real-time support through locking flexible boundaries

• Software coherency support

Features

• Writing policy programmable per memory segment as either write-back or write-through

• 0.25 Kbytes Write-back Buffer (WBB)

• Six 64-bit entry WTB

• Line pre-fetch capability

• Software pre-fetch, synchronize, and flush support by core instructions

— Unified L2 Cache/M2 Memory:

• 512 Kbyte

• 8 ways with 1024 indexes and a 64 byte line

• Physically addressed

• Dynamically configured as a DMA accessible M2 Memory

• Maximum user flexibility for real time support through address partitioning of the cache

• Support various write policies and methods to reduce cache inclusiveness

• Multi-channel, two dimensional software pre-fetch support

• Software coherency support with seamless transition from L1 cache coherency operation.

— Memory management unit (MMU):

• Highly flexible memory mapping capability

• Provides virtual to physical address translation

• Provides task protection

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Overview

• Supports multi-tasking

• Supports precise interrupts. Enabling to have an open RTOS.

— Debug and Profiling Unit (DPU) block:

• Supports the debugging and profiling of the platform in cooperation with the OCE Block

• Supports various breakpoint and event counting options

• Supports real-time tracing to the main memory with the Trace Write Buffer (TWB)

— Extended programmable interrupt controller (EPIC)

• 256 interrupts

• 32 priority levels with NMI support

— Two general-purpose 32-bit timers — Low-power design with the following modes of operation:

• Wait processing state for peripheral operation

• Stop processing state

— ECC/EDC support.

 Multi Accelerator Platform Engine for Baseband 2 (MAPLE-B2)

— One PGC unit for eTVPE. The PGC permits removal of power for the eTVPE

internally, either statically or dynamically, which can also reduce power consumption when this processing is not needed.

— Separate power for the Chip Rate Processing Element (CRPE). This can be disabled

for power reduction if the CRPE is not required.

— Two operating modes: 3G mode (3GLTE and UMTS standards) and WiMAX mode

(IEEE 802.16e and 802.16m standards).

— Second Generation Programmable System Interface (PSIF2)

• Software friendly buffer descriptor based handshake and task assignment.

• Support for high priority and low priority tasks via multiple descriptor rings.

• Processing elements management and scheduling.

• Four 128-bit master buses for data transfers from/to the system memory.

• Two 128-bit slave buses for the following purposes: — General purpose connection to CLASS, allowing any host or peripheral to

access the MAPLE-B2 internal memories for placing job-descriptors in the PSIF2 internal memories or read/write data from/into PEs internal memories. This port is a read/write port and is referred to as MBus Slave0 port.

— .Direct connection to CPRI for direct data transfer between the Antenna

interface and MAPLE-B2. This port is a write only port and is referred to as MBus Slave1 port.

• Interrupt or RapidIO Door Bell generation and/or status bit indication on job or multiple jobs completion.

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Features

• System memory utilized only for input/output data, all the internal calculations are performed using MAPLE-B memories.

— Turbo decoding for WiMAX, UMTS and 3GLTE systems using an eTVPE module:

• Turbo decoder, rate-dematcher and HARQ combining acceleration

• Each decoder scalable with 1, 2, or 4 Radix 4 dual-recursion engines

• Binary and duo-binary codes

• Trellis termination and tail biting

• Various rate de-matching functions support for rate 1/3 code including sub-block de-interleaving and de-interlacing

• Max Log Map or Linear Log Map (MAX*)

• Non Linear Dynamics extrinsic factorization

• Programmable number of iterations

• Multiple stop conditions: CRC check, hard output compare and a-posteriori quality indication

• SIMD type of operation utilizing high level of hardware parallelism to provide high throughput and low latency channel decoding capabilities

— Turbo encoding for WiMAX OFDMA, 3GLTE DL/UL-SCH and UMTS systems

using DEPE module:

• Information bits encoding and rate matching up to 1.8 Gbps for 3GLTE and WiMAX

• Code block CRC attachment and filler bits insertion for 3GLTE

• Bit randomization for WiMAX

• Transport block CRC attachment in 3GLTE in case of single code block.

• Information bits encoding and rate matching up to 900 Mbps for UMTS

• HS-DSCH and E-DCH (TDD and FDD) Turbo encoding and rate matching.

• CRC attachment for Transport Block <

• Optional bit scrambling for Transport Block <

5090. 5090 (FDD only).

• Transport Block generation assist in system memory using bit write granularity

• Transport Block segmentation assist using bit read granularity.

— Viterbi decoding for various technologies using eTVPE

module:

• Supports K =5,7,9

• Fully programmable polynomials

• Various rates/puncturing cases

— DFT/iDFT and FFT/iFFT processing using three eFTPE modules:

1.Viterbi and Turbo d ecoding share memories and share throughp ut; 100% throughp ut of Viterbi and 100% throughput of Turbo cannot be achieved simultaneously.

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Overview

• Variable length FFT/iFFT processing of 128, 256, 512, 1024, 1536 and 2048 points.

• Variable length DFT/iDFT processing of the form, up to 1200 points: 12, 24, 36, 48, 60, 72, 96, 108, 120, 144, 180, 192, 216, 240, 288, 300, 324, 360, 384, 432, 480, 540, 576, 600, 648, 720, 768, 864, 900, 960, 972, 1080, 1152 and 1200 points

• Variable input data size, supporting 16 bit {8I,8Q} or 32 bit {16I,16Q}

• Programmable guard band insertion and removal for iFFT and FFT processing.

• Programmable Cyclic Prefix insertion and removal.

• Pre-Multiplication (“array multiplication”) support by programmable complex values vector.

• Post-Multiplication support of all samples by programmable complex values vector.

• Phase rotation of input samples.

• Input data complex conjugate and re-ordering (1 to N samples reversed to N to 1)

• Zero padding of input data

• UMTS scrambled pilot samples generation in frequency domain

• Programmable scaling method, supporting one of the following methods:

• Automatic adaptive scaling using overflow detection between transform stages, and optional programmable overall scaling factor for the output data

• User defined scaling between transform stages

• Automatic or programmable input scale up for input data with small values, to increase calculation precision

— CRC check and insertion using CRCPE:

• CRC check & report for UL processing

• CRC insertion for DL processing

• Up to 10 Gbps, supporting the following polynomials: — CRC24 with polynomial D

— CRC24 with polynomial D

+ D4 + D3 + D + 1

D — CRC16 with polynomial D — CRC16 with polynomial D — CRC32 with polynomial D

+ D5 + D4 + D2 + D + 1

+ D — CRC18 with polynomial D

+ D2 + 1

— CRC12 with polynomial D

+ D23 + D6 + D5 + D + 1

+ D23 + D18 + D17 + D14 + D11 + D10 + D7 + D6 +

+ D12 + D5 + 1

+ D15 + D2 + 1

+ D26 + D23 + D22 + D16 + D12 + D11 + D10 + D8

+ D17 + D14 + D13 + D11 + D10 + D8 + D7 + D6 +

+ D11 + D10 + D8 + D5 + D4 + 1

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— CRC6 with polynomial D6 + D5 + D3 + D2 + D + 1

— Downlink Chip Rate Processing:

• Capacity of up to 512 Physical Channels including MIMO, STTD, TSTD and Closed Loop Mode 1 operation per channel.

• Input data precision of 16 bit {8I,8Q} complex symbols.

• Spreading with SF 4,8,16,32,64,128, and 256 using internally generated channelization codes.

• Scrambling using internally generated, up to 32 independent codes, including support for compressed mode codes.

• Supporting SF 1 special channels with spreading, scrambling bypass

• Programmable complex gains per Physical Channel, with differentiation between data and control information, supporting various slot formats.

• Physical channels combining and flexible assignment to up to 16 virtual antenna’s.

• Optional Beam Forming operation on combined Physical Channels.

• Output data precision of 32 bit {16I,16Q} complex chips.

Features

— Uplink Batch Processing - for data and control channels with variable spreading

factors

• Capacity of up to 384 Physical Channels with up to 2144 total fingers from up to 24 antenna streams with max 512 chips delay spread.

• Optional pre-de-spreading support with up to 80 Physical Channels with SF 4

• Input data precision of 16 bit {8I,8Q} complex chips.

• Optional Internal interpolation of x2 oversampled input stream, up to x16 resolution using programmable 8 tap polyphase filter.

• Despreading with SF 2,4,8,16,32,64,128,256 using internally generated channelization codes.

• Descrambling by short or long codes, with up to 384 different, internally generated, scrambling codes.

• Optional fingers combining using programmable weights.

• Optional frequency correction functionality using programmable correction factor.

• Multiple output formats: — 16 bit fixed point or custom 22 bit (16-bit mantissa and 6-bit exponent) floating

point formats for fingers combining option.

— complex 32 bit {16I,16Q} for fingers combining bypass option.

— Uplink Fast Processing for (E)DPCCH processing

• Capacity of up to 400 Physical channels with up to 3200 total fingers from up to 24 antenna streams.

• Input data precision of 16 bit {8I,8Q} complex chips.

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Overview

• Optional Internal interpolation of x2 oversampled input stream, up to x16 resolution using programmable 8 tap polyphase filter.

• Descrambling by short or long codes with internally generated scrambling codes.

• Despreading using SF 256 for DPCCH and E-DPCCH channels.

• Optional correlation with pilot sequence.

• Programmable slot format and early/on-time/late processing for various fields of control channels.

• Output 16 bit I and 16 bit Q.

• Internal commands FIFO for flexible updates of fingers and channels association.

• Latency of 68 chips including processing and write back of results to system memory

— PN code generator

• Short or Long codes generation based on programmable init values

• Generates scrambling code or scrambling code multiplied by Hadamard code with programmable spreading factor and OVSF.

• Two output formats:

• 16 bit {8I,8Q} format, with throughput of up to 4 Gsamples/s

• 2 bit {1I, 1Q} format, with throughput of up to 32 Gsamples/s

— Easily initialized and configured with minimal intervention:

• Software-friendly buffer descriptor handshake mechanism and task assignment

• Externally accessible memories and registers for debug purposes

• Internal, high throughput, DMA capabilities to fetch the input data and output the results to system memory

• Internal memory used for all module processing

— Multi-core support: Multiple configurable descriptor rings with support for high and

low priority tasks — System notification can generate RapidIO doorbells or interrupts on task completion — Programmable customization including processing management and scheduling:

Second Generation of Programmable System Interface (PSIF2) — When it is not required, the MAPLE-B power can be disabled internally to reduce

overall device power consumption.

 The Security Engine (SEC) includes 8 different execution units (EUs). For EUs for which

data flows in and out, each EU has buffer FIFOs of at least 256 bytes. EU types and features include the following:

— Advanced Encryption Standard Unit (AESU)

• Implements the Rijndael symmetric key cipher per U.S. National Institute of Standards and Technology FIPS 197.

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• Modes providing data confidentiality: ECB, CBC, CCM, Counter, GCM, XTS, CBC-RBP, OFB-128, and CFB-128.

• Modes providing data authentication: CCM, GCM, CMAC (OMAC1), and XCBC-MAC.

• 128, 192, 256 bit key lengths (only 128 bit keys in XCBC-MAC)

• ICV checking in CCM, GCM, CMAC (OMAC1), and XCBC-MAC mode

• XOR operations on 2–6 sources for RAID applications

— ARC Four Execution Unit (AFEU)

• Implements a stream cipher compatible with the RC4 algorithm

• 8-bit to 128-bit programmable key

— Cyclic Redundancy Check Unit (CRCU)

• Implements CRC32C as required for iSCSI header and payload checksums, CRC32 as required for IEEE Standard 802 packets, as well as for programmable 32 bit CRC polynomials

• ICV checking

Features

— Data Encryption Standard Execution Unit (DEU)

• DES, 3DES

• Two key (K1, K2, K1) or Three Key (K1, K2, K3)

• ECB, CBC, CFB-64 and OFB-64 modes for both DES and 3DES

— Kasumi Execution Unit (KEU)

• Implements cipher and authentication modes F8 and F9 used in 3G, A5/3 for GSM and EDGE, and GEA3 for GPRS

• 128-bit confidentiality key and 128-bit integrity key

• ICV checking for F9

— SNOW3G Execution Unit (STEU)

• Implements cipher and authentication modes UEA2 (F8) and UIA2 (F9)

• 128-bit confidentiality key and 128-bit integrity key

• ICV checking for F9

— Message Digest Execution Unit (MDEU)

• Implements SHA with 160-bit, 224-bit, 256-bit, 384-bit, and 512-bit message digest (as specified by the FIPS 180-2 standard)

• Implements MD5 with 128-bit message digest (as specified by RFC 1321)

• Implements HMAC computation with either message digest algorithm (as specified in RFC 2104 and FIPS-198)

• Implements SSL MAC computation

• ICV checking

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Overview

— Public Key Execution Unit (PKEU)

• RSA and Diffie-Hellman with programmable field size up to 4096 bits

• Elliptic curve cryptography —F

m and Fp modes

— Programmable field size up to 1023 bits

• Run time equalization to protect against timing and power attacks

— Random Number Generator (RNGU). Combines a True Random Number Generator

(TRNG) and a NIST-approved Pseudo-Random Number Generator (PRNG) (as described in Annex C of FIPS140-2 and ANSI X9.62).

 Chip-level arbitration and switching system (CLASS)

— A full fabric that arbitrates between the DSP cores and other CLASS masters to the

core M2 memory, shared M3 memory, DDR SDRAM controller, MAPLE-B2, and the

device configuration control and status registers (CCSRs). — High bandwidth. — Non-blocking allows parallel accesses from multiple initiators to multiple targets. — Fully pipelined. — Low latency. — Per target arbitration highly optimized to the target characteristics using prioritized

round-robin arbitration. — Reduces data flow bottlenecks and enables high-bandwidth internal data transfers.

 Internal memory. The 4608 Kbyte internal memory space includes:

— 32 Kbyte L1 ICache per core. — 32 Kbyte L1 DCache per core. — 512 Kbyte unified L2 Cache/M2 Memory per core. — 3072 Kbyte shared triple-bank, triple-port M3 memory. Power supply of two banks

(2048 Kbyte) can be turned off to reduce power dissipation. — 96 Kbyte boot ROM accessible from the cores.

 Clocks

— Four input clocks:

• Global input clock.

• Two differential input clocks (one per each SerDes PLL).

• Optional DDR clock

— Six PLLs:

• Three system PLLs

• Two SerDes PLLs

• DDR Controller PLL

— Clock ratios selected during reset via reset configuration pins. — Clock modes user-configurable after reset.

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 One DDR Controller supporting:

— Up to 667 MHz clock rate (1333 MHz data rate). — Supports DDR3 devices — Programmable timing — Support for a 64-bit data interface (72 bits including ECC), up to 1333 MHz data rate — Support for a 32-bit data interface (40 bits including ECC), up to 1333 MHz data rate — Full ECC support for single-bit error correction and multi-bit error detection up to the

maximum specified data rates — Two banks of memory via two chip selects. Each chip select supports up to 2 Gbytes,

but memory total cannot exceed 2 Gbytes. — DRAM chip configurations from 64 Mbits to 4 Gbits with x8/x16 data ports — Support burst lengths of 4 (burst chop) and On the Fly — Sleep mode support for self-refresh SDRAM — On-die termination support — Supports auto refreshing — Support for SODIMMs

 DMA Controller

Features

— 32 unidirectional channels, providing up to 16 memory-to-memory channels. — Buffer descriptor programing model. — Up to 1024 buffer descriptors per channel direction provide a total of 32 Kbyte buffer

descriptors. Buffer descriptors can reside in M2 or DDR memories. — Priority-based time-multiplexing between channels, using four internal priority groups

with round-robin arbitration between channels on equal priority group. — Earliest deadline first (EDF) priority scheme that assures task completion on time. — Flexible channel configuration with all channels supporting all features. — A flexible buffer configuration, including:

• Simple buffers

• Cyclic buffers

• Single address buffers (I/O device).

• Incremental address buffers

• Chained buffers

• 1D to 4D buffers, optimized for video applications

• 1D or 2–4D complex buffers, a combination of buffer types

— Two external DMA request (DREQ) and two DONE

signal lines that allow an external

device to trigger DMA transfers. — High bandwidth — Optimized for DDR SDRAM

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Overview

 High-Speed Serial Interface (HSSI)

— Eight multiplexed SerDes lanes — Serial RapidIO Subsystem

• Two Serial RapidIO ports one supporting x1/x2/x4 operation and the other supporting x1/x2 operation up to 5 Gbaud with a RapidIO enhanced messaging unit (eMSG) and two RapidIO DMA units.

• Each x1/x2/x4 Serial RapidIO endpoint operates at 1.25/2.5/3.125/5 Gbaud and complies with the following parts of Specification 2.1 of the RapidIO trade association interconnect specification:

— Part I (input and output logical specifications) — Part II (message passing logical specification) — Part III (common transport specification) — Part VI (physical layer 1x LP-serial specification) — Part VIII (error management extension specification)

• Each Serial RapidIO port supports read, write, messages, doorbells, data streaming and maintenance accesses:

— Small and large transport information field only — All priorities flow — Pass-through between the two ports that allows cascading devices using the

Serial RapidIO and enabling message/data path between the two Serial RapidIO ports without core intervention. A message/data that is not designated for the specific device passes through it to the next device.

• RapidIO Enhanced Messaging Unit supports: — RapidIO Interconnect Specification 1.3, Part 2: Message Passing Logical

Specification.

— RapidIO Interconnect Specification 1.3, Part 10: Data Streaming Logical

Specification.

— RapidIO Interconnect Specification 2.1, Part 10: Stream Management Flow

Control. Basic stream management flow control (XON/XOFF) using extended

header message format. — 64 outbound queues allowing multi-core environment. — 16 concurrent inbound reassembly operations. One additional reserved

reassembly for inbound unit 0 to carry session management protocol. — Multi unicast.

• Each RapidIO DMA unit supports:

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— Four high-speed/high-bandwidth channels accessible by local and remote

masters — Basic DMA operation modes (direct, simple chaining) — Extended DMA operation modes (advanced chaining and stride capability) — Programmable bandwidth control between channels — Up to 256 bytes for DMA sub-block transfers to maximize performance over

the RapidIO interface — Three priority levels supported for source and destination transactions

— Common Public Radio Interface (CPRI) Controller

• Supports v4.1 of the CPRI standard

• Up to 6 lanes

• Supports 1.2288 Gbaud, 2.4576 Gbaud, 3.072 Gbaud, 4.9152 Gbaud and 6.144 Gbaud

• Supports scrambling

Features

• Daisy-chain capability that allows cascading devices according to pre-determined user configuration. Chaining can be done for each lane using the CPRI controller. Chaining lanes does not require core intervention or internal device bandwidth overhead.

• Input power can be disabled for system power reduction if CPRI is not required.

 The QUICC Engine subsystem includes dual RISC processors and 48-Kbyte multi-master

RAM to handle the Ethernet and SPI interfaces, thus off loading the tasks from the cores. The three communication controllers support:

— Two Ethernet Controllers

• Two Ethernet physical interfaces: — 1000 Mbps SGMII protocol using a 4-pin SerDes interface multiplexed through

the HSSI SerDes port.

— 1000 Mbps RGMII protocol

• MAC-to-MAC connection in all modes

• Full-duplex operations

• Full-duplex flow control feature (IEEE Std. 802.3x)

• Receive flow control frames

• Detection of all erroneous frames as defined by IEEE Std. 802.3-2002

• Multi-buffer data structure

• Diagnostic modes: Internal and external loopback mode and echo mode

• Serial management interface MDC/MDIO

• Transmitter network management and diagnostics

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• Receiver network management and diagnostics

• VLAN Support

• IEEE Std. 802.1p/Q QoS

• Eight Tx/Rx queues

• Queuing decision for IP/MAC/UDP filtering based on MAC destination addresses, IP destination address, and UDP destination port

• Programmable maximum frame length

• Enhanced MIB statistics

• Optional shift of data buffer by two bytes for L3 header alignments

• Extended features — IP header checksum verification and calculation

— Parsing of frame headers and adding a frame control block at the frame head,

containing L3 and L4 information for CPU acceleration

— Serial peripheral interface (SPI)

• Four-signal interface (SPI_MOSI, SPI_MISO, SPI_CK and SPI_SL)

• Full-duplex operation

• Works with 32-bit data characters, or with a range from 4-bit to 16-bit data characters•Supports back-to-back character transmission and reception

• Supports master or slave SPI mode

• Supports multiple-master environment

• Continuous transfer mode for automatic scanning of a peripheral

• Maximum clock rate is (QUICC Engine clock)/8 in master mode and (QUICC Engine clock)/4 in slave mode (not in back-to-back operation)

• Independent programmable baud rate generator

• Programmable clock phase and polarity

• Local loopback capability for testing

• Open-drain outputs support multimaster configuration

• Communication with Ethernet PHY for configuration and status (MIIMCOM-MII management communication protocol)

• Multi-MIIMCOM environment with up to 32 PHYs

• Programmable clock gap between two characters in master mode

• Controlled by the DSP cores and the QUICC Engine RISC processors according to user configuration.

 I/O Interrupt Concentrator consolidates all chip maskable interrupt and non-maskable

interrupt sources and routes them to

INT_OUT, NMI_OUT, and the cores.

 UART

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— Bit rate up to 6.25 Mbps — Two signals for transmit data and receive data — Full-duplex operation — Standard mark/space non-return-to-zero (NRZ) format — 13-bit baud rate selection — Programmable 8-bit or 9-bit data format — Separately enabled transmitter and receiver — Programmable transmitter output polarity — Separate receiver and transmitter interrupt requests — Receiver framing error detection — Hardware parity checking — 1/16 bit-time noise detection — Single-wire and loop operations

 Timers

— Two general-purpose 32-bit timers for RTOS support per SC3850 core — Four TMR modules, each with four 16-bit timers; cascadable timers; count up/down;

programmable count modulo; count once or repeatedly; counters are preloadable; compare registers can be preloaded; counters can share available inputs; separate prescaler for each counter; each counter has capture and compare capability; any of the following clock sources: system clock or external clock input

— Two TIMER_32B modules, each with four 32-bit timers; cascadable timers; count

up/down; programmable count modulo; count once or repeatedly; counters are preloadable; compare registers can be preloaded; counters can share available inputs; separate prescaler for each counter; each counter has capture and compare capability; any of the following clock sources: system clock or external clock input.

— Eight software watchdog timer (SWT) modules

Features

 Eight programmable hardware semaphores, locked by simple write access without need

for read-modify-write operation by the DSP core.

 Virtual interrupts

— Generation of 32 virtual interrupts by a simple write access — Generation of virtual

C interface

 I

NMI by a simple write access

— Two-wire interface — Multi-master operational — Calling address identification interrupt — START and STOP signal generation/detection — Acknowledge bit generation/detection — Bus busy detection — Programmable clock frequency — On-chip filtering for spikes on the bus

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 General-purpose input/output (GPIO) ports:

— 32 GPIO ports — Each GPIO port can either serve the on-device peripherals or act as a programmable

I/O pin — Sixteen GPIO pins can be configured as external interrupt inputs — All ports are bidirectional — All ports are set as GPIO inputs at system reset — All port values can be read while the pin is connected to an internal peripheral — All ports have open-drain output capability

 Boot interface options:

— Ethernet — Serial RapidIO interface

—I

— SPI

 JTAG. Test Access Port (TAP) and Boundary Scan Architecture designed to comply with

IEEE Std. 1149.6.

 Reduced power dissipation

— Very low power CMOS design — Low-power standby modes — Optimized power management circuitry (instruction-dependent, peripheral-dependent,

and mode-dependent)

 Technology: The MSC8158E device is manufactured using CMOS 45 nm SOI

technology.

 Flip Chip-Plastic Ball Grid Array (FC-PBGA), 783-ball, 1 mm pitch, 29 mm × 29 mm

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1.2 Block Diagram

A block diagram of the MSC8158E is shown in Figure 1-1.

DDR Interface 64/32-bit

1333 MHz data rate

JTAG IEEE 1149.6

SC3850

DSP Core

32 Kbyte

ICacheL1DCache

512 Kbyte

L2 Cache / M2 Memory

Six DSP Cores at 1 GHz

Note: The arrow direction indicates master or slave.

DDR

Controller

QUICC

Engine™

Subsystem

Two RGMII

SPI

CLASS

Two SGM II

Figure 1-1. MSC8158E Block Diagram

CLASS1

High-Speed

Serial

Interface

Two Serial RapidIO (1 = x1/x2/x4; 2 = x1/x2) up to 5 Gbaud Six lanes CPRI v4.1 up to 6.144 Gbaud Two SGMII

CPRI data WR

M3 Memory

3072 Kbyte

MAPLE-B2

Block Diagram

I/O-Interrupt

Concentrator

UART

Clocks

Timers

Reset

DMA 32 ch

SEC

Semaphores

Virtual

Interrupts Boot ROM

Other Modules

1.3 Architecture

The MSC8158E architecture is carefully optimized to achieve the maximum channel density for a given device area, power, and cost. Also, the MSC8158E is a derivative of the same system internal platform Freescale uses to implement new DSPs. Therefore, Freescale can swiftly spin off DSP devices from the same platform and provide the customer with familiar modules and programming models.

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Overview

1.4 StarCore SC3850 DSP Subsystem

Figure 1-2 shows the block diagram of the StarCore SC3850 DSP subsystem, which contains the SC3850 core, the ICache, the DCache, the MMU for task and memory protection and address translation and two write buffers. In addition, there is an interrupt controller, two timers, a debug and profiling unit, and a trace write buffer. The SC3850 core fetches instructions through a 128-bit wide program bus (P-bus), and it fetches data through two 64-bit wide data buses (Xa-bus and Xb-bus). After a brief overview of the DSP platform, this section presents a subsection on each part of the platform.

TWB

Debug Support OCE30

DPU

SC3850

Core

128 bits master bus to CLASS

512 Kbyte L2 Cache / M2 Memory

IQBus

32 Kbyte

Instruction

Cache

P-bus Xa-bus Xb-bus

DQBus

128 bits slave bus from CLASS

Write-

Through

Buffer

(WTB)

32 Kbyte

Data

Cache

Figure 1-2. StarCore SC3850 DSP Subsystem Block Diagram

Instruction/data read accesses are performed as follows:

Interrupts

EPIC

Write-

Back

Buffer

(WBB)

Timer

Task

Protection

Address

Translation

MMU

 Non-cacheable instructions/data are read from the target memory (for example, M2

memory).

 Cacheable instructions/data are read from the ICache/DCache. If they do not reside in the

cache (a miss), they are first fetched directly from the target memory.

There are three write policies when writing data outside the core:

 Cacheable write-back. Information is written only to the cache. The modified cache lines

are written to main memory only when they are replaced. The subsequent write-back buffer is combined with the write-allocate write-miss policy in which the required lines are loaded to the cache whenever a write-miss occurs.

 Cacheable write-through. Both the cache and the higher-level memory are updated during

every write operation. In the StarCore SC3850 DSP subsystem, the write-through buffer is

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StarCore SC3850 DSP Subsystem

a non-write allocate buffer. Therefore, a cacheable write-through access does not update the cache unless there is a hit.

 Non-cacheable. The write is direct to memory and is not written to the cache. A hazard

mechanism ensures that read accesses read updated data.

The DSP subsystem supports a Real-Time Operating System (RTOS) as follows:

 Virtual-to-physical address translation in the MMU.  Two privilege levels: user and supervisor.  Memory protection.  Precise exceptions upon an MMU violation enabling dynamic memory management.

The embedded programmable interrupt controller (EPIC) handles up to 256 interrupts with 32 priorities, 222 of which are external platform inputs.

1.4.1 StarCore SC3850 DSP Core

The SC3850 core is a flexible, programmable DSP core that handles compute-intensive communications applications, providing high performance, low power, and high code density. It is fully binary-backward compatible with the MSC8101, MSC8102, MSC8103, MSC8112, MSC8113, MSC8122, MSC8126, MSC8144, and MSC8144E DSPs, and it introduces many new features and enhancements.

The SC3850 core includes a data arithmetic logic unit (DALU) that contains four arithmetic logic units (ALUs). The core also includes an address generation unit (AGU) that contains two address arithmetic units. The SC3850 efficiently deploys the variable-length execution set (VLES) execution model, allowing grouping of up to 4 DALU and 2 AGU instructions in a single clock cycle without sacrificing code size for unused execution slots.

Each ALU has two 16-bit × 16-bit multipliers and a 40-bit accumulation capability, a 40-bit parallel barrel shifter and a 40-bit adder/subtractor. Each ALU performs one MAC operation per clock cycle, so a single core running at 1 GHz can perform up to 8 GMACS. Each AAU in the AGU can perform one address calculation and drive one data memory access per cycle. Data access widths are flexible from 8 to 64 bits. The AGU can support a throughput of up to 128 Gbps between the core and the memory.

Arithmetic operations use both fractional and integer data types, enabling the user to choose an individual style of code development or to use coding techniques derived from an application-specific standard. Parts of many algorithms use data with reduced width such as 8 or 16 bits. For better efficiency, the SC3850 core also supports single-instruction multiple-data (SIMD) instructions working on 2-word or 4-byte operands packed in a register. This packing allows the core to perform 2 to 4 operations per instruction (a maximum of 10 to 18 operation per VLES including AGU operations).

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A new dual 20-bit packed data format enables you to accumulate two multiplication results from the dual multiply ALU into a single register with guard bits. Alternatively, accumulation of both multiplies can be combined into a single 40-bit accumulator (dot product). In addition, the SC3850 supports special instructions to support special operations, such as Viterbi and video applications.

Although the SC3850 is a DSP, the rich instruction set also gives special attention to control code, making the SC3850 core ideal for applications that embed DSP and communications operations as general control code. Among the features that support control code are the interlocked pipeline that solves dependency hazards. The powerful SC3850 compiler translates code written in C/C++ into parallel fetch sets and maintains high code density and/or high performance by taking advantage of these features and the compiler-friendly instruction set. Even compiled pure control code yields results with high code density.

The SC3850 core supports general micro-controller capabilities, making it a suitable target for advanced operating systems. These capabilities include support for user and supervisor privilege levels that enable (with the off-core MMU) a protected software model implementation. Precise exceptions for memory accesses allow implementation of advanced memory management schemes and soft error correction.

The SC3850 core includes a dynamic branch prediction mechanism that contains a 48-entry branch target buffer (BTB) to improve performance by reducing the change of flow latency.

1.4.2 L1 Instruction Cache

The instruction channel, which comprises the instruction cache (ICache) and the instruction fetch unit (IFU), provides the core with instructions that are stored in higher-level memory. The ICache operates at core speed and stores recently accessed instructions. Whenever an addressed instruction (from the cacheable memory area) is found in the array, it is immediately made available to the core (ICache hit). When the required address is not found in the array, it is loaded to the ICache from the external (off-subsystem) memory by the IFU (ICache miss). The IFU operates in parallel with the core to implement a HW line prefetching algorithm that loads the ICache with information that has a high probability of being needed soon. This action reduces the number of cache misses. When an instruction is addressed from a non-cacheable area, the IFU fetches it directly to the XP bus of the core without writing it to the cache.

1.4.3 L1 Data Cache

The data channel comprises the data cache (DCache), the data fetch unit (DFU), the data control unit (DCU), the write-back buffer (WBB), and the write-through buffer (WTB). This two-way channel reads and writes information from the core to/from higher-level memory (M2 or L2) and control memory (internal blocks and external peripherals) spaces.

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StarCore SC3850 DSP Subsystem

The DCache, which operates at core speed, keeps the recently accessed data. When addressed data (from a cacheable memory area) is found in the array, it is immediately made available to the core (DCache hit) in a read and updated if written to. When the required address is not found in the array, a DCache miss occurs, and the DFU loads the data to the DCache from the external (off-subsystem) memory and drives it to the core. The DFU operates in parallel with the core and implements a HW line prefetch algorithm that loads the DCache with information that has a high probability of being needed soon, thus reducing the number of data cache misses.

The channel differentiates between cacheable and non-cacheable addresses. For cacheable addresses, it supports the write-back allocate and write-through writing policies. The selection is made on an address segment basis, as programmed in the MMU. The data channel supports the arrangement of data in big-endian formats. Core data types can be byte, word, long (4 bytes), or 2 long (8 bytes) wide.

1.4.4 L2 Unified Cache/M2 Memory

The L2 cache processes data and program accesses to the external M3/DDR memory. Caching the accesses requested by the L1 subsystem reduces the average penalty of accessing the high latency M3. The L2 cache includes a slave arbitration and tag unit, cache logic and arrays, along with a write buffer for write back and write through accesses, fetch logic to fetch data from the off platform memory upon a miss or a non-cacheable access, and a master arbiter that arbitrates between the different internal units.

1.4.5 Memory Management Unit (MMU)

The MMU performs three main functions:

 Memory hardware protection for instruction and data access with two privilege levels

(user and supervisor).

 High-speed address translation from virtual to physical address to support memory

relocation.

 Cache and bus controls for advanced memory management

Memory protection increases the reliability of the system so that errant tasks cannot ruin the privileged state and the state of other tasks. Program and data accesses from the core can occur at either the user or supervisor level. The MMU checks each access to determine whether it matches the permissions defined for this task in the memory attributes and translation table (MATT). If it does not, the access is killed and a memory exception is generated.

1.4.6 Debug and Profiling Unit (DPU)

The on-chip emulator (OCE) and the debug and profiling unit (DPU) are hardware blocks for debugging and profiling. The OCE performs the following tasks:

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 Communicates with the host debugger through the SoC JTAG test access port (TAP)

controller

 Enables the SC3850 core to enter the debug processing state upon a varied set of

conditions to: — Single step

— Execute core commands inserted from the host debugger to upload and download

memory and core registers.

 Sets up to six address-related breakpoints on either PC or a data address  Sets a data breakpoint on a data value, optionally combined with a data address  Generates the PC tracing flow, optionally filtered to a subset of events such as only

jumps/returns from subroutine, interrupts, and so on.

The DPU has the following characteristics:

 Enables parallel counting of subsystem events in six dedicated counters, from more than

40 events

 Filters, processes, and adds task ID and profiling information on the OCE PC trace

information

1.4.7 Extended Programmable Interrupt Controller

The internal extended programmable interrupt controller (EPIC) manages internal and external interrupts. The EPIC handles up to 256 interrupts, 222 of which are external subsystem inputs. The rest of the interrupts serve internal subsystem conditions. The external interrupts can be configured as either maskable interrupts or non-maskable interrupts (NMIs). The EPIC can handle 33 levels of interrupt priorities, of which 32 levels are maskable at the core and 1 level is NMI.

1.4.8 Timer

The timer block includes two 32-bit general-purpose counters with pre-loading capability. It counts clocks at the core frequency. It is intended mainly for operating system use.

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MAPLE-B2

1.5 MAPLE-B2

Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, OFDMA and SC-FDMA equalization and CRC algorithms. The MAPLE-B2 consists of second generation Programmable-System-Interface (PSIF2), a programmable controller with DMA capabilities. Eight accelerators are attached to it:

 eTVPE (Enhanced Turbo/Viterbi Processing-Element). Accelerates Turbo Decoding,

Rate-De-Matching and HARQ combining.

 Three eFTPE (enhanced FFT/DFT Processing-Element). Accelerates various sizes of

Fourier

 DEPE (Turbo Encoder Processing-Element). Accelerates Turbo Encoding and Rate

Matching.

 CRPE (Chip Rate Processing-Element). Accelerates Downlink and Uplink UMTS chip

rate

 CRCPE (CRC Processing-Element). Accelerates CRC attachment or check.

In addition to the eight accelerators, MAPLE-B2 provides virtual processing elements which enable chained functionality of multiple processing elements:

transforms and various pre/post transform processing.

processing

 Convolution or Filtering functionality utilized by combination of eFTPE and FDU.  Turbo Decoding and Re-encoding including rate matching using combination of eTVPE

and

DEPE.

1.6 Security Engine (SEC)

The Security Coprocessor version 3.1.0 (SEC) performs computationally intensive security functions including the following:

 Key generation and exchange  Authentication  Bulk encryption.

It is optimized to process all the algorithms associated with internet protocol security (IPSec), internet key exchange (IKE), secure sockets layer/transport layer security (SSL/TLS), internet small computer system interface (iSCSI), secure real-time transport protocol (SRTP), the IEEE

802.11i security standard, worldwide interoperability for microwave access (WiMAX), third generation (G3) A3/5 for global system for mobile communication (GSM) and Enhanced Data Rates for GSM evolution (EDGE), and GEA3 for general packet radio service (GPRS). For applications requiring security protection for sensitive data, the SEC provides encryption/decryption capability without imposing process loading on the device core processors. The SEC includes a controller, four data channels, and eight execution units (EUs) including a shared random number generator (RNGU) that use a common interface to the

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controller. The EUs perform the specific mathematical manipulations required by protocols used in cryptographic processing.

1.7 Chip-Level Arbitration and Switching System (CLASS)

The Chip Level Arbitration and Switching System (CLASS) is the central internal interconnect system for the MSC8158E device. The CLASS is a non-blocking, full-fabric interconnect that allows any initiator to access any target in parallel with another initiator-target couple. The CLASS uses a fully pipelined low latency design. The CLASS demonstrates per-target prioritized round-robin arbitration, highly optimized to the target characteristics. The CLASS operates at 667 MHz, and is separate from the SC3850 core frequency to provide an optimized trade-off between power dissipation, memory technology, and miss latency. Controlling the intradevice data flow, the CLASS reduces bottle necks and permits high bandwidth fully pipe-lined traffic. The CLASS system is ready for use and does not require any special configuration to perform non-blocking pipelined transactions from any initiator to any memory. The configurable arbitration features described in this chapter are for fine-tuning the system for specific application requirements.

The fifteen CLASS initiators are:

 Six SC3850 core subsystems (initiator ports 0–5)  Four MAPLE bridges (initiator ports 6–7 and ports 13–14)  One 8-lane HSSI port shared by one Serial RapidIO controller, six CPRI controllers, and

two SGMIIs (initiator ports 8 and 12)

 Peripherals bridge shared by the SEC, SPI, RGMII, SGMII, and JTAG interface (initiator

port 9)

 Two DMA ports (initiator ports 10–11)

The ten CLASS targets are:

 Configuration Control and Status Registers (CCSR) (target port 0)  Two DDR ports (target ports 1 for writes and 2 for reads)  MAPLE module (target port 3)  Three core subsystem bridges (two core subsystems per bridge) (target ports 4–6)  Three M3 memory ports (target ports 7–9)

1.8 M3 Memory

The 3072 KB M3 memory can be used for both program and data and eliminates the need for an external memory in a variety of applications, thus reducing board space, power dissipation, and cost. The memory is divided into three 1 MB blocks. One block is always on when the chip is powered up; the other two blocks can be powered down. The M3 memory has three 128-bit wide

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