NXP Semiconductors MSC8113 Reference Manual

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MSC8113 Reference Manual

Tri Core 16-Bit Digital Signal Processor

MSC8113RM

Rev 0, May 2008

Page 2

How to Reach Us:

Home Page:

www.freescale.com

Web Support:

http://www.freescale.com/support

USA/Europe or Locations Not List e d:

Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support

Europe, Middle East, and Africa:

Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support

Japan: Freescale Semiconductor Japan Ltd.

Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com

Asia/Pacific:

Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 010 5879 8000 support.asia@freescale.com

For Literature Requests Only:

Freescale Semiconductor

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@hibbertgroup.com

Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. The re are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.

Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.

Freescale, the Freescale logo, StarCore, and CodeWarrior are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.

MSC8113RM Rev. 0 5/2008

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MSC8113 Overview

SC140 Core Overview

External Sign als

System Interface Unit (SIU)

Reset

Boot Program

Clocks

Memory Map

Extended Core

MQBus and M2 Memory

SQBus

Memory C ontroller

System Bus

Direct Slave Interface (DSI)

Hardware Semaphores

Direct Memory Access (DMA) Controller

Interrupt Processing

Debugging

Internal Peripheral Bus (IPBus)

Time-Division Multiplexing (TDM) Interface

Universal Asynchronous Receiver/Transmitter (UART)

Timers

General-Purpose Input/Output (GPIO)

I2C Software Module

Ethernet Controller

Programming Reference

MSC8113 Dictionary

MSC8113 Boot Code

Index

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MSC8113 Overview

SC140 Core Overview External Signals System Interface Unit (SIU) Reset Boot Program Clocks Memory Map Extended Core MQBus and M2 Memory SQBus Memory Controller System Bus

Direct Slave Interface (DSI) Hardware Semaphores Direct Memory Access (DMA) Controller Interrupt Processing Debugging Internal Peripheral Bus (IPBus) Time-Division Multiplexing (TDM) Interface Universal Asynchronous Receiver/Transmitter (UART) Timers General-Purpose Input/Output (GPIO) I2C Software Module Ethernet Controller

Programming Reference MSC8113 Dictionary MSC8113 Boot Code Index

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About This Book

Before Using This Manual—Important Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii

Audience and Helpful Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxii

Notational Conventions and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii

Conventions for Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiv

Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiv

Other MSC8113 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvii

Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvii

1 MSC8113 Overview

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.2.1 Extended Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.2.1.1 SC140 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1.2.1.2 M1 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.2.1.3 Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.2.1.4 QBus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14

1.2.2 Power Saving Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

1.2.2.1 Extended Core Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

1.2.2.2 Extended Core Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

1.2.3 M2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

1.2.4 System Interface Unit (SIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

1.2.4.1 60x-Compatible System Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

1.2.4.2 Memory Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

1.2.5 Direct Slave Interface (DSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17

1.2.6 Direct Memory Access (DMA) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18

1.2.7 Internal and External Bus Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19

1.2.8 TDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21

1.2.9 Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22

1.2.10 Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . . . 1-23

1.2.11 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23

1.2.12 GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24

1.2.13 Reset and Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24

1.2.14 Interrupt Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25

1.2.15 Signal Multiplexing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25

1.3 Internal Communication and Semaphores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26

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1.3.1 Internal Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26

1.3.2 Atomic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27

1.3.3 Hardware Semaphores. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27

2 SC140 Core Overview

2.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.1.1 Data Arithmetic Logic Unit (Data ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.1.1.1 Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.1.1.2 Multiply-Accumulate (MAC) Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.1.1.3 Bit-Field Unit (BFU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.1.2 Address Generation Unit (AGU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.1.2.1 Stack Pointer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.1.2.2 Bit Mask Unit (BMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.1.3 Program Sequencer Unit (PSEQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.1.4 Enhanced On-Chip Emulation (EOnCE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2.1 AGU Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.2.2 Data Arithmetic Logic Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.2.3 Program Control Unit Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.3 Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.4 Additional Programming Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

3 External Signals

3.1 Power Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.2 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.3 Reset and Configuration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.4 Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals . . . . . . . . . 3-4

3.5 Memory Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

3.6 GPIO, TDM, UART, and Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

3.7 Dedicated Ethernet Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27

3.8 EOnCE Event and JTAG Test Access Port Signals. . . . . . . . . . . . . . . . . . . . . . 3-27

3.9 Reserved Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28

4 System Interface Unit (SIU)

4.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2

4.1.1 Bus Monitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.1.2 Timers Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.1.3 Time Counter (TMCNT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.1.4 Periodic Interrupt Timer (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.1.5 SIU and General Software Watchdog Timers. . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.1.6 SIU Multiplexing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

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4.2 SIU Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

4.2.1 System Configuration and Protection Registers . . . . . . . . . . . . . . . . . . . . . . . 4-10

4.2.2 Periodic Interrupt Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27

5 Reset

5.1 Power-On Reset (PORESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.2 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.2.1 Reset Configuration Through the DSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.2.2 Reset Configuration Through the System Bus . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5.3 Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

5.4 Soft Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

5.5 Reset Configuration Writes Through the System Bus. . . . . . . . . . . . . . . . . . . . . 5-9

5.5.1 Single MSC8113 System Configuration From EPROM. . . . . . . . . . . . . . . . . . 5-9

5.5.2 Single Slave MSC8113 Configuration by System Bus Host . . . . . . . . . . . . . 5-10

5.5.3 Multi-MSC8113 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

5.5.4 Multiple MSC8113 Devices in a System With No EPROM . . . . . . . . . . . . . 5-13

5.6 Reset Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

5.6.1 Hard Reset Configuration Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

5.6.2 Reset Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16

6 Boot Program

6.1 Boot Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.2 Booting From an External Memory Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.3 Booting from an External Host (DSI or System Bus) . . . . . . . . . . . . . . . . . . . . . 6-4

6.4 Booting From the TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

6.4.1 Initializing the TDM Physical Layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.4.1.1 Receiver Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

6.4.1.2 Transmitter Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

6.4.2 TDM Logical Layer Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

6.4.2.1 Messages Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

6.4.2.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10

6.5 Booting From a UART Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13

6.6 Booting from I²C Slave Memory Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14

6.6.1 Procedure Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16

6.6.2 I

C System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17

7 Clocks

7.1 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

7.2 Board-Level Clock Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.2.1 Single Master Mode Board-Level Clock Distribution . . . . . . . . . . . . . . . . . . . 7-3

7.2.2 Multi-Master Mode Board-Level Clock Distribution . . . . . . . . . . . . . . . . . . . . 7-5

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7.3 Clock Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7

7.4 Clocks Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10

8 Memory Map

8.1 SC140 Core Internal Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8

8.2 QBus Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9

8.3 MQBus Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11

8.4 SQBus Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12

8.5 IPBus Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12

8.6 Local Bus Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27

8.7 System Bus Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-55

8.8 DSI Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-61

8.9 Pseudo Command Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-79

8.10 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-79

9 Extended Core

9.1 SC140 DSP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2

9.2 Extended Core Memory (M1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

9.2.1 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

9.2.1.1 Memory Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4

9.2.1.2 Memory Contention and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

9.2.2 Errors and Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

9.2.2.1 Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

9.2.2.2 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

9.3 Extended QBus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7

9.3.1 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8

9.3.1.1 Fetch Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9

9.3.2 QBus Execution Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11

9.3.3 QBus Banks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11

9.3.4 Bank Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12

9.3.5 Bank Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12

9.3.6 Reservation Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14

9.3.7 Setting a Data Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15

9.3.8 Instruction Cacheable Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17

9.3.9 EQBS Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18

9.4 Instruction Cache (ICache) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24

9.4.1 ICache Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28

9.4.2 Debugging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29

9.4.3 Multi-Task Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-32

9.4.4 ICache Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33

9.4.4.1 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-34

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9.4.4.2 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-34

9.4.4.3 Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35

9.4.4.4 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35

9.4.4.5 ICache Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36

9.5 Programmable Interrupt Controller (PIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-38

9.6 Local Interrupt Controller (LIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-38

9.7 Extended Core Power Saving Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39

9.7.1 Extended Core Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39

9.7.2 Extended Core Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39

10 MQBus and M2 Memory

10.1 MQBus Arbitration Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2

10.2 M2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

10.3 Reservation Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

11 SQBus

11.1 System Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.2 Reservation (Atomic) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

11.2.1 Reservation Operation in the SQBus Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

11.2.2 Reservation Operation on the System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

11.2.3 Conditions for Failure of the Reservation Operation . . . . . . . . . . . . . . . . . . . 11-3

12 Memory Controller

12.1 Basic Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3

12.1.1 Address and Address Space Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8

12.1.2 Page Hit Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8

12.1.3 Parity Generation and Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8

12.1.4 Transfer Error Acknowledge (TEA

12.1.5 Machine Check Interrupt (MCP

12.1.6 Data Buffer Controls (BCTL[0–1]

12.1.7 Atomic Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10

12.1.8 Partial Data Valid Indication (PSDVAL

12.1.9 ECC/Parity Byte-Select (PPBS

12.1.10 Data Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11

12.1.11 60x-Compatible Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12

12.1.12 External Memory Controller Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12

12.1.13 External Address Latch Enable Signal (ALE) . . . . . . . . . . . . . . . . . . . . . . . 12-12

12.1.14 BADDR[27–31] Signal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12

12.2 SDRAM Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13

12.2.1 Supported SDRAM Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14

12.2.2 SDRAM Power-On Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14

) Generation . . . . . . . . . . . . . . . . . . . . . . 12-9

) Generation . . . . . . . . . . . . . . . . . . . . . . . . . 12-9

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11

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12.2.3 JEDEC-Standard SDRAM Interface Commands . . . . . . . . . . . . . . . . . . . . . 12-16

12.2.4 Page-Mode Support and Pipeline Accesses . . . . . . . . . . . . . . . . . . . . . . . . . 12-16

12.2.5 Bank Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17

12.2.6 BNKSEL Signals in Single-MSC8113 Bus Mode . . . . . . . . . . . . . . . . . . . . 12-18

12.2.7 SDRAM Address Multiplexing (SDAM and BSMA) . . . . . . . . . . . . . . . . . 12-18

12.2.8 SDRAM Read/Write Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20

12.2.9 SDRAM Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20

12.2.10 SDRAM Signals: Device-Specific Parameters . . . . . . . . . . . . . . . . . . . . . . . 12-20

12.2.11 SDRAM Signals: General Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . 12-25

12.2.12 SDRAM Signals: mode-set Command Timing. . . . . . . . . . . . . . . . . . . . . . . 12-28

12.2.13 SDRAM Signals: Refresh Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28

12.2.14 SDRAM Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29

12.2.14.1 SDRAM Configuration Example (Page-Based Interleaving) . . . . . . . . . . 12-29

12.2.14.2 SDRAM Configuration Example (Bank-Based Interleaving) . . . . . . . . . . 12-31

12.3 General-Purpose Chip-Select Machine (GPCM). . . . . . . . . . . . . . . . . . . . . . . 12-33

12.3.1 GPCM Signals: Timing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34

12.3.1.1 Chip-Select Assertion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34

12.3.1.2 Chip-Select and Write Enable Deassertion Timing . . . . . . . . . . . . . . . . . . 12-36

12.3.1.3 Relaxed Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-37

12.3.1.4 Output Enable (POE

) Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38

12.3.1.5 Programmable Wait State Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38

12.3.1.6 Extended Hold Time on Read Accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . 12-40

12.3.2 GPCM Signals: External Access Termination . . . . . . . . . . . . . . . . . . . . . . . 12-42

12.3.3 Boot Chip-Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-44

12.3.4 Differences Between MPC8xx GPCM and MSC8113 GPCM. . . . . . . . . . . 12-44

12.4 User-Programmable Machines (UPMs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-45

12.4.1 Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-46

12.4.1.1 Memory Access Requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-47

12.4.1.2 UPM Refresh Timer Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-48

12.4.1.3 Software Requests—run Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-48

12.4.1.4 Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-48

12.4.2 Programming the UPMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-49

12.4.3 Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-49

12.4.4 RAM Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-50

12.4.4.1 RAM Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-51

12.4.4.2 Last Word (LAST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-59

12.4.4.3 Address Multiplexing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-59

12.4.4.4 Data Valid and Data Sample Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-59

12.4.4.5 Disable Timer Mechanism (TODT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-60

12.4.4.6 Signal Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-60

12.4.4.7 Wait Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-60

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12.4.4.8 Extended Hold Time on Read Accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . 12-61

12.4.5 DRAM Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-62

12.4.6 Interface Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-63

12.4.6.1 Memory System Interface Example Using UPM. . . . . . . . . . . . . . . . . . . . 12-63

12.4.6.2 EDO Interface Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-74

12.4.7 Differences Between MPC8xx UPM and MSC8113 UPM . . . . . . . . . . . . . 12-82

12.5 Handling Devices With Slow or Variable Access Times . . . . . . . . . . . . . . . . 12-82

12.5.1 Hierarchical Bus Interface Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-83

12.5.2 Slow Devices Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-83

12.6 External Master Support (60x-Compatible Mode) . . . . . . . . . . . . . . . . . . . . . 12-83

12.6.1 Strict 60x-Compatible External Masters. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-84

12.6.2 MSC8113-Type External Masters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-84

12.6.3 Extended Controls in 60x-Compatible Mode . . . . . . . . . . . . . . . . . . . . . . . . 12-84

12.6.4 Address Incrementing for External Bursting Masters. . . . . . . . . . . . . . . . . . 12-85

12.6.5 External Masters Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-85

12.7 Internal SRAM and IPBus Peripherals Support. . . . . . . . . . . . . . . . . . . . . . . . 12-92

12.7.1 UPM Programming Example — Internal SRAM . . . . . . . . . . . . . . . . . . . . . 12-92

12.7.2 GPCM Programming Example, IPBus Peripherals. . . . . . . . . . . . . . . . . . . . 12-94

12.7.3 Flyby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-94

12.8 Memory Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-95

13 System Bus

13.1 System Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1

13.1.1 Address Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3

13.1.2 Address Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5

13.1.3 Address Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5

13.1.4 Address Transfer Attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6

13.1.5 Address Transfer Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8

13.1.6 Data Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9

13.1.7 Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10

13.1.8 Data Transfer Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12

13.2 60x-Compatible Bus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14

13.2.1 System Bus Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14

13.2.1.1 Single MSC8113 Bus Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14

13.2.1.2 60x-Compatible Bus Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16

13.2.2 System Bus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17

13.2.2.1 Arbitration Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18

13.2.2.2 Address Pipelining and Split-Bus Transactions . . . . . . . . . . . . . . . . . . . . . 13-19

13.2.2.3 Memory Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19

13.2.3 Address Tenure Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19

13.2.3.1 Address Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20

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13.2.3.2 Address Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21

13.2.3.3 Address Transfer Attribute Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-22

13.2.3.4 Burst Ordering During Data Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-24

13.2.3.5 Effect of Alignment on Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-24

13.2.3.6 Effect of Port Size on Data Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26

13.2.3.7 60x-Compatible System Bus Mode—Size Calculation . . . . . . . . . . . . . . . 13-30

13.2.3.8 Extended Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31

13.2.3.9 Address Transfer Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-33

13.2.3.10 Address Retried With ARTRY

Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-33

13.2.3.11 Address Tenure Timing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-34

13.2.3.12 Pipeline Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-35

13.2.4 Data Tenure Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-36

13.2.4.1 Data Bus Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-36

13.2.4.2 Data Streaming Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-36

13.2.4.3 Data Bus Transfers and Normal Termination . . . . . . . . . . . . . . . . . . . . . . 13-37

13.2.4.4 Effect of ARTRY

13.2.4.5 Port Size Data Bus Transfers and PSDVAL

13.2.4.6 Data Bus Termination by Assertion of TEA

Assertion on Data Transfer and Arbitration . . . . . . . . . 13-38

Termination . . . . . . . . . . . . . 13-38

Signal. . . . . . . . . . . . . . . . . . 13-40

14 Direct Slave Interface (DSI)

14.1 Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3

14.1.1 Data Bus Width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3

14.1.2 DCR[BEM] Bit Access Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4

14.2 Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6

14.2.1 Sliding Window Addressing Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6

14.2.2 Full Address Addressing Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8

14.2.3 Host Chip ID Signals (HCID[0–3]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10

14.2.4 DSI Endian Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10

14.3 Host Access Modes and Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11

14.3.1 Single Strobe Versus Dual Strobe Access Modes. . . . . . . . . . . . . . . . . . . . . 14-11

14.3.2 Synchronous Versus Asynchronous Access Mode . . . . . . . . . . . . . . . . . . . . 14-12

14.3.2.1 Burst Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12

14.3.2.2 DSI Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13

14.3.3 Asynchronous Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13

14.3.3.1 Asynchronous Write Using Dual Strobe Mode . . . . . . . . . . . . . . . . . . . . . 14-13

14.3.3.2 Asynchronous Write Using Single Strobe Mode . . . . . . . . . . . . . . . . . . . . 14-15

14.3.3.3 Asynchronous Read Using Dual Strobe Mode. . . . . . . . . . . . . . . . . . . . . . 14-16

14.3.3.4 Asynchronous Read Using Single Strobe Mode . . . . . . . . . . . . . . . . . . . . 14-17

14.3.4 Synchronous Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18

14.3.4.1 Synchronous Single Write Using Dual Strobe Mode. . . . . . . . . . . . . . . . . 14-18

14.3.4.2 Synchronous Single Write Using Single Strobe Mode . . . . . . . . . . . . . . . 14-19

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14.3.4.3 Synchronous Single Read Using Dual Strobe Mode . . . . . . . . . . . . . . . . . 14-20

14.3.4.4 Synchronous Single Read Using Single Strobe Mode . . . . . . . . . . . . . . . . 14-21

14.3.4.5 Synchronous Burst Write Using Dual Strobe Mode . . . . . . . . . . . . . . . . . 14-22

14.3.4.6 Synchronous Burst Write Using Single Strobe Mode . . . . . . . . . . . . . . . . 14-23

14.3.4.7 Synchronous Burst Read Using Dual Strobe Mode . . . . . . . . . . . . . . . . . . 14-24

14.3.4.8 Synchronous Burst Read Using Single Strobe Mode. . . . . . . . . . . . . . . . . 14-25

14.3.5 Broadcast Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26

14.4 DSI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27

14.4.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28

14.4.2 DSI Reset During Host Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28

14.5 DSI Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29

14.5.1 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29

14.5.2 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-35

15 Hardware Semaphores 16 Direct Memory Access (DMA) Controller

16.1 DMA Signals: Requestor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3

16.1.1 Signal Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3

16.1.2 Peripheral Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4

16.2 DMA Operating Modes: Transfer Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8

16.2.1 DMA Transfer Size and Peripheral Port Size . . . . . . . . . . . . . . . . . . . . . . . . . 16-8

16.2.2 DMA Access Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8

16.2.3 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10

16.2.3.1 External Memory and an External Peripheral on the System Bus . . . . . . . 16-10

16.2.3.2 External Peripheral to Internal Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11

16.2.3.3 External Peripheral to External Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . 16-12

16.2.3.4 External Memory and External Memory on the System Bus. . . . . . . . . . . 16-13

16.2.3.5 External Memory to Internal Memory on the System Bus. . . . . . . . . . . . . 16-14

16.2.3.6 Internal Memory to Internal Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15

16.2.3.7 Flyby Transfer from External Peripheral to External Memory . . . . . . . . . 16-16

16.2.3.8 Flyby Transfers Between Internal Memories, M2 and M1 . . . . . . . . . . . . 16-17

16.2.3.9 Transfers Between Internal Memories M1 and M1 (Flyby Mode) . . . . . . 16-18

16.2.4 DMA Operating Modes: Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18

16.2.4.1 Simple Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21

16.2.4.2 Cyclic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22

16.2.4.3 Incremental Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23

16.2.4.4 Chained Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24

16.2.4.5 Complex Buffers—Dual Cyclic Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . 16-25

16.2.5 2D Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-26

16.3 DMA Transfer Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-29

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16.3.1 DMA Priority Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-30

16.3.1.1 Fixed-Priority Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-30

16.3.1.2 Round-Robin Priority Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-30

16.3.1.3 DMA Arbitration Device Level Considerations. . . . . . . . . . . . . . . . . . . . . 16-32

16.3.2 DMA Data Transfer Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-33

16.3.3 Terminating a DMA Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-33

16.4 DMA Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-34

16.4.1 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-35

16.4.2 DMA Status and Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-42

16.4.3 Bus Error Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-43

17 Interrupt Processing

17.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

17.1.1 Global Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4

17.1.1.1 INT_OUT

17.1.1.2 NMI

17.1.1.3 Virtual Interrupt Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7

17.1.1.4 Virtual NMI

17.1.1.5 GIC Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8

17.1.2 Local Interrupt Controller (LIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9

17.1.2.1 Resolving LIC Interrupts by the SC140 Cores. . . . . . . . . . . . . . . . . . . . . . 17-11

17.1.2.2 Level Interrupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12

17.1.2.3 Edge Interrupt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13

17.1.2.4 DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13

17.1.2.5 LIC Interrupt Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13

17.1.3 Programmable Interrupt Controller (PIC). . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17

17.1.4 Peripheral Bus (QBus) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18

17.1.4.1 Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18

17.1.5 Interrupt Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18

17.2 Interrupt Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21

17.2.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21

17.2.2 LIC and PIC Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22

17.2.3 Clearing Pending Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23

17.3 Interrupts Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23

17.3.1 GIC Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23

17.3.2 LIC Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-29

17.3.2.1 LIC Interrupt Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30

17.3.2.2 LIC Interrupt Enable Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-37

17.3.2.3 LIC Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-38

17.3.3 PIC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-40

17.3.3.1 Edge/Level-Triggered Interrupt Priority Registers . . . . . . . . . . . . . . . . . . 17-40

Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6

or NMI_OUT Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7

Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8

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17.3.3.2 Interrupt Priority Structure and Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-40

17.3.3.3 Interrupt Pending Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-43

18 Debugging

18.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2

18.2 TAP Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4

18.3 Instruction Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5

18.4 Multi-Core JTAG and EOnCE Module Concept. . . . . . . . . . . . . . . . . . . . . . . . 18-8

18.4.1 Enabling the EOnCE Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9

18.4.2 DEBUG_REQUEST and ENABLE_EOnCE Commands . . . . . . . . . . . . . . 18-10

18.4.3 Reading/Writing EOnCE Registers Through JTAG . . . . . . . . . . . . . . . . . . . 18-10

18.5 Signalling a Debug Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11

18.5.1 EE_CTRL Modifications for the MSC8113 . . . . . . . . . . . . . . . . . . . . . . . . . 18-12

18.5.2 Event Selector Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13

18.5.3 EDCA1_CTRL Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13

18.5.4 Real-Time Debug Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14

18.5.5 Exiting Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15

18.5.6 Accessing EOnCE Registers Through JTAG in Real Time . . . . . . . . . . . . . 18-15

18.5.7 External Debug Exception Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15

18.5.8 Generating a Debug Exception From an EDCA PC Detection Event . . . . . 18-16

18.6 Tracing in the MSC8113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-16

18.7 General JTAG Mode Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-17

18.8 JTAG and EOnCE Module Programming Model . . . . . . . . . . . . . . . . . . . . . . 18-18

18.8.1 Identification Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-18

18.8.2 Boundary Scan Register (BSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-18

18.8.3 Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21

18.8.3.1 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21

18.8.3.2 Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21

18.8.3.3 General-Purpose Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-22

18.8.3.4 Parallel Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-22

19 Internal Peripheral Bus (IPBus)

19.1 TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1

19.2 UART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

19.3 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

19.4 GPIOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

19.5 Hardware Semaphore Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

19.6 Global Interrupt Controller (GIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2

19.7 Direct Slave Interface (DSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3

19.8 Ethernet Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3

19.9 IPBus Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4

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19.10 Stop Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4

19.11 IPBus Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5

20 TDM Interface

20.1 Typical Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5

20.2 TDM Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6

20.2.1 Common Signals for the TDM Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8

20.2.2 Receiver and Transmitter Independent or Shared Operation . . . . . . . . . . . . 20-10

20.2.3 TDM Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13

20.2.4 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-15

20.2.4.1 Sync Out Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-15

20.2.4.2 Sync In Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16

20.2.4.3 Serial Interface Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18

20.2.4.4 Reverse Data Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-20

20.2.5 TDM Local Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21

20.2.6 Buffers Mapped on the Local Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22

20.2.6.1 Data Buffer Size and A/m-law Channels . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22

20.2.6.2 Data Buffer Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-23

20.2.6.3 Threshold Pointers and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-26

20.2.6.4 Unified Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-28

20.2.7 Adaptation Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-29

20.3 TDM Power Saving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-31

20.4 Channel Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-31

20.5 Loopback Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-32

20.6 TDM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-33

20.7 TDM Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-34

20.7.1 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-36

20.7.2 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-53

20.7.3 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-62

20.7.4 System Bus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-69

21 UART

21.1 Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6

21.1.1 Character Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7

21.1.2 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9

21.1.3 Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10

21.1.4 Parity Bit Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10

21.2 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10

21.2.1 Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11

21.2.2 Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12

21.2.3 Framing Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17

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21.2.4 Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-18

21.2.5 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-18

21.2.6 Baud-Rate Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-18

21.2.6.1 Slow Data Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-19

21.2.6.2 Fast Data Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-20

21.2.7 Receiver Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-20

21.2.7.1 Idle Input Line Wake-Up (WAKE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21

21.2.7.2 Address Mark Wake-Up (WAKE = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21

21.3 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21

21.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-22

21.4.1 Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-22

21.4.2 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-22

21.4.3 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-23

21.4.4 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-23

21.4.5 Receiver Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-23

21.5 Interrupt Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-24

21.6 UART Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-24

22 Timers

22.1 Timers Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8

22.1.1 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9

22.1.2 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-16

22.1.3 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-17

23 GPIO

23.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1

23.2 GPIO Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2

23.3 Ethernet Functionality of GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4

23.4 GPIO Connection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6

23.5 GPIO Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9

24 I²C Software Module

24.1 i2c_txrx_bit Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3

24.2 i2c_txrx_byte Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5

24.3 i2c_read_SequentialData Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7

24.4 i2c_sample_gpio Routine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9

24.5 i2c_assert_start Routine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-10

24.6 i2c_assert_stop Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11

24.7 i2c_WaitFor_StartCond_BusFreeTime Routine . . . . . . . . . . . . . . . . . . . . . . . 24-12

24.8 i2c_write_SequentialData Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13

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25 Ethernet Controller

25.1 Ethernet Basics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1

25.2 Media-Independent Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5

25.3 MSC8113 Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5

25.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6

25.4.1 MII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7

25.4.2 RMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7

25.4.3 SMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7

25.4.4 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8

25.4.4.1 Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8

25.4.4.2 Echo Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9

25.4.4.3 Low-Power Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9

25.4.5 Management Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9

25.5 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10

25.6 Ethernet Controller Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12

25.6.1 MII. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13

25.6.1.1 MII Transmit Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13

25.6.1.2 MII Receive Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14

25.6.2 RMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14

25.6.2.1 RMII Transmit Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15

25.6.2.2 RMII Receive Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16

25.6.3 SMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16

25.6.3.1 SMII Transmit Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17

25.6.3.2 SMII Receive Flow Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-19

25.7 MAC Control of CSMA/CD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-21

25.7.1 Handling Packet Collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-21

25.7.2 Controlling Packet Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-22

25.7.3 Controlling PHY Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-22

25.8 RMON Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-23

25.9 Frame Recognition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-23

25.9.1 Pattern Matching Recognition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-23

25.9.2 Destination Address Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-25

25.9.3 Hash Table Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-27

25.10 Buffer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-28

25.10.1 Data Buffer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-28

25.10.2 Receive Frame Processing with Pattern Matching . . . . . . . . . . . . . . . . . . . . 25-30

25.10.3 Receive Pattern Matching Filing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-31

25.10.4 Filing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-35

25.10.5 Transmit Frame Processing with Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . 25-36

25.11 Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-38

25.12 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-39

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25.13 Error-Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-41

25.14 Inter-Packet Gap Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-42

25.15 Connecting to Physical Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-42

25.16 Initialization and Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-46

25.17 Ethernet Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-49

25.17.1 General Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-53

25.17.2 FIFO Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-62

25.17.3 Transmit Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-69

25.17.4 Receive Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-78

25.17.5 MAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-84

25.17.6 MII Management Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-92

25.17.7 MIIGSK Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-96

25.17.8 RMON Management Information Base (MIB). . . . . . . . . . . . . . . . . . . . . . 25-105

25.17.9 Hash Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-131

25.17.10 Pattern Matching Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-133

25.17.11 Data Structures (Buffer Descriptors). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-137

A Programming Reference

A.1 Register Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

A.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2

A.3 Programming Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8

B MSC8113 Dictionary C MSC8113 Boot Code

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About This Book

The MSC8113 device is based on the StarCore® SC140 DSP core. It addresses the challenges of the networking market. The benefits of the MSC8113 include not only a very high level of performance but also a product design that enables effective software development and integration. Its tool suite provides a full-featured development environment for C/C++ and assembly languages as well as ease of integration with third-party software, such as off-the-shelf libraries and a real-time operating system. The MSC8113 is logically partitioned into three distinct blocks: three extended cores, a system interface unit (SIU), and communications peripherals.

Read Chapters 19–25

for information on the communications peripherals.

Serial I/O

Read Chapters 1–3 for an overview of the entire system.

Communications

Peripherals

Three Extended Cores

Read Chapters 2 and 9

for an overview of the SC140 extended core. Also, consult the

SC140 StarCore DSP Core Reference Manual.

Three Extended Cores

Each extended core contains an SC140 DSP core with internal memory for data and program storage, peripheral hardware, and two interrupt controllers. Memory includes 224 KB (896 KB total) of zero wait state SRAM and 16 KB (64 KB total) of instruction cache. The MSC8113 also includes 476 KB of shared memory (M2) and 4 KB of boot ROM. Minimum code density is achieved using a 16-bit instruction set that is grouped into execution sets by the compiler (or by the programmer) for high ins tructi on para llelis m.The D SI prov ides a glueless 32/64-bit interface to a host processo r for dat a and command communication. The programmable interrupt controller (PIC) and local interrupt controller (LIC) process all internal interrupt requests, notifying the SC140 DSP cores or external devices of an interrupt event.

SIU

System Bus

Direct Slave Interface

Read Chapters 10–18 for details on data operations and exception processing.

SIU

Supports internal and external system-related functions. The SIU includes hardware su ch as a direct memory access (DMA) controller, clocks, and reset configuration registers. It also includes the memory controllers, which interface to external memory devices and/or other devices s uch as a system host or other DSPs.

Read Chapters 4–8 for details on configuration and reset, including the SIU modules and functions.

Communications

Peripherals

Includes four TDM interfac es with 256 channels each, a UART, thirty-two 16-bit timers, thirty-two programmable GPIO signals, eight hardware semaphore registers, an I module, an Ethernet interface, and a global interrupt controller (GIC). The serial interfaces give additional functiona lity and flexibility. The semaphore registers provide resource control for external hosts. The GIC extends interrupt handling capability.

C software

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Before Using This Manual—Important Note

This manual describes the structure and function of the MSC8113 device. The information in this manual is subject to change without notice, as described in the disclaimers on the title page of this manual. As with any technical documentation, it is your responsibility as the reader to ensure that you are using the most recent version of the documentation. For more information, contact your sales representative.

Before using this manual, determine whether it is the latest revision and whether there are errata or addenda. To locate any published errata or updates associated with this manual or this product, refer to the Freescale web site. The address for the web site is listed on the back cover of this manual.

Audience and Helpful Hints

This manual is intended for software and hardware developers and applications programmers who want to develop products with the MSC8113. It is assumed that you have a working knowledge of DSP technology and that you may be familiar with Freescale products based on the Freescale DSP56000 or DSP56300 core. Familiarity with Freescale DSP products is not necessary.

For your convenience, the chapters of this manual are organized to make the information flow as predictably as possible. When feasible, the information in each chapter follows this general sequence:

 Features  Architecture  Signals  Operation/operating modes  Programming  Programming Examples  Programming Model (registers)

In chapters that include a Programming Model section, this section is the last one in the chapter, or module subsection for those chapters that include multiple modules, and describes all registers for the module discussed. The Programming Model section begins with a bulleted overview of the registers that includes the page number where the description of each register begins.

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Notational Conventions and Definitions

This manual uses the following notational conventions:

mnemonics Instruction mnemonics appear in lowercase bold.

COMMAND

names

Command names are set in small caps, as follows: GRACEFUL STOP TRANSMIT

ENTER HUNT MODE.

italics Book titles in text are set in italics, as are cross-referenced section titles. Also,

italics are used for emphasis and to highlight the main items in bulleted lists. 0x Prefix to denote a hexadecimal number. 0b Prefix to denote a binary number. REG[FIELD] Abbreviations or acronyms for registers or buffer descriptors appear in

uppercase text. Specific bits, fields, or numeric ranges appear in brackets. For

example, ICR[INIT] refers to the Force Initialization bit in the host Interface

Control Register.

ACTIVE HIGH SIGNALS

ACTIVE LOW SIGNALS

Names of active high signals appear in sans serif capital letters, as follows:

TT[04], TSIZ[0–3], and DP[0–7].

Signal names of active low signals appear in sans serif capital letters with an

overbar, as follows:

DBG, AACK, and EXT_BG[2].

x A lowercase italicized x in a register or signal name indicates that there are

multiple registers or signals with this name. For example, BRCGx refers to

BRCG[1–8], and MxMR refers to the MAMR/MBMR/MCMR registers.

On the MSC8113 device, the SC140 cores are 16-bit DSP processors. The following table shows the SC140 assembly language data types. For details, see the StarCore SC140 DSP Core Reference Manual (MNSC140CORE/D).

Name SC140

Byte/Octet 8 bits

Half Word 8 bits

Word 16 bits

Long/Long Word/2 Words 32 bits

Quad Word/4 Words 64 bits

The following table lists the SC140 C language data types recognized by the StarCore C compiler. For details, see the StarCore SC100 C Compiler User’s Manual (MNSC100CC/D).

Name Size

char/unsigned char 8 bits short/unsigned short 16 bits int/unsigned int 16 bits

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Name Size

fractional short 16 bits long/unsigned long 32 bits fractional long 32 bits pointer 32 bits

Conventions for Registers

The Programming Model section of each chapter includes a register bit table for each register in that module, as well as a table describing each bit in the register. The register bit table not only shows the names and positions of the bits/bit fields but also their reset value, value after boot, and their type (Read/Write). For registers that are not changed by the system boot, no boot line is listed. The register address is shown with the register name and mnemonic. Reserved bits/fields are indicated with a long dash (—). In the PPC_ALRH shown below, all of the bits are read/write (R/W). Other registers may include read-only (R) and write-only (W) bits. Notice that the most significant bit (MSB) is 0, or little-endian order.

PPC_ALRH System Bus Arbitration-Level Register

Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Priority Field 0 Priority Field 1 Priority Field 2 Priority Field 3

Type R/W

Reset 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 0

Boot 1 1 0 1 1 0 1 0 0 1 0 1 0 1 0 0

Bit16171819202122232425262728293031

Priority Field 4 Priority Field 5 Priority Field 6 Priority Field 7

Type R/W

Reset 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 1

Boot 0 1 1 1 1 0 0 0 1 0 0 1 1 1 1 0

Organization

Following is a summary and a brief description of the chapters of this manual:

 Chapter 1, MSC8113 Overview. Features, descriptive overview of main modules,

configurations, and application examples.

 Chapter 2, SC140 Core Overview. Target markets, features, overview of development

tools, descriptive overview of main modules.

 Chapter 3, External Signals. Identifies the external signals, lists signal groupings,

including the number of signal connections in each group, and describes each signal within a functional group.

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 Chapter 4, System Interface Unit (SIU). Describes the modules and functions of the

SIU, which controls system start-up and initialization as well as operation, protection, and the external 60x-compatible system bus.

 Chapter 5, Reset. Covers reset sources, causes, and configurations; gives examples of

different reset configuration scenarios, including systems with multiple MSC8113s.

 Chapter 6, Boot Program. Describes the bootloader program, which loads and executes

source code that initializes the MSC8113 after it completes a reset sequence and programs its registers for the required mode of operation. This chapter covers selection of bootloader modes, normal sequence of events for bootloading a source program, and booting in a multi-processor environment.

 Chapter 7, Clocks. Contains an overview of the MSC8113 clock module. For complete

clock information, refer to the MSC8113 Technical Data sheet. The data sheet is available in PDF format on the Freescale web site listed on the back cover of this manual.

 Chapter 8, Memory Map. Defines the address spaces for all MSC8113 modules; includes

cross references to all registers discussed.

 Chapter 9, Extended Core. Describes the structure of the extended core, which includes

the SC140 core, its internal memory (M1), the extended QBus structure (EQBS), the Instruction Cache (ICache), the programmable interrupt controller (PIC), and the local interrupt controller (LIC).

 Chapter 10, MQBus and M2 Memory. Describes how the MQBus supports a multi-core

environment by allowing all three SC140 cores to share the M2 memory through the MQBus. The MQBus ensures a low miss ratio for SC140 ICache accesses.

 Chapter 11, SQBus. Explains the structure and function of the SQBus, which is available

to all SC140 cores to fetch program code from external memory on the system bus.

 Chapter 12, Memory Controller. Covers the features and basic architecture of the

memory controller, which is part of the system interface unit (SIU). The memory controller provides an interface to internal DSP memory and DSP peripherals residing on the internal local bus and also to external memory and peripheral devices on the external 60x-compatible system bus. In addition to features and basic architecture, this chapter extensively covers the three basic machines that compose the memory controller: synchronous DRAM machine (SDRAM), general-purpose chip-select machine (GPCM), and the user-programmable machines (UPMs).

 Chapter 13, System Bus. Discusses the system bus, which is a 60x-compatible bus that

provides flexible support for the on-chip SC140 cores as well as other internal and external 60x-compatible bus masters.

 Chapter 14, Direct Slave Interface (DSI). Discusses the DSI host interface, which is a

32/64-bit wide, full-duplex, double-buffered, parallel port that can directly connect to the data bus of a host processor. The DSI supports a variety of buses and provides glueless connection with a number of industry-standard microcomputers, microprocessors, and DSPs.

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 Chapter 15, Hardware Semaphores. Describes the function and programming of the

hardware semaphores, which control resource sharing.

 Chapter 16, Direct Memory Access (DMA) Controller. Describes the different DMA

operating modes, transfer types, and buffer types. The chapter also gives procedures for programming different types of transfers. The multi-channel DMA controller includes hardware support for up to 16 time-multiplexed channels including buffer alignment, connects to both the system bus and the local bus, and functions as a bridge between both buses. The DMA controller supports flyby transactions on either bus. and enables hot swaps between channels, by using time-multiplexed channels that impose no cost in clock cycles.

 Chapter 17, Interrupt Processing. Discusses the three interrupt controllers that provide

maximum flexibility in handling MSC8113 interrupts, enabling interrupts to be handled by the SC140 core internally, by an external host, or by a combination of the two; also discusses source priority schemes.

 Chapter 18, Debugging. Includes aspects of the JTAG implementation that are specific

to the SC140 and should be used with the supporting IEEE® Std. 1149.1™ documentation. The discussion covers the items that the standard requires to be defined and provides additional information specific to the MSC8113 implementation.

 Chapter 19, Internal Peripheral Bus (IPBus). Describes the internal peripheral buss

(IPBus), the devices that connect to it, energy management capabilities for devices on the bus (Stop modes), and the programming model.

 Chapter 20, TDM Interface. Describes the four TDM interfaces. Each can handle up to

256 channels. The interfaces support the serial bus rate and format for most standard TDM buses, including T1 and E1 highways, pulse-code modulation (PCM) highway, and the ISDN buses in both basic and primary rates.

 Chapter 21, UART. Describes the UART interface, which is a full-duplex serial port

used to communicate with other devices.

 Chapter 22, Timers Discusses the 32 identical 16-bit general-purpose timers residing in

two timer modules (A and B) that each have their set of configuration registers.

 Chapter 23, GPIO. Discusses the thirty-two GPIO signals. Each pin is multiplexed with

a TDM, UART, or timer signal and can be configured as an input or output or a dedicated peripheral pin. Part of the pins can be configured as open-drain (that is, the pin can be configured in a wired-OR configuration on the board). The pin drives a zero voltage but tri-states when driving a high voltage.

 Chapter 24, I²C Software Module. Describes the I

C interface. which allows the

MSC8113 to boot from a serial EEPROM device.

 Chapter 25, Ethernet Controller. Discusses the Ethernet controller, which supports three

modes of operation: MII, RMII, and SMII.

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 Appendixes:

— Appendix A, Programming Reference. — Appendix B, MSC8113 Dictionary. — Appendix C, MSC8113 Boot Code.

MSC8113 Overview 1

The MSC8113 device is a highly integrated DSP that combines three StarCore SC140 cores with large internal memory spaces, an extended core, and several industry-standard peripherals and external interfaces to target highly computational DSP network and communication applications. The device is optimized for high-bandwidth wireless transcoding and a high-density packet telephony DSP farm, as well as high-bandwidth base station applications. The MSC8113 delivers enhanced performance while maintaining low power dissipation and greatly reducing overall system cost.

Each SC140 core has four ALUs that provide performance of up to 1600 DSP million multiply and accumulate commands per second (MMACS) using an internal 400 MHz clock. The MSC8113 three-core device therefore delivers a total performance of up to 4800 DSP MMACS.

Each core is part of an extended core that includes a level-1 224 KB internal memory (M1) for program and data storage, a 16 KB 16-way instruction cache (ICache), a fetch unit for the ICache, and a 4-entry write buffer queue for boosting core performance. Each extended core also includes a programmable interrupt controller (PIC), a local interrupt controller (LIC), and debugging registers in an Enhanced On-Chip Emulation (EOnCE) module and JTAG TAP controller. All the extended cores share an internal 476 KB level-2 memory (M2) and a general interrupt controller (GIC).

The external interfaces and peripherals include a system and local bus managed by a system interface unit (SIU) and memory controller, a 32/64-bit direct slave interface (DSI) port, four 256-channel TDM interfaces, a serial universal asynchronous receiver/transmitter (UART),

timers, an Ethernet interface that can operate in any of three modes (MII, RMII, or SMII), an I

C interface to allow booting from a serial EEPROM, and general-purpose input/output (GPIO) ports.The MSC8113 device is backward-compatible with the MSC8102; that is, it can replace a MSC8102 device and execute the same code with no modifications.

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MSC8113 Overview

1.1 Features

The tables in this section list the features of the MSC8113 device.

Table 1-1. Extended SC140 Cores and Core Memories

Feature Description

Three SC140 cores:

• Up to 4800 MMACS using 12 ALUs running at up to 400 MHz.

• A total of 1196 KB of internal SRAM (224 KB per core). Each SC140 core provides the following:

• Up to 1600 MMACS using an internal 400 MHz clock. A MAC operation includes a multiply-accumulate command with the associated data move and pointer update.

• 4 ALUs per SC140 core.

SC140 Core

Extended Core

Multi-Core Shared Memories

M2-Accessible Multi-Core Bus

(MQBus)

• 16 data registers, 40 bits each.

• 27 address registers, 32 bits each.

• Hardware support for fractional and integer data types.

• Very rich 16-bit wide orthogonal instruction set.

• Up to six instructions executed in a single clock cycle.

• Variable-length execution set (VLES) that can be optimized for code density and performance.

• IEEE Std. 1149.1 JTAG port.

• Enhanced on-device emulation (EOnCE) with real-time debugging capabilities.

Each SC140 core is embedded within an extended core that provides the following:

• 224 KB M1 memory that is accessed by the SC140 core with zero wait states.

• Support for atomic accesses to the M1 memory.

• 16 KB instruction cache, 16 ways.

• A four-entry write buffer that frees the SC140 core from waiting for a write access to finish.

• External cache support by as sertin g the glob al signal (G BL) whe n predefined memory banks are accessed.

• Programmable Interrupt Controller (PIC).

• Local Interrupt Controller (LIC).

• M2 memory (shared memory):

− A 476 KB memory working at the core frequency.

− Accessible from the local bus

− Accessible from all three SC140 cores using the MQBus.

• 4 KB bootstrap ROM.

• A QBus protocol multi-master bus connecting the three SC140 cores to the M2 memory.

• Data bus access of up to 128-bit read and up to 64-bit write.

• Operation at the SC140 core frequency.

• A central efficient round-robin arbiter controlling SC140 core access on the MQBus.

• Atomic operation control of access to M2 memory by the three SC140 cores and the local bus.

Table 1-2. Phase-Lock Loop (PLL)

Feature Description

• Generates up to 500 MHz core clock and up to 166 MHz bus clocks for the

Internal PLL

1-2 Freescale Semiconductor

60x-compatible local and system buses and other modules.

• PLL values are determined at reset based on configuration signal values.

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Feature Description

System Bus

Direct Slave Interface (DSI)

3-Mode Signal Multiplexing

Memory Controller

Features

Table 1-3. Buses and Memory Controller

• 64/32-bit data and 32-bit address 60x bus.

• Support for multiple-master designs.

• Four-beat burst transfers (eight-beat in 32-bit wide mode).

• Port size of 64, 32, 16, and 8 controlled by the internal memory controller.

• Bus can access externa l memo ry expa nsion or off-dev ice p eriphera ls, or it can ena ble an external host device to access internal resources.

• Slave support, direct acces s by an external host to interna l resources inc luding the M 1 and M2 memories.

• On-device arbitration betwe en up to four master dev ic es .

A 32/64-bit wide slave host interface that operates only as a slave device under the control o f an external host processor.

• 21–25 bit address, 32/64-bit data.

• Direct access by an external host to internal resources, including the M1 and the M2 memories as well as external devic es on the system bus.

• Synchronous and asynch rono us acce ss es , with burst ca pab ili ty in the sy nc hron ous mode.

• Dual or Single strobe modes.

• Write and read buffers improve host bandwidth.

• Byte enable signals enables 1, 2, 4, and 8 byte write access granularity.

• Sliding window mode enables access with reduced number of address pins.

• Chip ID decoding enables using one CS

• Broadcast CS

• Big-endian, little-endian, and munged little-endian support.

• 64-bit DSI and 32-bit system bus.

• 32-bit DSI and 64-bit system bus.

• 32-bit DSI and 32-bit system bus.

Flexible eight-bank memory controller:

• Three user-programmable machines (UPMs), general-purpose chip-select machine (GPCM), and a page-mode SDRAM machine

• Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash memory, and other user-definable peripherals.

• Byte enables for either 64 -bit or 32-bit bus width mode.

• Eight external memory banks (banks 0–7). Two additional memory banks (banks 9,

11) control IPBus peripherals and internal memories. Each bank has the following features:

− 32-bit address decoding with programmable mask.

− Variable block sizes (32 KB to 4 GB).

− Selectable memory controller machine.

− Two types of data errors check/correction: normal odd/even parity and

read-modify-write (RMW) odd/even parity for single accesses.

− Write-protection capability.

− Control signal generation machine selection on a per-bank basis.

− Support for internal or external masters on the system bus.

− Data buffer controls activated on a per-bank basis.

− Atomic operation.

− RMW data parity check (on system bus only).

− Extensive external memory-controller/bus-slave support.

− Parity byte select pin, which enables a fast, glueless connection to

RMW-parity devices (on system bus only).

− Data pipeline to reduce data set-up time for synchronous devices.

signal enables parallel write to multiple DSPs.

signal for multiple DSPs.

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MSC8113 Overview

Feature Description

Multi-Channel DMA Controller

Feature Description

Time-Division Multiplexing

(TDM)

Table 1-4. DMA Controller

• 16 time-multiplexed unidirectional channels.

• Services up to four external peripherals.

• Supports DONE

• Each channel group services 16 internal requests generated by eight internal FIFOs. Each FIFO generates:

− A watermark request to indicate that the FIFO contains data for the DMA to empty and write to the destination.

− A hungry request to indicate that the FIFO can accept more data.

• Priority-based time-multiplexing between channels using 16 internal priority levels.

• Round-robin time-multiplexing between channels.

• A flexible channel configuration:

− All channels support all features.

− All channels connect to the system bus or local bus.

• Flyby transfers in which a single data access is transferred directly from the source to the destination without using a DMA FIFO.

or DRACK protocol on two external peripherals.

Table 1-5. Serial Interfaces

Up to four independent TDM modules, each with the following features:

• Optional operating configurations:

− Totally independent receiv e and t ransmi t chan nels, each h aving one data li ne, one clock line, and one frame sync line

− Four data lines with one cl ock an d o ne fr ame sync shared among the transmit and receive lines.

− Glueless interface to E1/T1 framers and switches, as well as to common buses, such as the ST-BUS.

• Hardware A-law/μ-law conversion

• Up to 62.5 Mbps per TDM (62.5 MHz bit clock if one data line is used, 31.25 MHz if two data lines are used, 15.625 MHz if four data lines are used).

• Up to 256 channels.

• Up to 16 MB per channel buffer (granularity 8 bytes), where A/μ law buffer size is double (granularity 16 byte).

• Receive buffers share one global write offset pointer that is written to the same offset relative to their start address.

• Transmit buffers share o ne g lo bal rea d offset pointer that is read from the same off set relative to their start address.

• All channels share the same word size.

• Two programmable receive and two programmable transmit threshold levels with interrupt generation that can be used, for example, to implement double buffering.

• Each channel can be programmed to be active or inactive.

• 2-, 4-, 8-, or 16-bit channels are stored in the internal memory as 2-, 4-, 8-, or 16-bit channels, respectively.

• The TDM Transmitter Sync Signal (TxTSYN) can be configured as either input or output.

• Frame Sync and Data signals can be programmed to be sampled either on the rising edge or on the falling edge of the clock.

• Frame sync can be programmed as active low or active high.

• Selectable delay (0–3 bits) between the Frame Sync signal and the beginning of the frame.

• MSB or LSB first support.

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Feature Description

UART

General-Purpose I/O (GPIO)

port

C Software Module

Features

Table 1-5. Serial Interfaces (Continued)

• Two signals for transmit data and receive data.

• No clock, asynchronous mode.

• Can be serviced either by the SC 140 DSP core s or an ex ternal host o n the syst em bus or the DSI.

• Full-duplex operation.

• Standard mark/space non-return-to-zero (NRZ) format.

• 13-bit baud rate selection.

• Programmable 8-bit or 9-bit data format.

• Separately enabled transmitter and receiver.

• Programmable transmitter output polarity.

• Two receiver wake-up methods:

− Idle line wake-up.

− Address mark wake-up.

• Separate receiver and transmitter interrupt requests.

• Eight flags, the first five can generate interrupt request:

− Transmitter empty.

− Transmission complete.

− Receiver full.

− Idle receiver input.

− Receiver overrun.

− Noise error.

− Framing error.

− Parity error.

• Receiver framing error detection.

• Hardware parity checking.

• 1/16 bit-time noise detection.

• Maximum bit rate 6.25 Mbps.

• Single-wire and loop operations.

• 32 bidirectional signal lines that either serve the peripherals or act as programmable I/O ports.

• Each port can be programmed separately to serve up to two dedicated peripherals, and each port supports open-drain output mode.

• Supports booting from a serial EEPROM

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MSC8113 Overview

Feature Description

Ethernet Controller

Table 1-5. Serial Interfaces (Continued)

• Designed to comply with IEEE Std. 802.3™, 802.3u™, 802.3x™, and 802.3ac™

• Three Ethernet physical interfaces:

− 10/100 Mbps IEEE Std. 802.3 MII.

− 10/100 Mbps RMII.

− 10/100 Mbps SMII.

• Full and half-duplex support.

• IEEE Std. 802.3® full-duplex flow control (automatic PAUSE frame generation or software programmed PAUSE frame generation and recogniti on ).

• Support of out-of-sequence transmit queue (for initiating flow-control).

• Programmable maximum frame length supports jumbo frames (up to 9.6k) and IEEE Std. 802.1™ virtual local area network (VLAN) tags and priority.

• Retransmission from transmit FIFO following a collision.

• CRC generation and verification of inbound/outbound packets.

• Address r ecognition:

− Each exact match can be programmed to be accepted or rejected.

− Broadcast address (accept/reject).

− Exact match 48-bit individual (unicast) address.

− Hash (256-bit hash) check of individual (unicast) addresses.

− Hash (256-bit hash) check of group (multicast) addresses.

− Promiscuous mode.

• Pattern matching:

− Up to 16 unique 4-byte patterns.

− Pattern match on bit-basis.

− Matching range up to 256 bytes deep into the frame.

− Offsets to a maximum of 252 bytes.

− Programmable pattern size in 4-byte increments up to 64 bytes.

− Accept or reject frames if a match is detected.

− Up to eight unicast addresses for exact matches.

− Pattern matching accepts/rejects IP addresses.

• Filing of receive frames based on pattern match; prioritization of frames.

• Insertion with expansion or replacement for transmit frames; VLAN tag insertion.

• RMON statistics.

• Master DMA on the local bus for fetching descriptors and accessing the buffers.

• Ethernet PHY can be exposed either on GPIO pins or on the high ms bits of the DSI/system when the DSI and the system bus are both 32 bits.

• MPC8260(PQ2) 8 byte width buffer descriptor mode as well as 32 byte width buffer descriptor mode.

• MII Bridge (MIIGSK):

− Programmable selection of the 50 MHz RMII reference clock source (external or internal).

− Independent 2 bit wide transmit and receive data paths .

− Six operating modes.

− Four general-purpose control signals.

− Programmable transmitted inter-frame bits to support inter-frame gap for

frames in the SMII domain.

• SMII features:

− Convey complete MII information between the PHY and MAC.

− Allow direct MAC-to-MAC communication in SMII mode.

− Can generate an interrupt request line while receiving inter-frame segments.

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Feature Description

Timers

Hardware Semaphores

Global Interrupt Controller

(GIC)

Feature Description

Reduced Power Dissipation

Packaging

Features

Table 1-6. Miscellaneous Modules

Two modules of 16 timers each. Each timer has the following features:

• Cyclic or one-shot.

• Input clock polarity control.

• Interrupt request when counting reaches a programmed threshold.

• Pulse or level interrupts.

• Dynamically updated programmed threshold.

• Read counter any time.

Watchdog mode for the timers that connect to the device. Eight coded hardware semaphores, locked by simple write access without need for

read-modify-write mechanism.

• Consolidation of chip maskable interrupt and non-maskable interrupt sources and routing to INT_OUT

• Generation of 32 virtual interrupts (eight to each SC140 core) by a simple write access.

• Generation of virtual NMI

, NMI_OUT, and to the cores.

(one to each SC140 core) by a simple write access.

Table 1-7. Power and Packaging

• Low power CMOS design.

• Separate power supply for internal logic and I/O.

• Low-power standby modes.

• Optimized power ma nagemen t circuitry (i nstruc tion-depen dent, perip heral-depe ndent, and mode-dependent).

• 0.8 mm pitch High Temperature Coeff icient for Ex pansi on Flip-Ch ip Ceram ic Ball-G rid Array (CBGA (HCTE)).

• 431-connection (ball).

• 20 mm × 20 mm.

Feature Description

Real-Time Operating System

(RTOS)

Multi-Core Support

Distributed System Support

Table 1-8. Software Support

The Real-Time Operating Syst em (RTOS) ful ly sup por ts de vice architecture (multi-core, memory hierarchy, ICache, timers, DMA controller, interrupts, peripherals), as follows:

• High-performance and deterministic, delivering predictive response time.

• Optimized to provide low interrupt latency with high data throughput.

• Preemptive and priority-based multitasking.

• Fully interrupt/event driven.

• Small memory footprint.

• Comprehensive set of APIs.

• Use of one instance of kernel code in all three SC140 cores.

• Dynamic and static memory allocation from local memory (M1) and shared memory (M2).

Enables transparent int er-task comm unicatio ns betwee n tasks runnin g insi de the SC140 cores and the other tasks running in on-board de vices or remote network devices:

• Messaging mechanism between tasks using mailboxes and semaphores.

• Networking support; data tra nsfer between tasks running ins ide and outside the device using networking protocols.

• Includes integrated device drivers for such peripherals as TDM, UART, and external buses.

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MSC8113 Overview

Feature Description

Additional Features

Boot Options

Table 1-8. Software Support (Continued)

• Incorporates task debugging utilities integrated with compilers and vendors.

• Board support package (BSP) for the application development system (ADS).

• Integrated Development Environment (IDE):

− C/C++ compiler with in-line assembly. Enables the developer to generate highly optimized DSP code. It translates code written in C/C++ into parallel fetch sets and maintains high code density.

− Librarian. Enables the user to create libraries for modularity.

− C libraries. A collection of C/C++ functions for the developer’s use.

− Linker. Highly efficient linker to produce executables from object code.

− Debugger. Seamlessly integrated real-time, non-intrusive multi-mode

debugger that enables debugging of highly optimized DSP algorithms. The developer can choose to debug in source code, assembly code, or mixed mode.

− Simulator. Device simulation mo del s, ena ble s des ig n and sim ul atio n befo re the hardware arrival.

− Profiler. An analysis tool using a patented Binary Code Instrumentation (BCI) technique that enables the developer to identify program design inefficiencies.

− Version control. CodeWarrior™ includes plug-ins for ClearCase, Visual SourceSafe, and CVS.

• External memory.

• External host.

•UART.

•TDM.

•I

Table 1-9. Application Development System (ADS) Board

Feature Description

• Host debug through single JTAG connector supports both processors.

• MSC8103 as the MSC8113 host with both devices on the board. The MSC8103 system bus connects to the MSC8113 DSI.

• Flash memory for stand-alone applications.

• Communications ports:

− 10/100Base-T.

− 155 Mbps ATM over Optical.

MSC8113ADS

− T1/E1 TDM interface.

− H.110.

− Voice codec.

− RS-232.

− High-density (MICTOR) logic analyzer connectors to monitor MSC8113

signals

− 6U cPCI form factor.

• Emulates MSC8113 DSP farm by connecting to three other ADS boards.

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Architecture

1.2 Architecture

Figure 1-1 shows the MSC8113 block diagram. Note that the arrows on the buses describe the direction of the address flow; an arrow points from the master of the bus to the slave(s).

Extended Core

MQBus

Boot

ROM

PLL/Clock JTAG Port

SC140

System

Interface

476 KB

RAM

PLL

JTAG

SC140

Extended Core

SQBus

Banks 9, 11

Local Bus

DMA

Controller

Internal System Bus

Memory

Controller

Bridge

128

IP Master

IPBus

SC140

Extended Core

128

SIU

Registers

Local Bus

GIC

32 Timers

UART

4 TDMs

8 Hardware

Semaphores

10/100

Ethernet

Controller

Direct

Slave

Interface

(DSI)

Memory

Controller

Banks 0–7

SC140

Extended Core

Interrupts

RS-232

GPIO

(I2C)

MII/RMII/SMII

MII/RMII

DSI Port

32/64

System Bus

32/64

Figure 1-1. MSC8113 Block Diagram

Data is transferred to the MSC8113 device from either the system bus port, the DSI, the Ethernet, the TDM, the Ethernet interface. The SC140 core processes the data in the buffers and the result is transferred back to one of the ports.

The MSC8113 architecture is optimized so that applications can efficiently use the available 4800 MMACS for the three SC140 cores. For most applications:

 The data is accessed for a bounded number of times while the critical code is run in loops

for many cycles. DSP applications have a high degree of code locality and a low degree of data locality.

 Different channels can share code but do not share data.  A small portion of the code is run for most of the time (the “20–80” rule).

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MSC8113 Overview

Since the instructions can be shared, a typical application stores them in the shared memory, M2. Since each DSP core typically spends most of the time running loops of selected routines, these routines can be stored either in the local M1 memory or automatically fetched to the local cache. Achieving high hit ratios on the cache prevents core stalls and thus boosts overall performance. During a miss, instructions are fetched from the M2 memory through the MQBus. Since the miss ratio is very low, the probability of a collision with another SC140 core on the MQBus is low. Therefore, the overall fetch latency is low. Since different channels do not typically share data, the data can be located in the local M1 memory. The architecture is flexible enough to enable storage of data in M2 as well. In fact, the powerful DMA can perform data overlays between the M2 and the M1 memories or between the M1 memory of one SC140 core to the M1 memory of another SC140 core. For example, while performing channel N, the DMA controller can bring in the data needed for channel N+1. To achieve the best transfer rate, these DMA transfers can be programmed as flyby transfers, also called “single access transactions.” For a flyby transfer, the data path is between a peripheral and memory with the same port size, located on the same bus. Flyby transactions can occur only between external peripherals and external memories located on the system bus, between internal peripherals and internal SRAM located on the local bus, and between internal memories.

The SC140 core accesses the M2 memory through the MQBus. All accesses to other internal peripherals and accesses external to the MSC8113 occur on a separate bus, the SQBus. This separation ensures that the latencies for SC140 core accesses to the M2 memory remain as low as possible. Write accesses with high latencies are typically routed through the write buffer. The write buffer can store the write access, release the SC140 core, and execute it at a later time.

The SC140 cores should be focused on the intensive computational work and should not have to deal with bringing new data buffers. Data can be prepared in the M1 (or M2) memory in a “next” buffer while the SC140 core processes the ‘current’ buffer. The SC140 core can use the flexible DMA controller to transfer large blocks of data from the external memory to the internal memory and also between the internal memories. In some applications, data is written from an external host directly to the MSC8113 M1 and M2 memories through the DSI interface while the SC140 handles the computational work in parallel.

Note: For details on the SC140 core, see Chapter 2, SC140 Core Overview.

1.2.1 Extended Core

The extended core contains the SC140 core, its M1 memory, an instruction cache, a write buffer, a programmable interrupt controller (PIC), a local interrupt controller (LIC) and interfaces to the MQBus and the SQBus through which accesses are performed to addresses outside the extended core. See Figure 1-2.

Note: Details on extended core functionality are in Chapter 9, Extended Core.

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SC140 Core

EOnCE™

Xa Xb

QBus

Notes: 1. The arrows show the data transfer direction.

2. The QBus interface includes a bus switch, write buffer, fetch unit, and a

128

Instruction

Cache

128

PIC

IRQs

LIC

IRQs

MQBus

SQBus

Local Bus

controller that defines four QBus banks.

QBus

Bank1

IRQs

QBus

Bank3

RAM

Figure 1-2. MSC8113 SC140 Extended Core

QBC

EQBS

128

1.2.1.1 SC140 Core

The SC140 core is a flexible, programmable DSP core that handles compute-intensive communications applications, providing high performance, low power, and code density. It efficiently deploys a novel variable-length execution set (VLES), attaining maximum parallelism by allowing multiple address generation and data arithmetic logic units to execute multiple operations in a single clock cycle. The SC140 core contains four ALU units, each with a 16-bit × 16-bit MAC that results in a 40-bit wide and 40-bit parallel barrel shifter. Each ALU performs one MAC operation per clock cycle, so a single core running at 400 MHz can perform 1600 MMACS. Having three such cores, the MSC8113 can perform up to 4800 MMACS per second. An address generation unit includes two address arithmetic units and one bit mask unit. There are also 16 address registers, of which eight can serve as base address registers.

The main reason for the high code density of the SC140 is that all instructions are 16 bits wide. During each clock cycle, the SC140 core reads eight instruction words, referred to as a fetch set. The SC140 core identifies which instructions can be performed in parallel and runs them on the ALUs and address generation units. In one clock cycle, up to six instructions, four ALU operations, and two address generation operations can be performed. In the rich instruction set, special attention is given to control code, making the SC140 core ideal for applications embedding DSP and communications. Arithmetic operations are performed using both fractional and integer data types, enabling the user to choose a style of code development or use coding techniques derived from an application-specific standard. The programming model of the SC140 core is highly orthogonal, and both data and instructions reside in one unified memory. The

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powerful SC140 compiler translates code written in C/C++ into parallel fetch sets and maintains high code density and/or high performance by taking advantage of the core high code orthogonality and unified memory architecture. For details, see the SC140 DSP Core Reference Manual, MNSC140CORERM/D.

Note: For details, see Chapter 2, SC140 Core Overview.

1.2.1.2 M1 Memory

The 224 KB M1 memory can be accessed with zero wait states from the SC140 core. Three accesses are performed concurrently on every SC140 core clock cycle. The SC140 core accesses one 128-bit instruction fetch set and two 64-bit data words. In addition, an external host or the DMA controller can access a 64-bit word through the local bus at the bus clock rate. To reduce the size of the memory, M1 is a single-access memory and is hierarchically divided so that four accesses can be performed in parallel. An intelligent memory allocation significantly decreases the probability of collisions between an SC140 core bus and the DMA bus. For example, two accesses cannot collide if they belong to different 32 KB memory groups, which is usually the case since program code is stored in a different group than the data space of the program. The DMA stores the “next” buffers in yet a different group. Even in the same group, if two data elements are placed on a different 4 KB module, a collision between two SC140 core buses is prevented. When a collision does occur, the SC140 core stalls for one clock cycle. The overall memory size available for one SC140 core in both M1 and M2 memories and the partition between the memories is carefully designed as a trade-off between chip size and the memory requirements imposed by the bandwidth of the SC140 core. Typically the M1 memory contains critical routines and most of the channel data.

Note: For details, see Section 9.2, Extended Core Memory (M1), on page 9-3.

1.2.1.3 Instruction Cache

The instruction cache is highly optimized for real-time DSP applications and minimizes miss ratios, latencies, bus bandwidth requirements, and silicon area. The 16 KB instruction cache is 16-way set associative. Figure 1-3 illustrates its logic structure and demonstrates how an address is mapped to this structure. Each of the 16 ways contains four 256-byte lines and is divided into 16 fetch sets, each with an associated valid bit. The 2-bit index field of the address serves as an index to the line within the way. The line whose tag matches the tag field of the address is the selected line.

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31 0347

TAG

98 Index

Figure 1-3. Mapping an Address to the Instruction Cache

Fetch Set#

TAG

Address

Valid bits Line

256 bytesone per fetch set

Way0; Index0 Way0; Index1 Way0; Index2 Way0; Index3 Way1; Index0 Way1; Index1 Way1; Index2 Way1; Index3

Way15; Index0 Way15; Index1 Way15; Index2 Way15; Index3

When a cache miss occurs, the new data is fetched in bursts of 1, 2, or 4 fetch sets. There is also an option to fetch until the end of the line. This option, referred to as pre-fetch, takes advantage of the spatial locality of the code. When there is a need to fetch new data to the cache and the cache is full, one of the lines of the cache is thrashed using the least recently used (LRU) algorithm. The cache can be programmed so that only part of it is thrashed. For example, suppose task A needs to be preempted in favor of task B. While task B runs, the instructions of task A are thrashed from the instruction cache. When task B finishes and task A takes over, task A may not find its most recently used instructions in the cache. To prevent such a situation and thus keep task A’s most recently used instructions in the cache, the operating system can exclude the ways of task A from the part of the cache that can be thrashed. Another method of guaranteeing that the critical routines are always available for a task is to store them in the SC140 core M1 private memory. All the cache entries are flushed by issuing a cache flush command from the SC140 core, which is useful, for example, when new code is written to lines in the M2 memory that are already cached. The ICache has run-time debug support. A counter in the Emulation and Debug (EOnCE) module is incremented for cache hits and misses. When the SC140 core is in Debug mode, its fetch unit is in Debug mode and all the cache arrays can be read.

Note: For details, see Section 9.4, Instruction Cache (ICache).

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1.2.1.4 QBus System

The QBC is a bus controller that handles internal memory contentions. It snoops the activity on the buses connected to the internal memory and freezes the SC140 core and address bus activity. It creates the atomic instruction acknowledge to the SC140 core during the reservation process. The EQBS enables the SC140 core to communicate with external devices efficiently. It handles the switching between the three core buses and the QBus. SC140 core accesses that apply to memory space above the internal memory (QBus Base Line = 0x00F00000) are transferred to the QBus through the EQBS. The EQBS also connects to the instruction cache and initiates requests for cache updates in order to improve the hit ratio. The EQBS operates at the same frequency as the SC140 core. The module handles the SC140 core and the instruction cache requests, bringing the data on the QBus. As Figure 1-4 shows, the EQBS consists of a bus switch to handle data read operations, a write buffer to handle data write operations, a fetch unit to handle all program read operations, a control unit, and the banks to handle the communication with the slaves and all EQBS registers.

EQBS

Registers

Banks

Bus Switch

QBus

EQBS

Control

Unit

128

Multiplexer

Write Buffer

128

Multiplex

Fetch Unit

Figure 1-4. EQBS Block Diagram

ICache

Valid

Array

Tag

Array

P-Bus

XA-Bus XB-Bus

Data

Address

I-Cache

Memory

Note: For details, see Section 9.4, Instruction Cache (ICache), on page 9-24. The QBus masters are the fetch unit, write buffer, and bus switch. The control unit is the arbiter

for the QBus masters.The bus switch handles all data read above the QBus baseline, write operations when the write buffer is disabled, and atomic (read modify write) write operations. Read accesses of program (fetch) that are above the QBus baseline occur through the fetch unit.

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This unit is triggered by a cache “miss” access. It brings the data into the SC140 core and continues to update the cache until the end of the cache line or until a new “miss” is accepted. This improves the overall performance of the cache in the system. The fetch unit initiates cache update requests for data of consecutive addresses after every “miss.” The block and burst sizes are configurable. When the SC140 core writes to an external address (that is, to an address beyond the M1 memory), it can stall while waiting for the access to complete. To prevent such stalls, all the external accesses are first written to a write buffer. The write buffer releases the SC140 core and then completes the access. Located on the SC140 core buses, the write buffer is a zero wait state client and thus boosts the SC140 core performance. The write buffer is a four-entry FIFO that automatically handles data coherency problems. For example, if the write buffer contains data to be written to address A, and a read access occurs before the buffer completes the write access, the contents of the write buffer are written to the destination before the read can be executed. Not all writes beyond the M1 memory are routed through the write buffer. Write accesses do not use the write buffer in the following cases:

 The address of the destination belongs to a bank that is defined as immediate.  It is an atomic operation essentially writing to a semaphore.  The write buffer is disabled.

The write buffer counts the number of clocks that elapse between the time data is written to the write buffer and the time it is emptied. When the counter exceeds a pre-programmed value, the contents of the write buffer are flushed so that the time for the write accesses through the write buffer can be limited.

1.2.2 Power Saving Modes

The MSC8113 device is a low-power CMOS design. Also, you can put unused modules into power saving modes. The TDM, DSI, timers, GPIO, GIC, UART, and Ethernet controller can be put into Stop mode, in which their clocks are frozen as described in Section 19.10, Stop Options. Each of the extended cores can be put into either Stop or Wait mode.

1.2.2.1 Extended Core Wait Mode

An extended core enters Wait mode when it issues the wait instruction. In Wait mode, the SC140 core consumes minimal power because its clocks are frozen. The clocks of other modules inside the extended core do not stop, so the QBus, PIC, LIC, and MQBus and SQBus controllers are functional. The extended core exits Wait mode when there is an interrupt or a reset or when the MSC8113 device enters Debug mode by either a JTAG DEBUG_REQUEST command or assertion of

EE0.

Note: When multiple cores are in Wait mode, issuing a simultaneous virtual interrupt to all

these cores does not guarantee that the cores exit Wait mode on the same clock cycle.

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1.2.2.2 Extended Core Stop Mode

An extended core enters Stop mode when it issues the stop instruction. In Stop mode, the SC140 core and all the extended core peripherals except for the MQBus and SQBus controllers consume minimal power because their clocks are frozen. The extended core exits this mode when reset.

1.2.3 M2 Memory

The M2 is a 476 KB RAM and 4 KB ROM that is shared between the three SC140 cores. Up to 128 bits of data are accessed at up to 500 MHz. Each SC140 core treats the M2 as its secondary memory. Only one SC140 core can access this memory at a given time. When an SC140 core needs to access this memory, it arbitrates on the MQBus, and when access is granted it performs the access. The DMA controller or an external host can also access the M2 memory through the local bus. Enabling the DMA controller or an external host to write program and data directly to the M2 alleviates the load on the SC140 cores and keeps their focus on the intensive DSP processing. In a typical application that carefully considers memory allocation and uses the cache wisely, fewer SC140 core accesses occur to the M2 memory.

Note: For details, see Section 8.4, SQBus Address Space.

1.2.4 System Interface Unit (SIU)

The SIU is based on the MPC8260 SIU and is similar to the one used in the MSC8101. This unit controls the system bus and the internal local bus. It contains a flexible memory controller for accessing various memory devices both internally and externally. The SIU also controls the system start-up and initialization as well as operation and protection.

Note: For details, see Chapter 4, System Interface Unit (SIU).

1.2.4.1 60x-Compatible System Bus Interface

The system bus interface can function as a master in a multi-master environment. It runs at up to 166 MHz and supports 32-bit addressing, a 32/64-bit data bus, and burst operations that transfer up to 256 bits of data per burst. The 60x-compatible data bus is accessible in 8-bit, 16-bit, 32-bit, and 64-bit data widths. In 32-bit mode, the system bus supports accesses of 1–4 bytes, aligned or unaligned, on 4-byte (word) boundaries and 1–8 bytes, aligned or unaligned on 8-byte (double word) boundaries. The address and data buses support synchronous, one-level pipelined transactions and non-pipelined SRAM-like accesses. Various applications can use this bus interface—for example, a system in which the MSC8113 uses a shared external memory. An external host can directly access the device internal memories and peripherals because the system bus is bridged to the internal local bus where the memories and peripherals are located. At reset, the system bus can also be configured in a single bus master mode so that it can connect gluelessly to slaves, typically memory devices, using only the memory controller. This mode is useful when the SC140 cores use an external memory private to the MSC8113 device.

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Note: For details, see Chapter 13, System Bus.

1.2.4.2 Memory Controller

The memory controller controls up to 12 memory banks, four of which access internal modules (two of them reserved) and eight of which access external devices. These memory banks are shared by a high-performance SDRAM machine, a general-purpose chip-select machine (GPCM), and three user-programmable machines (UPMs). Internally, Bank 9 is assigned to the IPBus peripherals (four TDMs, DSI, UART, GPIO, GIC, HS, Ethernet controller, and Ethernet controller), and Bank 11 is assigned to the internal M1 and M2 memories. The memory controller supports a glueless interface to synchronous DRAM (SDRAM), SRAM, EPROM, flash EPROM, burstable RAM, regular DRAM devices, extended data output DRAM devices, and other peripherals. It allows the implementation of memory systems with very specific timing requirements. The SDRAM machine provides an interface to synchronous DRAMs using SDRAM pipelining, bank interleaving, and back-to-back page mode to achieve the highest performance. The GPCM provides interfacing for simpler, slow memory resources and memory-mapped devices. GPCM performance is inherently lower than that of the SDRAM machine because it does not support bursting. Therefore, GPCM-controlled banks are mainly used for boot-loading and access to low-performance memory-mapped peripherals. The UPMs support address multiplexing of the system bus and refresh timers as well as generation of programmable control signals for row address and column address strobes, providing a glueless interface to DRAMs, burstable SRAMs, and almost any other kind of peripheral. The refresh timers allow refresh cycles to be initiated. The UPM can generate different timing patterns for the control signals that govern a memory device. These patterns define how the external control signals behave during a read, write, burst-read, or burst-write access request. Also, refresh timers can periodically generate user-defined refresh cycles.

Note: For details, seeChapter 12, Memory Controller.

1.2.5 Direct Slave Interface (DSI)

The DSI gives an external host direct access to the MSC8113 internal and external memory space, including internal memories and the registers of internal modules as well as access to the system bus. When a 21-bit address is used, the DSI can access all the internal 2 MB address space as well as the system bus through a 32 KB sliding window. When more address bits (between 22 to 25 bit address) are used, the DSI can directly access the system bus. The DSI data bus is 32/64-bit wide and provides the following slave interfaces to an external host:

 Asynchronous interface (no clock reference) enabling the host single accesses.  Synchronous interface enabling host single or burst accesses of 256 bits (8 accesses of 32

bits or 4 accesses of 64 bits) with its external clock de-coupled from the internal bus clock.

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Supporting various interfaces flexibly, the DSI interfaces to most available processors in the market. The DSI write buffer stores the address and the data of the accesses until they are performed. The external host can therefore perform multiple writes without waiting for those accesses to complete. Latencies that are typical during accesses to internal memories are greatly reduced by the DSI read prefetch mechanism. An external host addresses up to 16 MSC8113 devices using a single chip-select by which the most significant bits on the address bus identify the addressed MSC8113 device. The host can also write the same data to multiple MSC8113 devices simultaneously by asserting a dedicated broadcast chip select. This can be proved useful during boot from DSI and also for 3G uplink processing where the same chip rate data is being processed differently in each and every MSC8113 slave device.

Note: For details, see Chapter 14, Direct Slave Interface (DSI).

1.2.6 Direct Memory Access (DMA) Controller

The multi-channel DMA controller connects to both the system bus and the local bus. Transfers on both buses can be performed in parallel. Transfers that occur on the same bus between clients with the same port size can use the flyby mode on which the data is read and written in the same cycle. Other transfers are dual accesses that occur in two phases so that data is first read to a DMA internal FIFO and then written from that FIFO. Eight internal DMA FIFOs support this mode. Flyby mode is used for data transfers between internal memories, all residing on the internal local bus. Table 1-10 lists the possible DMA transfers.

Table 1-10. DMA Transfers

DMA client DMA client Flyby

Internal memory Internal memory Memory device on the system bus.

Internal memory Peripheral on the system bus. Memory device on the system bus Peripheral on the system bus. Only if on the same bus with the

Memory devi ce on the system bus Memory device on the system bus. Peripheral on the system bus Peripheral on the system bus.

Notes: 1. Source internal memory is different than the destination internal memory.

2. Using start-address + a counter on the M1 memory.

3. Not recommended if Flyby is possible.

Internal memory

same port size.

—+ —+

The DMA controller receives requests from the following clients:

 8 requests from each flyby counter of each SC140 core.  4 requests from clients external to the MSC8113 device.

Through

FIFO in the

DMA

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DMA requests are tied to up to 16 DMA channels that run concurrently. Each channel is programmed as either flyby or dual-access. The arbitration algorithm can be priority-based using 16 priority levels or round-robin-based. All clients connect to the DMA controller through the

DREQ and DACK signals. A client uses the DREQ signal to request a DMA data transfer. This signal

can be either level or edge. The DMA controller asserts the access. The DMA controller asserts The bidirectional

DONE signal indicates that the channel must be terminated. The DMA supports

DRACK to indicate that it has sampled the peripheral request.

DACK signal to perform the data

a flexible buffer configuration, including: simple buffers, cyclic buffers, single-address buffers (I/O device), incremental address buffers, chained buffers, and complex buffers by hardware.

Note: For details, see Chapter 16, Direct Memory Access (DMA) Controller.

1.2.7 Internal and External Bus Architecture

The SC140 cores and other MSC8113 modules interconnect via a variety of bus and interface structures that provide great flexibility for transferring and storing data both within the MSC8113 device and with external devices. The internal bus structures include the following:

 SC140 core buses. Each SC140 core can access its own M1 memory, ICache, and the

write buffer with zero wait states using its internal 128-bit instruction bus and two 64-bit data buses. These buses include:

— 32-bit program address bus (PAB) that allows the SC140 core to specify program

addresses in the local unified memory (M1).

— 128-bit program data bus (PDB) that transfers the program data to and from M1 or the

ICache.

— Two 32-bit address buses (XABA and XABB) to specify data locations in M1 for the

two data streams required for DSP operations.

— Two 64-bit data buses (XDBA and XDBB) to transfer data values to and from M1.

 QBus. A 128-bit wide, single-master, multi-slave bus within each extended core. The

SC140 core is the master and all other modules on the bus are slaves: LIC, PIC, and QBus memory controller. The QBus memory controller directs QBus accesses by the slave devices and interfaces the MQBus and SQBus. It includes a Fetch Unit that moves program code into the ICache when required and a four-entry write buffer so that the SC140 core does not have to wait for a write access to finish before continuing instruction processing. When an SC140 core accesses an address beyond a programmable address referred to as the QBus base line, this access is forwarded to the QBus. The PIC is a slave on this bus and needs zero QBus wait states for an access. Accesses to the same bank can be pipelined.

 MQBus. A 128-bit wide bus that connects all the extended cores to the internal shared

memory (M2) and Boot ROM. Each core accesses the MQBus through its own QBus Bank1. The SC140 core requires low latencies when it access the M2 memory. To minimize latencies when the M2 is accessed, M2 accesses occur on a dedicated separate

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bus called the MQBus. The boot ROM can be accessed through the MQBus. The MQBus is a multi-master bus whose masters are the three SC140 cores and whose sole slave is the M2 memory. This bus can transfer up to 128 bits at 500 MHz.

— Data bus access of up to 128-bit read and up to 64-bit write. — Operation at the SC140 core frequency. — A central efficient round-robin arbiter controlling SC140 core access on the MQBus. — Atomic operation control of access to M2 memory by the three SC140 cores and the

local bus.

 SQBus. A 128-bit wide, multi-master, multi-slave bus that connects the SC140 cores to the

system interface unit (SIU) and the IP master module. Each SC140 core accesses the SQBus through its own QBus Bank 3. The SC140 core does not require reduced latency when accessing the typically slower peripherals. The SC140 core access to other peripherals, including the system and the local interfaces, occurs through the SQBus. The SQBus is a multi-master bus whose masters are the three SC140 cores. This bus accesses either the external memory or other slaves through the IPBus.

 IPBus. A 32-bit wide bus controlled by an IP master that connects the local bus and

SQBus to some system peripherals. This one-master multi-slave bus runs at up to 166 MHz and enables access to the control and the status registers of the DSI, the TDM interface, the ethernet controller, the timers, the UART, the hardware semaphores, the virtual interrupt registers, and the GPIOs. Either an external host or an SC140 core accesses the clients on this bus as follows:

— An SC140 core accesses the IPBus through the SQBus. — An external host on the DSI accesses the IPBus through the IP master from the local

bus.

— An external host on the system bus accesses the IPBus through the bridge and the IP

master.

 DSI. A 32/64-bit slave host interface to connect an external host processor.

— 21-25 bit address, 32/64-bit data. — Direct access by an external host to internal and external resources, including the M1

and the M2 memories as well as the system bus.

— Synchronous and asynchronous accesses, with burst capability in the synchronous

mode. — Dual or Single strobe modes. — Write and read buffers improve host bandwidth. — Byte enable signals enable 1-, 2-, 4-, and 8-byte write access granularity. — Sliding Window mode enables accesses with a reduced number of address lines. — Chip ID decoding enables the use of one — Broadcast

CS signal enables parallel writes to multiple DSPs.

CS signal for multiple DSPs.

— Big-endian, little-endian, and munged little-endian support.

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 Local bus. A 64-bit wide bus connecting the Ethernet Controller, TDM, DSI, DMA

controller, and the local-to-system bus bridge to each other. The extended cores also share this bus, which connects to the M1 memory of each SC140 core. This multi-master multi-slave bus runs at 166 MHz. The DSI, TDM, DMA controller, and the bridge are the masters of this bus. The internal memories are slaves to this bus, which is primarily used for transferring data between the chip interfaces to the internal memories.

 System bus. A 64-bit wide bus controlled by the SIU that connects the DMA controller and

system interface (from the SQBus) through the SIU memory controller to the external 32/64 bit system bus. It also connects to the local-to-system bus bridge to allow data transfers between the 60x-compatible local and internal system buses.

— 64/32-bit data and 32-bit address bus. — Support for multiple-master designs. — Four-beat burst transfers (eight-beat in 32-bit wide mode). — Port size of 64, 32, 16, and 8 controlled by the internal memory controller. — Bus accesses external memory or peripherals, or an external host device uses it to

access internal resources. — Slave support, direct access by an external host to internal resources including the M1

and M2 memories. — Internal arbitration between up to four master devices.

 The external buses can be configured during reset in three modes:

— 64-bit data DSI and 32-bit data system bus. — 32-bit data DSI and 64-bit data system bus. — 32-bit data DSI, 32 bit data system, and Ethernet MII or RMII.

1.2.8 TDM Serial Interface

The TDM interface connects gluelessly to common telecommunication framing schemes, such as T1 and E1 lines. It can also connect to multiple framers and switches, as well as to commons buses such as the ST-BUS. The TDM contains four identical and independent engines. Each TDM engine can be configured in one of the following options:

 Two independent receive and transmit links.

— The transmit has an input clock of up to 50 MHz, output data, and a frame sync that is

configured as either input or output. Up to 256 transmit channels are supported. — The receive has an input clock of up to 50 MHz, input data, and an input frame sync.

Up to 256 receive channels are supported.

 Two receive and two transmit links share the clock and the frame sync. The input clock

runs up to 25 MHz, and the sync is configured as either input or output. Each of the two receive links supports up to 128 channels, and each transmit link supports up to 128 channels.

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 One receive and one transmit link share the clock and the frame sync. The input clock runs

at up to 50 MHz, and the sync is configured as either input or output. There are up to 256 channels for the receive link and up to 256 channels for the transmit link.

Each channel can be 2, 4, 8, or 16 bits wide. When the slot size is 8 bits wide, selected channels can be defined as A-law/μ-law. These channels are converted to 13–14 bits, which are padded into 16 bits and stored as such in memory. Each receive channel and each transmit channel can be active or not. An active channel has a buffer that is placed into the M1 and M2 memories or into memory devices on the system bus. All the buffers belonging to one TDM interface have the same size and are filled/emptied at the same rate. A-law/μ-law buffers are filled at twice the rate, so their buffer size is twice that of the non A-law/μ-law channels.

For receives, all the buffers belonging to a specific TDM interface fill at the same rate and therefore share the same write pointer relative to the beginning of the buffer. When the write pointer reaches a pre-determined threshold, an interrupt to the SC140 core is generated. The SC140 core empties the buffers while the TDM continues to fill the buffers until a second threshold line is reached, and an interrupt is generated to the SC140 core. The SC140 core empties the data between the first and the second threshold lines. Both the first and the second threshold lines are programmable. Using threshold lines, the SC140 core and the TDM can implement a double buffer handshake. In addition, the TDM generates an interrupt on frame start to the SC140 core, which helps synchronize to the TDM system.

For transmits, the SC140 core fills all the buffers belonging to a specific TDM interface, and the TDM empties them. A similar method employing two threshold line interrupts is used for a double-buffer handshake between the SC140 core and the TDM.

Note: For details, see Chapter 20, TDM Interface.

1.2.9 Ethernet Controller

The Ethernet controller complies with the IEEE Std. 802.3 standard and supports 10Mb/s and 100Mb/s operation as a media-independent interface (MII), a reduced media-independent interface (RMII), or a serial media-independent interface (SMII). The Ethernet controller works with minimal SC140 core intervention and operates in two modes:

 Full Duplex mode, for connecting the Ethernet to an on-board Ethernet switch.  Half-Duplex mode, for connecting the Ethernet to an on-board physical layer (PHY).

On the receive side, the SC140 core prepares empty buffers and points to these buffers through up to four rings residing in memory (for example M2). The Ethernet controller reads the descriptors, fills their associated buffers with the received buffers, and interrupts the SC140 core when done. On the transmit side, the SC140 core prepares buffers in memory and prepares a descriptor ring that points to those buffers. The Ethernet controller reads these descriptors, reads the data from the buffers, and sends the data over the Ethernet. Enhanced pattern matching

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enables you to process received frames with a wide variety of tools to assist network applications. Features such as extraction of data and filing of frames in queues based on a pattern hit can accelerate post processing of data. It can further enhance the address recognition process by applying additional filtering to frames that pass the destination address check. Flexibility is built into pattern matching architecture to give you more control in manipulating receive frames. When the receiver detects the first bytes of a frame, the Ethernet controller begins to perform the frame recognition functions. It first tries to “filter” the frames based on matching a pattern in the frame, and if it fails it filters according to the MAC address. Pattern matching is performed using user-selected patterns of flexible length, up to 256 bytes into the frame. For example, if four patterns of 16 bytes are used, incoming frames can be filtered to four destination queues, with each queue dedicated to one DSP subsystem. Frames can be filtered not only by their MAC address but also by their IPv4 or IPv6 address and even their UDP port number. Based on these matches, the frame is accepted or rejected. Once a frame is accepted, the Ethernet controller processes it on the basis of user-defined attributes. The receiver can also receive physical (individual), group (multicast), and broadcast addresses. The Ethernet transmitter requires very little SC140 core intervention. The transmitter takes data from the Tx FIFO and transmits data to the MAC. The MAC transmits the data through the MII/RMII/SMII interface to the physical media. Once initialized, the transmitter runs until the end-of-frame (EOF) condition is detected, unless a collision within the collision window occurs (half-duplex mode) or an abort condition is encountered. In addition to the MAC-to-PHY interface, the Ethernet controller also supports a MAC-to-MAC interface with the SMII mode. In all three modes, the Ethernet controller can automatically gather network statistics required for RMON without the need to receive all addresses using promiscuous mode.

Note: For details, see Chapter 25, Ethernet Controller.

1.2.10 Universal Asynchronous Receiver/Transmitter (UART)

The UART is used mainly for debugging or booting. It provides a full-duplex port for serial communications via transmit data (

TXD) and receive data (RXD) lines. During reception, the

UART generates an interrupt request when a new character is available in the UART data register. During transmission, the UART generates an interrupt request when a new character can be written to its data register. When it accepts an interrupt request, an SC140 core or external host should read the UART status register to identify the interrupt source and service it accordingly.

Note: For details, see Chapter 21, UART.

1.2.11 Timers

The MSC8113 device contains 32 identical general-purpose 16-bit timers divided into two 16-timer groups. Within a group, each timer functions independently or as part of a programmable cascade of two timers. Each timer is programmable as either one-shot or cyclic. The SC140 cores can program the counters, read their updated values, and also be interrupted

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when the timers reach a predefined value. The timers are clocked by either the internal clock generator or one of four dedicated external signals or from the receive and transmit TDM clocks. When a timer reaches a predefined value, it either toggles or generates a pulse that can be directed to one of the four dedicated external signals or to other timers. In addition, it can generate an interrupt.

Note: For details, see Chapter 22, Timers.

1.2.12 GPIOs

The MSC8113 device has 32 general-purpose I/O (GPIO) signals. Each connection in the I/O ports is configured either as a GPIO signal or as a dedicated peripheral interface signal. In addition, fifteen of the GPIO signals can generate interrupts to the global interrupt controller (GIC). Each line is configured as an input or output (with a register for data output that is read or written at any time). All outputs can also be configured as open-drain (that is, configured in an active low wired-OR configuration on the board). In this mode, the signal drives a zero voltage but goes to tri-state (high impedance) when driving a high voltage. GPIO signals do not have internal pull-up resistors. Dedicated MSC8113 peripheral functions are multiplexed onto the shared external connections. The functions are grouped to maximize connection use for the greatest number of MSC8113 applications.

Note: For details, see Chapter 23, GPIO.

1.2.13 Reset and Boot

The Hard Reset Configuration Word (HRCW) contains the essential information for resetting the device, including the PLL divide ratio, signal configuration, and the DSI host endian mode. This configuration word is initialized by writing to it either from the system configuration source. When the MSC8113 is reset from the system bus, the configuration word is latched using a dedicated latches it to the other DSPs. When resetting from an external host, the HRCW is latched from the 32 least significant bits (lsb) of the DSI bus. Immediately after reset, SC140 core 0 starts executing the code on the internal boot ROM. The value in the configuration register identifies the boot source. There are five possible boot sources:

 System port  External host  TDM interface  UART



RSTCONF signal. In another reset procedure, a master DSP reads data from the ROM and

C software module

Note: For details, see Chapter 5, Reset and Chapter 6, Boot Program.

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1.2.14 Interrupt Scheme

Each of the three extended cores contains two local interrupt modules, the programmable interrupt controller (PIC) and the local interrupt controller (LIC). The PIC has 24 maskable and 8 non maskable interrupts, and its SC140 core accesses it directly. The PIC handles interrupts from the SC140 DSP core EOnCE module and some external interrupts. The PIC also receives interrupts from the LIC, which in turn concentrates interrupts from the MSC8113 peripherals (TDMs, timers, DMA controller, UART, and virtual interrupts), the SIU, and other external interrupts, such the Ethernet interface. With interrupt controllers local to the SC140 core, each SC140 core can handle the relevant interrupts and either treat them as level sources or capture them as edge-triggered sources. For example, when the TDM generates an interrupt upon reaching the first threshold of its buffers, this interrupt could be useful for multiple cores. Therefore, the interrupt pulse can be captured, as well as an edge source in all of the LIC modules, and each SC140 core can process the interrupt and clear the local status bit separately, without unnecessary arbitration. A global interrupt controller (GIC) concentrates interrupts from the SIU, the UART, and external signals and drives the interrupts for core-to-core and external host-to-core interrupts.

INT_OUT signal. It also generates the virtual

Note: For details, see Chapter 17, Interrupt Processing.

1.2.15 Signal Multiplexing Options

The MSC8113 device allows various external signal multiplexing options to distribute the external signal lines among the system bus, DSI bus, TDM interfaces, Ethernet signals, and GPIO signals. Table 1-11 summarizes the multiplexing options.

Table 1-11. External Signal Multiplexing Options

Configuration Setting Configuration Options

Bus Width in Bits Ethernet

DSI64

0 0 0 None 0, 1, 2, 3 32 64 — — 0 0 1 00 = MII 0,1 32 64 — MII 0 0 1 01 = RMII 0,1, 3 32 64 — RMII 0 0 1 10 = SMII 0,1, 3 32 6 4 — SMII

ETHSEL

Ethernet

Enable

Ethernet

Mode

Available

TDMs

DSI

System

Bus

DSI/

System

Bus

GPIO

0 1 0 None 0, 1, 2, 3 32 32 — — 0 1 1 00 = MII 0, 1, 2, 3 32 32 MII — 0 1 1 01 = RMII 0, 1, 2,3 32 32 RMII — 0 1 1 10 = SMII 0, 1, 2, 3 32 32 — — 1 0 0 None 0, 1, 2, 3 64 32 — —

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Table 1-11. External Signal Multiplexing Options

Configuration Setting Configuration Options

Bus Width in Bits Ethernet

DSI64

1 0 1 00 = MII 0, 1 64 32 — MII 1 0 1 01 = RMII 0, 1, 3 64 32 — RMII 1 0 1 10 = SMII 0, 1, 3 64 32 — SMII 1 1 X None 0, 1, 2, 3 64 32 — —

Notes: 1. Represents the sampled value when PORESET is deasserted.

2. The value of the ETHSEL bit in the Hard Reset Configuration Word.

3. The value of the EN bit in the MIIGSK Enable Register.

4. The value of the IFMODE bits in the MIIGSK Configuration Register.

ETHSEL

Ethernet

Enable

Ethernet

Mode

Available

TDMs

DSI

1.3 Internal Communication and Semaphores

System

Bus

DSI/

System

Bus

GPIO

The MSC8113 device contains flexible mechanisms for communicating between SC140 cores and between an SC140 core and an external host. An SC140 core sends a message to another SC140 core either by accessing an agreed location (mailbox) in the shared M2 memory or by accessing any of the M1 memories and using an interrupt to indicate the access. Access to shared resources can be protected by semaphores.

1.3.1 Internal Communication

Each SC140 core or an external host can generate an interrupt to another SC140 core or to an external host by writing the destination core number and the virtual interrupt number to a virtual interrupt register. Each generated interrupt destination is programmable and can be forwarded to one or multiple destination SC140 cores.

Note: For details, see Chapter 17, Interrupt Processing.

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1.3.2 Atomic Operations

When the SC140 core executes the bmtset instruction, it issues a read access followed by a write access to the semaphore address and then asserts the atomic signal. The MQBus and the SQBus prevent the SC140 cores from writing to the same semaphore address. A semaphore shared by an SC140 core and an external host on the system bus is protected by a snooper on the bus interface. When the system bus interface receives a read with atomic signal, the snooper starts to snoop the bus. The snooper returns a failure if the external host writes to the same location. Snoopers also protect the M1 and the M2 memories, which are accessible to both the SC140 cores and external hosts.

Note: For details, see Section 9.3, Extended QBus System.

1.3.3 Hardware Semaphores

There are eight coded hardware semaphores. Each semaphore is an 8-bit register with a selective write protection mechanism. When the register value is zero, it is writable to any new value. When the register value is not zero, it is writable only to zero. Each SC140 core/host/task has a unique pre-defined lock number (8-bit code). When trying to lock the semaphore, the SC140 core writes its lock number to the semaphore and then reads it. If the read value equals its lock number, the semaphore belongs to that host and is essentially locked. An SC140 core/host/task releases the semaphore by simply writing 0.

Note: For details, see Chapter 15, Hardware Semaphores.

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SC140 Core Overview 2

The SC140 digital signal processing (DSP) core features an innovative architecture that addresses the key market needs of the next-generation DSP applications, mainly in the field of wireline and wireless infrastructure and subscriber communication. This flexible DSP core supports compute-intensive applications by providing high performance, low power, efficient compile, and high code density. The SC140 core efficiently deploys a novel variable-length execution set (VLES) execution model, maximizing parallelism by allowing multiple address generation and data arithmetic logic units to execute multiple operations in a single clock cycle. This section provides an overview of the key features and main modules of the SC140 core, as well as the programming model and instruction set list.

Note: The information in this chapter is based on Revision 3 of the SC140 DSP Core

Reference Manual. To get the updates in later revisions of this manual, visit the

Freescale Web site shown on the back cover of this manual.

The 16-bit SC140 core packs four data arithmetic-logic execution units (ALUs), each consisting of a multiply-accumulate unit (MAC), a logic unit, and a bit field unit (BFU), which also serves as a barrel shifter. In addition to the four data execution units, the core contains two address arithmetic units (AAUs), one bit manipulation unit (BMU) and one branch unit. Overall, the SC140 can issue and execute up to six instructions per clock—for example, four independent arithmetic instructions and two pointer-related instructions (such as moves or other operations on addresses). At a clock speed of 400 MHz, the SC140 can therefore execute 1600 true DSP MIPS—1600 million multiply-accumulate operations per second (MMACS), concurrent with associated data movement functions and pointer updates.

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The SC140 core can sustain this high performance over time because of the flexibility of its data execution units and ability to transfer up to 128 data bits per cycle. The four data execution units can operate simultaneously in any combination. For example, the SC140 core can execute four multiply-accumulate operations in a single clock, or one MAC, two arithmetic/logical operations and one bit field operation. All four data ALUs are identical, permitting great flexibility in assigning and executing instructions, increasing the likelihood that four execution units can be kept busy on any given cycle and enabling programs to take better advantage of the SC140 core parallel architecture.

2.1 Architecture

This section discusses the main functional blocks of the SC140 core. Figure 2-1 shows a block diagram of the core as used by the MSC8113.

Extended Core Unified Data/Program Memory (M1)

128

PDB

Program

Sequencer

Instruction Bus

See Section 2.3 for details

PAB

Address Generator

AGU

XABA

2 AAUs 4 ALUs

XABB

BMU

XDBA

128

XDBB

Data ALU

EOnCE™

Module

DALU

SC140 Core

Figure 2-1. Block Diagram of the SC140 Core in the MSC8113

Note: The SC140 DSP core defines the PLL Control Registers 0–1 (PCTL[0–1]) for PLL and

clock control. The MSC8113 does not use these registers in its design. In addition, the

manual defines six debug modules and seven EE signal lines in the EOnCE module.

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The MSC8113 device uses only two of these modules (0 and 1) and two signals (EE0

and EE1).

2.1.1 Data Arithmetic Logic Unit (Data ALU)

The Data ALU performs arithmetic and logical operations on data operands in the MSC8113. The data registers can be read or written to memory over the XDBA and the XDBB as 8-bit, 16-bit, or 32-bit operands. The 64-bit wide data buses XDBA and XDBB support the transfer of several operands on a single access. The source operands for the Data ALU, which may be 16, 32, or 40 bits, originate either from data registers or from immediate data. The results of all Data ALU operations are stored in the data registers. All Data ALU operations are performed in one clock cycle. Up to four parallel arithmetic operations can be performed in each cycle. The destination of every arithmetic operation can be used as a source operand for the operation immediately following, without any time penalty.

The components of the Data ALU are as follows:

 A bank of sixteen 40-bit registers  Four parallel ALUs, each ALU containing a MAC unit and a BFU with a 40-bit barrel

shifter

 Eight data bus shifter/limiter circuits, to allow limiting four 16-bit fractional words over

each of the 64-bit data buses in a single cycle.

All the MAC units and BFUs can access all the Data ALU registers. Each register is partitioned into three portions: two 16-bit registers (low and high portion of the register) and one 8-bit register (extension portion). The 16-bit high and low register portions are typically used as an inputs for arithmetic operations. The full 40-bit register can be used as an input operand, but is generally used as an output operand for most instructions. The two 64-bit wide data buses that connect between the Data ALU register file and the memory enable a very high data bandwidth between memory and registers. Load and store instructions utilize the maximum width of the bus according to the application requirement because there are different versions of the instructions for different bandwidths:

 move.b loads or stores bytes (8-bit)  move.w or move.f loads or stores integer or fractional words (16-bit)  move.l loads or stores long words (32-bit)  move.2w

or move.2f loads or stores double-integers and double-fractions, respectively

(32-bit)

 move.4w or move.4f loads or stores quad-integers and quad-fractions respectively (64-bit)  move.2l loads or stores two long words (64-bits total)

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Figure 2-2 shows the architecture of the Data ALU.

Memory Data Bus 1 (XDBA) Memory Data Bus 2 (XDBB)

64 64 64 64

Shifter/Limiter

Data Registers D[0–15]

4040 40 40 40 40 40

40 404040

40 40 40 40 40 40

ALUALU ALU

40 40 40

ALU

Figure 2-2. Data ALU Architecture

With the ability to execute any two

MOVE instructions in parallel every clock cycle, a maximum

data throughput of 6.4 GBps (at 400 MHz) can be achieved between the memory and the register file.

2.1.1.1 Data Registers

The Data ALU registers are read or written over the data buses (XDBA and XDBB). The source operands for Data ALU arithmetic instructions always originate from Data ALU registers. All the Data ALU operations are performed in one clock cycle so that a new instruction can be initiated in every clock, yielding a rate of up to four Data ALU instructions per clock cycle. The destination of every arithmetic operation can be used as a source operand for the operation immediately following, without any time penalty.

2.1.1.2 Multiply-Accumulate (MAC) Unit

The MAC unit comprises the main arithmetic processing unit of each SC140 core and performs all the calculations on data operands. The MAC unit outputs one 40-bit result in the form of [Extension:Most Significant Portion:Least Significant Portion] (EXT:MSP:LSP). The multiplier executes 16-bit × 16-bit fractional or integer multiplication between two’s complement signed, unsigned, or mixed operands. The 32-bit product is right-justified and added to the 40-bit contents of one of the sixteen data registers.

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2.1.1.3 Bit-Field Unit (BFU)

The BFU contains a 40-bit parallel bidirectional shifter with a 40-bit input and a 40-bit output, mask generation unit, and logic unit. The BFU is used in the following operations:

 Multi-bit left/right shift (arithmetic or logical)  One-bit rotate (right or left)  Bit-field insert and extract  Count leading bits  Logical operations  Sign or zero extension operations

2.1.2 Address Generation Unit (AGU)

The AGU is one of the execution units in the SC140 core. The AGU performs effective address calculations using the integer arithmetic necessary to address data operands in memory, and it contains the registers to generate the addresses. It performs four types of arithmetic: linear, modulo, multiple wrap-around modulo, and reverse-carry. The AGU operates in parallel with other chip resources to minimize address generation overhead. The AGU also generates change-of-flow program addresses and manages the stack pointer (SP). The major components of the AGU are as follows:

 Eight address registers (R[0–7])  Eight alternative address registers (R[8–15]) or eight base address registers (B[0–7])  Two stack pointers (NSP, ESP), only one of which is active at a time (SP)  Four offset registers (N[0–3])  Four modifier registers (M[0–3])  A Modifier Control Register (MCTL)  Two Address Arithmetic Units (AAU)  One Bit Mask Unit (BMU)

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Figure 2-3 shows a block diagram of the AGU.

PABXABBXABA

B0/R8 B1/R9 B2/R1 B3/R1 B4/R1 B5/R1 B6/R1 B7/R1

M0 M1 M2 M3

MCTL

Program Count er (PC) Addres s

Memory Data Bus 1 (XDBA)

Memory Data Bus 2 (XDBB)

N0 N1 N2 N3

Figure 2-3. AGU Block Diagram

Address

Arithmetic

Unit (AAU)

R0 R1 R2 R3 R4 R5 R6 R7

NSP, ESP

Bit

Mask

Unit

(BMU)

The two AAUs are identical. Each contains a 32-bit full adder called an offset adder and a 32-bit full adder called a modulo adder. The offset adder performs the following operations:

 Add or subtract an AGU registers or PC to/from an AGU register  Add or subtract an immediate value to/from an AGU register  Compare to or test an AGU register  Logical and arithmetic shift operations on AGU registers  Sign or zero-extend an AGU register  Add with reverse carry

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The offset values added in this adder are pre-shifted by 1, 2, or 3, according to the access width. In reverse-carry mode, the carry propagates in the opposite direction. The modulo adder adds the summed result of the first full adder to a modulo value, M or minus M, where M is stored in the selected modifier register. In modulo mode, the modulo comparator tests whether the result is inside the buffer by comparing the results to the B register and chooses the correct result from between the offset adder and the modulo adder.

2.1.2.1 Stack Pointer Registers

To facilitate use of a software stack, two special registers with special addressing modes are assigned to the AGU: the Normal Mode Stack Pointer (NSP) and the Exception Mode Stack Pointer (ESP). Both the ESP and the NSP are 32-bit read/write address registers with predecrement and post-increment updates, as well as offset with immediate values to allow random access to the software stack. Stack instructions use the ESP when the MSC8113 is in the Exception mode of operation, which it enters when exceptions occur. The NSP is used in Normal mode, while not servicing an exception. The two stack pointers make it easier to support multitasking systems and optimizes stack usage for these systems.

2.1.2.2 Bit Mask Unit (BMU)

The BMU performs bit mask operations, such as setting, clearing, changing, or testing a destination, according to an immediate mask operand. Data is loaded to the BMU over the data memory buses XDBA or XDBB. The result is written back over XDBA or XDBB to the destinations in the next cycle. All bit mask instructions typically execute in two cycles and work on 16-bit data. This data can be a memory location, or a portion (high or low) of a register. The BMU supports a set of bit mask instructions that operate on:

 All AGU pointers (R[0–15])  All Data ALU registers (D[0–15])  All control registers (EMR, VBA, SR, MCTL)  Memory locations

Only a single bit mask instruction is allowed in any single execution set, since only one execution unit exists for these instructions. A subset of the bit mask instructions (BMTSET) allows support for hardware semaphores.

2.1.3 Program Sequencer Unit (PSEQ)

The PSEQ fetches and dispatches instructions, controls hardware loops, and controls exception processing. The PSEQ implements three out of the five stages of the pipeline and controls the different processing states of the MSC8113 core. It consists of three hardware blocks:

 Program address generator (PAG). Generates the program counter (PC) for instruction

fetch operations and controls the hardware loop functionality.

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 Program dispatch unit (PDU). Detects the execution set out of the fetch set and dispatches

the various instructions of the execution set to their appropriate execution units.

 Program control unit (PCU). Controls the overall pipeline behavior of the program flow.

The PSEQ implements its functions using the following registers:

 Program Counter Register (PC)  Status Register (SR)  Four Loop Start Address Registers (SA[0–3])  Four Loop Counter Registers (LC[0–3])  Exception and Mode Register (EMR)  Vector Base Address Register (VBA)

2.1.4 Enhanced On-Chip Emulation (EOnCE)

The EOnCE module allows nonintrusive interaction with the MSC8113 and its peripherals so that you can examine registers, memory, or on-chip peripherals, define various breakpoints, and read the trace-FIFO. These interactions facilitate hardware and software development on the MSC8113 processor. The EOnCE module interfaces with the debugging system through on-chip JTAG TAP controller signals. For details, see the SC140 DSP Core Reference Manual.

2.2 Programming Model

The three main units of the SC140 DSP core programming model are the Address Generation Unit (AGU), the Data Arithmetic Logic Unit (Data ALU), and the PSEQ (see Figure 2-4). This section gives a brief overview of each of these units.

2.2.1 AGU Programming Model

The address registers can be programmed for linear, modulo (regular or multiple wrap-around), and bit-reverse addressing. Automatic updating of address registers is available when address register indirect addressing is used.

 Address Registers (R[0–15]). The sixteen 32-bit address registers R[0–15] contain

addresses or general-purpose data. These are 32-bit read/write registers. The 32-bit address in a selected address register is used in calculating the effective address of an operand. The contents of an address register point directly to memory or are used as an offset. R[0–15] are composed of two separate banks, a lower bank (R[0–7]) and an upper bank (R[8–15]). The lower bank registers can be used for linear, modulo, or bit reverse addressing. An upper bank register can be used in linear addressing modes only if the respective register in the lower bank is not using modulo addressing mode. In modulo addressing mode, each lower bank register Rn is assigned a corresponding base address register Bn. Registers B[0–7] and R[8–15] are mapped to the same physical register,

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respectively. Therefore, for example, R8 is available only if R0 is not being used in modulo addressing, since this requires the base address register B0. See Section 2.2.2, Data Arithmetic Logic Programming Model, on page 2-11 for further information.

If an address register is updated, one of the modifier control registers (MCTL) specifies the type of update arithmetic. Offset registers (Ni) are used for post-addition and indexing by offset. The address register modification is performed by either of the two AAUs.

 Stack Pointer Registers (NSP, ESP). The MSC8113 has two stack pointer registers: the

Normal Stack Pointer (NSP) and the Exception Stack Pointer (ESP). These 32-bit registers are used implicitly in all PUSH and POP instructions. Only one stack pointer is active at a time, according to the mode:

— In Normal mode, the NSP is used. — In Exception mode, the ESP is used.

The Status Register EXP bit determines the active mode. The active stack pointer (SP) is used explicitly for memory references in the address register indirect modes. The stack pointers point to the next unoccupied location in the stacks. They are post-incremented on all the implicit PUSH operations and pre-decremented on all the implicit POP operations.

Note: You must explicitly initialize both stack pointer registers after reset.

 Offset Registers (N[0–3]). The 32-bit read/write offset registers N[0–3] contain offset

values to increment or decrement address registers in address register update calculations. These registers are also used for 32-bit general-purpose storage. For example, the contents of an offset register specify the offset into a table or the base of the table for indexed addressing. An offset register can be used to step through a table at a specified rate—such as five locations per step for waveform generation. Each address register can be used with each offset register. For example, R0 can be used with N0, N1, N2, or N3 for offset address calculation.

 Base Address Registers (B[0–7]). The 32-bit read/write base address registers B[0–7] are

used in modulo calculations. Each B register is associated with an R register (B0 with R0, and so on). When the modulo addressing mode is activated, the B register contains the lower boundary value of the modulo buffer. The upper boundary of the modulo buffer is calculated by B+M-1, where M is the modifier register associated with the register used. When not used for modulo accessing, these registers can function as alternative address registers (R[8–15]). Both Rx and B

share the same physical register. For example, if R0

X-8

is not programmed for modulo addressing, the base address register B0 can serve as an additional address register R8.

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ADDRESS GENERATION UNIT

31 0

R0 R1 R2 R3 R4 R5 R6 R7

SP (NSP,

ESP)

31 0

R8/B0

R9/B1 R10/B2 R11/B3 R12/B4 R13/B5 R14/B6 R15/B7

Address Registers Base Address

Registers

PROGRAM CONTROL UNIT

31 0

N0 N1 N2 N3

M0 M1 M2 M3

MCTL

Offset and Modifier Registers

DATA ARITHMETIC LOGIC UNIT

7 0 15 0 15 0 D0 D0.e D0.h D0.I D1 D1.e D1.h D1.I D2 D2.e D2.h D2.I D3 D3.e D3.h D3.I D4 D4.e D4.h D4.I D5 D5.e D5.h D5.I D6 D6.e D6.h D6.I D7 D7.e D7.h D7.I

D8 D8.e D8.h D8.I D9 D9.e D9.h D9.I

D10 D10.e D10.h D10.I D11 D11.e D11.h D11.I D12 D12.e D12.h D12.I D13 D13.e D13.h D13.I

31 0

Program Counter

31 0

SA0 SA1 SA2 SA3

Start Address Registers

31 0

Status Register

31 0

Loop Counter Registers

31 0

EMR

Mode and Exception Status Register

LC0 LC1 LC2 LC3

D14 D14.e D14.h D14.I D15 D15.e D15.h D15.I

Figure 2-4. SC140 Programming Model

 Modifier Registers (M[0–3]). The 32-bit read/write modifier registers M[0–3] contain the

value of the modulus modifier. These registers are also used for general-purpose storage. The address arithmetic unit (AAU) supports linear, modulo, multiple wrap-around modulo, and reverse-carry arithmetic types for most address register indirect addressing modes. When the modulo arithmetic is activated, the contents of Mj specify the modulus.

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Each address register can be used with each modifier register, as programmed in the MCTL register.

 Modifier Control Register (MCTL). The 32-bit read/write register to program the address

mode (AM) for each of the eight address registers (R[0–7]). The addressing mode of the upper address register file (R[8–15]) cannot be programmed and functions in linear mode only.

2.2.2 Data Arithmetic Logic Programming Model

The Data ALU programming model is shown in Figure 2-4. Register D0 refers to the entire 40-bit register, whereas D0.e, D0.h, D0.l refer to the extension, most significant and least significant portions of the D0 register, respectively. The D[0–15] data registers, referred to as Dx, give maximum flexibility, since they are used as source operands, destination storage, or accumulators.The registers serve as input buffer registers between the XDBA or XDBB and the ALUs. They are used as Data ALU source operands, allowing new operands to be loaded for the next instruction while the register contents are used by the current arithmetic instruction.

Each data register Dx has an additional associated flag bit, the limit tag bit Lx, to signify that limiting could occur when reading Dx over XDBA and XDBB. For saving and restoring, the limit tag bit Lx is coupled with the extension portion Dx.e, to form a 9-bit operand. The limit tag bit Lx is updated when a result is written from the ALU to the Dx register.

The data registers are accessed with three types of data width:

 A long-word type access, writing or reading 32-bit operands  A word type access, writing or reading 16-bit operands  A byte type access, writing or reading 8-bit operands

Fractional data in Dx registers that is transferred to memory over XDBA and XDBB is replaced by a limiting constant if the value cannot be represented by the number of bits in the access width. The contents of Dx are not affected if limiting occurs. Only the value transferred over XDBA or XDBB is limited. This process is commonly referred to as transfer saturation, and it should not be confused with the arithmetic saturation mode. The overflow protection is performed after the contents of the register are shifted according to the scaling mode. Shifting and limiting are performed only when a fractional operand is specified as the source for a data move over XDBA or XDBB. When an integer operand is specified as the source for a data move, shifting and limiting are not performed.

Automatic sign extension or zero extension of the data values into the 40-bit registers is provided when an operand is transferred from memory to a data register. If a fractional word operand is to be written to a data register, the MSP portion of the register is written with the word operand, the LSP portion is zero-extended, and the EXT portion is sign-extended from MSP. When an integer operand is to be written to a data register, the LSP portion of the register is written with the word operand, and the MSP portion and EXT are either zero-extended or sign-extended from the LSP.

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Long-word operands are written into the MSP:LSP portions of the register, and the EXT portion is either zero- or sign-extended.

When a byte operand is to be written to a data register, the register’s first eight bit portion of the LSP (Dx.1[7–0]) is written with the byte operand, and the remaining bits are either zero-extended or sign-extended from the LSP lower byte.

2.2.3 Program Control Unit Programming Model

The Program Control Unit (PCU) is part of the Program Sequencer Unit (PSEQ). The PCU controls the overall pipeline behavior of the program flow. The PCU implements its functions using the following registers:

 Program Counter Register (PC)  Status Register (SR)  Four Start Address Registers (SA[0–3])  Four Loop Counter Registers (LC[0–3])  Exception and Mode Register (EMR). The EMR reflects and controls exception situations

in the core. It contains bits that reflect memory configuration, servicing of a non-maskable interrupt, and the following exception conditions: Data ALU overflow, illegal execution set, and illegal instruction flow.

The EMR GP[0–6] and BEM fields are initialized at reset as described in Table 2-1.

Table 2-1. EMR GP[6–0] and B EM Field Reset Values

Field Reset Value

BEM 1 GP0 EE1 GP1 0 GP2 ISBSEL2 from Hard Reset Configuration Word (HRCW) bit 15 GP3 ISBSEL1 from HRCW bit 14 GP4 ISBSEL0 from HRCW bit 13 GP5 0 GP6 0

Note: GP4 equals the inversion of the HRCW bit 13.

2.3 Instruction Set Overview

The SC140 instruction set is divided into the following functional groups:

 Data ALU arithmetic  AGU arithmetic

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Instruction Set Overview

 Move  Stack support  Bit mask  Change-of-flow  Program control

This following tables list the SC140 instructions alphabetically within the appropriate functional group.

Table 2-2. DALU Arithmetic Instructions

Instruction Description

ABS Absolute value ADC Add long with carry ADD Add ADD2 Add two 16-bit values ADDNC.W Add without changing the carry bit in the status register ADR Add and round ASL Arithmetic shift left by one bit ASR Arithmetic shift right by one bit CLR Clear CMPEQ Compare data registers for equal CMPEQ.W Compare immediate value to data register for equal CMPGT Compare data registers for greater than CMPGT.W Compare data register to immediate for greater than CMPHI Compare for higher (unsigned) DECEQ Decrement a data register and set T if zero DECGE Decrement a data register and set T if greater than or equal to zero DIV Divide iteration DMACSS Multiply signed by signed and accumulate with data register right shifted by word size DMACSU Multiply signed by unsigned and accumulate with data register right shifted by word size IADD Integer addition - no saturation IMAC Signed integer multiply-accu mu lat e IMACLHUU Integer mult iply-accum ulate unsi gned times unsigned; firs t source from lower portion se cond from

upper IMACUS Integer multiply-accumulate unsigned times signed IMPY Signed integer multiply IMPYHLUU Integer multiply unsigned times unsigned; first source from upper portion second from lower IMPYSU Integer multiply signed times unsigned IMPYUU Integer multiply unsigned times unsigned INC Increment a data register (as integer data)

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Table 2-2. DALU Arithmetic Instructions (Continued)

Instruction Description

INC.F Increment a data register (as fractional data) MAC Signed fractional multiply -ac cum ula te MACR Signed fractional multiply-accumulate and round MACSU Signed/unsigned fractional multiply-accumulate MACUS Unsigned/signed fractional multiply-accumulate MACUU Unsigned/unsigned frac tio nal multi pl y-ac c um ula te MAX Transfer maximum signed value MAX2 Transfer two 16-bit maximum signed value MAX2VIT Specialized MAX2 version for Viterbi kernel MAXM Transfer maximum magnitude value MIN Transfer minimum signed value MPY Signed fractional multiply MPYR Signed fractional multiply and round MPYSU Signed/unsigned fractional multiply MPYUS Unsigned/signed fractional multiply MPYUU Unsigned/unsigned fractional multiply NEG Negate RND Round SAT.F Saturate value in data register to fit in top 16 bits SAT.L Saturate value in data register to fit in 32 bits SBC Subtract long with carry SBR Subtract and round SUB Subtract SUB2 Subtract two 16-bit values SUBL Shift left and subtract SUBNC.W Subtract without changing the carry bit in the status register TFR Transfer data register to a data register TFRF Conditional data register transfer if the T bit is clear TFRT Conditional data register transfer if the T bit is set TSTEQ Test for equal to zero TSTGE Test for greater than or equal to zero TSTGT Test for greater than zero

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Table 2-3. DALU Logical Instructions

Instruction Description

AND Logical AND ASLL Multi-bit arithmetic shift left ASLW Word arithmetic shift left (16-bit shift) ASRR Multi-bit arithmetic shift right ASRW Word arithmetic shift right (16-bit shift) CLB Count leading bits EOR Logical exclusive OR EXTRACT Extract signed bit field EXTRACTU Extract unsigned bit field INSERT Insert bit field LSLL Multi-bit logical shift left LSR Logical shift left by one bit LSRR Multi-bit logical shift right LSRW Word logical shift right (16-bit shift)

Instruction Set Overview

NOT Logical complement OR Logical inclusive OR ROL Rotate one bit left through the carry bit ROR Rotate one bit right through the carry bit SXT.B Sign extend byte SXT.L Sign extend long SXT.W Sign extend word ZXT.B Zero extend byte ZXT.L Zero extend long ZXT.W Zero extend word

Table 2-4. AGU Arithmetic Instructions

Instruction Description

ADDA AGU add ADDL1A AGU add with 1-bit left shift of source operand ADDL2A AGU add with 2-bit left shift of source operand ASL2A AGU arithmetic shift left by 2 bits (32-bit) ASLA AGU arithmetic shift left (32-bit) ASRA AGU arithmetic shift ri ght (32-bit) CMPEQA AGU compare for equal CMPGTA AGU compare for greater than CMPHIA AGU compare for higher (unsigned) DECA AGU decrement register

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Table 2-4. AGU Arithmetic Instructions (Continued)

Instruction Description

DECEQA AGU decrement and set T if zero DECGEA AGU decrement and set T if equal or greater than zero INCA AGU increment register LSRA AGU logical shift right (32-bit) SUBA AGU subtract SXTA.B AGU sign extend byte SXTA.W AGU sign extend word TFRA AGU register transfer TSTEQA.L AGU test for equal on all 32 bits TSTEQA.W AGU test for equal on lower 16 bits TSTGEA.L AGU test for greater than or equal TSTGTA AGU test for greater than ZXTA.B AGU zero extend byte ZXTA.W AGU zero extend word

Table 2-5. Move Instructions

Instruction Description

MOVE.2F Move two fractional words from memory to a register pair MOVE.2L Move two longs to/from a register pair MOVE.2W Move two integer words to/from a register pair MOVE.4F Move four fractional words from memory to a regi ster quadrant MOVE.4W Move fou r integer words to/from a register quadrant MOVE.B Move byte (sign-extended for memory reads) MOVE.F Move fractional word to and from memory MOVE.L Move long (sign extended for memory or register reads) MOVE.W Move integer word (sign extended for memory reads ) MOVEF Move address register to address register, depending on T bit of SR MOVES.F Move fractional word to memory with saturation enabled MOVES.L Move long to memory with saturation enabled MOVES.2F Move two fractional words to memory with saturation enabled MOVES.4F Move four fractional words to memory with saturation enabled MOVET Move address register to address register, depending on T bit of SR MOVEU.B Move unsigned byte from memory MOVEU.L Move unsigned long from memory MOVEU.W Move unsigned integer word from memory VSL.2F Viterbi shift left: specialized move to support Viterbi kernel VSL.2W Viterbi shift left: specialized move to support Viterbi kernel

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Instruction Set Overview

Table 2-5. Move Instructions (Continued)

Instruction Description

VSL.4F Viterbi shift left: specialized move to support Viterbi kernel VSL.4W Viterbi shift left: specialized move to support Viterbi kernel

Table 2-6. Stack Support Instructions

Instruction Description

POP Pop a register from the software stack POPN Pop a register from the software stack using the normal stack po inter PUSH Push a register into the software stack PUSHN Push a register into the software stack using the normal stack pointer TFRA OSP Move the “other” stack pointer to/from a register, inversely defined by the exception mode

Table 2-7. Bit Mask Instructions

Instruction Description

AND Logical AND on a 16-bit operand AND.W Logical AND on a 16-bit immediate value BMCHG Bit-mask change for a 16-bit operand BMCHG.W Bit-mask change for a 16-bit operand in memory BMCLR Bit-mask clear for a 16-bit operand BMCLR.W Bit-mask clear for a 16-bit operand in memory BMSET Bit-mask set for a 16-bit operand BMSET.W Bit-mask set for a 16-bit operand in memory BMTSET Bit mask test and set for a 16-bit operand BMTSET.W Bit mask test and set for a 16-bit operand in memory BMTSTC Bit-mask test if clear for a 16-bit operand BMTSTC.W Bit-mask test if clear for a 16-bit operand in memory BMTSTS Bit-mask test if set for a 16-bit operand BMTSTS.W Bit-mask test if set for a 16-bit operand in memory EOR Logical Exclusive OR on a 16-bit operand EOR.W Logical Exclusive OR on a 16-bit operand in memory NOT Binary inversion of a 16-bit operand NOT.W Binary inversion of a 16-bit operand in memory OR Logical OR on a 16-bit operand OR.W Logical OR on a 16-bit operand in memory

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Table 2-8. AGU Non-Loop Ch ange-of-Flow Instructions

Instruction Description

BF Branch if false BFD Branch if false (delayed) BRA Branch BRAD Branch (delayed) BSR Branch to subroutine BSRD Branch to subroutine (del ayed) BT Branch if true BTD Branch if true (delayed) JF Jump if false JFD Jump if false (delayed) JMP Jump JMPD Jump (delayed) JSR Jump to subroutine JSRD Jump to subroutine (delayed) JT Jump if true JTD Jump if true (delayed) RTE Return from exception RTED Retu rn from exception (delayed) RTS Return from subroutine RTSD Return from subroutine (delayed) RTSTK Force restore PC from the stack, updating SP RTSTKD Force restore PC from the stack, updating SP (delayed) TRAP Execute a precise software exception.

Table 2-9. AGU Loop Control (including Loop COF) Instruc tions

Instruction Description

BREAK Terminate the loop and branch to an address CONT Jump to the start of the loop to start the next iteration CONTD Jump to the start of the loop to start the next iteration (delayed) DOENn Do enable - set the “nth” loop counter and enable the loop as a long loop DOENSHn Do enable short - set the “nth” loop counter and enable the loop as a short loop DOSETUPn Setup the “nth” hardware loop start address SKIPLS Test the active LC and skip the loop if LCn is equal or smaller than zero

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Additional Programming Considerations

Table 2-10. AGU Program Control Instructions

Instruction Description

DEBUG Enter debug mode DEBUGEV Signal debug event DI Disable interrupts (sets the DI bit in the status register) EI Enable interrupts (clears the DI bit in the status register) ILLEGAL Triggers an illegal instruction exception MARK Push the PC into the trace buffer STOP Stop processing (lowest power stand-by) WAIT Wait for interrupt (low power stand-by)

Table 2-11. Prefix Instructions

Instruction Description

IFA Execute current execution set or subset unconditionally IFF Execute current execution set or subset if the T bit is clear IFT Execute current execution set or subset if the T bit is set NOP No operation, not dispatched to an execution unit

2.4 Additional Programming Considerations

 Use the last 64 bytes of M1 memory for data only. Because of system pipelining, code

fetches from this area by the cores can result in an attempt to access areas beyond the end of the M1 memory. Such fetches may cause the system to stop operation. To prevent this occurrence, do not store instruction code in the range 0x00037FC0–0x00037FFF.

 In some rare instances, accesses to illegal addresses may not generate the correct illegal

address exception. If this occurs, program execution does not continue beyond the illegal address access.

 In rare situations, an illegal execution set fetched by the SC140 core can alter the settings

of system registers or cause the SC140 core to enter a freeze state that can only be released by reset. The SC140 illegal instruction trap does not provide 100 percent protection against illegal instruction execution.

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External Signals 3

The MSC8113 external signals are organized into functional groups, as shown in Table 3-1 and Figure 3-1. Table 3-1 lists the functional groups, the number of signal connections in each

group, and references the table that gives a detailed listing of multiplexed signals within each group. Figure 3-1 shows MSC8113 external signals organized by function.

Table 3-1. MSC8113 Functional Signal Groupings

Number of

Functional Group

Signal

Connections

Detailed Description

Power (V Clock 3 Table 3-3 on page 3-3

Reset and Configuration 4 Table 3-4 on page 3-3 DSI, System Bus, Ethernet, and Interrupts 210 Table 3-1 on page 3-4 Memory Controller 16 Table 3-2 on page 3-16 General-Purpose Input/Output (GPIO), Time-Division Multiplexed

(TDM) Interface, Universal Asynchronou s Receive r/ Transmi tter (UART), Ethernet, and Timers

Ethernet signals 3 Table 3-4 on page 3-28 EOnCE module and JTAG Test Access Port 7 Table 3-5 on page 3-28 Reserved (denotes connections that are always reserved) 1 Table 3-6 on page 3-29

, VCC, and GND) 155 Table 3-2 on page 3-3

32 Table 3-3 on page 3-19

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External Signals

HD0/SWTE ↔

HD1/DSISYNC ↔

HD2/DSI64 ↔ HD3/MODCK1 ↔ HD4/MODCK2 ↔

HD5/CNFGS ↔

HD[32-39]/D[32-39]/reserved ↔

HD40/D40/ETHRXD0 ↔

HD41/D41/ETHRXD1 ↔ HD42/D42/ETHRXD2/reserved ↔ HD43/D43/ETHRXD3/reserved ↔

HD[44-45]/D[44-45]/reserved ↔

HD46/D46/ETHTXD0 ↔

HD47/D47/ETHTXD1 ↔ HD48/D48/ETHTXD2/reserved ↔ HD49/D49/ETHTXD3/reserved ↔

HD[50-53]/D[50-53]/reserved ↔

HD54/D54/ETHTX_EN ↔

HD55/D55/ETHTX_ER/reserved ↔

HD56/D56/ETHRX_DV/ETHCRS_DV ↔

S[0–3]/HDBS[0–3]/HWBE[0–3]/HDBE[0–3] → 4 1 ↔ IRQ7/DP7/DREQ4

HWB

S[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/

HWB

GPIO10/TDM2TCLK/IRQ8/ETHRX_DV/ETHCRS_DV/NC ↔ 1

GPIO11/TDM2TDAT/IRQ9/

GPIO12/TDM2RSYN/IRQ10/

GPIO0/CHIP_ID0/IRQ4/ETHTXD0 ↔ 1

GPIO1/TIMER0/CHIP_ID1/IRQ5

GPIO3/TDM3TSYN/IRQ1/ETHTXD2 ↔ 1 1 → PSDA10/PGPL0

GPIO4/TDM3TCLK/IRQ2/

GPIO5/TDM3TDAT/IRQ3/

GPIO6/TDM3RSYN/IRQ4/

GPIO7/TDM3RCLK/IRQ5/

GPIO8/TDM3RDAT/IRQ6/ETHCOL ↔ 1 1 → PSDAMUX/PGPL5

GPIO9/TDM2TSYN/IRQ7/

GPIO13/TDM2RCLK/IRQ11/

GPIO14/TDM2RDAT/IRQ12/

GPIO16/TDM1TCLK/DONE1/DRACK1 ↔ 1 1

GPIO22/TDM0TCLK/DONE2

HD57/D57/ETHRX_ER ↔

HD58/D58/ETHMDC ↔

HD59/D59/ETHMDIO ↔

HD60/D60/ETHCOL/reserved ↔

HD[61–63]/D[61-63]/reserved ↔

E[4–7]/PSDDQM[4–7]/PBS[4–7]

HRDS/HRW/HRDE →

HDST[0–1]/HA[9–10] → 2 1 → NMI_OUT

GPIO2/TIMER1/CHIP_ID2/IRQ6

ETHRX_ER/ETHTXD ↔ 1 1 → EE1

ETHRXD1/ETHSYNC ↔ 1 C

GPIO15/TDM1TSYN/DREQ1 ↔

GPIO17/TDM1TDAT/DACK1 ↔ 1 1

GPIO18/TDM1RSYN/DREQ2 ↔ 1 1 ← RSTCONF

GPIO19/TDM1RCLK/DACK2 ↔ 1

GPIO20/TDM1RDAT ↔ GPIO21/TDM0TSYN

GPIO23/TDM0TDAT/IRQ13 ↔ 1 1 →

GPIO24/TDM0RSYN/IRQ14

GPIO25/TDM0RCLK/IRQ15 ↔ 1

GPIO26/TDM0RDAT ↔ 1

GPIO27/URXD/DREQ1 ↔ 1

GPIO28/UTXD/DREQ2 ↔ 1

GPIO29/CHIP_ID3/ETHTX_EN ↔ 1

GPIO30/TIMER2/TMCLK/SDA ↔

GPIO31/TIMER3/SCL ↔

HD[6–31] ↔

HCID[0–2] →

HCID3/HA8 →

HA[11–29] →

↔ 4 1 ↔ TA

HBRST → 1 1 ← NMI

HCS → 1 1 ↔ PSDVAL

HBCS → 1 1 ↔ IRQ7/INT_OUT

HTA ← 1

HCLKIN → 1 1 → BCTL1/CS5

/ETHTXD1 ↔ 1 1 → ALE

↔ 1 4 → PWE[0–3]/PSDDQM[0–3]/PBS[0–3]

ETHTX_ER ↔ 1 1 → PSDWE/PGPL1

ETHRXD3 ↔ 1 1 → POE/PSDRAS/PGPL2 ETHRXD2/NC ↔ 1 1 → PSDCAS/PGPL3 ETHTXD3/NC ↔ 1 1 ↔ PGTA/PUPMWAIT/PGPL4/PPBS

ETHMDIO ↔ 1

ETHMDC ↔ 1 1 ← Reserved

ETHRXD0/NC ↔ 1 1 ← CLKIN

↔

/DRACK2 ↔ 1 1 ←

↔ 1

1 1 1 ↔ TT0/HA7

1 1 ↔ TT1

1 3 ↔ TT[2–4]/CS[5–7]

1 5 → CS[0–4]

1 4 ↔ TSZ[0–3]

26 1 ↔ TBST

8 1 ↔ IRQ1/GBL

1 1 ↔ IRQ3/BADDR31

1 1 ↔ IRQ2/BADDR30

1 1 ↔ IRQ5/BADDR29

1 1 → BADDR28

2 1 → BADDR27

E T

1 1 ↔ BR

1 1 ↔ BG

1 1 ↔ DBG

1 1 ↔ ABB/IRQ4

4 1 ↔ DBB/IRQ5

1 1 ↔ TS

1 1 ↔ AACK 1 1 ↔ ARTRY 1 32 ↔ D[0–31] 1 1 ↔ reserved/DP0/DREQ1/EXT_BR2 1 1 ↔ IRQ1/DP1/DACK1/EXT_BG2 1 1 ↔ IRQ2/DP2/DACK2/EXT_DBG2 3 1 ↔ IRQ3/DP3/DREQ2/EXT_BR3 3

1 1 ↔ IRQ5/DP5/DACK4/EXT_BG3

19 1 ↔ IRQ6/DP6/DREQ3

M C

1 1

T D M

/ E T

R N

1 R

/ T

1 1 ← TDI

1 1 ← TCK

I 2

1 1 ← 1 1 ←

32 ↔ A[0–31]

S Y S T E M

B U S

1 ↔ IRQ4/DP4/DACK3/EXT_DBG3

TEA

↔

1 → BCTL0 M E

3 ↔ BM[0–2]/TC[0–2]/BNKSEL[0–2] M

C S

Y S

1 ← EE0

Debug

1 → CLKOUT L K

1 ← PORESET E S E T

J T A G

Ded.

Ether

net

HRESET

↔ ↔ SRESET

1 ← TMS

TRST TDO

1 ←

ETHRX_CLK/ETHSYNC_IN ETHTX_CLK/ETHREF_CLK/ETHCLOCK ETHCRS/ETHRXD

Note: Power signals are: V

DDH

, V

, GND, GNDH, and GND

CCSYN

. Reserved signals can be left unconnected. NC signals must not be connected.

SYN

, V

Figure 3-1. MSC8113 External Signa ls

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3.1 Power Signals

Table 3-2. Power and Ground Signal Inputs

Signal Name Description

DDH

CCSYN

GND System Ground

GND

SYN

Internal Logic Power

dedicated for use with the device core. The voltage should be well-regulated and the input should be

provided with an extremely low impedance path to the V

Input/Output Power

This source supplies power for the I/O buffers. The user must provide adequate external decoupling capacitors.

System PLL Power

dedicated for use with the system Phase Lock Loop (PLL). The voltage should be well-regulated and

the input should be prov ided with an extremely low impedance path to the VCC power rail.

An isolated ground fo r the i nternal pr ocessin g log ic an d I/O buffers . Thi s conne ction must be ti ed ex ternall y to all chip ground connections, except GND

capacitors.

System PLL Ground

Ground dedicated for system PLL use. The connection should be provided with an extremely low-impedance path to ground.

. The user must provide adequate external decoupling

SYN

power rail.

Power Signals

3.2 Clock Signals

Table 3-3. Clock Signals

Signal Name Type Signal Description

CLKIN Input Clock In

Primary clock input to the MSC8113 PLL.

CLKOUT Output Clock Out

The bus clock.

Reserved Input Pull down.

3.3 Reset and Configuration Signals

Table 3-4. Reset and Configuration Signals

Signal Name Type Signal Description

PORESET

RSTCONF Input Reset Configuration

Input Power-On Reset

When asserted, this line causes the MSC8113 to enter power-on reset state.

Used during reset configu ration se quenc e of the ch ip. A detail ed expl anatio n of its fun ction i s provided in the MS C81 13 R efere nc e Manual . This signal is sampled upon deassertion of PORESET

Note: When PORESET

• BM[0–2]—Selects the boot mode.

• MODCK[1–2]—Selects the clock configuration.

• SWTE—E nables the software watchdog timer.

• DSISYNC, DSI64, CNFGS, and CHIP_ID[0–3]—Configures the DSI.

Refer to Table 3-5 for details on these signals.

is deasserted, the MSC8113 also samples the following signals:

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External Signals

Table 3-4. Reset and Configuration Signals (Continued)

Signal Name Type Signal Description

HRESET Input/

Output

SRESET

Input/

Output

Hard Reset

When asserted as an input, this signal causes the MSC8113 to enter the hard reset state. After the device enters a hard reset state, it drives the signal as an open-drain output.

Soft Reset

When asserted as an input, this signal causes the MSC8113 to enter the soft reset state. After the device enters a soft reset state, it drives the signal as an open-drain output.

3.4 Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals

The direct slave interface (DSI) is combined with the system bus because they share some common signal lines. Individual assignment of a signal to a specific signal line is configured through internal registers. Table 3-5 describes the signals in this group. Although there are fifteen interrupt request (IRQ) connections to the core processors, there are multiple external lines that can connect to these internal signal lines. After reset, the default configuration enables only

IRQ[1–7], but includes two input lines each for IRQ[1–3] and IRQ7. The designer must select one

line for each required interrupt and reconfigure the other external signal line or lines for alternate functions. Additional alternate IRQ lines and

IRQ[8–15] are enabled through the GPIO signal lines.

Table 3-5. DSI, System Bus, Ethernet, and Interrupt Signals

Signal Name Type Description

HD0

SWTE

HD1

DSISYNC

HD2

DSI64

HD3

MODCK1

Input/

Output

Input

Input/

Output

Input

Input/

Output

Input

Input/

Output

Input

Host Data Bus 0

Bit 0 of the DSI data bus. Software Watchdog Timer Disable.

It is sampled on the rising edge of PORESET

Host Data Bus 1

Bit 1 of the DSI data bus. DSI Synchronous

Distinguishes betw een sync hronous an d asynch ronous ope ration of the D SI. It is sampled on the rising edge of PORESET

Host Data Bus 2

Bit 2 of the DSI data bus.

DSI 64

Defines the width of the DSI and SYSTEM Data buses. It is sampled on the rising edge of PORESET

Host Data Bus 3

Bit 3 of the DSI data bus. Clock Mode 1

Defines the clock frequencies. It is sampled on the rising edge of PORESET

signal.

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Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals

Table 3-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

HD4

MODCK2

HD5

CNFGS

HD[6–31] Input/

HD[32–39]

D[32–39]

Reserved

HD40

Input/

Output

Input

Input/

Output

Input

Output

Input/

Output

Input/

Output

Input

Input/

Output

Host Data Bus 4

Bit 4 of the DSI data bus. Clock Mode 2

Defines the clock frequencies. It is sampled on the rising edge of PORESET

Host Data Bus 5

Bit 5 of the DSI data bus.

Configuration Source

One signal out of two tha t indicates res et configur ation mo de. It is sam pled on the ris ing edge of PORESET

Host Data Bus 6–31

Bits 6–31 of the DSI data bus.

Host Data Bus 32–39

Bits 32–39 of the DSI data bus.

System Bus Data 32–39

For write transactions , the bus m aster driv es valid data on th is bus. For rea d transac tions, the slave drives valid data on this bus.

If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can be left unconnected.

Host Data Bus 40

Bit 40 of the DSI data bus.

signal.

D40

ETHRXD0

HD41

D41

ETHRXD1

HD42

D42

ETHRXD2

Reserved

Input/

Output

Input

Input/

Output

Input/

Output

Input

Input/

Output

Input/

Output

Input

System Bus Data 40

For write transactions, th e bus mast er drives va lid data on this line. Fo r read transa ctions, th e slave drives valid data on this bus.

Ethernet Receive Da ta 0

In MII and RMII modes, bit 0 of the Ethernet receive data.

Host Data Bus 41

Bit 41 of the DSI data bus.

System Bus Data 41

For write transactions, th e bus mast er drives va lid data on this line. Fo r read transa ctions, th e slave drives valid data on this bus.

Ethernet Receive Da ta 1

In MII and RMII modes, bit 1 of the Ethernet receive data.

Host Data Bus 42

Bit 42 of the DSI data bus.

System Bus Data 42

For write transactions, th e bus mast er drives va lid data on this line. Fo r read transa ctions, th e slave drives valid data on this bus.

Ethernet Receive Da ta 2

In MII mode only, bit 2 of the Ethernet receive data. In RMII mode, this pin is reserved and can be left unconnected.

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Table 3-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

HD43

D43

ETHRXD3

Reserved HD[44–45]

D[44–56]

Reserved

HD46

D46

Input/

Output

Input/

Output

Input

Input/

Output

Input/

Output

Input

Input/

Output

Input/

Output

Host Data Bus 43

Bit 43 of the DSI data bus.

System Bus Data 43

For write transactions, th e bus mast er drives va lid data on this line. Fo r read transa ctions, th e slave drives valid data on this bus.

Ethernet Receive Da ta 3

In MII mode only, bit 3 of the Ethernet receive data. In RMII mode, this pin is reserved and can be left unconnected.

Host Data Bus 44–45

Bits 44–45 of the DSI data bus.

System Bus Data 44–45

For write transactions , the bus m aster driv es valid data on th is bus. For rea d transac tions, the slave drives valid data on this bus.

If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can be left unconnected.

Host Data Bus 46

Bit 46 of the DSI data bus.

System Bus Data 46

For write transactions, th e bus mast er drives va lid data on this line. Fo r read transa ctions, th e slave drives valid data on this bus.

ETHTXD0

HD47

D47

ETHTXD1

HD48

D48

ETHTXD2

Reserved

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input

Ethernet Transmit Data 0

In MII and RMII modes, bit 0 of the Ethernet transmit data.

Host Data Bus 47

Bit 47 of the DSI data bus.

System Bus Data 47

For write transactions, th e bus mast er drives va lid data on this line. Fo r read transa ctions, th e slave drives valid data on this bus.

Ethernet Transmit Data 1

In MII and RMII modes, bit 1 of the Ethernet transmit data.

Host Data Bus 48

Bit 48 of the DSI data bus.

System Bus Data 48

For write transactions, th e bus mast er drives va lid data on this line. Fo r read transa ctions, th e slave drives valid data on this bus.

Ethernet Transmit Data 2

In MII mode only, bit 2 of the Ethernet transmit data. In RMII mode, this pin is reserved and can be left unconnected.

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Table 3-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

HD49

D49

ETHTXD3

Reserved HD[50–53]

D[50–53]

Reserved

HD54

D54

Input/

Output

Input/

Output

Input

Input/

Output

Input/

Output

Input

Input/

Output

Input/

Output

Host Data Bus 49

Bit 49 of the DSI data bus.

System Bus Data 49

For write transactions, th e bus mast er drives va lid data on this line. Fo r read transa ctions, th e slave drives valid data on this bus.

Ethernet Transmit Data 3

In MII mode only, bit 3 of the Ethernet transmit data. In RMII mode, this pin is reserved and can be left unconnected.

Host Data Bus 50–53

Bits 50–53 of the DSI data bus.

System Bus Data 50–53

For write transactions , the bus m aster driv es valid data on th is bus. For rea d transac tions, the slave drives valid data on this bus.

If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can be left unconnected.

Host Data Bus 54

Bit 54 of the DSI data bus.

System Bus Data 54

For write transactions, th e bus mast er drives va lid data on this line. Fo r read transa ctions, th e slave drives valid data on this bus.

ETHTX_EN

HD55

D55

ETHTX_ER

Reserved

HD56

D56

ETHRX_DV

ETHCRS_DV

Output

Input/

Output

Input/

Output

Input

Input/

Output

Input/

Output

Input

Ethernet Transmit Data Enable

In MII and RMII modes, indicates that the transmit data is valid.

Host Data Bus 55

Bit 55 of the DSI data bus.

System Bus Data 55

For write transactions, th e bus mast er drives va lid data on this line. Fo r read transa ctions, th e slave drives valid data on this bus.

Ethernet Transmit Data Error

In MII mode only, indicates a transmit data error. In RMII mode, this pin is reserved and can be left unconnected.

Host Data Bus 56

Bit 56 of the DSI data bus.

System Bus Data 56

For write transactions, th e bus mast er drives va lid data on this line. Fo r read transa ctions, th e slave drives valid data on this bus.

Ethernet Receive Da ta Valid

Indicates that the receive data is valid.

Ethernet Carrier Sense/Receive Data Valid

In RMII mode, indicates that a carri er is det ec ted a nd after the connection is established that the receive data is valid.

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External Signals

Table 3-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

HD57

D57

ETHRX_ER

HD58

D58

ETHMDC

HD59

D59

ETHMDIO

Input/

Output

Input/

Output

Input

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Host Data Bus 57

Bit 57 of the DSI data bus.

System Bus Data 57

For write transactions, th e bus mast er drives va lid data on this line. Fo r read transa ctions, th e slave drives valid data on this bus.

Ethernet Receive Da ta Error

In MII and RMII modes, indicates a receive data error.

Host Data Bus 58

Bit 58 of the DSI data bus.

System Bus Data 58

For write transactions, th e bus mast er drives va lid data on this line. Fo r read transa ctions, th e slave drives valid data on this bus.

Ethernet Management Clock

In MII and RMII modes, used for the MDIO reference clock.

Host Data Bus 59

Bit 59 of the DSI data bus.

System Bus Data 59

For write transactions, th e bus mast er drives va lid data on this line. Fo r read transa ctions, th e slave drives valid data on this bus.

Ethernet Management Data

In MII and RMII modes, used for station management data input/output.

HD60

D60

ETHCOL

Reserved HD[61–63]

D[61–63]

Reserved

HCID[0–2] Input Host Chip ID 0–2

Input/

Output

Input/

Output

Input/

Output

Input

Input/

Output

Input/

Output

Input

Host Data Bus 60

Bit 60 of the DSI data bus.

System Bus Data 60

For write transactions, th e bus mast er drives va lid data on this line. Fo r read transa ctions, th e slave drives valid data on this bus.

Ethernet Collision

In MII mode only, indicates that a collision was detected. In RMII mode, this pin is reserved and can be left unconnected.

Host Data Bus 61–63

Bits 61–63 of the DSI data bus.

System Bus Data 61–63

For write transactions , the bus m aster driv es valid data on th is bus. For rea d transac tions, the slave drives valid data on this bus.

If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can be left unconnected.

With HCID3, carries the chip ID of the DSI. The DSI is accessed only if HCS HCID[0–3] matches the Chip_ID, or if HBCS

is asserted and

is asserted.

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Table 3-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

HCID3

HA8

HA[11–29] Input Host Bu s Address 11–29

HWBS[0–3]

HDBS[0–3]

HWBE[0–3]

HDBE[0–3]

HWBS[4–7]

HDBS[4–7]

Input

Host Chip ID 3

With HCI[0–2], carries the chip ID of the DSI. The DSI is accessed only if HCS and HCID[0–3] matches the Chip_ID, or if HBCS

Host Bus Address 8

Used by an external host to access the internal address space.

Used by external host to access the internal address space. Host Write Byte Strobes (In Asynchronous dual mode)

One bit per byte is used as a strobe for host write accesses. Host Data Byte Strobe (in Asynchronous single mode)

One bit per byte is used as a strobe for host read or write accesses Host Write Byte Enable (In Synchronous dual mode)

One bit per byte is used to indicate a valid data byte for host read or write accesses. Host Data Byte Enable (in Synchrono us si ngl e mod e)

One bit per byte is used as a strobe enable for host write accesses Host Write Byte Strobes (In Asynchronous dual mode)

One bit per byte is used as a strobe for host write accesses. Host Data Byte Strobe (in Asynchronous single mode)

One bit per byte is used as a strobe for host read or write accesses

is asserted

is asserted.

HWBE[4–7]

HDBE[4–7]

PWE[4–7]

PSDDQM[4–7]

PBS[4–7]

HRDS

HRW

HRDE

Input

Output

Input

Host Write Byte Enable (In Synchronous dual mode) One bit per byte is used to indicate a valid data byte for host write accesses.

Host Data Byte Enable (in Synchrono us si ngl e mod e) One bit per byte is used as a strobe enable for host read or write accesses

System Bus Write Enable

Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte lanes for write operations.

System Bus SDRAM DQM

From the SDRAM control machine. These pins select specific byte lanes of SDRAM devices.

System Bus UPM Byte Select

From the UPM in the memory controller, these signals select specific byte lanes during memory operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the address and size of the transaction and the port size of the accessed device.

Host Read Data Strobe (In Asynchronous dual mode) Used as a strobe for host read accesses.

Host Read/Write Select (in Asynchronous/Synchronous single mode) Host read/write select.

Host Read Data Enable (In Synchronous dual mode) Indicates valid data for host read accesses.

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Table 3-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

HBRST Input Host Burst

The host asserts this pin to indicate that the current transaction is a burst transaction in synchronous mode only.

HDST[0–1]

HA[9–10]

HCS

HBCS

HTA

HCLKIN Input Host Clock Input

A[0–31] Input/

TT0

Input Host Data Structure 0–1

Defines the data structure of the host access in DSI little-endian mode.

Host Bus Address 9–10

Used by an external host to access the internal address space.

Input Host Chip Select

DSI chip select. The DSI is accessed only if HCS Chip_ID.

Input Host Broadcast Chip Select

DSI chip select for broadcast mode. Enables more than one DSI to share the same host chip-select pin for broadcast write accesses.

Output Host Transfer Acknowledge

Upon a read access, indicates to the host when the data on the data bus is valid. Upon a write access, indicates to the host that the data on the data bus was written to the DSI write buffer.

Host clock signal for DSI synchronous mode.

Address Bus

Output

Input/

Output

When the MSC8113 is in external master bus mode, these pins function as the system address bus. The MSC8113 drives the address of its internal bus masters and responds to addresses generated by external bus masters. When the MSC8113 is in internal master bus mode, these pins are used as address lines con nected to mem ory devic es and are contro lled by the MSC8113 memory control le r.

Bus Transfer Type 0

The bus master drives this pins during the address tenure to specify the type of the transaction.

is asserted and HCID[0–3] matches the

HA7

TT1 Input/

Output

TT[2–4]

CS[5–7]

CS[0–4] Output Chip Select 0–4

TSZ[0–3] Input/

Input/

Output

Host Bus Address 7

Used by an external host to access the internal address space.

Bus Transfer Type 1

The bus master drives this pins during the address tenure to specify the type of the transaction. Some applications use only the TT1 signal, for example, from MSC8113 to MSC8113 or MSC8113 to MSC8101 and vice versa. In these applications, TT1 functions as read/write signal.

Bus Transfer Type 2–4

The bus master drives these pins during the address tenure to specify the type of the transaction.

Chip Select 5–7

Enables specific memory devices or peripherals connected to the system bus.

Transfer Size 0–3

The bus master drives these pins with a value indicating the number of bytes transferred in the current transaction.

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Table 3-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

TBST Input/

Output

IRQ1

GBL

IRQ3

BADDR31

IRQ2

BADDR30

IRQ5

Input

Output

Input

Output

Input

Output

Input

Bus Transfer Burst

The bus master asserts this pin to indicate that the current transaction is a burst transaction (transfers eight words).

Interrupt Request 1

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

Global

When a master within th e M SC 811 3 in iti ate s a b us tran sa ction, it drives this pin. Assertion of this pin indicates that the transfer is global and should be snooped by caches in the system.

Interrupt Request 3

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

Burst Address 31

There are five burst address output pins, which are outputs of the memory controller. These pins connect directly to burstable memory devices without internal address incrementors controlled by the MSC8113 memory controller.

Interrupt Request 2

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

Burst Address 30

Interrupt Request 5

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

BADDR29

Output

Bus Burst Address 29

BADDR28 Output Burst Address 28

BADDR27 Output Burst Address 27

Input/

Output

Bus Request

When an external arbiter is used, the MSC8113 asserts this pin as an output to request

ownership of the bus. When the MSC8113 controller is used as an internal arbiter, an external master asserts this pin as an input to request bus ownership.

Input/

Output

Bus Grant

When the MSC8113 acts as an internal arbiter, it asserts this pin as an output to grant bus

ownership to an external bus master. When an external arbiter is used, it asserts this pin as an input to grant bus ownership to the MSC8113.

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External Signals

Table 3-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

DBG Input/

Output

ABB

Input/

Output

IRQ4

Input

DBB

Input/

Output

IRQ5

Input

Input/

Output

Data Bus Grant

When the MSC8113 acts as an internal arbiter, it asserts this pin as an output to grant data bus ownership to an external bus master. When an external a rbit er i s us ed, it asserts this p in as an input to grant data bus ownership to the MSC8113.

Address Bus Busy

The MSC8113 asserts this pin as an output for the duration of the address bus tenure. Following an AACK

, which terminates the add res s bus tenu re, th e MSC 81 13 deas se rts ABB for a fraction of a bus cycle and then stops driving this pin. The MSC8113 does not assume bus ownership as l ong a s it s ens es t his pin is asserted as an i npu t b y an e xte rna l bus m as ter.

Interrupt Request 4

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

Data Bus Busy

The MSC8113 assert s this p in as a n output for the duration of the data b us te nur e. Following

, which terminates the data bus tenure, the MSC8113 deasserts DBB for a fraction of a

a TA bus cycle and then stops driving this pin. The MSC8113 does not assume data bus ownership as long as it sense s that this p in is as serted as an in put by a n external b us mas ter.

Interrupt Request 5

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

Bus Transfer Start

Assertion of this pin signals the beginning of a new address bus tenure. The MSC8113 asserts this signal when one of its internal bus masters begins an address tenure. When the MSC8113 senses that this pin is asserted by an external bus master, it responds to the address bus tenure as required (snoop if enabled, access internal MSC8113 resources, memory controller support).

AACK

Input/

Output

ARTRY

Input/

Output

D[0–31] Input/

Output

Reserved

DP0

Input

Input/

Output

DREQ1

Input

EXT_BR2

Input

Address Acknowledge

A bus slave asserts this signal to indicate that it has identified the address tenure. Assertion of this signal terminates the address tenure.

Address Retry

Assertion of this signal indicates that the bus master should retry the bus transaction. An external master asserts this signal to enforce data coherency with its caches and to prevent deadlock situations.

Data Bus Bits 0–31

In write transactions, the bus master drives the valid data on this bus. In read transactions, the slave drives the valid data on this bus.

The primary configuration selec tio n (defa ult afte r reset) is reserv ed.

System Bus Data Parity 0

The agent that drives the data bus al so drives the data parity si gnals. The va lue driven on the data parity 0 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 0 and D[0–7].

DMA Request 1

Used by an external peripheral to request DMA service.

External Bus Request 2

An external master asserts this pin to request bus ownership from the internal arbiter.

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Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals

Table 3-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

IRQ1

DP1

DACK1

EXT_BG2

IRQ2

DP2

DACK2

Input

Input/

Output

Input

Input/

Output

Interrupt Request 1

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

System Bus Data Parity 1 The agent that drives the data bus al so drives the data parity si gnals. The va lue driven on the data parity 1 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 1 and D[8–15].

DMA Acknowledge 1

The DMA drives this output to acknowledge the DMA transaction on the bus.

External Bus Grant 2

The MSC8113 asserts this pin to grant bus ownership to an external bus master.

Interrupt Request 2

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

System Bus Data Parity 2

The agent that drives the data bus al so drives the data parity si gnals. The va lue driven on the data parity 2 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 2 and D[16–23].

DMA Acknowledge 2

The DMA drives this output to acknowledge the DMA transaction on the bus.

EXT_DBG2

IRQ3

DP3

DREQ2

EXT_BR3

Output

Input

Input/

Output

Input

External Data Bus Grant 2

The MSC8113 asserts this pin to grant data bus ownership to an external bus master.

Interrupt Request 3

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

System Bus Data Parity 3

The agent that drives the data bus al so drives the data parity si gnals. The va lue driven on the data parity 3 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 3 and D[24–31].

DMA Request 2

Used by an external peripheral to request DMA service.

External Bus Request 3

An external master should assert this pin to request bus ownership from the internal arbiter.

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External Signals

Table 3-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

IRQ4

DP4

DACK3

EXT_DBG3

IRQ5

DP5

DACK4

Input

Input/

Output

Input

Input/

Output

Interrupt Request 4

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

System Bus Data Parity 4

The agent that drives the data bus al so drives the data parity si gnals. The va lue driven on the data parity 4 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 4 and D[32–39].

DMA Acknowledge 3

The DMA drives this output to acknowledge the DMA transaction on the bus.

External Data Bus Grant 3

The MSC8113 asserts this pin to grant data bus ownership to an external bus master.

Interrupt Request 5

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

System Bus Data Parity 5

The agent that drives the data bus al so drives the data parity si gnals. The va lue driven on the data parity 5 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 5 and D[40–47].

DMA Acknowledge 4

The DMA drives this output to acknowledge the DMA transaction on the bus.

EXT_BG3

IRQ6

DP6

DREQ3

IRQ7

DP7

DREQ4

Output

Input

Input/

Output

Input

Input/

Output

Input

External Bus Grant 3

The MSC8113 asserts this pin to grant bus ownership to an external bus.

Interrupt Request 6

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

System Bus Data Parity 6

The agent that drives the data bus al so drives the data parity si gnals. The va lue driven on the data parity 6 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 6 and D[48–55].

DMA Request 3

Used by an external peripheral to request DMA service.

Interrupt Request 7

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

System Bus Data Parity 7

The agent that drives the data bus al so drives the data parity si gnals. The va lue driven on the data parity 7 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 7 and D[56–63].

DMA Request 4

Used by an external peripheral to request DMA service.

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Table 3-5. DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name Type Description

TA Input/

Output

TEA

NMI

NMI_OUT

PSDVAL Input/

Input/

Output

Input Non-Maskable Interrupt

Output Non-Maskable Interrupt Output

Output

Transfer Acknowledge

Indicates that a data beat is valid on the data bus. For single-beat transfers, TA indicates the termination of the transfer. For burst transfers, TA indicate the transfer of eight data beats, with the last assertion indicating the termination of the burst transfer.

Transfer Error Acknowledge

Assertion indicates a failure of the data tenure transaction.The masters within the MSC8113 monitor the state of this pin. The MSC8113 internal bus monitor can assert this pin if it identifies a bus transfer that does not complete.

When an external device asserts this line, it generates an non-maskable interrupt in the MSC8113, which is processed internally (default) or is directed to an external host for processing (see NMI_OU T

An open-drain pin driven from the MSC8113 internal interrupt controller. Assertion of this output indicates that a non-maskable interrupt is pending in the MSC8113 internal interrupt controller, waiting to be handled by an external host.

Port Size Data Valid

Indicates that a data b eat is vali d on th e data bus. The di fferenc e betw een th e T A PSDVAL PSDVAL always asserted. However, when PSDVAL example, if the DMA initiate s a doubl e word (2 × 64 bits) transaction to a memory devi ce wi th a 32-bit port size, PSDVAL is asserted three times without TA and, finally, both pins are asserted to terminate the transfer.

pin is that the TA pin is asserted to indicate data transfer terminations, while the signal is asserted wit h each data be at moveme nt. When T A is asserted, PSDVAL is

is asserted, TA is not necessarily asserted. For

is asserted eight times to

assertion

pin and the

IRQ7

INT_OUT

Notes: 1. See the System Interface U n it (SIU) chapter in the MSC8113 Reference Manual for deta ils o n ho w to c onfigure

these pins.

2. When used as the bus control arbiter, the MSC8113 can support up to three externa l bus master s. Each master uses its own set of Bus Request, Bus Grant, and Data Bus Grant signals (BR EXT_BR2 configured to indicate whether the external master is or is not a MSC8113 master device. See the Bus Configuration Register (BC R) descrip tion in the System Int erface Unit (SI U) chapte r in the MSC8113 Reference Manual for details on how to configure these pins. The second and third set of pins is defined by EXT_xxx to indicate that they can only be used with external master devices. The first set of pins (BR function. When the MSC8113 is no t the b us arb iter, i t uses th ese s ignal s (B R of the bus.

Input

Output

/EXT_BG2/EXT_DBG2, and EXT_BR3/EXT_BG3/EXT_DBG3). Each of these signal sets must be

Interrupt Request 7

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

Interrupt Output

Assertion of this output indicates that an unmasked interrupt is pending in the MSC8113 internal interrupt controller.

/BG/DBG,

/BG/DBG) have a dual

/BG/DBG) to obtain master control

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External Signals

3.5 Memory Controller Signals

Refer to the Memory Controller chapter in the MSC8113 Reference Manual for details on configuring these signals.

Table 3-6. Memory Controller Signals

Signal Name Type Description

BCTL0

BCTL1

CS5

BM[0–2]

TC[0–2]

BNKSEL[0–2]

ALE Output Address Latch Enable

PWE[0–3]

PSDDQM[0–3]

Output System Bus Buffer Control 0

Controls buffers on the data bus. Usually used with BCTL1 defined by the value of SIUMCR[BCTLC].

Output

Input

Input/

Output Output

Output

System Bus Buffer Control 1

Controls buffers on the data bus. Usually used with BCTL0 defined by the value of SIUMCR[BCTLC].

System and Local Bus Chip Select 5

Enables specific memory devices or peripherals connected to MSC8113 buses.

Boot Mode 0–2

Defines the boot mode of the MSC8113. This signal is sampled on PORESET

Transfer Code 0–2

The bus master drives these pins during the address tenure to specify the type of the code.

Bank Select 0–2

Selects the SDRAM bank when the MSC8113 is in 60x-compatible bus mode.

Controls the external address latch used in an external master bus.

System Bus Write Enable

Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte lanes for write operations.

System Bus SDRAM DQM

From the SDRAM control machine. These pins select specific byte lanes of SDRAM devices.

. The exact function of this pin is

deassertion.

System Bus UPM Byte Select

PBS[0–3]

PSDA10

PGPL0

PSDWE

PGPL1

3-16 Freescale Semiconductor

Output

System Bus SDRAM A10

From the bus SDRAM controller. The precharge command defines which bank is precharged. When the row address is driven, it is a part of the row address. When column address is driven, it is a part of column address.

System Bus UPM General-Purpose Line 0

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM.

System Bus SDRAM Write Enable From the bus SDRAM controller. Should connect to SDRAM WE input.

System Bus UPM General-Purpose Line 1

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM.

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Table 3-6. Memory Controller Signals (Continued)

Signal Name Type Description

Memory Controller Signals

POE

PSDRAS

PGPL2

PSDCAS

PGPL3

PGTA

PUPMWAIT

PGPL4

Output

Input

Output

System Bus Output Enable

From the bus GPCM. Controls the output buffer of memory devices during read operations. System Bus SDRAM RAS

From the bus SDRAM controller. Should connect to SDRAM RAS input.

System Bus UPM General-Purpose Line 2

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM.

System Bus SDRAM CAS From the bus SDRAM controller. Should connect to SDRAM CAS input.

System Bus UPM General-Purpose Line 3

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM.

System GPCM TA

Terminates external transactions during GPCM operation. Requires an external pull-up resistor for proper operation.

System Bus UPM Wait

An external device holds this pin low to force the UPM to wait until the device is ready to continue the operation.

System Bus UPM General-Purpose Line 4

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM.

PPBS

PSDAMUX

PGPL5

Output

System Bus Parity Byte Select

In systems that store data parity in a separate chip, this output is used as the byte-select for that chip.

System Bus SDRAM Address Multiplexer

Controls the system bus SDRAM address multiplexer when the MSC8113 is in external master mode.

System Bus UPM General-Purpose Line 5

One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM.

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External Signals

3.6 GPIO, TDM, UART, and Timer Signals

The general-purpose input/output (GPIO), time-division multiplexed (TDM), universal asynchronous receiver/transmitter (UART), and timer signals are grouped together because they use a common set of signal lines. Individual assignment of a signal to a specific signal line is configured through internal registers. Table 3-7 describes the signals in this group.

Table 3-7. GPIO, TDM, UART, Ethernet, and Timer Signals

Signal Name Type Description

GPIO0

CHIP_ID0

IRQ4

ETHTXD0

GPIO1

TIMER0

CHIP_ID1

Input/

Output

Input

Output

Input/

Output

Input/

Output

Input

General-Purpose Input Output 0

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

Chip ID 0 Determines the chip ID of the MSC8113 DSI. It is sampled on the rising edge of PORESET signal.

Interrupt Request 4

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.

Ethernet Transmit Data 0

For MII or RMII mode, bit 0 of the Ethernet transmit data.

General-Purpose Input Output 1

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

Timer 0

Each signal is configured as either input to or output from the counter. For details, see

Chapter 22, Timers. Chip ID 1

Determines the chip ID of the MSC8113 DSI. It is sampled on the rising edge of PORESET signal.

IRQ5

ETHTXD1

3-18 Freescale Semiconductor

Input

Output

Interrupt Request 5

One of the fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.

Ethernet Transmit Data 1

For MII or RMII mode, bit 1 of the Ethernet transmit data.

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Table 3-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)

Signal Name Type Description

GPIO, TDM, UART, and Timer Signals

GPIO2

TIMER1

CHIP_ID2

IRQ6

GPIO3

TDM3TSYN

IRQ1

Input/

Output

Input/

Output

Input

Input/

Output

Input/

Output

Input

General-Purpose Input Output 2

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

Timer 1 Each signal is configured as either input to or output from the counter. For details, see

Chapter 22, Timers.

Chip ID 2

Determines the chip ID of the MSC8113 DSI. It is sampled on the rising edge of PORESET signal.

Interrupt Request 6

One of the fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.

General-Purpose Input Output 3

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

TDM3 Transmit Frame Sync Transmit frame sync for TDM 3. See Chapter 20, TDM Interface.

Interrupt Request 1

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

ETHTXD2

Reserved

GPIO4

TDM3TCLK

IRQ2

ETHTX_ER

Output

Input/

Output

Input

Output

Ethernet Transmit Data 2

For MII mode only, bit 2 of the Ethernet transmit data. In RMII or SMII mode, this signal is reserved and can be left unconnected.

General-Purpose Input Output 4

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

TDM3 Transmit Clock Transmit Clock for TDM 3. For configuration details, see Chapter 20, TDM Interface.

Interrupt Request 2

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

Ethernet Transmit Data Error

For MII mode only, indicates whether a transmit data error occurred.

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External Signals

Table 3-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)

Signal Name Type Description

GPIO5

TDM3TDAT

IRQ3

ETHRXD3

Reserved

GPIO6

TDM3RSYN

IRQ4

Input/

Output

Input/

Output

Input

Input/

Output

Input/

Output

Input

General-Purpose Input/Output 5

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

TDM3 Serial Transmitter Data

The serial transmit data signal for TDM 3. As an output, it provides the DATA_D signal for TDM 3. For configuration details, see Chapter 20, TDM Interface.

Interrupt Request 3

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

Ethernet Receive Data 3

For MII mode only, bit 3 of the Ethernet receive data. For RMII or SMII mode, this pin is reserved and can be left unconnected.

General-Purpose Input Output 6

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

TDM3 Receive Frame Sync

The receive sync signal for TDM 3. As an input, this can be the DATA_B data signal for TDM

3. For configuration details, see Chapte r 20, TDM Interface.

Interrupt Request 4

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

ETHRXD2

Reserved

GPIO7

TDM3RCLK

IRQ5

ETHTXD3

Reserved

Input

Input/

Output

Input/

Output

Input

Output

Ethernet Receive Data 2

For MII mode only, bit 2 of the Ethernet receive data. For RMII or SMII mode, this pin is reserved and can be left unconnected.

General-Purpose Input Output 7

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

TDM3 Receive Clock

The receive clock s ignal for T DM 3. As an output, t his can be th e DATA_C data signal for TDM

3. For configuration details, see Chapte r 20, TDM Interface.

Interrupt Request 5

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

Ethernet Transmit Data 3

For MII mode only, bit 3 of the Ethernet transmit data. For RMII or SMII mode, this pin is reserved and can be left unconnected.

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Table 3-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)

Signal Name Type Description

GPIO, TDM, UART, and Timer Signals

GPIO8

TDM3RDAT

IRQ6

ETHCOL

Reserved

GPIO9

TDM2TSYN

IRQ7

Input/

Output

Input/

Output

Input

Input/

Output

Input/

Output

Input

General-Purpose Input Output 8

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

TDM3 Serial Receiver Data

The receive data signal for TDM 3. As an input, this can be the DATA_A data signal for TDM

3. For configuration details, see Chapte r 20, TDM Interface.

Interrupt Request 6

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

Ethernet Collision

For MII mode only, indicates whether a collision was detected. For RMII or SMII mode, this pin is reserved and can be left unconnected.

General-Purpose Input Output 9

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

TDM2 Transmit frame Sync Transmit Frame Sync for TDM 2. For configuration details, see Chapter 20, TDM Interface.

Interrupt Request 7

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

ETHMDIO

GPIO10

TDM2TCLK

IRQ8

ETHRX_DV

ETHCRS_DV

Input/

Output

Input/

Output

Input

Ethernet Management Data

Station management data input/output line in MII, RMII, and SMII modes.

General-Purpose Input Output 10

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

TDM 2 Transmit Clock Transmit Clock for TDM 2. For configuration details, see Chapter 20, TDM Interface.

Interrupt Request 8

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

Ethernet Receive Data Valid

In MII mode, this signal indicates that the receive data is valid.

Ethernet Carrier Sense/Receive Data Valid

In RMII mode, this signal indicates that a carrier is sense or that the receive data is valid.

Not Connected

For SMII mode, this signal must be left unconnected.

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External Signals

Table 3-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)

Signal Name Type Description

GPIO11

TDM2TDAT

IRQ9

ETHRX_ER

ETHTXD

GPIO12

TDM2RSYN

IRQ10

Input/

Output

Input/

Output

Input

Output

Input/

Output

Input/

Output

Input

General-Purpose Input Output 11

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

TDM2 Serial Transmitter Data

The transmit data sig nal for TDM 2 . As an outp ut, this can b e the DATA_ D data sign al for TDM

2. For configuration details, see Chapte r 20, TDM Interface.

Interrupt Request 9

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

Ethernet Receive Data Error

In MII and RMII modes indicates that a receive data error occurred.

Ethernet Transmit Data

In SMII, used as the Ethernet transmit data line.

General-Purpose Input Output 12

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

TDM2 Receive Frame Sync

The receive sync signal for TDM 2. As an input, this can be the DATA_B data signal for TDM

2. For configuration details, see Chapte r 20, TDM Interface.

Interrupt Request 10

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

ETHRXD1

ETHSYNC

GPIO13

TDM2RCLK

IRQ11

ETHMDC

Input

Output

Input/

Output

Input/

Output

Input

Output

Ethernet Receive Data 1

In MII or RMII mode, bit 1 of the Ethernet receive data.

Ethernet Sync Signal

In SMII mode, this is the SMII sync signal.

General-Purpose Input Output 13

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

TDM2 Receive Clock

The receive clock signal for TDM 2. As an input, this can be the DATA_C data signal for TDM

2. For configuration details, see Chapte r 20, TDM Interface.

Interrupt Request 11

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

Ethernet Management Clock

Used for the MDIO reference clock for MII, RMII, and SMII modes.

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Table 3-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)

Signal Name Type Description

GPIO, TDM, UART, and Timer Signals

GPIO14

TDM2RDAT

IRQ12

ETHRXD0

GPIO15

TDM1TSYN

DREQ1

Input/

Output

Input/

Output

Input Input

Input

Input/

Output

Input/

Output

Input

General-Purpose Input Output 14

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

TDM2 Serial Receiver Data

The receive data signal for TDM 2. As an input, this can be the DATA_A data signal for TDM

2. For configuration details, see Chapte r 20, TDM Interface.

Interrupt Request 12

One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140.

Ethernet Receive Data 0

Bit 0 of the Ethernet receive data (MII and RMII).

Not Connected

For SMII mode, this signal must be left unconnected.

General-Purpose Input Output 15

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

TDM1 Transmit frame Sync Transmit Frame Sync for TDM 1. For configuration details, see Chapter 20, TDM Interface.

DMA Request 1

Used by an external peripheral to reque st DMA servic e.

GPIO16

TDM1TCLK

DONE1

DRACK1

GPIO17

TDM1TDAT

Input/

Output

Input

Input/

Output

Input/

Output

Input/

Output

General-Purpose Input Output 16

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

TDM1 Transmit Clock Transmit Clock for TDM 1. For configuration details, see Chapter 20, TDM Interface.

DMA Done 1

Signifies that the channel must be terminated. If the DMA generates DONE handling this peripheral is inactive. As an input to the DMA, DONE like a normal channel closing.

See the MSC8113 Reference Manual chapters on DMA and GPIO for information on configuring the DRACK

DMA Data Request Acknowledge 1

Asserted by the DMA co ntrolle r to ind icate that th e DMA c ontroll er has samp led the periph eral request.

General-Purpose Input Output 17

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

TDM1 Serial Transmitter Data

The transmit data sig nal for TDM 1 . As an outp ut, this can b e the DATA_ D data sign al for TDM

1. For configuration details, see Chapte r 20, TDM Interface.

or DONE mode and pin direction.

closes the channel much

, the channel

DACK1

Freescale Semiconduc tor 3-23

Output

DMA Acknowledge 1

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

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External Signals

Table 3-7. GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)

Signal Name Type Description

GPIO18

TDM1RSYN

DREQ2

GPIO19

TDM1RCLK

DACK2

GPIO20

TDM1RDAT

Input/

Output

Input/

Output

Input

Input/

Output

Input/

Output

Input/

Output

Input/

Output

General-Purpose Input Output 18

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

TDM1 Receive Frame Sync

The receive sync signal for TDM 1. As an input, this can be the DATA_B data signal for TDM

1. For configuration details, see Chapte r 20, TDM Interface.

DMA Request 1

Used by an external peripheral to reque st DMA servic e.

General-Purpose Input Output 19

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

TDM1 Receive Clock

The receive clock signal for TDM 1. As an input, this can be the DATA_C data signal for TDM

1. For configuration details, see Chapte r 20, TDM Interface.

DMA Acknowledge 2

The DMA controller drives this output to acknowledge the DMA transaction on the bus.

General-Purpose Input Output 20

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

TDM1 Serial Receiver Data

The receive data signal for TDM 1. As an input, this can be the DATA_A data signal for TDM

1. For configuration details, see Chapte r 20, TDM Interface.

GPIO21

TDM0TSYN

GPIO22

TDM0TCLK

DONE2

DRACK2

Input/

Output

Input/

Output

Input/

Output

Input

Input/

Output

General-Purpose Input Output 21

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

TDM0 Transmit frame Sync Transmit Frame Sync for TDM 0. For configuration details, see Chapter 20, TDM Interface.

General-Purpose Input Output 22

One of 32 GPIO pins used as GPIO o r a s on e o f two dedicated inputs or one of t wo d edi ca ted outputs. For details, see Chapter 23, GPIO.

TDM 0 Transmit Clock Transmit Clock for TDM 0. For configuration details, see Chapter 20, TDM Interface.

DMA Done 2

Signifies that the channel must be terminated. If the DMA generates DONE, the channel handling this peripheral is inactive. As an input to the DMA, DONE closes the channe l much like a normal channel closing.

Note: See the MSC8113 Reference Manual c hapters on DMA an d GPIO for in formati on on

configuring the DRACK

DMA Data Request Acknowledge 2

Asserted by the DMA co ntrolle r to ind icate that th e DMA c ontroll er has samp led the periph eral request.

or DONE mode and pin direction.

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