NXP Semiconductors MPT612 User Manual

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Rev. 1 — 16 December 2011 User manual

Document information

Info Content Keywords ARM, ARM7, embedded, 32-bit, MPPT, MPT612 Abstract This document describes all aspects of the MPT612, an IC designed for

applications using solar photovoltaic (PV) cells, or fuel cells.

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Revision history

Rev Date Description

1 20111216 initial version

Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

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1. Introduction

The MPT612 is the first dedicated IC perf or min g Maximum Power Point Tracking (MPPT) designed for applications using solar photovoltaic (PV) cells, or fuel cells. To simplify development and maximize system efficiency, the MPT612 is supported by:

• a patent-pending MPPT algorithm

• an application-specific software library

• easy-to-use application programming interfaces ( A PIs)

Dedicated hardware functions for PV panels, including voltage and current measurement and panel parameter configuration, simplify design and speed development.

MPT612 is based on a low-power ARM7TDMI-S RISC core operating up to 70 MHz achieving overall system efficiency ratings up to 98 %. It controls the external switching device through a signal derived from a patent-pending MPPT algorithm which delivers up to 99.5% Maximum Power Point Tra cking (MPPT) efficiency. The solar PV DC source can be connected to the IC through appropriate voltage and current sensors. The IC dynamically extracts the maximum power from the PV panel without user intervention when enabled. The IC can be configured for boundar y conditions set in so ft ware. Ther e is up to 15 kB of flash memory available for application software.

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2. Features

In this user manual, solar PV terminology is primarily used as an example. However, the MPT612 is equally useful for fuel cells or any other DC source which has MPP characteristics.

• ARM7TDMI-S 32-bit RISC core operating at up to 70 MHz

• 128-bit wide interface and accelerator enabling 70 MHz operation

• 10-bit ADC providing:

– Conversion times as low as 2.44 s per channel and dedicated result registers

minimize interrupt overhead

– Five analog inputs available for user-specific applications

• One 32-bit timer and external event counter with four capture and four compare

channels

• One 16-bit timer and external event counter with four compare channels

• Low-power Real-Time Clock (RTC) with independent power supply and dedicated

32 kHz clock input

• Serial interfaces including:

– Two UARTs (16C550)

– Two Fast I – SPI and SSP with buffering and variable data length capabilities

C-buses (400 kbit/s)

• Vectored interrupt controller with configurable priorities and vector addresses

• Up to 28, 5 V-tolerant fast general-purpose I/O pins

• Up to 13 edge- or level-sensitive external interrupt pins available

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• Three levels of flash Code Read Protection (CRP)

• 70 MHz maximum clock available from programmable on-chip PLL with input

• Integrated oscillator operates with an external crystal at between 1 MHz and 25 MHz

• Power-saving modes include:

• Individual enabling/disabling of periph eral fu nct i ons an d pe rip h er al clo ck sca ling for

• Processor wake-up from Power-down and Deep po wer-down mode using an extern al

• In-System/In-Application Programming (ISP/IAP) via on-chip bootloader software.

3. Applications

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frequencies between 10 MHz and 25 MHz and a settling time of 100 ms

– Idle mode – Two Power-down modes; one with the RTC active and with the RTC deactivated

additional power optimization

interrupt or the RTC

Single flash sector or full chip erase in 100 ms and programming of 256 bytes in 1 ms

• Battery charge controller for solar PV power and fuel-cells. The use cases are

– Battery charging for home appliances such as lighting, DC fans, DC TV , DC motors

or any other DC appliance

– Battery charging for public lighting and signaling, such as: LED street lighting,

garden/driveway lighting, dusk-to-dawn lighting, railway signaling, traffic signaling, remote telecom terminals/towers

– Battery charging for portable devices

• DC-to-DC converter per panel to provide improved efficiency

• Micro inverter per panel removes the need for one large system inverter

4. Device information

Table 1. MPT612 device information

Type number Flash memory RAM ADC Temperature

MPT612FBD48 32 kB 8 kB 8 inputs 40 to +85

5. Architectural overview

The MPT612 comprises:

range (C)

• ARM7TDMI-S CPU with emulation support

• ARM7 Local Bus for interface to on-chip memory controllers

• AMBA Advanced High-performance Bus (AHB) to interface the interrupt controller

• ARM Peripheral Bus (APB, a compatible superset of ARM AMBA Advanced

Peripheral Bus) for connecting on-chip peripheral functions

The MPT612 configures the ARM7TDMI-S processor core in little endian byte order.

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AHB peripherals are allocated a 2 MB range of addresses at the top of the 4 GB ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the AHB address space. A pin connect block controls on-chip peripheral connections to device pins (see Section 12.4 “ application requirements for the use of peripheral functions and pins.

5.1 ARM7TDMI-S processor

The ARM7TDMI-S is a general purpose 32-bit processor core offering high performance and very low-power consumption. The ARM architecture is based on Red uced Instruction Set Computer (RISC) principles making the instruction set and decode mechanisms much simpler than micro programmed Complex Instruction Set Computers (CISC). This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small, cost-effective processor core.

Pipeline techniques are employed ensuring all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded and a third instruction is being read from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb making it suitable for high-volume applications with memory restrictions, or applications where code density is an issue.

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The key idea behind Thumb is a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:

• the standard 32-bit ARM set

• the 16-bit Thumb set

The Thumb 16-bit instruction sets allow up to twice the density of standard ARM code while retaining most of the performance advantage of ARM over a traditional 16-bit processor using 16-bit registers, made possible using the ARM code 32-bit register set.

Thumb code provides up to 65 % of standar d ARM code and 16 0 % of the perfo rmance of an equivalent ARM processor connected to a 16-bit memory system.

The particular flash implementation in the MPT612 also allows full speed execution in ARM mode. Programming performance-critical and short code sections in ARM mode is recommended. The impact on the overall code size is minimal but the speed can increase by 30 % over Thumb mode.

5.2 On-chip flash memory system

The MPT612 incorporates a 32 kB flash memory system. This memory can be used for both code and data storage. V ari ous methods can be used to program flash memory, such as using:

• the built-in JTAG interface

• In Systems Programming (ISP)

• UART

• In Application Programming (IAP)

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The application program can erase and/or program flash memory while the application is running using IAP, allowing greater flexibility, for example, data storage field firmware upgrades. The entire flash memory is available for user code as the bootloader resides in a separate memory.

The MPT612 flash memory provides a minimum of 100 000 erase/write cycles and 20 years of data-retention memory.

5.3 On-chip Static RAM (SRAM)

On-chip static RAM can be used for code and/or data storage. The SRAM can be accessed as 8-bit, 16-bit and 32-bit. The MPT612 provides 8 kB of static RAM.

6. Block diagram

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PV configuration parameters

MPT612

PV voltage sense

PV current sense

battery voltage sense

battery current sense

temperature sense

load current sense

PV VOLTAGE

MEASUREMENT

PV CURRENT

MEASUREMENT

BATTERY VOLTAGE

MEASUREMENT

BATTERY CURRENT

MEASUREMENT

TEMPERATURE

MEASUREMENT

LOAD CURRENT MEASUREMENT

these blocks are needed for MPPT functionality

these blocks can be used for customer specific applications

PV CONFIGURATION

BLOCK

MPPT ALGORITHM

BATTERY CHARGE

CYCLE ALGORITHM

BATTERY

CONFIGURATION BLOCK

LOAD MANAGEMENT

LOAD CONFIGURATION

BLOCK

load configuration

parameters

STATUS INDICATION

PROTECTION BLOCK

LOAD PROTECTION

battery configuration

parameters

SWITCH CIRCUIT

CONTROL

BATTERY

LEDs

PWM

battery

load

001aam089

Fig 1. MPT612 block diagram

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7. Memory addressing

7.1 Memory maps

The MPT612 incorporates several distinct memory regions, shown in Figure 2 to Figure 4.

Figure 2

viewpoint following reset. The interrupt vector area supports address remapping, which is described later in this section.

shows the overall map of the entire address space from the user program

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4.0 GB

AHB PERIPHERALS

3.75 GB

APB PERIPHERALS

3.5 GB

3.0 GB 0xC000 0000

RESERVED ADDRESS SPACE

2.0 GB 0x8000 0000

BOOT BLOCK

RESERVED ADDRESS SPACE

8 kB ON-CHI P STATI C RAM

0xFFFF FFFF

0xF000 0000

0xE000 0000

0x7FFF E000 0x7FFF DFFF

0x4000 2000 0x4000 1FFF

1.0 GB

0.0 GB

RESERVED ADDRESS SPACE

32 kB ON-CHIP NON-VOLATILE MEMORY

aaa-000568

0x4000 0000

0x0000 8000 0x0000 7FFF

0x0000 0000

Fig 2. System memory map

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4.0 GB

4.0 GB - 2 MB

3.75 GB

0xFFFF FFFF

AHB PERIPHERALS

0xFFE0 0000 0xFFDF FFFF

RESERVED

0xF000 0000 0xEFFF FFFF

RESERVED

3.5 GB + 2 MB

APB PERIPHERALS

3.5 GB

AHB section is 128  16 kB blocks (totaling 2 MB). APB section is 128  16 kB blocks (totaling 2 MB).

aaa-000569

0xE020 0000 0xE01F FFFF

0xE000 0000

Fig 3. Peripheral memory map

Figure 3, Figure 4, and Table 2 show different views of the peripheral address space. Both

the AHB and APB peripheral areas are 2 MB spaces which are divided up into 128 peripherals. Each peripheral space is 16 kB in size, simplifying address decoding for each peripheral. All peripheral register addresses are wor d aligned (to 32-bit boundaries) regardless of their size, eliminating the need for byte lane mapping hardware to allow b yte

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(8-bit) or half-word (16-bit) accesses at smaller boundarie s. This method requires all wo rd and half-word registers to be accessed at once. For example, it is not possible to read or write the upper byte of a word register separately.

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VECTORED INTERRUPT CONTROLLER

(AHB PERIPHERAL #126)

(AHB PERIPHERAL #125)

(AHB PERIPHERAL #124)

0xFFFF F000 (4G - 4K)

0xFFFF C000

0xFFFF 8000

0xFFFF 4000

0xFFFF 0000

0xFFE1 0000

(AHB PERIPHERAL #3)

(AHB PERIPHERAL #2)

(AHB PERIPHERAL #1)

(AHB PERIPHERAL #0)

Fig 4. AHB peripheral map

aaa-000570

0xFFE0 C000

0xFFE0 8000

0xFFE0 4000

0xFFE0 0000

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Table 2. APB peripheries and base addresses

APB peripheral Base address Peripheral name

0 0xE000 0000 Watchdog timer 1 0xE000 4000 reserved 2 0xE000 8000 Timer 1 3 0xE000 C000 UART0 4 0xE001 0000 UART1 5 0xE001 4000 not used 6 0xE001 8000 not used 7 0xE001 C000 I 8 0xE002 0000 SPI0 9 0xE002 4000 RTC 10 0xE002 8000 GPIO 11 0xE002 C000 pin connect block 12 0xE003 0000 not used 13 0xE003 4000 ADC 14 to 22 0xE003 8000

23 0xE005 C000 I 24 0xE006 0000 not used 25 0xE006 4000 not used 26 0xE006 8000 SSP 27 0xE006 C000 not used 28 0xE007 0000 reserved 29 0xE007 4000 Timer 3 30 to 126 0xE007 8000

127 0xE01F C000 system control block

0xE005 8000

0xE01F 8000

not used

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7.2 MPT612 memory remapping and boot block

7.2.1 Memory map concepts and operating modes

Basically, each memory area in the MPT612 has a "natural" location in the memory map, and is the address range for which code residing in that area is written. Most memory spaces remain permanently fixed in the same location, eliminating the need to design parts of the code to run in different address ranges.

Because of the ARM7 processor interrupt vector locations (at addresses 0x0000 0000 through 0x0000 001C, as shown in Table 3 spaces need remapping to allow alternative uses of interrupts in the different operating modes described in Table 4

. Remapping of the interrupts is accomplished via the memory

mapping control feature (Section 10.7 “

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), a small portion of the boot block and SRAM

Memory mapping control” on page 42).

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Table 3. ARM exception vector locations

Address Exception

0x0000 0000 reset 0x0000 0004 undefined instruction 0x0000 0008 software interrupt 0x0000 000C prefetch abort (instruction fetch memory fault) 0x0000 0010 data abort (data access memory fault) 0x0000 0014 reserved

0x0000 0018 IRQ 0x0000 001C FIQ

Table 4. MPT612 memory mapping modes

Mode Activation Usage

Boot loader mode

User flash mode

User RAM mode

hardware activation by any reset

software activation by boot code

software activation by user program

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Remark: Identified as reserved in ARM documentation, used by the

bootloader as the valid user program key. Details described in

Section 25.5.2 on pa ge 218

bootloader always executes after any reset. Boot block interrupt vectors are mapped to the bottom of memory to allow handling exceptions and using interrupts during the boot loading process.

activated by bootloader when a valid user program signature is recognized in memory and bootloader operation is not forced. Interrupt vectors are not remapped and are found at the bottom of the flash memory.

activated by a user program as desired. Interrupt vectors are remapped to the bottom of the static RAM.

7.2.2 Memory remapping

In order to allow for compatibility with future derivatives, the entire boot block is mapped to the top of the on-chip memory space. This arrangem en t avo id s larg er or sm alle r fla sh modules having to change the location of the boot block (which requires changing the bootloader code) or changing the boot block interrupt vector mapping. Memory spaces other than the interrupt vectors remain in fixed locations. Figure 5 memory mapping in the modes defined in Table 4

shows the on-chip

The portion of memory remapped to allow interrupt processing in different modes includes the interrupt vector area (32 bytes) and an additional 32 bytes for a total of 64 bytes. The remapped code locations overlay addresses 0x0000 0000 through 0x0000 003F. A typical user program in the flash memory can place the entire FIQ handler at address 0x0000 001C without any need to consider memory boundaries. The vector in the SRAM, external memory, and boot block, must contain branches to the interrupt handlers, or to other instructions that establish the branch to the interrupt handlers.

There are three reasons this configuration was chosen:

• To give the FIQ handler in the flash memory the advantage of not having to take a

memory boundary, caused by the remapping, into account.

• Minimize the need for the SRAM and boot block vectors to deal with arbitrary

boundaries in the middle of code space.

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aaa-000571

8 kB BOOT BLOCK

32 kB ON-CHIP FLASH MEMORY

0.0 GB

ACTIVE INTERRUPT VECTORS

FROM BOOT BLOCK

0x7FFF FFFF

2.0 GB - 8 kB

2.0 GB

(BOOT BLOCK INTERRUPT VECTORS)

0x0000 0000

0x0000 7FFF

0x7FFF E000

(SRAM INTERRUPT VECTORS)

ON-CHIP SRAM

8 kB ( 0x4000 2000)

RESERVED ADDRESS SPACE

1.0 GB

0x4000 0000

RESERVED ADDRESS SPACE

• To provide space to store constants, for jumping beyond the range of single word

Remapped memory areas, including the interrupt vectors, continue to appear in their original location in addition to the remapped address.

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branch instructions.

Details of remapping and examples can be found in Section 10.7 “

Memory mapping

control” on page 42.

Fig 5. Map of lower memory showing remapped and remappable areas (MPT612 with

32 kB flash)

7.3 Prefetch abort and data abort exceptions

If an access is attempted for an address that is in a reserved or unassigned address region, the MPT612 generates the appropriate bus cycle abort exception. The reg ions are:

• Areas of the memory map that are not implemented for a specific ARM derivative. Fo r

the MPT612: – Address space between on-chip Non-Volatile Memo ry and o n-ch ip SRAM, labe led

"Reserved Address Space" in Figure 2 from 0x0000 8000 to 0x3FFF FFFF.

– Address space between on-chip static RAM and the boot block. Labeled

"Reserved Address Space" in Figure 2 from 0x4000 2000 to 0x7FFF DFFF.

– Address space between 0x8000 0000 and 0xDFFF FFFF, labeled "Reserved

Address Space".

– Reserved regions of the AHB and APB spaces; see Figure 3

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• Unassigned AHB peripheral spaces; see Figure 4.

• Unassigned APB peripheral spaces; see Table 2.

. For this device, memory address range is

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For these areas, both attempted data acce ss and in struction fetch genera te an exception. In addition, a prefetch abort exception is generated for any instruction fetch tha t maps to an AHB or APB peripheral address.

Within the address space of an existing APB peripheral, a data abort exception is not generated in response to an access to an undefined address. Address decoding within each peripheral is limited to distinguish only defined registers within the peripheral itself. For example, an access to address 0xE000 D000 (an undefined address within the UART0 space) can result in a register access defined at address 0xE000 C000. Details of such address aliasing within a peripheral space are not defined in the MPT612 documentation and are not a supported feature.

Remark: the ARM core stores the prefetch abort flag and the (meaningless) associated instruction in the pipeline, and processes the abort only if an attempt is made to execute the instruction fetched from the illegal address. This method prevents accidental aborts caused by prefetches occurring when code is executed very close to a memory boundary.

8. Memory Acceleration Module (MAM)

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The MAM block in the MPT612 maximizes the performance of the ARM processor when it is running code in flash memory using a single flash bank.

8.1 Operation

Essentially, the Memory Accelerator Module (MAM) attempts to have the next ARM instruction that is needed in its latches in time to prevent CPU fetch stalls. The MPT612 uses one bank of flash memory, compared to the two banks used on predecessor devices. It includes three 128-bit buffers called the prefetch buffer, the branch trail buffer and the data buffer. The ARM is stalled while a fetch is initiated for the 128-bit line for an Instruction Fetch not satisfied by either the prefetch or branch trail buffer, or a prefetch not initiated for that line. If a prefetch is initiated but not yet completed, the ARM is stalled for a shorter time. Unless aborted by a dat a access, a prefetch is initi ated wh en th e flash has completed the previous access. The flash module latches the prefetched line, but the MAM does not capture the line in its prefetch buffer until the ARM core presents the address from which the prefetch is made. If the core present s a dif ferent addre ss from the one from which the prefetch is made, the prefetched line is discarded.

The prefetch and branch trail buffers each include four 32-bit ARM instructions or eight 16-bit Thumb instructions. During sequential code execution, typically the prefetch buffer contains the current instruction and the entire flash line that contains it.

The MAM uses the LPROT[0] line to differentiate between instruction and data accesses. Code and data accesses use separate 128-bit buffers. Three of every four sequential 32-bit code or data accesses "hit" in the buffer without requiring a flash access (7 of 8 sequential 16-bit accesses, 15 of every 16 sequential byte accesses). The fourth (eighth, 16th) sequential data access must access flash, aborting any prefetch in progress. When a flash data access is concluded, any prefetch in progress is re-initiated.

Timing of flash read operations is programmable and is described later in this section. There is no code fetch penalty for sequential instruction execution when the CPU clock

period is greater than or equal to one fourth of the flash access time. The average amount of time spent processing program branches is relatively small (less than 25 %) and can be

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minimized in ARM (rather than Thumb) code by using the conditional execution feature present in all ARM instructions. This conditional execution can often be used to avoid small forward branches that would otherwise be necessary.

Branches and other program flow changes cause a break in the sequential flow of instruction fetches previously described. The branch trail buf f er ca ptur es th e line to wh ich such a non-sequential break occurs. If the same branch is taken again, the next instruction is taken from the branch trail buffer. When a branch outside the contents of the prefetch and branch trail buffer is taken, the br anch trail buffer is loaded af ter several clock periods. Typically, there are no further instruction fetch delays until a new and different branch occurs.

8.2 MAM blocks

The MAM is divided into several functional bloc ks:

• A flash address latch and an incrementing function to form prefetch addresses

• A 128-bit prefetch buffer and an associated address latch and comparator

• A 128-bit branch trail buffer and an associated address latch and comparator

• A 128-bit data buffer and an associated address latch and comparator

• Control logic

• Wait logic

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Figure 6

In the following descriptions, the term “fetch” applies to an explicit flash read request from the ARM. “Pre-fetch” is used to denote a flash read of instructions beyond the current processor fetch address.

shows a simplified block diagram of the MAM data paths.

8.2.1 Flash memory bank

There is one bank of flash memory on the MPT612 MAM. Flash programming operations are handled as a separate function and not controlled by

the MAM. A separate boot block in ROM contains flash programming algorithms that can be called by the application program, and a loader that can be run to allow serial programming of flash memory.

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Fig 6. Simplified block diagram of the Memory Accelerator Module (MAM)

ARM LOCAL BUS

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MEMORY ADDRESS

FLASH MEMORY

BANK

BUS

INTERFACE

BUFFERS

aaa-000572

8.2.2 Instruction latches and data latches

The MAM treats code and data accesses separately. There is a 128-bit latch, a 15-bit address latch, and a 15-bit comparator associated with each buf fer (pre fetch, bran ch trail, and data). Each 128-bit latch holds 4 words (4 ARM instructions, or 8 Thumb instructions). Also associated with each buffer are 32 4:1 multiplexers that select the requested word from the 128-bit line.

Each data access that is not in the data latch causes a flash fetch of 4 words of data, which are captured in the data latch. This speeds up sequential data operations, but has little or no effect on random accesses.

8.2.3 Flash programming issues

Since the flash memory does not allow access dur ing programming and erase operation s, the MAM must force the CPU to wait if a memory access to a flash address is requested while the flash module is busy . Under some conditions, this delay can result in a watchdog time-out. You must ensure that an unwanted watchdog reset does not cause a system failure while programming or erasing the flash memory.

To preclude the possibility of stale data being read from the flash memory, the MPT612 MAM holding latches are automatically invalidated at the beginning of any flash programming or erase operation. Any subsequent read from a flash address initiates a new fetch after the flash operation has completed.

8.3 MAM operating modes

There are three MAM modes of operation defined, trading off performance for ease of predictability:

Mode 0: MAM off. All memory requests result in a flash read operation (see Table 5 note 2). No instruction prefetches are performed.

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Mode 1: MAM partially enabled. If the data is present, sequential instruction accesses

are fulfilled by the holding latches. Instruction prefetch is enabled. Non-sequential instruction accesses initiate flash read operations (see Table 5 all branches cause memory fetches. All data operations cause a flash read because buffered data access timing is hard to predict and is very situation-dependent.

Mode 2: MAM fully enabled. Any memory request (code or data) for a value that is contained in one of the corresponding holding latches is fulfilled from the latch. Instruction prefetch is enabled. Flash read operations are initiated for instruction prefetch and code or data values not available in the corresponding holding latches.

T able 5. MAM Responses to program accesses of various types

Program memory request type MAM mode

Sequential access, data in latches initiate fetch

Sequential access, data not in latches initiate fetch initiate fetch Non-sequential access, data in latches initiate fetch

Non-sequential access, data not in latches initiate fetch initiate fetch

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, note 2). This means that

0 1 2

[2]

use latched

[1]

data

[1]

[2]

initiate fetch

[1][2]

[1]

use latched

[1]

data initiate fetch use latched

[1]

data initiate fetch

[1]

[1] Instruction prefetch is enabled in modes 1 and 2. [2] If available, the MAM actually uses latched data, but mimics the timing of a flash read operation. This

method saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the fetch timing value in MAMTIM to one clock.

Table 6. MAM responses to data accesses of various types

Data memory request type MAM mode

0 1 2

Sequential access, data in latches initiate fetch

[1]

initiate fetch

[1]

use latched data Sequential access, data not in latches initiate fetch initiate fetch initiate fetch Non-sequential access, data in latches initiate fetch

[1]

initiate fetch

[1]

use latched data Non-sequential access, data not in latches initiate fetch initiate fetch initiate fetch

[1] If available, the MAM actually uses latched data, but it mimics the timing of a flash read operation. This

method saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the fetch timing value in MAMTIM to one clock.

8.4 MAM configuration

After reset the MAM defaults to the disabled state. Software can turn memory access acceleration on or off at any time. This method allows most of an application to be run at the highest possible performance, while certain functions can be run at a slower but more predictable rate if more precise timing is required.

8.5 Register description

All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function.

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T able 7. Summary of MAM registers

Name Description Access Reset

MAMCR MAM control register. Determines MAM functional

MAMTIM MAM timing control. Determines number of clocks

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

8.6 MAM Control register (MAMCR - 0xE01F C000)

Two configuration bits select the three MAM operating modes, as shown in Table 8. Following reset, MAM functions are disabled. Changing the MAM operating mode causes the MAM to invalidate all of the holding latches, resulting in new reads of flash information as required.

Table 8. MAMCR - address 0xE01F C000 bit description

Bit Symbol Value Description Reset

1:0 MAM_mode

7:2 - - reserved; user software must not write logic 1s to reserved

mode: to what extent the MAM performance enhancements are enabled; see Table 8

used for flash memory fetches (1 to 7 processor clocks).

00 MAM functions disabled 0

_control

01 MAM functions partially enabled 10 MAM functions fully enabled 11 reserved; not to be used in application

bits; value read from a reserved bit is not defined

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Address

[1]

value

R/W 0x0 0xE01F C000

R/W 0x07 0xE01F C004

value

n/a

8.7 MAM Timing register (MAMTIM - 0xE01F C004)

The MAM Timing register determines how many CCLK cycles are used to access the flash memory. This method allows tuning MAM timing to match the processor operating frequency. Flash access times from 1 clock to 7 clocks are possible. Single clock flash accesses removes the MAM from timing calculations. In this case, the MAM mode can be selected to optimize power usage.

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T able 9. MAM Timing register (MAMTIM - address 0xE01F C004) bit description

Bit Symbol Value Description Reset

2:0 MAM_fetch_

7:3 - - reserved; user software must not write logic 1s to reserve d

cycle_timing

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value

000 0 - reserved 07 001 1 - MAM fetch cycles are 1 processor clock (CCLK) in

duration 010 2 - MAM fetch cycles are 2 CCLKs in duration 011 3 - MAM fetch cycles are 3 CCLKs in duration 100 4 - MAM fetch cycles are 4 CCLKs in duration 101 5 - MAM fetch cycles are 5 CCLKs in duration 110 6 - MAM fetch cycles are 6 CCLKs in duration 111 7 - MAM fetch cycles are 7 CCLKs in duration Remark: these bits set duration of MAM flash fetch operations as

listed. Improper setting of values can result in incorrect operation of the device.

n/a

bits; value read from a reserved bit is not defined

8.8 MAM usage notes

When changing MAM timing, the MAM is turned off by writing a zero to MAMCR. A new value can then be written to MAMTIM. Finally, the MAM can be turned on again by writing a value (1 or 2) corresponding to the desired operating mode to MAMCR.

For a system clock slower than 20 MHz, MAMTIM can be 001. A suggested flash access time for a system clock between 20 MHz and 40 MHz is 2 CCLKs, while systems with a system clock faster than 40 MHz, 3 CCLKs are proposed. System clocks of 60 MHz and above require 4CCLKs.

Table 10. Suggestions for MAM timing selection

System clock Number of MAM fetch cycles in MAMTIM

< 20 MHz 1 CCLK 20 MHz to 40 MHz 2 CCLK 40 MHz to 60 MHz 3 CCLK > 60 MHz 4 CCLK

9. Vectored Interrupt Controller (VIC)

9.1 Features

• ARM PrimeCell Vectored Interrupt Controller

• 32 interrupt request inputs

• 16 vectored IRQ interrupts

• 16 priority levels dynamically assigned to interrupt requests

• Software interrupt generation

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9.2 Description

The Vector ed Interrupt Controller (VIC) t akes 32 interrupt request inputs and assigns th em to 3 categories, FIQ, vectored IRQ, and non-vectored IRQ. The programmable assignment scheme means that priorities of interrupt s from the va rious peripherals can be dynamically assigned and adjusted.

Fast Interrupt reQuest (FIQ) requests have the high est priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ because the FIQ service routine then deals with that device. If the FIQ class is assigned several requests, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) reques tin g an interr up t.

Vectored IRQs have the midd le priority, but only 16 of the 32 requests can be assigned to this category. Any of the 32 requests can be assigned to any of the 16 vectored IRQ slots where slot 0 has the highest priority and slot 15 the lowest.

Non-vectored IRQs have the lowest priority. The VIC ORs the requests from all the vectored and non-vectored IRQs to produce the

IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If a vectored IRQ is requesting, the VIC provides the address of the highest-priority requesting IRQ service routine, otherwise it provides the address of a default routine shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active.

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All registers in the VIC are word registers. Byte and halfword rea d/write are not suppo rted. Additional information on the Vectored Interrupt Controller is available in the ARM

PrimeCell Vectored Interrupt Controller (PL190) documentation.

9.3 Register description

The VIC implements the registers shown in Table 11. More detailed descriptions follow.

Table 11. VIC register map

Name Description Access Reset

VICIRQStatus IRQ status register. Reads out status of interrupt requests that are

VICFIQStatus FIQ status requests. Reads out status of interrupt requests that are

VICRawIntr raw interrupt status register. Reads out status of the 32 interrupt

VICIntSelect interrupt select register. Classifies each of the 32 interrupt requests

VICIntEnable interrupt enable register. Controls which of the 32 interrupt requests

VICIntEnClr interrupt enable clear register. Allows software to clear one or more

VICSoftInt software interrupt register. Contents of this register are ORed with

value

RO 0 0xFFFF F000

enabled and classified as IRQ.

RO 0 0xFFFF F004

enabled and classified as FIQ.

RO 0 0xFFFF F008

requests/software interrupts, regardless of enabling or classification.

R/W 0 0xFFFF F00C

contributing to FIQ or IRQ.

R/W 0 0xFFFF F010

and software interrupts are enabled to contribute to FIQ or IRQ.

WO 0 0xFFFF F014

bits in the interrupt enable register.

R/W 0 0xFFFF F018

the 32 interrupt requests from various peripheral functions.

Address

[1]

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Table 11. VIC register map

Name Description Access Reset

VICSoftIntClear software interrupt clear register. Allows software to clear one or more

bits in the software interrupt register.

VICProtection protection enable register. Allows limiting access to the VIC registers

by software running in privileged mode.

VICVectAddr vector address register. When an IRQ interrupt occurs, the IRQ

service routine can read this register and jump to the value read.

VICDefVectAddr default vector address register. Holds address of Interrupt Service

Routine (ISR) for non-vectored IRQs.

VICVectAddr0 vector address 0 register. Vector address registers 0 to 15 hold

addresses of ISRs for the 16 vectored IRQ slots. VICVectAddr1 vector address 1 register R/W 0 0xFFFF F104 VICVectAddr2 vector address 2 register R/W 0 0xFFFF F108 VICVectAddr3 vector address 3 register R/W 0 0xFFFF F10C VICVectAddr4 vector address 4 register R/W 0 0xFFFF F110 VICVectAddr5 vector address 5 register R/W 0 0xFFFF F114 VICVectAddr6 vector address 6 register R/W 0 0xFFFF F118 VICVectAddr7 vector address 7 register R/W 0 0xFFFF F11C VICVectAddr8 vector address 8 register R/W 0 0xFFFF F120 VICVectAddr9 vector address 9 register R/W 0 0xFFFF F124 VICVectAddr10 vector address 10 register R/W 0 0xFFFF F128 VICVectAddr11 vector address 11 register R/W 0 0xFFFF F12C VICVectAddr12 vector address 12 register R/W 0 0xFFFF F130 VICVectAddr13 vector address 13 register R/W 0 0xFFFF F134 VICVectAddr14 vector address 14 register R/W 0 0xFFFF F138 VICVectAddr15 vector address 15 register R/W 0 0xFFFF F13C VICVectCntl0 vector control 0 register. V ector control registers 0 to 15 each control

one of the 16 vectored IRQ slots. Slot 0 has highest priority and slot

15 the lowest. VICVectCntl1 vector control 1 register R/W 0 0xFFFF F204 VICVectCntl2 vector control 2 register R/W 0 0xFFFF F208 VICVectCntl3 vector control 3 register R/W 0 0xFFFF F20C VICVectCntl4 vector control 4 register R/W 0 0xFFFF F210 VICVectCntl5 vector control 5 register R/W 0 0xFFFF F214 VICVectCntl6 vector control 6 register R/W 0 0xFFFF F218 VICVectCntl7 vector control 7 register R/W 0 0xFFFF F21C VICVectCntl8 vector control 8 register R/W 0 0xFFFF F220 VICVectCntl9 vector control 9 register R/W 0 0xFFFF F224 VICVectCntl10 vector control 10 register R/W 0 0xFFFF F228 VICVectCntl11 vector control 11 register R/W 0 0xFFFF F22C VICVectCntl12 vector control 12 register R/W 0 0xFFFF F230

…continued

Address

[1]

value

WO 0 0xFFFF F01C

R/W 0 0xFFFF F020

R/W 0 0xFFFF F030

R/W 0 0xFFFF F034

R/W 0 0xFFFF F100

R/W 0 0xFFFF F200

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Table 11. VIC register map

Name Description Access Reset

VICVectCntl13 vector control 13 register R/W 0 0xFFFF F234 VICVectCntl14 vector control 14 register R/W 0 0xFFFF F238 VICVectCntl15 vector control 15 register R/W 0 0xFFFF F23C

[1] Reset value reflects the data stored in used bits only. It does not include content of reserved bits.

…continued

value

Address

[1]

9.4 VIC registers

The following section describes the VIC registers in the order in which they are used in the VIC logic, from the closest to the interrupt request inputs to the most abstracted for use by software. In most cases, it is the best order to read about the registers when learning the VIC.

9.4.1 Software interrupt register (VICSoftInt - 0xFFFF F018)

The contents of this register are ORed with the 32 interrupt requests from the various peripherals, before any other logic is applied.

Table 12. Software interrupt register (VICSoftInt - address 0xFFFF F 018) bit allocation

Reset value: 0x0000 0000

Bit 31 30 29 28 27 26 25 24 Symbol ----TIMER3reserved-Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 23 22 21 20 19 18 17 16 Symbol ----I2C1AD0-EINT2 Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 15 14 13 12 11 10 9 8 Symbol EINT1 EINT0 RTC PLL SSP/SPI1 SPI0 I2C0 - Access R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 Symbol UART1 UART0 TIMER1 reserved ARMCore1 ARMCore0 - WDT Access R/W R/W R/W R/W R/W R/W R/W R/W

Table 13. Software interrupt register (VICSoftInt - address 0xFFFF F018) bit description

Bit Symbol Value Description Reset

31:0 see Table 12

0 do not force interrupt request with this bit number; writing logic 0s to

bits in VICSoftInt has no effect (see VICSoftIntClear); see

Section 9.4.2

1 force interrupt request with this bit number

value

9.4.2 Software interrupt clear register (VICSoftIntClear - 0xFFFF F01C)

This register allows software to clear one or more bits in the software interrupt register, without having to read it first.

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Table 14. Software interrupt clear register (VICSoftIntClear - address 0xFFFF F01C) bit allocation

Reset value: 0x0000 0000

Bit 31 30 29 28 27 26 25 24 Symbol ----TIMER3reserved-Access WO WO WO WO WO WO WO WO Bit 23 22 21 20 19 18 17 16 Symbol ----I2C1AD0-EINT2 Access WO WO WO WO WO WO WO WO Bit 15 14 13 12 11 10 9 8 Symbol EINT1 EINT0 RTC PLL SSP/SPI1 SPI0 I2C0 - Access WO WO WO WO WO WO WO WO Bit 7 6 5 4 3 2 1 0 Symbol UART1 UART0 TIMER1 reserved ARMCore1 ARMCore0 - WDT Access WO WO WO WO WO WO WO WO

Table 15. Software interrupt clear register (VICSoftIntClear - address 0xFFFF F01C) bit description

Bit Symbol Value Description Reset

value

31:0 see Table 14

0 writing logic 0 leaves corresponding bit in VICSoftInt unchanged 0 1 writing logic 1 clears corresponding bit in software interrupt register,

releasing forced request

9.4.3 Raw interrupt status register (VICRawIntr - 0xFFFF F008)

This register is read only. It reads out the state of the 32 interrupt requests and software interrupts, regardless of enabling or classification.

Table 16. Raw interrupt status register (VICRawIntr - address 0xFFFF F008) bit allocation

Reset value: 0x0000 0000

Bit 31 30 29 28 27 26 25 24 Symbol ----TIMER3reserved-Access RO RO RO RO RO RO RO RO Bit 23 22 21 20 19 18 17 16 Symbol ----I2C1AD0-EINT2 Access RO RO RO RO RO RO RO RO Bit 15 14 13 12 11 10 9 8 Symbol EINT1 EINT0 RTC PLL SSP/SPI1 SPI0 I2C0 - Access RO RO RO RO RO RO RO RO Bit 7 6 5 4 3 2 1 0 Symbol UART1 UART0 TIMER1 reserved ARMCore1 ARMCore0 - WDT Access RO RO RO RO RO RO RO RO

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Table 17. Raw interrupt status register (VICRawIntr - address 0xFFFF F008) bit description

Bit Symbol Value Description Reset

value

31:0 see Table 16

0 does not assert hardware or software interrupt request with this bit

number

1 asserts hardware or software interrupt request with this bit number

9.4.4 Interrupt enable register (VICIntEnable - 0xFFFF F010)

This register is read/write accessible. It controls which of the 32 interrupt requests and software interrupts contribute to FIQ or IRQ.

Table 18. Interrupt enable register (VICIntEnable - address 0xFFFF F010) bit allocation

Reset value: 0x0000 0000

Table 19. Interrupt enable register (VICIntEnable - address 0xFFFF F010) bit description

Bit Symbol Description Reset

value

31:0 see Table 18

when this register is read, 1s indicate interrupt requests or software interrupts

enabled to contribute to FIQ or IRQ. when this register is written, 1s enable interrupt requests or software interrupts

to contribute to FIQ or IRQ, 0s have no effect. To disable interrupts, see

Section 9.4.5

and Table 21.

9.4.5 Interrupt enable clear register (VICIntEnClear - 0xFFFF F014)

This register is write only. It allows software to clear one or more bits in the interrupt enable register without having to read it first; see Section 9.4.4

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Table 20. Software interrupt clear register (VICIntEnClear - address 0xFFFF F014) bit allocation

Reset value: 0x0000 0000

Table 21. Software interrupt clear register (VICIntEnClear - address 0xFFFF F014) bit description

Bit Symbol Value Description Reset

value

31:0 see Table 20

0 writing logic 0 leaves corresponding bit in VICIntEnable unchanged 0 1 writing logic 1 clears corresponding bit in interrupt enable register,

disabling interrupts for this request

9.4.6 Interrupt select register (VICIntSelect - 0xFFFF F00C)

This register is read/write accessible. It classifies each of the 32 interrupt requests as contributing to FIQ or IRQ.

Table 22. Interrupt select register (VICIntSelect - address 0xFFFF F00C) bit allocation

Reset value: 0x0000 0000

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Table 23. Interrupt select register (VICIntSelect - address 0xFFFF F00C) bit description

Bit Symbol Value Description Reset

value

31:0 see Table 22

0 assigns interrupt request with this bit number to IRQ category 0 1 assigns interrupt request with this bit number to FIQ category

9.4.7 IRQ Status register (VICIRQStatus - 0xFFFF F000)

This register is read only. It reads out the state of those interrupt requests that are enabled and classified as IRQ. It does not differentiate between vectored and non-vectored IRQs.

Table 24. IRQ Status register (VICIRQStatus - address 0xFFFF F000) bit allocation

Reset value: 0x0000 0000

Table 25. IRQ Status register (VICIRQStatus - address 0xFFFF F000) bit description

Bit Symbol Description Reset

value

31:0 see Table 24

a bit read as logic 1 indicates a corresponding interrupt request being enabled,

classified as IRQ, and asserted

9.4.8 FIQ Status register (VICFIQStatus - 0xFFFF F004)

This register is read only. It reads out the state of those interrupt requests that are enabled and classified as FIQ. If more than one request is classified as FIQ, the FIQ service routine can read this register to see which request(s) is (are) active.

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Table 26. FIQ Status register (VICFIQStatus - address 0xFFFF F004) bit allocation

Reset value: 0x0000 0000

Bit 31 30 29 28 27 26 25 24 Symbol ----TIMER3reserved-Access RO RO RO RO RO RO RO RO Bit 23 22 21 20 19 18 17 16 Symbol ----I2C1AD0-EINT2 Access RO RO RO RO RO RO RO RO Bit 15 14 13 12 11 10 9 8 Symbol EINT1 EINT0 RTC PLL SSP/SPI1 SPI0 I2C0 -0 Access RO RO RO RO RO RO RO RO Bit 7 6 5 4 3 2 1 0 Symbol UART1 UART0 TIMER1 reserved ARMCore1 ARMCore0 - WDT Access RO RO RO RO RO RO RO RO

Table 27. FIQ Status register (VICFIQStatus - address 0xFFFF F004) bit description

Bit Symbol Description Reset

value

31:0 see Table 26

a bit read as logic 1 indicates a corresponding interrupt request being enabled,

classified as FIQ, and asserted

9.4.9 Vector control registers 0 to 15 (VICVectCntl0-15 0xFFFF F200 to 23C)

These registers are read/write accessible. Each controls one of th e 16 vectored IRQ slots. Slot 0 has the highest priority and slot 15 the lowest. Disabling a vectored IRQ slot in one of registers VICVectCn tl does not disable the interrupt itself, the interrupt is changed to the non-vectored form.

Table 28. Vector control registers 0 to 15 (VICVectCntl0 to 15 - 0xFFFF F200 to 23C) bit description

Bit Symbol Description Reset

4:0 int_request/

sw_int_assig

5 IRQslot_en if logic 1, enables vectored IRQ slot and can produce a unique ISR address

31:6 - reserved; user software must not write logic 1s to reserved bits; value read from

the number of interrupt requests or software interrupts assigned to this vectored IRQ slot. Software must not assign the same interrupt number to more than one enabled vectored IRQ slot, otherwise a lower numbered slot is used when interrupt request or software interrupt is enabled, classified as IRQ, and asserted.

when its assigned interrupt request or software interrupt is enabled, classified as IRQ, and asserted

a reserved bit is not defined

value

n/a

9.4.10 Vector address registers 0 to 15 (VICVectAddr0 to 15 0xFFFF F100 to 13C)

These registers are read/write accessible. They hold the addresses of the Interrupt Service routines (ISRs) for the 16 vectored IRQ slots.

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Table 29. Vector address registers 0 to 15 (VICVectAddr0 to 15 - addresses 0xFFFF F100 to 13C) bit description

Bit Symbol Description Reset value

31:0 IRQ_vector if an interrupt request or software interrupt is enabled, classified as IRQ,

asserted and assigned to an enabled vectored IRQ slot, the value from this register is used for the highest priority slot, and is provided when IRQ service routine reads vector address register -VICVectAddr; see Section 9.4.10

0x0000 0000

9.4.11 Default vector address register (VICDefVectAddr - 0xFFFF F034)

This register is read/write accessible. This register holds the address of the Interrupt Service routine (ISR) for non-vectored IRQs.

Table 30. Default vector address register (VICDefVectAddr - address 0xFFFF F034) bit description

Bit Symbol Description Reset value

31:0 IRQ_vector if an IRQ service routine reads the vector address register (VICVectAddr), and

0x0000 0000

no IRQ slot responds as described above, this address is returned

9.4.12 Vector address register (VICVectAddr - 0xFFFF F030)

This register is read/write accessible. When an IRQ interrupt occurs, the IRQ service routine can read this register and jump to the value read.

Table 31. Vector address register (VICVectAddr - address 0xFFFF F030) bit descriptio n

Bit Symbol Description Reset value

31:0 IRQ_vector if an interrupt request or software interrupt assigned to a vectored IRQ slot is

0x0000 0000 enabled, classified as IRQ and asserted, reading this register returns the address in this register for the highest priority (lowest-numbered) slot. Otherwise it returns the address in the default vector address register.

Writing to this register does not set the value for future reads from it. Instead, write to this register near the end of an ISR to update the priority hardware.

9.4.13 Protection enable register (VICProtection - 0xFFFF F020)

This register is read/write accessible. It controls access to the VIC registers by software running in User mode.

Table 32. Protection enable register (VICProtection - address 0xFFFF F020) bit description

Bit Symbol Value Description Reset

0 VIC_access 0 VIC registers can be accessed in User or Privileged mode 0

31:1 - reserved; user software must not write logic 1s to reserved bits;

value

1 VIC registers can only be accessed in Privileged mode

n/a

value read from a reserved bit is not defined

9.5 Interrupt sources

Table 33 lists the interrupt sources for each peripheral function. Each peripheral device

has one interrupt line connected to the Vectored Interrupt Controller, but can have several internal interrupt flags. Individual interrupt flags can represent more than one interrupt source.

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Table 33. Connection of interrupt sources to the Vectored Interrupt Controller (VIC)

Block Flag(s) VIC Channel # and Hex

mask

WDT Watchdog Interrupt (WDINT) 0 0x0000 0001

- reserved for software interrupts only 1 0x0000 0002 ARM Core EmbeddedICE, DbgCommRx 2 0x0000 0004 ARM Core EmbeddedICE, DbgCommTX 3 0x0000 0008

- reserved for internal use; do not modify 4 0x0000 0010 TIMER1 Match 0 to 3 (MR0, MR1, MR2, MR3)

5 0x0000 0020

Capture 0 to 3 (CR0, CR1, CR2, CR3)

UART0 Rx Line Status (RLS)

6 0x0000 0040 Transmit Holding Register Empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI)

UART1 Rx Line Status (RLS)

7 0x0000 0080 Transmit Holding Register Empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI)

- reserved 8 0x0000 0100

C0 SI (state change) 9 0x0000 0200

SPI0 SPI0 Interrupt Flag (SPI0F)

10 0x0000 0400 Mode Fault (MODF)

SPI1 (SSP) Tx FIFO at least half empty (TXRIS)

11 0x0000 0800 Rx FIFO at least half full (RXRIS) Receive Timeout condition (RTRIS) Receive overrun (RORRIS)

PLL PLL Lock (PLOCK) 12 0x0000 1000 RTC Counter Increment (RTCCIF)

13 0x0000 2000 Alarm (RTCALF)

System Control External Interrupt 0 (EINT0) 14 0x0000 4000

External Interrupt 1 (EINT1) 15 0x0000 8000 External Interrupt 2 (EINT2) 16 0x0001 0000 reserved 17 0x0002 0000

ADC A/D Converter 0 end of conversion 18 0x0004 0000

C1 SI (state change) 19 0x000 8 0000

- reserved 20-250x0010 0000 0x0200 0000

- reserved for internal use; do not modify 26 0x0400 0000

TIMER3 Match 0 - 3 (MR0, MR1, MR2, MR3) 27 0x0800 0000

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aaa-000573

FIQSTATUS

[31:0]

VECTIRQ0

HARDWARE

PRIORITY

LOGIC

IRQSTATUS

[31:0]

nVICFIQ

NonVectIRQ

non-vectored IRQ interrupt logic

priority0

nVICIRQ

VECTADDR0[31:0]

VECTIRQ1

VECTIRQ15

VECTADDR1[31:0]

VECTADDR15[31:0]

IRQ

address select for highest priority interrupt

VECTADDR

[31:0]

VICVECT ADDROUT [31:0]

DEFAULT

VECTADDR

[31:0]

priority15

priority2

priority1

VECTADDR

[31:0]

SOURCE

VECTCNTL[5:0]

ENABLE

vector interrupt0

vector interrupt1

vector interrupt 15

RAWINTERRUPT

[31:0]

INTSELECT

[31:0]

SOFTINT

[31:0]

INTENABLE

[31:0]

SOFTINTCLEAR

[31:0]

INTENABLECLEAR

[31:0]

VICINT SOURCE [31:0]

IRQSTATUS[31:0]

FIQSTATUS[31:0]

nVICFIQIN non-vectored FIQ interrupt logic

interrupt priority logic

interrupt request, masking and selection

nVICIRQIN VICV ECTADDRIN[31:0]

IRQ

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Fig 7. Block diagram of the Vectored Interrupt Controller (VIC)

9.6 Spurious interrupts

Spurious interrupt s are possib le in the ARM7TDMI based ICs such as the MPT612 due to asynchronous interrupt handling. The asynchronous character of the interrupt processing has its roots in the interaction of the core and the VIC. If the VIC sta te is changed between the moments when the core detects an interrupt, and the core actually processes an interrupt, problems can be generated.

Real-life applications can experience the fo llowing sc en arios:

1. VIC decides there is an IRQ interrupt and sends the IRQ signal to the core

2. Core latches the IRQ state

3. Processing continues for a few cycles due to pipelining

4. Core loads IRQ address from VIC

Furthermore, it is possible that the VIC state has changed during step 3. For example, VIC was modified so that the interrupt that triggered the sequence starting with step 1) is no longer pending, interrupt got disabled in the executed code. In this case, the VIC is not able to identify clearly the interrupt that generated the interrupt request, and as a result the VIC returns the default interrupt VicDefVectAddr (0xFFFF F034).

This potentially disastrous chain of events can be prevented in two ways:

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• Application code must be set up in a way to prevent the spurious interrupts from

• Correctly set up and test the VIC default handler.

9.6.1 Details and case studies on spurious interrupts

This chapter contains details that can be obtained from the official ARM website, FAQ section.

What happens if an interrupt occurs as it is being disabled? Applies to: ARM7TDMI If an interrupt received by the core during execution of an instruction disables interrupts,

the ARM7 family still takes the interrupt (IRQ or FIQ). For example, consider the following instruction sequence:

MRS r0, cpsr ORR r0, r0, #I_Bit:OR:F_Bit ;disable IRQ and FIQ interrupts MSR cpsr_c, r0

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occurring. Simple guarding of changes to the VIC cannot be enough since, for example, glitches on level-sensitive interrupts can also cause spurious interrupts.

If an IRQ interrupt is received during execut ion of the MSR instruction, then the behavior is as follows:

1. The IRQ interrupt is latched.

2. The MSR cpsr, r0 executes to completion setting both bit I and bit F in the CPSR.

3. The IRQ interrupt is taken because the core was committed to taking the interrupt exception before bit I was set in the CPSR.

4. The CPSR (with bit I and bit F set) is moved to the SPSR_IRQ.

This means that, on entry to the IRQ interrupt service routine, you can see the unusual effect that an IRQ interrupt has been taken while bit I in SPSR is set. In the example above, bit F is also set in both CPSR and SPSR. This means that FIQs are disabled upon entry to the IRQ service routine until explicitly re-enabled. The IRQ return sequence does not automatically re-enable FIQs.

Although the example shows both IRQ and FIQ interrupts be ing disabled, similar beha vior occurs when only one of the two interrupt types is being disabled. The core processes the IRQ after completing the MSR instruction which disables IRQs, and does not normally cause a problem, as an interrupt arriving one cycle earlier is expected to be taken. When the interrupt routine returns with an instruction like:

SUBS pc, lr, #4

the SPSR_IRQ is restored to the CPSR. The CPSR now has bit I and bit F set, and therefore execution continues with all interrupts disabled. However, problems can be caused in the following cases:

Problem 1: A particular routine maybe called as an IRQ handler, or as a regular subroutine. In the latter case, the system guarantees that IRQs have been disabled before the routine being called. The routine exploits this restriction to determine how it was called (by examining bit I of SPSR), and returns using the appropr iate instruction. If the routine is

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entered due to an IRQ being received when executing the MSR instruction which disables IRQs, then bit I is set in SPSR. The routine therefore assumes th at it could not have be en entered via an IRQ.

Problem 2: FIQs and IRQs are both disabled by the same write to the CPSR. In this case, if an IRQ is received during the CPSR write, FIQs are disabled for the execution time of the IRQ handler. This arrangement cannot be acceptable in a system where FIQs must not be disabled for more than a few cycles.

9.6.2 Workaround

There are 3 suggested workarounds. The one which is most appl icable depends up on the requirements of the particular system.

9.6.3 Solution 1: Test for an IRQ received during a write to disable IRQs

Add code similar to the following at the start of the interrupt routine.

SUB lr, lr, #4 ; Adjust LR to point to return STMFD sp!, {..., lr} ; Get some free legs MRS lr, SPSR ; See if we got an interrupt while TST lr, #I_Bit ; interrupts were disabled. LDMNEFD sp!, {..., pc}^ ; If so, just return immediately. ; The interrupt remains pending since we have not ; acknowledged it and is reissued when interrupts ; are next enabled. ; Rest of interrupt routine

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This code tests for the situation where the IRQ was received during a write to disable IRQs. If so, the code returns immediately - resulting in the IRQ not being acknowledged (cleared), and further IRQs being disabled.

In order to resolve the first issue, similar code can also be applied to the FIQ handler. This method is the recommended workaround, as it overcomes both prob lems mentioned

previously. However, in the case of problem two, it does add several cycles to the maximum length of time FIQs are disabled.

9.6.4 Solution 2: Disable IRQs and FIQs using separate writes to the CPSR

MRS r0, cpsr ORR r0, r0, #I_Bit ;disable IRQs MSR cpsr_c, r0 ORR r0, r0, #F_Bit ;disable FIQs MSR cpsr_c, r0

This arrangement is the best workaround where the maximum time for which FIQs are disabled is critical (it does not increase this time at all). However , it does not so lve problem one, and requires extra instructions at every point where IRQs and FIQs are disabled together.

9.6.5 Solution 3: Re-enable FIQs at the beginning of the IRQ handler

As the required state of all bits in the CPSR c field are known, this solution is efficiently achieved by writing an immediate value to CPSR_C, for example:

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MSR cpsr_c, #I_Bit:OR:irq_MODE ;IRQ must be disabled ;FIQ enabled ;ARM state, IRQ mode

This arrangement requires modification of only the IRQ handler, and FIQs can be re-enabled more quickly than by using workaround 1. However, use it only if the system can guarantee that FIQs are never disabled while IRQs are enabled. It does not address problem one.

9.7 VIC usage notes

If user code is running from an on-chip RAM and an application uses interrupts, interrupt vectors must be re-mapped to on-chip address 0x0. This method is necessary because all the exception vectors are at addresses 0x0 an d above, and easily achieved by configuring register MEMMAP (see Section 10.7.1 “

0xE01F C040)” on page 43) to User RAM mode. Link the application code so that

0x4000 0000 resides at the Interrupt Vector Table (IVT). Although multiple sources can be selected (VICIntSelect) to generate FIQ request, use

one dedicated interrupt service routine to service all available/present FIQ request(s). Therefore, if several interrupt sources are classified as FIQ, the FIQ interrupt service routine must read VICFIQStatus to decide based on this content what to do and how to process the interrupt request. However, it is recommended that only one interrupt source is classified as FIQ. Classifying more than one interrupt source as FIQ increases the interrupt latency.

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Memory mapping control register (MEMMAP -

Following the completion of the desired interrupt service routine, clearing of the interrupt flag on the peripheral level propagates corresponding bits in VIC registers (VICRawIntr, VICFIQStatus and VICIRQStatus). Also, before the next interrupt can be serviced, it is necessary that write is performed into register VICVectAddr before the return from interrupt is executed. This write clears the respective interrupt flag in the interna l inter rupt priority hardware.

In order to disable the interrupt at the VIC, clear the corresponding bit in register VICIntEnClr, which in turn clears the related bit in register VI CIntEnable. This also applies to the VICSoftInt and VICSoftIntClear in which VICSoftIntClear clears the respective bits in VICSoftInt. For example, VICSoftIntClear = 0x0000 0001 clears VICSoftInt = 0x0000 0005 if bit 0 must be cleared. Assign VICSoftIntClear = 0x0000 0000 before the new clear operation is next performed on the same bit in VICSoftInt by writing to VICSoftIntClear. Therefore writing logic 1 to any bit in register Clear has a one-time-effect in the destination register.

If the watchdog is enabled for interrupt on underflow or invalid feed sequence only, then there is no way of clearing the interrupt. The only way you can perform return from interrupt is by disabling the interrupt at the VIC (using VICIntEnClr).

Example:

Assuming that UART0 and SPI0 are generating interrupt requests that are classified as vectored IRQs (UART0 being on the higher level than SPI0), while UART1 and I generating non-vectored IRQs, the following is one possibility for VIC setup:

C are

VICIntSelect = 0x0000 0000 ; SPI0, I2C0, UART1 and UART0 are IRQ => ; bit10, bit9, bit7 and bit6=0

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VICIntEnable = 0x0000 06C0 ; SPI0, I2C0, UART1 and UART0 are enabled interrupts

; bit10, bit9, bit 7 and bit6=1 VICDefVectAddr = 0x... ; holds address at what routine for servicing ; non-vectored IRQs (that is, UART1 and I2C) starts VICVectAddr0 = 0x... ; holds address where UART0 IRQ service routine starts VICVectAddr1 = 0x... ; holds address where SPI0 IRQ service routine starts VICVectCntl0 = 0x0000 0026 ; interrupt source with index 6 (UART0) is enabled as ; the one with priority 0 (the highest) VICVectCntl1 = 0x0000 002A ; interrupt source with index 10 (SPI0) is enabled ; as the one with priority 1

After any IRQ requests (SPI0, I2C, UART0 or UART1) are made, the MPT612 redirects code execution to the address specified at location 0x0000 0018. For vectored and non-vectored IRQs the following instruction can be placed at 0x0000 0018:

LDR pc, [pc,#-0xFF0]

This instruction loads PC with the address that is present in register VICVectAddr.

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In case UART0, request is made, VICV ectAddr is identical to VICVectAddr0, while in case SPI0 request is made, the value from VICVectAddr1 is found here. If either UART0 or SPI0 have not generated an IRQ request but UART1 and/or I content of VICVectAddr is identical to VICDefVectAddr.

10. System control block

10.1 Summary of system control block functions

The system control block includes several system features and control registers for a number of functions that are not related to specific peripheral devices. These include:

• Crystal oscillator

• External interrupt inputs

• Miscellaneous system controls and status

• Memory mapping control

• PLL

• Power control

• Reset

• APB divider

• Wake-up timer

C are the reason, the

Each type of function has its own register(s) if any are required, and unwanted bits ar e defined as reserved in order to allow future expansion. Unrelated functions never share the same register addresses.

10.2 Pin description

Table 34 shows pins that are associated with system control block functions.

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Table 34. Pin summary

Pin name Pin

XTAL1 input crystal oscillator input: input to the oscillator and internal clock

XTAL2 output crystal oscillator output: output from the oscillator amplifier EINT0 input external interrupt input 0: active LOW/HIGH level or falling/rising edge

EINT1 input external interrupt input 1: see EINT0 description.

EINT2 input external interrupt input 2: see EINT0 description.

RESET

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Pin description

direction

generator circuits

general purpose interrupt input. Pin can be used to wake up the processor from Idle or Power-down modes.

pin PIO16 can be selected to perform EINT0 function.

pin PIO14 can be selected to perform EINT1 function. Remark: LOW level on pin PIO14 immediately after reset is considered

as external hardware request to start ISP command handler. see

Section 25.5 “

serial boot loader.

pin PIO15 can be selected to perform EINT2 function.

input external reset input: a LOW on this pin resets the chip changing I/O

ports and peripherals to their default states, and processor to start execution at address 0x0000 0000.

Description” on page 217 for more details on ISP and

10.3 Register description

All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function.

T able 35. Summary of system control registers

Name Description Access Reset

External interrupts

EXTINT external interrupt flag register R/W 0 0xE01F C140 INTWAKE interrupt wake-up register R/W 0 0xE01F C144 EXTMODE external interrupt mode register R/W 0 0xE01F C148 EXTPOLAR external interrupt polarity register R/W 0 0xE01F C14C

Memory mapping control

MEMMAP memory mapping control R/W 0 0xE01F C040

Phase-locked loop

PLLCON PLL control register R/W 0 0xE01F C080 PLLCFG PLL configuration register R/W 0 0xE01F C084 PLLSTAT PLL status register RO 0 0xE01F C088 PLLFEED PLL feed register WO NA 0xE01F C08C

Power control

PCON power control register R/W 0 0xE01F C0C0 PCONP power control for peripherals R/W 0x03BE 0xE01F C0C4

APB divider

APBDIV APB divider control R/W 0 0xE01F C100

value

[1]

Address

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T able 35. Summary of system control registers

Name Description Access Reset

Reset

RSIR reset source identification register R/W 0 0xE01F C180

Code security/debugging

CSPR code security protection register RO 0 0xE01F C184

Syscon miscellaneous registers

SCS system controls and status R/W 0 0xE01F C1A0

[1] Reset value reflects the data stored in used bits only. It does not include the content of reserved bits.

10.4 Crystal oscillator

The MPT612 onboard oscillator circuit supports external crystals in the range 1 MHz to 25 MHz. If the on-chip PLL system or the bootloader is used, the input clock frequency is limited to an exclusive range 10 MHz to 25 MHz.

The oscillator output frequency is called f referred to as CCLK for purposes such as rate equations found elsewhere in this document. f Refer to the Section 10.8 “ frequency limitations.

and CCLK are the same value unless the PLL is running and connected.

osc

…continued

[1]

value

and the ARM processor clock frequency is

osc

Address

Phase-Locked Loop (PLL)” on page 43 for details and

The onboard oscillator in the MPT612 can operate in one of two modes: slave mode and oscillation mode.

In slave mode, couple the input clock signal with a capacitor of 100 pF (C

in Figure 8,

drawing a), with an amplitude of at least 200 mV (RMS). Pin XTAL2 in this configuration can be left unconnected. If slave mode is selected, the f

signal of 50-to-50 duty cycle

osc

can range from 1 MHz to 25 MHz. External components and models used in oscillation mode are shown in Figure 8

drawings b and c, and in Table 36 only a crystal and the capacitors C fundamental mode oscillation (L, C Capacitance C

in Figure 8, drawing c, represents the parallel package capacitance and

must not be larger than 7 pF. Parameters f

. Since the feedback resistance is integrated on chip,

and CX2 must be connected externally in case of

and RS represent the fundamental frequency).

, CL, RS and CP are supplied by the crystal

manufacturer. Choosing an oscillation mode as an on-board oscillator mode of operation limits f

osc

clock

selection to 1 MHz to 25 MHz.

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MPT612

XTAL1 XTAL2

Clock

a) b) c)

MPT612

XTAL1 XTAL2

Xtal

< = >

aaa-000574

Fig 8. Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external

crystal model used for C

T able 36. Recommended values for C

evaluation

X1/X2

in oscillation mode (crystal and external

X1/X2

components parameters)

Fundamental oscillation frequency f

osc

Crystal load capacitance C

Maximum crystal

series resistance R

External load capacitors CX1,

CX2

1MHz to 5MHz 10 pF n/a n/a

20 pF n/a n/a 30 pF < 300  58 pF, 58 pF

5 MHz to 10 MHz 10 pF < 300  18 pF, 18 pF

20 pF < 300  38 pF, 38 pF 30 pF < 300  58 pF, 58 pF

10 MHz to 15 MHz 10 pF < 300  18 pF, 18 pF

20 pF < 220  38 pF, 38 pF 30 pF < 140  58 pF, 58 pF

15 MHz to 20 MHz 10 pF < 220  18 pF, 18 pF

20 pF < 140  38 pF, 38 pF 30 pF < 80  58 pF, 58 pF

20 MHz to 25 MHz 10 pF < 160  18 pF, 18 pF

20 pF < 90  38 pF, 38 pF 30 pF < 50  58 pF, 58 pF

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osc

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selection

Fig 9. f

osc

10.4.1 XTAL1 input

The input voltage to the on-chip oscillators is limited to 1.8 V. If a clock drives the oscillator in slave mode, it is recommended that the input is coupled through a capacitor with C 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground C minimum of 200 mV

which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a

MIN f

= 10 MHz

osc

= 25 MHz

MAX f

osc

mode a and/or b mode a mode b

selection algorithm

is needed.

rms

true

on-chip PLL used

in application?

false

ISP used for initial

code download?

false

external crystal

oscillator used?

false

MIN f

= 1 MHz

osc

= 50 MHz

MAX f

osc

true

MIN f

MAX f

= 1 MHz

osc

= 30 MHz

osc

aaa-000575

MPT612

XTAL1

100 pF

aaa-001862

Fig 10. Slave mode operation of the on-chip oscillator

10.4.2 XTAL and RTC Printed-Circuit Board (PCB) layout guidelines

Place the crystal on the PCB as close as possible to the chip oscillator input and output pins. Take care that the load capacitors C crystal usage, have a common ground plane. Connect the external components to the ground plain. Make loops as small as possible to reduce the noise coupled in via the PCB as small as possible. Parasitics must be as small as possible. Start with small values for C

and Cx2 and, if necessary , increase the value in proportio n to the level of parasitics on

the PCB layout.

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and Cx2, and Cx3 in case of third overtone

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10.5 External interrupt inputs

The MPT612 includes up to three external interrupt inputs as selectable pin functions. When the pins are combined, external events can be processed as three independent interrupt signals. The external interrupt inputs can optionally be used to wake up the processor from Power-down or Deep power-down mode.

Additionally, all 10 capture inputs can also be used as external interrupts without the option to wake up the device from Power-down mode.

10.5.1 Register description

The external interrupt function has four registers associated with it. Register EXTINT contains the interrupt flags and register EXTWAKE contains bits that enable individual external interrupts to wake up the MPT612 from Power-down mode. Registers EXTMODE and EXTPOLAR specify the level and edge sensitivity parameters.

Table 37. External interrupt registers

Name Description Access Reset

EXTINT external interrupt flag register contains interrupt

INTWAKE interrupt wake-up register contains four enable

EXTMODE external interrupt mode register controls

EXTPOLAR external interrupt polarity register controls

flags for EINT0, EINT1, EINT2 and EINT3; see

Table 38

bits that control whether each external interrupt causes the processor to wake up from Power-down mode; see Table 39.

whether each pin is edge- or level sensitive.

which level or edge on each pin causes an interrupt.

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Address

[1]

value

R/W 0 0xE01F C140

R/W 0 0xE01F C144

R/W 0 0xE01F C148

R/W 0 0xE01F C14C

[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.

10.5.2 External interrupt flag register (EXTINT - 0xE01F C140)

If a pin is selected for its external interrupt function, the level or edge o n that pin (s elected by bits in registers EXTPOLAR and EXTMODE) sets its interrupt flag in this register. This asserts the corresponding interrupt request to the VIC, which causes an interrupt if interrupts from the pin are enabled.

Writing ones to bits EINT0 through EINT2 in register EXTINT clears the corresponding bits. In level-sensitive mode, this action is efficacious only when the pin is in its inactive state.

Once a bit from EINT0 to EINT2 is set and an appropriate code st arts to execute (hand ling wake-up and/or external interrupt), this bit in register EXTINT must be cleared. Otherwise the event triggered by activity on pin EINT is not recognized in the future.

Remark: when a change of external interrupt operating mode (that is, active level/edge) is performed (including the initialization of an external interrupt), the corresponding bit in register EXTINT must be cleared. For details, see Section 10.5.4

User manual Rev. 1 — 16 December 2011 38 of 268

and Section 10.5.5.

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For example, if a system wakes up from power-down using a LOW level on external interrupt 0 pin, its post-wake-up code must reset bit EINT0 to allow future entry into the power-down mode. If bit EINT0 is left set to logic 1, subsequent attempt(s) to invoke power-down mode fail. This also applies to external interrupt handling.

More details on power-down mode are discussed in the following chapters.

Table 38. External interrupt flag register (EXTINT - address 0xE01F C140) bit description

Bit Symbol Description Reset

0 EINT0 in level-sensitive mode, this bit is set if EINT0 function is selected for its pin, and pin is in its

1 EINT1 in level-sensitive mode, this bit is set if EINT1 function is selected for its pin, and pin is in its

2 EINT2 in level-sensitive mode, this bit is set if EINT2 function is selected for its pin, and the pin is in its

7:3 - reserved; user software must not write logic 1s to reserved bits; value read from a reserved bit is

value

0 active state. In edge-sensitive mode, this bit is set if EINT0 function is selected for its pin, and the selected edge occurs on the pin.

cleared by writing a logic 1 to it, except in level-sensitive mode when pin is in its active state (for example, if EINT0 is selected to be LOW, level-sensitive and a LOW level is present on the corresponding pin, this bit cannot be cleared; it can only be cleared when signal on pin is HIGH).

0 active state. In edge-sensitive mode, this bit is set if EINT1 function is selected for its pin, and the selected edge occurs on the pin.

cleared by writing a logic 1 to it, except in level-sensitive mode when pin is in its active state (for example, if EINT1 is selected to be LOW, level-sensitive and a LOW level is present on the corresponding pin, this bit cannot be cleared; it can only be cleared when signal on pin is HIGH).

0 active state. In edge-sensitive mode, this bit is set if EINT2 function is selected for its pin, and the selected edge occurs on the pin.

cleared by writing a logic 1 to it, except in level-sensitive mode when pin is in its active state (for example, if EINT2 is selected to be LOW, level-sensitive and a LOW level is present on the corresponding pin, this bit cannot be cleared; it can be cleared only when the signal on the pin is HIGH).

n/a not defined

10.5.3 Interrupt wake-up register (INTWAKE - 0xE01F C144)

Enable bits in register INTWAKE allow the external interrupts and other sources to wake up the processor if it is in Power-down mode. Map the related EINTn function to the pin in order for the wake-up process to take place. It is not necessary for the inter rupt to be enabled in the V ectored Interrupt Controller for a wake-up to t ake place. This arrangement allows capabilities, such as an external interrupt input wake-up the processor from Power-down mode without causing an interrupt (simply resuming operation), or allowing an interrupt to be enabled during Power-down without waking the processor if it is asserted (eliminating the need to disable the interrupt if the wake-up feature is not desirable in the application).

If an external interrupt pin is required to be a source for waking the MPT612 from Power-down mode, the corresponding bit in register External Interrupt Flag must be cleared; see Section 10.5.2

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Table 39. Interrup t wake-up register (INTWAKE - address 0xE01F C144) bit de scription

Bit Symbol Description Reset

0 EXTWAKE0 if logic 1, assertion of EINT0 wakes up processor from

1 EXTWAKE1 if logic 1, assertion of EINT1 wakes up the processor from

2 EXTWAKE2 if logic 1, assertion of EINT2 wakes up processor from

14:3 - reserved, user software must not write logic 1s to reserved bits;

15 RTCWAKE when logic 1, assertion of an RTC interrupt wakes up processor

Remark: A LOW level applied to the external interrupt inputs EINT[2:0] always wakes the chip from Deep power-down mode regardless of the settings in registers INTWAKE or PINSEL. Waking up from Deep power-do wn mode through the EINT pins cannot be disabled.

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value

Power-down mode

n/a

value read from a reserved bit is not defined

from Power-down mode

10.5.4 External interrupt mode register (EXTMODE - 0xE01F C148)

The bits in this register select whether ea ch EINT pin is le vel- or edge- sensitive. Only pins that are selected for the EINT function (see Section 12.4 “

62) and enabled via register VICIntEnable (see Section 9.4 “VIC registers” on page 21)

can cause interrupts from th e External Interrupt function (though pins selected for other functions can cause interrupts from those functions).

Remark: Software must only change a bit in this register if its interrupt is disabled in register VICIntEnable, and must write the corresponding logic 1 to registe r EXTINT before enabling (initializing) or re-enabling the interrupt, to clear bit EXTINT that might be set by changing the mode.

Table 40. Exter nal in terrupt mode register (EXTMODE - address 0xE01F C148) bit

description

Bit Symbol Value Description Reset

0 EXTMODE0 0 level-sensitivity is selected for EINT0 0

1 EINT0 is edge sensitive

1 EXTMODE1 0 level-sensitivity is selected for EINT1 0

1 EINT1 is edge sensitive

2 EXTMODE2 0 level-sensitivity is selected for EINT2 0

1 EINT2 is edge sensitive

7:3 - - reserved, user software must not write logic 1s to reserved

bits; value read from a reserved bit is not defined

value

n/a

10.5.5 External interrupt polarity register (EXTPOLAR - 0xE01F C14C)

In level-sensitive mode, the bits in this register select whether the corresponding pin is high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or falling-edge sensitive. Only pins that are selected for the EINT function (see Section 12.4

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NXP Semiconductors

“Register description” on page 62) and enabled in register VICIntEnable (see Section 9.4 “VIC registers” on page 21) can cause interrupts from the External Interrupt function

(though pins selected for other functions can cause interrupts from those functions). Remark: Software must only change a bit in this register if its interrupt is disabled in

register VICIntEnable, and must write the corresponding logic 1 to registe r EXTINT before enabling (initializing) or re-enabling the interrupt, to clear bit EXTINT that might be set by changing the polarity.

Table 41. External interrupt polarity register (EXTPOLAR - address 0xE01F C14C) bit

Bit Symbol Value Description Reset

0 EXTPOLAR0 0 EINT0 is low-active or fallin g-edge sensitive (depending on

1 EXTPOLAR1 0 EINT1 is low-active or fallin g-edge sensitive (depending on

2 EXTPOLAR2 0 EINT2 is low-active or fallin g-edge sensitive (depending on

7:3 - - reserved, user software must not write logic 1s to reserved

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description

value

EXTMODE0)

1 EINT0 is high-active or rising-edg e sensitive (depending on

EXTMODE0)

EXTMODE1)

1 EINT1 is high-active or rising-edg e sensitive (depending on

EXTMODE1)

EXTMODE2)

1 EINT2 is high-active or rising-edg e sensitive (depending on

EXTMODE2)

n/a

bits; value read from a reserved bit is not defined

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GLITCH

FILTER

wake-up enable

(one bit of EXTWAKE)

APB Read of EXTWAKE

EINTi to wake-up timer

(1)

PCLK

interrupt flag

(one bit of EXTINT)

APB read of EXTINT

to VIC

EINTi

APB Bus Data

EXTMODEi

reset

write 1 to EXTINTi

EXTPOLARi

PCLK

aaa-000576

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(1) See Figure 14 “Reset block diagram including the wake-up timer” on page 54.

Fig 11. External interrupt logic

10.6 Other system controls

Some aspects of controlling MPT612 operation that do not fit into peripheral or other registers are grouped as shown below.

10.6.1 System control and status flags register (SCS - 0xE01F C1A0)

Table 42. System control and status flags register (SCS - address 0xE01F C1A0) bit description

Bit Symbol Value Description Reset

0 GPIO0M GPIO port 0 mode selection 0

31:1 - reserved, user software must not write logic 1s to reserved bits; value read from a

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10.7 Memory mapping control

0 GPIO port 0 is accessed via APB addresses 1 high-speed GPIO is enabled on GPIO port 0, accessed via addresses in the

on-chip memory range; this mode includes the port masking feature described in

Section 13.4.2 “

Fast GPIO mask register (FIOMASK, FIO0MASK - 0x3FFF C010)”

on page 69

reserved bit is not defined

The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. This allows code running in different memory spaces to have control of the interrupts.

value

n/a

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NXP Semiconductors

10.7.1 Memory mapping control register (MEMMAP - 0xE01F C040)

Whenever an exception handling is necessary, the MPT612 fetches an instruction residing on the exception corresponding address as described in Table 3 “

vector locations” on page 11. Register MEMMAP determines the source of data that fills

this table.

Table 43. Memory ma pping control register (MEMMAP - address 0xE01F C040) bit

Bit Symbol Value Description Reset

1:0 MAP 00 Boot loader mode. Interrupt vectors are remapped to boot

7:2 - - reserved, user software must not write logic 1s to reserved

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ARM exception

description

value

block.

01 User flash mode. Interru pt vectors are not remapped and

reside in flash.

10 User RAM mode. Interrupt vectors are remapped to static

RAM. 11 reserved; do not use this option Remark: improper setting of this value can result in incorrect operation

of the device.

n/a

bits; value read from a reserved bit is not defined

10.7.2 Memory mapping control usage notes

The Memory Mapping Control simply selects one out of three available sources of data (sets of 64 bytes each) necessary for handling ARM exceptions (interrupts).

For example, whenever a Software Interrupt request is generated, the ARM core always fetches 32-bit data "residing" on 0x0000 0008 see Table 3 “

locations” on page 11. This means that when MEMMAP[1:0] = 10 (User RAM Mode), a

read/fetch from 0x0000 0008 provides data stored in 0x4000 0008. If MEMMAP[1:0] = 00 (Boot Loader Mode), a read/fetch from 0x0000 0008 provides data available also at 0x7FFF E008 (boot block remapped from on-chip Bootloader).

10.8 Phase-Locked Loop (PLL)

The PLL accepts an input clock frequency in the range 10 MHz to 25 MHz only. The input frequency is multiplied up in the range 10 MHz to 60 MHz using a Current Controlled Oscillator (CCO). The multiplier can be an integer from 1 to 32; in practice, the multiplier value cannot be higher than 6 on the MPT612 due to the upper frequency limit of the CPU. The CCO operates in the range 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider can be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is ensured that the PLL output has a 50 % duty cycle. A block diagram of the PLL is shown in Figure 12

PLL activation is controlled via register PLLCON. Register PLLCFG control the PLL multiplier and divider values. In order to pr event accidental alteration of PL L parameters or deactivation of the PLL, these two registers are protected. Since all chip operations, including the watchdog timer, depend on the PLL when it is providing the chip clock,

ARM exception vector

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NXP Semiconductors

accidental changes to the PLL setup can re sult in unexpected behavior of the MPT612. A feed sequence similar to that of the watchdog timer provides the protection. Details are provided in the description of register PLLF EED.

The PLL is turned off and byp assed following a chip reset and when enter ing Power-down mode. The PLL is enabled by software only. The program must configure and activate the PLL, wait for the PLL to lock, then connect to the PLL as a clock source.

10.8.1 Register description

The PLL is controlled by the registers shown in Table 44. More detailed descriptions follow.

Remark: Improper setting of the PLL values can result in incorrect operation of the device.

Table 44. PLL reg isters

Generic name

PLLCON PLL control register. Holding register for updating

PLLCFG PLL configuration register. Holding register for

PLLSTAT PLL status register. Read-back register for PLL

PLLFEED PLL feed register. Register enables loading of

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MPT612 User manual

Description Access Reset

value

R/W 0 0xE01F C080 PLL control bits. Values written to this register do not take effect until a valid PLL feed sequence occurs.

R/W 0 0xE01F C084 updating PLL configuration values. Values written to this register do not take effect until a valid PLL feed sequence occurs.

RO 0 0xE01F C088 control and configuration information. If PLLCON or PLLCFG have been written to, but a PLL feed sequence has not yet occurred, they do not reflect the current PLL state. Reading this register provides actual values controlling the PLL and status of PLL.

WO n/a 0xE01F C08C PLL control and configuration information from registers PLLCON and PLLCFG into shadow registers actually affecting PLL operation.

Address

[1]

[1] Reset value reflects the data stored in used bits only. It does not include the content of reserved bits.

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PLLC

PLLE

osc

PSEL[1:0]

PLOCK

MSEL[4:0]

direct

bypass

PHASE-

FREQUENCY

DETECTOR

out

DIV-BY-M

MSEL[4:0]

SYNCHRONIZATION

CCO

CLOCK

cco

/2P

CCLK

Fig 12. PLL block diagram

10.8.2 PLL control register (PLLCON - 0xE01F C080)

Register PLLCON contains the bits that enable and connect the PLL. Enabling the PLL allows it to attempt to lock to the current settings of the multiplier and divider values. Connecting the PLL causes the processor and all chip functions to run from the PLL output clock. Changes to register PLLCON do not take effect until a correct PLL feed sequence is given (see Section 10.8.7 “

page 47 and Section 10.8.3).

Table 45. PLL control register (PLLCON - address 0xE01F C080) bit description

Bit Symbol Description Reset

0 PLLE PLL enable. If logic 1, and after a valid PLL feed, this bit activates

1 PLLC PLL connect. If PLLC and PLLE are both set to logic 1, and after a

7:2 - reserved, user software must not write logic 1s to reserved bits;

aaa-000577

PLL Feed register (PLLFEED - 0xE01F C08C)” on

PLL and allows it to lock to requested frequency; see register PLLSTAT, Table 47

valid PLL feed, connects PLL as clock source for MPT612. Otherwise, oscillator clock is used directly by MPT612; see register PLLSTAT, Table 47

value read from a reserved bit is not defined

value

n/a

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The PLL must be set up, enabled, and lock established before it can be used as a clock source. When switching from the oscillator clock to the PLL output or vice versa, internal circuitry synchronizes the operation in order to ensure that glitches are not generated. If lock is lost during operation, hardware does not ensure that the PLL is locked before it is connected nor automatically disconnects the PLL. If PLL lock is lost, it is likely that the oscillator clock will become unstable which cannot be remedied by disconnecting the PLL.

10.8.3 PLL configuration register (PLLCFG - 0xE01F C084)

Register PLLCFG contains the PLL multiplier and divider values. Changes to register PLLCFG do not take effect until a correct PLL feed sequence is given (see

Section 10.8.7

found in the PLL frequency calculation in Section 10.8.9

Table 46. PLL configuration register (PLLCFG - address 0xE01F C084) bit description

Bit Symbol Description Reset

4:0 MSEL PLL multiplier value. Supplies value "M" in PLL frequency

6:5 PSEL PLL divider value. Supplies value "P" in PLL frequency calculations.

7 - reserved, user software must not write logic 1s to reserved bits;

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). Calculations for the PLL frequency, and multiplier and divider values are

value

calculations. Remark: For details on selecting correct value for MSEL, see

Section 10.8.9

Remark: For details on selecting correct value for PSEL, see

Section 10.8.9

value read from a reserved bit is not defined

n/a

10.8.4 PLL status register (PLLSTAT - 0xE01F C088)

The read-only register PLLSTAT provides the actual PLL parameters that are in effect at the time it is read, as well as the PLL status. PLLSTAT can disagree with values found in PLLCON and PLLCFG because changes to those registers do not take effect until a proper PLL feed has occurred (see Section 10.8.7

Table 47. PLL status register (PLLSTAT - address 0xE01F C088) bit description

Bit Symbol Description Reset

4:0 MSEL read-back for the PLL multiplier value. Value currently used by PLL. 0 6:5 PSEL read-back for the PLL divider value. Value currently used by PLL. 0 7 - reserved, user software must not write l o gi c 1s to rese rve d bi ts;

value read from a reserved bit is not defined

8 PLLE read-back for bit PLL Enable. When logic 1, PLL is currently

activated. When logic 0, PLL is off. Automatically cleared when Power-down mode activated.

value

n/a

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Table 47. PLL status register (PLLSTAT - address 0xE01F C088) bit description …continued

Bit Symbol Description Reset

9 PLLC read-back for bit PLL Connect. When PLLC and PLLE are both

10 PLOCK reflects the PLL Lock status. When logic 0, the PLL is not locked.

15:11 - reserved, user software must not write logic 1s to reserved bits; the

10.8.5 PLL interrupt

Bit PLOCK in register PLLSTAT is connected to the interrupt controller. This allows for software to turn on the PLL and continue with other functions without having to wait for the PLL to achieve lock. When the interrupt occurs (PLOCK = 1), the PLL can be connected, and the interrupt disabled. For details on how to enable and disable the PLL interrupt, see

Section 9.4.4 “ Section 9.4.5 “

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value

0 logic 1, the PLL is connected as the clock source for the MPT612. When either PLLC or PLLE is logic 0, the PLL is bypassed and the oscillator clock is used directly by the MPT612. This bit is automatically cleared when Power-down mode is activated.

0 When logic 1, the PLL is locked onto the requested frequency.

n/a value read from a reserved bit is not defined

Interrupt enable register (VICIntEnable - 0xFFFF F010)” on page 23 and Interrupt enable clear register (VICIntEnClear - 0xFFFF F014)” on p age 23 .

10.8.6 PLL modes

The combinations of PLLE and PLLC are shown in Table 48.

Table 48. PLL Control bit combinations

PLLC PLLE PLL Function

0 0 PLL is off and disconnected. CCLK equals the unmodified clock input. 0 1 PLL is active, but not yet connected. PLL can be connected after PLOCK is

asserted.

1 0 same as 00 combination. Prevents possibility of PLL being connected without

also being enabled.

1 1 PLL is active and connected. CCLK/system clock is sourced from the PLL.

10.8.7 PLL Feed register (PLLFEED - 0xE01F C08C)

In order for changes to registers PLLCON and PL LCFG to t ake ef fect, write a correct feed sequence to register PLLFEED. The feed sequence is:

1. Write the value 0xAA to PLLFEED.

2. Write the value 0x55 to PLLFEED.

The two writes must be in the correct sequence, and must be consecutive APB bus cycles. The latter requirement implies that interrupts must be disabled for the duration of the PLL feed operation. If either of the feed values is incorrect, or one of the previously mentioned conditions is not met, any changes to register PLLCON or PLLCFG are not effective.

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Table 49. PLL Feed register (PLLFEED - address 0xE01F C08C) bit description

Bit Symbol Description Reset

7:0 PLLFEED PLL feed sequence must be written to this register for changes to PLL

10.8.8 PLL and Power-down mode

Power-down mode automatically turns off and disconnects activated PLL(s). Wake-up from Power-down mode does not automatically restore the PLL settings. This must be done in software. Typically, a routine to activate the PLL, wait for lock, and then connect the PLL can be called at the beginning of any interrupt service routine that might be called due to the wake-up. It is important not to attempt to restart the PLL by simply feeding it when execution resumes after a wake-up from Power-down mode. This enables and connects the PLL at the same time, before PLL lock is established.

10.8.9 PLL frequency calculation

The PLL equations use the following parameters:

Table 50. Parameters determining PLL frequency

Element Description

osc

CCO

CCLK PLL output frequency (also processor clock frequency) M PLL multiplier value from MSEL bits in register PLLCFG P PLL divider value from PSEL bits in register PLLCFG

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value

0x00

configuration and control register to take effect

frequency of crystal oscillator/external oscillator frequency of PLL current controlled oscillator

The PLL output frequency (when the PLL is both active and connected) is given by: CCLK = M  f

or CCLK = f

osc

CCO

/ (2  P)

The CCO frequency can be computed as:

= CCLK  2  P or f

CCO

= f

osc

 M  2  P

The PLL inputs and settings must meet the following requirements:

• f

is in the range 10 MHz to 25 MHz.

osc

• CCLK is in the range 10 MHz to f

(the maximum allowed frequency for the

max

MPT612 - embedded in and determined by the system MPT612).

• f

is in the range 156 MHz to 320 MHz.

CCO

10.8.10 Procedure for determining PLL settings

If a particular application uses the PLL, its configuration can be determined as follows:

1. Choose the desired processor operating frequency (CCLK). This can be base d on processor throughput requirements, such as the need to support a specific set of UART baud rates, and so on, Bear in mind that peripheral devices can be running from a lower clock than the processor (see Section 10.11 “

2. Choose an oscillator frequency (f multiple of f

osc

). CCLK must be the whole (non-fractional)

osc

APB Divider” on page 54).

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3. Calculate the value of M to configure the MSEL bits. M = CCLK / f

. M must be in the

osc

range 1 to 32. The value written to the MSEL bits in PLLCFG is M  1; see Table 52

4. Find a value for P to configure the PSEL bits, such that f frequency limits. f

is calculated using the equation given above. P must have one

CCO

is within its defined

CCO

of the values 1, 2, 4, or 8. The value written to bits PSEL in PLLCFG is 00 for P = 1; 01 for P = 2; 10 for P = 4; 11 for P = 8 (see Table 51

Table 51. PLL Divider values

PSEL bits (PLLCFG bits [6:5]) Value of P

00 1 01 2 10 4 11 8

Table 52. PLL Multiplier values

MSEL bits (PLLCFG bits [4:0]) Value of M

0 0000 1 0 0001 2 0 0010 3 0 0011 4

... ...

1 1110 31 1 1111 32

10.8.11 PLL configuration examples

Example: a PLL configuration application.

System design asks for f

= 10 MHz and requires CCLK = 60 MHz.

osc

Based on these specifications, M = CCLK / f M  1 = 5 is written as PLLCFG[4:0].

Value for P can be derived from P = f in the range 156 MHz to 320 MHz. Assuming the lowest allowed frequency for f

= 156 MHz, P = 156 MHz / (2  60 MHz) = 1.3. The highest f

CCO

produces P = 2.67. The only solution for P that satisfies both of these requirements and is listed in Table 51

is P = 2. Therefore, PLLCFG[6:5] = 1 is used.

10.9 Power control

The MPT612 supports three reduced power modes: Idle mode, Power-down mode, and Deep power-down mode.

In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation du ring Idle mode and can generate interrupts to cause the processor to resume execution. Idle mode elimina tes power used by the processor, memory systems and related controllers, and internal buses.

= 60 MHz / 10 MHz = 6. Consequently,

osc

/ (CCLK  2), using condition that f

CCO

frequency criteria

CCO

must be

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In Power-down mode, the oscillator is shut down, and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power-down mode and the logic levels of chip pins remain static. The Power-down mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power-down mode reduces chip power consumption to nearly zero.

If the RTC is running with its external 32 kHz oscillator at the time of entry into Power-down mode, operation can resume using an interrupt from the RTC; see Section

24.6.1 “RTC interrupts” on page 205.

Use program execution to coordinate entry to Power-down a nd Idle modes. W ake-up fr om Power-down or Idle modes via an interrupt resume s program execution in such a way that no instructions are lost, incomplete, or repeated. Wake up from Power-down mode is discussed further in Section 10.12 “

A power control for peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings.

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Wake-up timer” on page 56.

The Deep power-down mode is controlled through the RTC block (see Section 24.6.14

“Power control register group” on page 210). In Deep power-down mode, all power is

removed from the internal chip logic except for the RTC module, the I/O ports, the SRAM and the 32 kHz external oscillator. For additional power savings, SRAM and the 32 kHz oscillator can be powered down individually. The Deep power-down mode produces the lowest possible power consumption without actually removing power from the entir e chip. In Deep power-down mode, the contents of registers and memory are not preserved except for SRAM, if selected, and three general-purpose registers. Therefore, to resume operations, a full chip reset process is required.

10.9.1 Register description

The Power Control function contains two registers, as shown in Table 53. More detailed descriptions follow . The Deep power-down mod e is controlled through the R TC block ( see

Section 24.6.14 “

Table 53. Power contr ol registers

Name Description Access Reset

PCON power control register. Contains control bits

that enable the two reduced power operating modes of the MPT612; see Table 54

PCONP power control for peripherals register.

Contains control bits that enable and disable individual peripheral functions, allowing elimination of power consumption by peripherals that are not needed.

Power control register group” on page 210).

[1]

value

R/W 0x00 0xE01F C0C0

R/W 0x0018 17BE 0xE01FC0C4

Address

[1] Reset value reflects the data stored in used bits only. It does not include the content of reserved bits.

10.9.2 Power control register (PCON - 0xE01F COCO)

Register PCON contains 2 bits. Writin g a logic 1 to the corresponding bit causes entry to either the Power-down or Idle mode. If both bits are set, Power-down mode is entered.

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Table 54. Power contr ol register (PCON - address 0xE01F COCO) bit description

Bit Symbol Description Reset

0 IDL Idle mode. If logic 1, causes processor clock to stop, while on-chip

1 PD Power-down mode. If logic 1, causes oscillator and all on-chip clocks to

7:2 - reserved, user software must not wri te l o gi c 1s to reserved bits; value

10.9.3 Power control for peripherals register (PCONP - 0xE01F COC4)

To save power, register PCONP turns off selected peripheral functions. This is accomplished by gating off the clock source to the specified peripheral blocks. A few peripheral functions cannot be turned off (that is, the watchdog timer, GPIO, the pin connect block, and the system control block). Some peripherals, particularly analog functions, can consume power that is not clock-dependent. These perip herals can conta in a separate disable control that turns off additional circuitry to reduce power. Each bit in PCONP controls one of the peripherals. The bit numbers correspond to the related peripheral number as shown in the APB peripheral map Table 2 “

base addresses” on page 10 in Section 7.1 “Memory maps” on page 7.

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value

0 peripherals remain active. Any enabled interrupt from a peripheral or an external interrupt source causes processor to resume execution.

0 stop. A wake-up condition from an external interrupt can cause the oscillator to restart, bit PD to be cleared, and processor to resume execution.

n/a read from a reserved bit is not defined.

APB peripheries and

If a peripheral control bit is logic 1, that peripheral is enabl ed. If a pe rip he r al bit is log ic 0,

that peripheral is disabled to conserve power. For example if bit 19 is logic 1, the I interface is enabled. If bit 19 is logic 0, the I

C1? interface is disabled.

C1?

Remark: A valid read from a peripheral re gister and a valid write to a peripheral register is possible only if the peripheral is enabled in register PCONP.

Table 55. Power contr ol for pe rip herals register (PCONP - address 0xE01F C0C4) bit

description

Bit Symbol Description Reset

value

0 - reserved, user software must not write logic 1s to reserved bits; value

read from a reserved bit is not defined 1 - reserved 1 2 PCTIM1 timer counter1 power/clock control bit 1 3 PCUART0 UART0 power/clock control bit 1 4 PCUART1 UART1 power/clock control bit 1 6:5 - reserved, user software must not write logic 1s to reserved bits; value

read from a reserved bit is not defined

7PCI2C0I 8 PCSPI SPI interface power/clock control bit 1 9 PCRTC RTC power/clock control bit 1 10 PCSPI SSP interface power/clock control bit 1 1 1 - reserved, user software must not write logic 1s to reserved bits; value

C0? interface power/clock control bit 1

read from a reserved bit is not defined

n/a

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Table 55. Power contr ol for pe rip herals register (PCONP - address 0xE01F C0C4) bit

Bit Symbol Description Reset

12 PCAD A/D converter 0 (ADC0) power/clock control bit.

18:13 - reserved, user software must not write logic 1s to reserved bits; value

19 PCI2C1 I 21:20 - reserved, user software must not write logic 1s to reserved bits; value

22 - reserved 1 23 PCTIM3 timer counter3 power/clock control bit 1 31:24 - reserved, user software must not write logic 1s to reserved bits; value

10.9.4 Power control usage notes

description

Remark: Clear bit PDN in ADCR before clearing this bit, and set this

bit before setting PDN.

read from a reserved bit is not defined

C1 interface power/clock control bit 1

read from a reserved bit is not defined

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…continued

value

n/a

After every reset, register PCONP contains the value that enables all interfaces and peripherals controlled by the PCONP to be enabled. Therefore, in order to start using any of the on-board peripherals, apart from proper configuring via peripheral dedicated registers, the application has no need to access PCONP.

Power saving oriented systems must have logic 1s in register PCONP only in positions that match peripherals used in the application. All other bits, declared to be Reserved or dedicated to the peripherals not used in the current application, must be cleared to logic 0.

10.10 Reset

Reset has two sources on the MPT612: pin RESET and watchdog reset. Pin RESET is a Schmitt trigger input pin with an additional glitch filter . Assertion of chip reset by any source starts the wake-up timer (see Section 10.12 “ remain asserted until the external reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip circuitry has completed its initialization. The relationship between reset, the oscillator, and the wake-up timer are shown in

Figure 13

The reset glitch filter allows the processor to ignore external reset pulses that are short, and also determines the minimum duration of RESET guarantee a chip reset. Once asserted, pin RESET crystal oscillator is fully running and an adequate signal is present on pin XTAL1 of the MPT612. Assuming that an external crystal is used in the crystal oscillator subsystem, after power-on, pin RESET the crystal oscillator is already running and a stable signal is on pin XTAL1, pin RESET needs to be asserted for only 300 ns.

Wake-up timer”), causing reset to

. The reset logic is shown in Figure 14.

that must be asserted in order to

can be deasserted only when the

must be asserted for 10 ms. For all subsequent resets when

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DD(lO)

(no sequencing requirements)

, V

sequencing

DDC

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[2]

oscillator

DD(lO)

GND

DDC

GND

reset

processor status

oscillator starts

1.65 V

reset time

0.5 ms

3.0 V

[3]

[4]

[1]

valid clocks

[3]

clock stability

time

4096 clocks

1000

clocks

boot time

PLL lock time = 100 μs

SPI boot time

jump to user code

019aac140

(1) Reset time: The reset time must be held LOW. This time depends on system parameters such as V

the oscillator start-up time. There are no restrictions from the MPT612 except that V

DDC

within the specific operating range. (2) There are no sequencing requirements for V (3) When V

DD(IO)

and V

reach the minimum voltage, a reset is registered within two valid oscillator clocks.

DDC

DD(IO)

and V

DDC

(4) Typical start-up time is 0.5 ms for a 12 MHz crystal.

Fig 13. Start-up sequence diagram

When the internal reset is removed, the processor begins executing at address 0, which is initially the reset vector mapped from the boot block. At that po int, all of the processor and peripheral registers have been initialized to predetermined values.

External and internal resets have some small differences. An external reset causes the value of certain pins to be latched to configure the part. External circuitry cannot determine when an internal reset occurs in order to allow setting up those special pin s, so those latches are not reloaded during an inter nal reset. Pin 26 (R TCK) is examined durin g an external reset (see Section 11.2 on page 58 (see Section 25 “

Flash memory system and programming” on page 217) examines the

and Section 12.4 on page 62). Pin PIO14

on-chip bootloader when this code is executed after every reset. It is possible for a chip reset to occur during a Flash programming or erase operation. The

Flash memory interrupts the ongoing operatio n and holds off the completion of reset to the CPU until internal Flash high voltages have settled.

, V

DD(IO)

DDC

, and the oscillator must be

rise time, and

DD(IO)

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external

reset

watchdog

reset

power

down

EINT0 wake-up EINT1 wake-up EINT2 wake-up

oscillator

output

osc

)

PLL

Fig 14. Reset block diagram including the wake-up timer

WAKE-UP

TIMER

START

write “1”

from APB

Reset

reset to the on-chip circuitry

reset to PCON.PD

COUNT2n

ABP read of PDBIT in PCON

osc

to CPU

aaa-000578

10.10.1 Reset source identification register (RSIR - 0xE01F C180)

This register contains 1 bit for each source of reset. Writing a logic 1 to any of these bits clears the corresponding read-side bit to logic 0. The interactions amon g the four source s are described below.

T able 56. Reset source identification register (RSIR - address 0xE01F C180) bit description

Bit Symbol Description Reset

0 POR Power-On Reset (POR) event sets this bit, and clears all other bits in

this register. If another reset signal (such as External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other reset sources.

1 EXTR assertion of the RESET

but is not affected by WDT reset.

2 WDTR this bit is set when the watchdog timer times out and bit WDTRESET in

the watchdog mode register is logic 1. It is cleared by any of the other reset sources.

7:3 - reserved, user software must not write logic 1s to reserved bits; the

value read from a reserved bit is not defined

signal sets this bit. This bit is cleared by POR,

10.11 APB Divider

The APB Divider determines the relationship between the processor clock (CCLK) and the clock used by peripheral devices (PCLK).

value

see text

n/a

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The APB Divider serves two purposes:

• provides peripherals with desired PCLK via APB bus so that they can operate at the

• allows power savings when an application does not require any peripherals to run at

The connection of the APB Divider relative to the oscillator and the processor clock is shown in Figure 15 on page 56 the PLL remains active (if it was running) during Idle mode.

10.11.1 Register description

Only one register is used to control the APB Divider.

Table 57. APB Divider register map

Name Description Access Reset

APBDIV controls the rate of APB clock in relation to

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speed chosen for the ARM processor. To achieve this, the APB bus can be slowed down to one half or one fourth of the processor clock rate. Because the APB bus must work properly at power-up (and its timing cannot be altered if it does not work as the APB divider control registers reside on the APB bus), the default condition at reset is for the APB bus to run at one quarter speed.

the full processor rate

. Because the APB Divider is connected to the PLL output,

Address

[1]

value

R/W 0x00 0xE01F C100

processor clock

[1] Reset value reflects the data stored in used bits only. It does not include the content of reserved bits.

10.11.2 APBDIV register (APBDIV - 0xE01F C100)

T able 58. APB Divider register (APBDIV - address 0xE01F C100) bit description

Bit Symbol Value Description Reset

1:0 APBDIV 00 APB bus clock is one fourth of the processor clock 00

01 APB bus clock is the same as the processor clock 10 APB bus clock is one half of the processor clock 1 1 reserved, if this value is written to register APBDIV it has no

effect (previous setting is retained)

7:2 - - reserved, user software must not write logic 1s to reserved

bits; value read from a reserved bit is not defined

value

n/a

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crystal oscillator or

external clock source

Fig 15. APB Divider connections

10.12 Wake-up timer

The purpose of the wake-up timer is to ensure that the oscillator and other analog functions required for chip operation are fully functional before th e processor is allowed to execute instructions. This is important at power-on, all types of reset, and whenever any of the previously mentioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode uses the wake-up timer.

The wake-up timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of V and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (for example, capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.

)

osc

PLL0

APB DIVIDER

ramp (in the case of power-on), the type of crystal

processor clock

(CCLK)

APB clock

(PCLK)

aaa-000579

Once a clock is detected, the wake-up timer count s 4096 cloc ks, then enables the o n-chip circuitry to initialize. When the on-board module’s initialization is complete, the processor is released to execute instructions if the external reset is de-asserted. In the case where an external clock source is used in the system (as opposed to a crystal connected to the oscillator pins), the possibility that there can be little or no delay for oscillator start-up must be considered. The wake-up timer design then ensures that any other required chip functions are operational before the beginning of program execution.

Any of the various resets can bring the MPT612 out of Power-down mode, as can the external interrupts EINT2:0 and the RTC interrupt if the RTC is operating from its own oscillator on the RTCX1-2 pins. When one of these interrupts is enabled for wake-up and its selected event occurs, an oscillator wake-up cycle is started. The actual interrupt (if any) occurs after the wake-up timer expires, and is handled by the Vectored Interrupt Controller.

To put the device in Power-down mode and allow activity on one or more of these buses or lines to power it back up, software must reprogram the pin function to external interrupt, select the appropriate mode and polarity for the interr upt, and then select Power-down mode. At wake-up, software must restore the pin multiplexing to the peripheral function.

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MPT612FBD48

PIO19/MAT1_2/MISO1 PIO11/CTS1/CAP1_1/AD4 PIO20/MAT1_3/MOSI1 PIO10/RTS1/CAP1_0/AD3 PIO21/SSEL1/MAT3_0 PVCURRENTSENSE

DD(RTC)

PVVOLTSENSEBOOST

DDC

PVVOLTSENSEBUCK

RST GNDADC

GND PIO9/RXD1/PWMOUT2

PIO27/TRST PIO8/TXD1/PWMOUT1

PIO28/TMS PWMOUT0 PIO29/TCK JTAGSEL

XTAL1 RTCK XTAL2 RTCX2

PIO18/CAP1_3/SDA1

PIO17/CAP1_2/SCL1

PIO16/EINT0

PIO15/RI1/EINT2

PIO14/DCD1/SCK1/EINT1

GND

DD(ADC)

PIO13/DTR1/MAT1_1

DD(IO)

PIO26/AD7

PIO25/AD6

PIO12/DSR1/MAT1_0/AD5

PIO0/TXD0/MAT3_1

PIO1/RXD0/MAT3_2

PIO30/TDI/MAT3_3

PIO31/TDO

DD(IO)

PIO2/SCL0

GND

RTCX1

PIO3/SDA0

PIO4/SCK0

PIO5/MISO0

PIO6/MOSI0

001aam091

1 2 3 4 5 6 7 8

9 10 11 12

36 35 34 33 32 31 30 29 28 27 26 25

1314151617181920212223

4847464544434241403938

To summarize: on the MPT612, the wake-up timer enforces a minim u m re se t dura tio n based on the crystal oscillator, and is activated whenever there is a wake-up from Power-down mode or any type of reset.

10.13 Code security vs. debugging

Applications in development typically need the debugging and tracing facilities in the MPT612. Later in the life cycle of an application, it can be more important to protect the application code from observation by hostile or competitive eyes. The Code Read Protection feature on the MPT612 allows an application to control whether it can be debugged or protected from observa tion.

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Details on the way Code Read Protection works ca n be found in Section 25.8 “

Protection (CRP)” on page 223.

11. Pin configuration

11.1 Pinout

Code Read

Fig 16. LQFP48 pin configuration

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11.2 MPT612 pin description

The MPT612 pin functions are briefly described in Table 59.

pins of Port 0 can be used as general purpose bidirectional digital I/Os while PIO31 is an output-only pin. Operation of port 0 pins depends upon pin function selected via pin connect block.

[1]

I/O PIO0: general purpose input/output digital pin O TXD0: transmitter output for UART0 O MAT3_1: PWM output 1 for timer 3

[1]

I/O PIO1: general purpose input/output digital pin I RXD0: receiver input for UART0 O MAT3_2: PWM output 2 for timer 3

[2]

I/O PIO2: general purpose input/output digital pin; output is open-drain

I/O SCL0: I

[2]

I/O PIO3: general purpose input/output digital pin; output is open-drain I/O SDA0: I

[1]

I/O PIO4: general purpose input/output digital pin

C0 clock Input/output; open-drain output (for I2C-bus compliance)

C0 data input/output; open-drain output (for I2C-bus compliance)

I/O SCK0: serial clock for SPI0; SPI clock output from master or input to slave

[1]

I/O PIO5: general purpose input/output digital pin I/O MISO0: master in slave out for SPI0. Data input to SPI master or data output from SPI

slave

[1]

I/O PIO6: general purpose input/output digital pin I/O MOSI0: master out slave in for SPI0. Data output from SPI master or data input to SPI

slave

[1]

O PWMOUT0: PWM output used for switching the MOSFET; do not use for any other

purpose

[1]

I/O PIO8: general purpose input/output digital pin O TXD1: transmitter output for UART1 O PWMOUT1: PWM output; same frequency as PWMOUT0, however, the duty cycle can be

changed

[1]

I/O PIO9: general purpose input/output digital pin I RXDI: receiver input for UART1 O PWMOUT2: PWM output; same frequency as PWMOUT0, however, the duty cycle can be

changed

[3]

I/O PIO10: general purpose input/output digital pin O RTS1: request to send output for UART1 I CAP1_0: capture input for timer 1, channel 0 I AD3: ADC 0, input 3

[3]

I/O PIO11: general purpose input/output digital pin I CTS1: clear to send input for UART1 I CAP1_1: capture input for timer 1, channel 1 I AD4: ADC 0, input 4

Table 59. Pin description

Symbol Pin Type Description

PIO0 to PIO31 I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. A total of 31

PIO0/TXD0/ MAT3_1

PIO1/RXD0/ MAT3_2

PIO2/SCL0 18

PIO3/SDA0 21

PIO4/SCK0 22

PIO5/MISO0 23

PIO6/MOSI0 24

PWMOUT0 28

PIO8/TXD1/ PWMOUT1

PIO9/RXD1/ PWMOUT2

PIO10/RTS1/ CAP1_0/AD3

PIO11/CTS1/ CAP1_1/AD4

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Table 59. Pin description …continued

Symbol Pin Type Description

PIO12/DSR1/ MAT1_0/AD5

PIO13/DTR1/ MAT1_1

PIO14/DCD1/ SCK1/EINT1

PIO15/RI1/ EINT2

PIO16/EINT0 46

PIO17/CAP1_2 / SCL1

PIO18/CAP1_3 / SDA1

PIO19/MAT1_2 / MISO1

PIO20/MAT1_3 / MOSI1

PIO21/SSEL1/ MAT3_0

PVVOLTSENS EBUCK

PVVOLTSENS EBOOST

PVCURRENTS ENSE

PIO25/AD6 38

[1]

[3]

I/O PIO12: general purpose input/output digital pin I DSR1: data set ready input for UART1 O MAT1_0: PWM output for Timer 1, channel 0 I AD5: ADC 0, input 5

[1]

I/O PIO13: general purpose input/output digital pin O DTR1: data terminal ready output for UART1 O MAT1_1: PWM output for timer 1, channe l 1

[4][5]

I/O PIO14: general purpose input/output digital pin I DCD1: data carrier detect input for UART1 I/O SCK1: serial clock for SPI1. SPI clock output from master or input to slave I EINT1: external interrupt 1 input

[4]

I/O PIO15: general purpose input/output digital pin I RI1: ring indicator input for UART1 I EINT2: external interrupt 2 input

[4]

I/O PIO16: general purpose input/output digital pin I EINT0: external interrupt 0 input

[6]

I/O PIO17: general purpose input/output digital pin. The output is not open-drain. I CAP1_2: capture input for timer 1, channel 2 I/O SCL1: I2C1 clock input/output. This pin is an open-drain output if I2C1 function is selected

in the pin connect block.

[6]

I/O PIO18: general purpose input/output digital pin. The output is not open-drain. I CAP1_3: capture input for timer 1, channel 3

I/O SDA1: I

C1 data input/output. This pin is an open-drain output if I2C1 function is selected

in the pin connect block. I/O PIO19: general purpose input/output digital pin O MAT1_2: PWM output for timer 1, channe l 2 I/O MISO1: master in slave out for SSP. Data input to SSP master or data output from SSP

slave. I/O PIO20: general purpose input/output digital pin O MAT1_3: PWM output for timer 1, channe l 3 I/O MOSI1: master out slave In for SSP. Data output from SSP master or data input to SSP

slave. I/O PIO21: general purpose input/output digital pin I SSEL1: slave select for SPI1. Selects the SPI interface as a slave. O MAT3_0: PWM output for timer 3, channe l 0

[3]

I PVVOLTSENSEBUCK: PV voltage sense for buck mode

[3]

I PVVOLTSENSEBOOST: PV voltage sense for boost mode; this pin is not connected

when only buck mode is used

[3]

I PVCURRENT SENSE: PV current sense

[3]

I/O PIO25: general purpose input/output digital pin I AD6: ADC 0, input 6

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Table 59. Pin description …continued

Symbol Pin Type Description

PIO26/AD7 39

PIO27/TRST

PIO28/TMS 9

PIO29/TCK 10

PIO30/TDI/ MAT3_3

PIO31/TDO 16

RTCX1 20 RTCX2 25 RTCK 26

XTAL1 11 I input to osci llator circuit and internal clock generator circuits; input voltage must not

XTAL2 12 O output from the oscillator amplifier JTAGSEL 27 I JTAG select: when LOW, the part operates normally; when externally pulled HIGH at

RST

GND 7, 19, 43I Ground: 0 V reference

[3]

I/O PIO26: general purpose input/output digital pin I AD7: ADC 0, input 7

[1]

I/O PIO27: general purpose input/output digital pin I TRST

: test reset for JTAG interface. If JTAGSEL is HIGH, this pin is automatically

configured for use with EmbeddedICE (Debug mode).

[1]

I/O PIO28: general purpose input/output digital pin I TMS: Test Mode Select for JTAG interface. If JTAGSEL is HIGH, this pin is automatically

configured for use with EmbeddedICE (Debug mode).

[1]

I/O PIO29: general purpose input/output digital pin

I TCK: test clock for JTAG interface. This clock must be slower than

⁄6 of the CPU clock

(CCLK) for the JTAG interface to operate. If JTAGSEL is HIGH, this pin is automatically

configured for use EmbeddedICE (Debug mode).

[1]

I/O PIO30: general purpose input/output digital pin I TDI: test data In for JTAG interface. If JTAGSEL is HIGH, this pin is automatically

configured for use with EmbeddedICE (Debug mode). O MAT3_3: PWM output 3 for timer 3

[1]

O PIO31: general-purpose output only digital pin O TDO: test data out for JTAG interface. If JTAGSEL is HIGH, this pin is automatically

configured for use with EmbeddedICE (Debug mode).

[7][8]

I input to RTC oscillator circuit; input voltage must not exceed 1.8 V

[7][8]

O output from RTC oscillator circuit

[7]

I/O Returned test clock output: extra signal added to the JTAG port; assists debugger

synchronization when processor frequency varies; bidirectional pin with internal pull-up

exceed 1.8 V

reset, PIO27 to PIO31 are configured as JTAG port, and the part is in Debug mode

[9]

input with internal pull-down

6IExternal reset input: a LOW on this pin resets device changing I/O ports and peripherals

to their default states and processor execution to start at address 0; TTL with hysteresis,

5Vtolerant

;

GNDADC 31 I analog ground: 0 V reference; must be nominally same voltage as GND and isolated to

minimize noise and error

DD(ADC)

42 I analog 3.3 V power supply: must be nominally same voltage as V

and isolated to

DD(IO)

minimize noise and error; level on this pin also provides voltage reference level for ADC

DDC

DD(IO)

DD(RTC)

[1] 5 V tolerant (if V

control.

[2] Open-drain 5 V tolerant (if V

pull-up to provide an output functionality. Open-drain configuration applies to ALL functions on that pin.

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5I1.8 V core power supply: power supply voltage for internal circuitry and on-chip PLL 17, 40 I 3.3 V pad power supply: power supply voltage for I/O ports 4IRTC power supply: 3.3 V on this pin supplies power to the RTC

DD(IO)

and V

 3.0 V) pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate

DD(ADC)

DD(IO)

and V

 3.0 V) digital I/O I2C-bus 400 kHz specification compatible pad. It requires external

DD(ADC)

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[3] 5 V tolerant (if V

analog input function. If configured for an input function, this pad utilizes a built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input, digital section of the pad is disabled.

[4] 5 V tolerant (if V

control. If configured for an input function, this pad utilizes a built-in glitch filter that blocks pulses shorter than 3 ns. [5] A LOW level during reset on pin PIO14 is considered as an external hardware request to start the ISP command handler. [6] Open-drain 5 V tolerant (if V

pull-up to provide output functionality. Open-drain configuration applies only to I [7] Pad provides special analog functionality. [8] For lowest power consumption, leave pins floating when the RTC is not used. [9] See Section 26.8 “

and V

DD(IO)

and V

DD(IO)

Debug mode” on page 241 for details.

 3.0 V) pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and

DD(ADC)

 3.0 V) pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate

DD(ADC)

DD(IO)

and V

 3.0 V) digital I/O I2C-bus 400 kHz specification compatible pad. It requires external

DD(ADC)

C function on that pin.

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12. Pin connect block

12.1 Features

The pin connect block allows individual pin configuration.

12.2 Applications

The purpose of the pin connect block is to configure the MPT612 pins to the desired functions.

12.3 Description

The pin connect block allows selected pins of the MPT612 to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals.

Connect peripherals to the appropriate pins before activation, and before any related interrupt(s) being enabled. Consider activity of any enabled peripheral function that is not mapped to a related pin as undefined.

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Selection of a single function on a port pin completely excludes all other functions otherwise available on the same pin.

The only partial exception from the above rule of exclu sion is the case of inputs to the ADC. Regardless of the function that is currently selected for the port pin hosting the ADC input, this ADC input can be read at any time and variations of the voltage level on this pin is reflected in the ADC readings. However, valid analog reading(s) can be obtained o nly if the function of an analog input is selected. Only in this ca se the pro pe r inte r fac e circ uit is active between the physical pin and the ADC module. In all other cases, a part of digital logic necessary for the digital function to be performed is activ e an d disrupts proper behavior of the ADC.

12.4 Register description

The pin control module contains 2 registers as shown in Table 60.

Table 60. Pin connect block register map

Name Description Access Reset value

PINSEL0 pin function select

PINSEL1 pin function select

[1] Reset value reflects the data stored in used bits only. It does not include the content of reserved bits.

[1]

read/write 0x0000 0000 0xE002 C000

read/write 0x0000 0000 0xE002 C004

Address

12.4.1 Pin function Select register 0 (PINSEL0 - 0xE002 C000)

on page 66. The direction control bit in register IO0DIR is effective only when the GPIO

function is selected for a pin. For other functions, direction is controlled automatically.

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Table 61. Pin function select register 0 (PINSEL0 - address 0xE002 C000)

PINSEL0 Pin name Value Function Value after reset

1:0 PIO0 00 GPIO pin 0 0

3:2 PIO1 00 GPIO pin 1 0

5:4 PIO2 00 GPIO pin 2 0

7:6 PIO3 00 GPIO pin 3 0

9:8 PIO4 00 GPIO pin 4 0

11:10 PIO5 00 GPIO pin 5 0

13:12 PIO6 00 GPIO pin 6 0

15:14 PIO7 00 GPIO pin 7 0

17:16 PIO8 00 GPIO pin 8 0

19:18 PIO9 00 GPIO pin 9 0

21:20 PIO10 00 GPIO pin 10 0

01 TXD0 (UART0) 10 MAT3.1(Timer 3) 1 1 reserved

01 RXD0 (UART0) 10 MAT3.2 (Timer 3) 1 1 reserved

01 SCL0 (I

C0)

1 1 reserved

01 SDA0 (I

C0)

1 1 reserved

01 SCK0 (SPI0) 1 1 reserved

01 MISO0 (SPI0) 1 1 reserved

01 MOSI0 (SPI0) 1 1 reserved

01 SSEL0 (SPI0) 10 PWMOUT0 1 1 reserved

01 TXD1 (UART1) 10 PWMOUT1 1 1 reserved

01 RXD1 (UART1) 10 PWMOUT2 1 1 reserved

01 RTS1(UART1) 10 CAP1.0 (Timer 1) 11 AD3

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Table 61. Pin function select register 0 (PINSEL0 - address 0xE002 C000)

PINSEL0 Pin name Value Function Value after reset

23:22 PIO11 00 GPIO pin 11 0

01 CTS1 (UART1) 10 CAP1.1 (Timer 1) 11 AD4

25:24 PIO12 00 GPIO pin 12 0

01 DSR1 (UART1) 10 MAT1.0 (Timer 1) 11 AD5

27:26 PIO13 00 GPIO pin 13 0

01 reserved 10 MAT1.1 (Timer 1) 11 DTR1 (UART1)

29:28 PIO14 00 GPIO pin 14 0

01 EINT1 10 SCK1 (SSP1) 11 DCD1 (UART1)

31:30 PIO15 00 GPIO pin 15 0

01 EINT2 10 reserved 1 1 RI1 (UART1)

…continued

12.4.2 Pin function select register 1 (PINSEL1 - 0xE002 C004)

Register PINSEL1 controls the functions of the pins as per the settings listed in the following tables. The direction control bit in register IO0DIR is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically.

Table 62. Pin function select register 1 (PINSEL1 - address 0xE002 C004)

PINSEL1 Pin Name Value Function Value after reset

1:0 PIO16 00 GPIO pin 16 0

01 EINT0 1 1 reserved

3:2 PIO17 00 GPIO pin 17 0

01 SCL1 (I 10 CAP1.2 (Timer 1) 1 1 reserved

5:4 PIO18 00 GPIO pin 18 0

01 SDA1 (I 10 CAP1.3 (Timer 1) 1 1 reserved

C1)

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Table 62. Pin function select register 1 (PINSEL1 - address 0xE002 C004)

PINSEL1 Pin Name Value Function Value after reset

7:6 PIO19 00 GPIO pin 19 0

01 MISO1 (SPI1) 10 MAT1.2 (Timer 1) 1 1 reserved

9:8 PIO20 00 GPIO pin 20 0

01 MOSI1 (SPI1) 10 MAT1.3 (Timer 1) 1 1 reserved

11:10 PIO21 00 GPIO pin 21 0

01 SSEL1 (SPI1) 10 MAT3.0 (Timer 3) 1 1 reserved

13:12 PIO22 00 GPIO pin 22 0

01 reserved 10 reserved 1 1 PVVOLTSENSEBUCK

15:14 PIO23 00 GPIO pin 23 0

01 reserved 10 reserved 11 PVVOLTSENSEBOOST

17:16 PIO24 00 GPIO pin 24 0

01 reserved 10 reserved 11 PVCURRENTSENSE

19:18 PIO25 00 GPIO pin 25 0

01 reserved 10 reserved 11 AD6

21:20 PIO26 00 GPIO pin 26 0

01 reserved 10 reserved 11 AD7

23:22 PIO27 00 GPIO pin 27 0

01 TRST (JTAG) 1 1 reserved

25:24 PIO28 00 GPIO pin 28 0

01 TMS (JTAG) 1 1 reserved

27:26 PIO29 00 GPIO pin 29 0

01 TCK (JTAG) 1 1 reserved

…continued

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Table 62. Pin function select register 1 (PINSEL1 - address 0xE002 C004)

PINSEL1 Pin Name Value Function Value after reset

29:28 PIO30 00 GPIO pin 30 0

01 TDI (JTAG) 10 MAT3.3 (Timer 3) 1 1 reserved

31:30 PIO31 00 GPIO pin 31 0

01 TDO (JTAG) 10 reserved 1 1 reserved

12.4.3 Pin function select register values

The PINSEL registers control the functions of device pins as shown Table 63. Pairs of bits in these registers correspond to specific device pins.

Table 63. Pin function select register bits

PINSEL0 and PINSEL1 values Function Value after reset

00 primary (default) function, typically GPIO

port 01 first alternate function 10 second alternate function 11 third alternate function

…continued

The direction control bit in register IO0DIR is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Each derivative typically has a different pinout and therefore a dif ferent set of functions possible for each pin. Details for a specific derivative can be found in the appropriate data sheet.

13. General-Purpose Input/Output (GPIO) ports

13.1 Features

• Every physical GPIO pin is accessible through two independent sets of registers. One

set provides enhanced features and higher speed GPIO pin access. The other register set provides slow speed GPIO pin access.

• Enhanced GPIO functions:

– GPIO registers are relocated to the ARM local bus to achieve the fastest possible

I/O timing

– Mask registers allow sets of port bits to be treated as a group, leaving other bits

unchanged

– All registers are byte and half-word addressable – An entire port value can be written in one instruction

• Bit-level set and clear registers allow a single instruction set, or clear any number of

bits

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• Individual bits can be direction controlled

• All I/O pins default to inputs after reset

13.2 Applications

General-purpose I/O

•

• Driving LEDs or other indicators

• Controlling off-chip devices

• Sensing digital inputs

13.3 Pin description

Table 64. GPIO pin description

Pin Type Description

PIO0 to PIO31 input/

output

general-purpose input/output; the number of GPIOs available depends on the use of alternate functions

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13.4 Register description

MPT612 has one 32-bit General-Purpose I/O port. A total of 32 input/output pins are available on PORT0 which is controlled by registers shown in Table 65

Slow speed GPIO pin registers are shown in Table 65 The registers in Table 66

MPT612. All of these registers are located directly on the local bus of the CPU for the fastest possible read and write timing and are byte, half-word, and word accessible. A mask register allows writing to individual pins of the GPIO port without the overhead of software masking.

The user must select in register System Control and Status flags (SCS) whether a GPIO will be accessed via registers that provide enhanced features or the set of slow speed GPIO registers (see Section 10.6.1 “

0xE01F C1A0)” on page 42). While both fast and slow speed GPIO registers of a port are

controlling the same physical pins, these two port control branches are mutually exclusive and operate independently. For example, changing a pin’s output via a fast register is not observable via the corresponding slow speed GPIO register.

The following text refers to slow speed GPIO as slow GPIO, while the GPIO with enhanced features selected is referred to as the fast GPIO.

Slow GPIO registers are word accessible only. Fast GPIO registers are byte, half-word, and word accessible. In Table 65 corresponds to PIO31.

and Table 66.

represent the enhanced GPIO features available on the

System control and status flags register (SCS -

and Table 66, bit 0 corresponds to PIO0, and bit 31

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Table 65. GPIO register map (slow speed GPIO APB accessible registers)

Generic

Description Access Reset value

name

IOPIN GPIO pin value register. Current state of GPIO configured pins can

R/W n/a 0xE002 8000

always be read from this register, regardless of pin direction.

IOSET GPIO output set register. Controls state of output pins with register

R/W 0x0000 0000 0xE002 8004 IOCLR. Writing logic 1s produces HIGHs at the corresponding port pins. Writing logic 0s has no effect.

IODIR GPIO direction control register. Individually controls the direction of

R/W 0x0000 0000 0xE002 8008 each port pin.

IOCLR GPIO output clear register. Controls state of output pins. Writing

WO 0x0000 0000 0xE002 800C logic 1s produces LOWs at corresponding pins and clears corresponding bits in register IOSET. Writing logic 0s has no effect.

[1] Reset value reflects the data stored in used bits only. It does not include the content of reserved bits.

Table 66. GPIO register map (local bus accessible registers - enhanced GPIO features)

Generic

Description Access Reset value

name

FIODIR fast GPIO direction control register. Individually controls direction

R/W 0x0000 0000 0x3FFF C000

of each pin.

FIOMASK fast mask register for pins. Writes, sets, clears, and reads pins (via

R/W 0x0000 0000 0x3FFF C010

writes to FIOPIN, FIOSET, and FIOCLR, and reads of FIOPIN). Only bits enabled by logic 0s in this register are altered or returned.

Remark: Bits in register FIOMASK are active LOW.

FIOPIN fast GPIO pin value register using FIOMASK. Current state of

R/W 0x0000 0000 0x3FFF C014

digital pins can be read from this register, regardless of pin direction or alternate function selection (when pins are not configured as an input to ADC). Value read is masked by ANDing

IOMASK. Writing to this register puts corresponding values

with F in all bits enabled by logic 0s in FIOMASK.

FIOSET fast GPIO output set register using FIOMASK. Controls state of

R/W 0x0000 0000 0x3FFF C018

output pins. Writing logic 1s produces HIGHs at corresponding pins. Writing logic 0s has no effect. Reading this register returns current content of port output register. Only bits enabled by logic 0s in FIOMASK can be altered.

FIOCLR fast GPIO output clear register using FIOMASK. Controls state of

WO 0x0000 0000 0x3FFF C01C

output pins. Writing logic 1s produces LOWs at corresponding pins. Writing logic 0s has no effect. Only bits enabled by logic 0s in FIOMASK can be altered.

[1]

PORT0 address and name

IO0PIN

IO0SET

IO0DIR

IO0CLR

[1]

PORT0 address and name

FIO0DIR

FIO0MASK

FIO0PIN

FIO0SET

FIO0CLR

[1] Reset value reflects the data stored in used bits only. It does not include the content of reserved bits.

13.4.1 GPIO Direction register (IODIR, IO0DIR - 0xE002 8008; FIODIR, FIO0DIR 0x3FFF C000)

This word accessible register is used to control the direction of the pins when they are configured as GPIO pins. Set the direction bit for any pin according to the pin functionality.

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IO0DIR is the slow speed GPIO register, while the enhanced GPIO functions are supported via the register FIO0DIR.

Table 67. GPIO Direction register (IO0DIR - address 0xE002 8008) bit description

Bit Symbol Value Description Reset value

31:0 P0xDIR slow GPIO direction control bits. Bit 0 controls PIO0 ... bit 30 controls PIO30. 0x0000 0000

0 controlled pin is input 1 controlled pin is output

Table 68. Fast GPIO direction register (FIO0DIR - address 0x3FFF C000) bit description

Bit Symbol Value Description Reset value

31:0 FP0xDIR fast GPIO direction control bits. Bit 0 in FIO0DIR controls PIO0 ... Bit 30 in

0x0000 0000

Aside from the 32-bit long and word only accessible register FIODIR, every fast GPIO pins can also be controlled via several byte and half-word accessible registers listed in

Table 69

. Next to providing the same functions as register FIODIR, these additional

registers allow easier and faster access to the physical pins.

Table 69. Fast GPIO Direction control byte and half-word accessible register description

FIO0DIR0 8 (byte) 0x3FFF C000 fast GPIO direction control register 0. Bit 0 in register FIO0DIR0

FIO0DIR1 8 (byte) 0x3FFF C001 fast GPIO direction control register 1. Bit 0 in register FIO0DIR1

FIO0DIR2 8 (byte) 0x3FFF C002 fast GPIO direction control register 2. Bit 0 in register FIO0DIR2

FIO0DIR3 8 (byte) 0x3FFF C003 fast GPIO direction control register 3. Bit 0 in register FIO0DIR3

FIO0DIRL 16

FIO0DIRU 16

(half-word)

Address Description Reset

corresponds to PIO0 ... bit 7 to PIO7.

corresponds to PIO8 ... bit 7 to PIO15.

corresponds to PIO16 ... bit 7 to PIO23.

corresponds to PIO24 ... bit 7 to PIO31.

0x3FFF C000 fast GPIO direction control lower half-word register. Bit 0 in register

FIO0DIRL corresponds to PIO0 ... bit 15 to PIO15.

0x3FFF C002 fast GPIO direction control upper half-word register. Bit 0 in register

FIO0DIRU corresponds to PIO16 ... bit 15 to PIO31.

value

0x00

0x0000

13.4.2 Fast GPIO mask register (FIOMASK, FIO0MASK - 0x3FFF C010)

This register is available in the enhanced group of registers only. It is used to select pins that are not affected by a write acce ss to r egi ster FIOPIN, FIOSET or FIOCLR. Th e mask register also filters out the pin’s content when register FIOPIN is read.

A bit set to logic 0 in this register enables an access to the corresponding physical pin via a read or write access. If a bit in this register is logic 1, the correspon d ing pin is no t changed with write access and if read, is not reflected in the updated register FIOPIN. For software examples, see Section 13.5 “

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GPIO usage notes” on page 73.

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Table 70. Fast GPIO mask register (FIO0MASK - address 0x3FFF C010) bit description

Bit Symbol Value Description Reset value

31:0 FP0xMASK fast GPIO physical pin access control. 0x0000 0000

0 pin is affected by writes to registers FIOSET, FIOCLR, and FIOPIN. Current

state of pin is observable in register FIOPIN.

1 physical pin is unaffected by writes to registers FIOSET, FIOCLR and

FIOPIN. When register FIOPIN is read, this bit is not updated with state of physical pin

Aside from the 32-bit long and word-only accessible register FIOMASK, every fast GPIO pin can also be controlled via several byte and half-word accessible registers listed in

Table 71

. Next to providing the same functions as register FIOMASK, these additional

registers allow easier and faster access to the physical pins.

Table 71. Fast GPIO mask byte and half-word accessible register description

FIO0MASK0 8 (byte) 0x3FFF C010 fast GPIO mask register 0. Bit 0 in register FIO0MASK0

FIO0MASK1 8 (byte) 0x3FFF C011 fast GPIO mask register 1. Bit 0 in register FIO0MASK1

FIO0MASK2 8 (byte) 0x3FFF C012 fast GPIO mask register 2. Bit 0 in register FIO0MASK2

FIO0MASK3 8 (byte) 0x3FFF C013 fast GPIO mask register 3. Bit 0 in register FIO0MASK3

FIO0MASKL 16

FIO0MASKU 16

(half-word)

Address Description Reset

corresponds to PIO0 ... bit 7 to PIO7.

corresponds to PIO8 ... bit 7 to PIO15.

corresponds to PIO16 ... bit 7 to PIO23.

corresponds to PIO24 ... bit 7 to PIO31.

0x3FFF C001 fast GPIO mask lower half-word register. Bit 0 in register

FIO0MASKL corresponds to PIO0 ... bit 15 to PIO15.

0x3FFF C012 fast GPIO mask upper half-word register. Bit 0 in register

FIO0MASKU corresponds to PIO16 ... bit 15 to PIO31.

value

0x00

0x0000

13.4.3 GPIO Pin value register (IOPIN, IO0PIN - 0xE002 8000; FIOPIN, FIO0PIN 0x3FFF C014)

This register provides the values of pins that are configured to perform only digital functions. The register gives the logic value of the pin regardless of whether the pin is configured for input or output, or as GPIO or an alternate digital function. As an example, a particular pin can have GPIO input or GPIO output, UART receive, and PWM output as selectable functions. Any configuration of that pin allows its current logic state to be read from register IOPIN.

If a pin has an analog function as one of its options, the pin state cannot be read if the analog configuration is selected. Selecting the pin as an A/D input disconnects the digital features of the pin. In that case, the pin value read in register IOPIN is not valid.

Writing to register IOPIN stores the value in the pin ou tput register, bypassing the need to use both registers IOSET and IOCLR to obtain the entire written value. Use this feature carefully in an application since it affects all pins.

The slow speed GPIO register is the IO0PIN, while the enhanced GPIOs are supported via register FIO0PIN. Access to pins via register FIOPIN is conditioned by the corresponding register FIOMASK (see Section 13.4.2 on page 69

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Only pins masked with logic 0s in the mask register (see Section 13.4.2 on page 69) are correlated to the current content of the Fast GPIO pin value register.

Table 72. GPIO Pin value register (IO0PIN - address 0xE002 8000) bit description

Bit Symbol Description Reset value

31:0 P0xVAL slow GPIO pin value bits. Bit 0 in IO0PIN corresponds to PIO0 ... Bit 31 in IO0PIN

n/a

corresponds to PIO31.

Table 73. Fast GPIO pin value register (FIO0PIN - address 0x3FFF C014) bit description

Bit Symbol Description Reset value

31:0 FP0xVAL fast GPIO pin value bits. Bit 0 in FIO0PIN corresponds to PIO0 ... Bit 31 in FIO0PIN

n/a

corresponds to PIO31.

Aside from the 32-bit long and word-only accessible register FIOPIN, every fast GPIO can also be controlled via several byte and half-word accessible registers listed in Table 74 Next to providing the same functions as register FIOPIN, these additional registers allow easier and faster access to the physical pins.

Table 74. Fast GPIO pin value byte and half-word accessible register description

FIO0PIN0 8 (byte) 0x3FFF C014 fast GPIO pin value register 0. Bit 0 in register FIO0PIN0

FIO0PIN1 8 (byte) 0x3FFF C015 fast GPIO pin value register 1. Bit 0 in register FIO0PIN1

FIO0PIN2 8 (byte) 0x3FFF C016 fast GPIO pin value register 2. Bit 0 in register FIO0PIN2

FIO0PIN3 8 (byte) 0x3FFF C017 fast GPIO pin value register 3. Bit 0 in register FIO0PIN3

FIO0PINL 16

FIO0PINU 16

(half-word)

Address Description Reset

corresponds to PIO0 ... bit 7 to PIO7.

corresponds to PIO8 ... bit 7 to PIO15.

corresponds to PIO16 ... bit 7 to PIO23.

corresponds to PIO24 ... bit 7 to PIO31.

0x3FFF C014 fast GPIO pin value lower half-word register. Bit 0 in register

FIO0PINL corresponds to PIO0 ... bit 15 to PIO15.

0x3FFF C016 fast GPIO pin value upper half-word register. Bit 0 in register

FIO0PINU corresponds to PIO16 ... bit 15 to PIO31.

value

0x00

0x0000

13.4.4 GPIO output set register (IOSET, IO0SET - 0xE002 8004; FIOSET, FIO0SET 0x3FFF C018)

This register is used to produce a HIGH level output at pins configured as GPIO in an OUTPUT mode. Writing logic 1 produces a HIGH level at the corresponding pins. Writing logic 0 has no effect. If any pin is configured as an input or a secondary function, writing logic 1 to the corresponding bit in IOSET has no effect.

Reading register IOSET returns the value of this register, as determined by previous writes to IOSET and IOCLR (or IOPIN as noted above). This value does not reflect the effect of any outside world influence on the I/O pins.

IO0SET is the slow speed GPIO register while the enhanced GPIOs are supported via register FIO0SET . Access to pins via register FIOSET is conditioned by the corresponding register FIOMASK (see Section 13.4.2 on page 69

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Table 75. GPIO output set register (IO0SET - address 0xE002 8004) bit description

Bit Symbol Description Reset value

31:0 P0xSET slow GPIO output value set bits. Bit 0 in IO0SET corresponds to PIO0 ... Bit 31

0x0000 0000

in IO0SET corresponds to PIO31.

Table 76. Fast GPIO output set register (FIO0SET - address 0x3FFF C018) bit description

Bit Symbol Description Reset value

31:0 FP0xSET fast GPIO output value set bits. Bit 0 in FIO0SET corresponds to PIO0 ... Bit 31

0x0000 0000

in FIO0SET corresponds to PIO31.

Aside from the 32-bit long and word-only accessible register FIOSET, every fast GPIO can also be controlled via several byte and half-word accessible registers listed in Table 77 Next to providing the same functions as register FIOSET, these additional registers allow easier and faster access to the physical pins.

Table 77. Fast GPIO port 0 output set byte and half-word accessible register description

FIO0SET0 8 (byte) 0x3FFF C018 fast GPIO output set register 0. Bit 0 in register FIO0SET0

FIO0SET1 8 (byte) 0x3FFF C019 fast GPIO output set register 1. Bit 0 in register FIO0SET1

FIO0SET2 8 (byte) 0x3FFF C01A fast GPIO output set register 2. Bit 0 in register FIO0SET2

FIO0SET3 8 (byte) 0x3FFF C01B fast GPIO output set register 3. Bit 0 in register FIO0SET3

FIO0SETL 16

(half-word)

FIO0SETU 16

(half-word)

Address Description Reset

corresponds to PIO0 ... bit 7 to PIO7.

corresponds to PIO8 ... bit 7 to PIO15.

corresponds to PIO16 ... bit 7 to PIO23.

corresponds to P0in24 ... bit 7 to PIO31.

0x3FFF C018 fast GPIO output set lower half-word register. Bit 0 in register

FIO0SETL corresponds to PIO0 ... bit 15 to PIO15.

0x3FFF C01A fast GPIO output set upper half-word register. Bit 0 in register

FIO0SETU corresponds to PIO16 ... bit 15 to PIO31.

value

0x00

0x0000

13.4.5 GPIO output clear register (IOCLR, IO0CLR - 0xE002 800C; FIOCLR, FIO0CLR - 0x3FFF C01C)

This register is used to produce a LOW level output at pins configured as GPIO in an OUTPUT mode. Writing logic 1 produces a LOW level at the corr esponding pin and clears the corresponding bit in register IOSET. Writing logic 0 has no effect. If any pin is configured as an input or a secondary function, writing to IOCLR has no effect.

IO0CLR is the slow speed GPIO register while the enhanced GPIOs are supported via register FIO0CLR. Access to pins via register FIOCLR is conditioned by the corresponding register FIOMASK (see Section 13.4.2 on page 69

Table 78. GPIO output clear register 0 (IO0CLR - address 0xE002 800C) bit description

Bit Symbol Description Reset value

31:0 P0xCLR slo w GPIO output value clear bits. Bit 0 in IO0CLR corresponds to PIO0 ... Bit

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31 in IO0CLR corresponds to PIO31.

0x0000 0000

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Table 79. Fast GPIO output clear register 0 (FIO0CLR - address 0x3FFF C01C) bit description

Bit Symbol Description Reset value

31:0 FP0xCLR fast GPIO output value clear bits. Bit 0 in FIO0CLR corresponds to PIO0 ... Bit

0x0000 0000

31 in FIO0CLR corresponds to PIO31.

Aside from the 32-bit long and word-only accessible reg ister FIOCLR, every fast GPIO pin can also be controlled via several byte and half-word accessible registers listed in

Table 80

. Next to providing the same functions as register FIOCLR, these additional

registers allow easier and faster access to the physical pins.

Table 80. Fast GPIO output clear byte and half-word accessible register description

FIO0CLR0 8 (byte) 0x3FFF C01C fast GPIO output clear register 0. Bit 0 in register FIO0CLR0

FIO0CLR1 8 (byte) 0x3FFF C01D fast GPIO output clear register 1. Bit 0 in register FIO0CLR1

FIO0CLR2 8 (byte) 0x3FFF C01E fast GPIO output clear register 2. Bit 0 in register FIO0CLR2

FIO0CLR3 8 (byte) 0x3FFF C01F fast GPIO output clear register 3. Bit 0 in register FIO 0 CL R 3

FIO0CLRL 16

FIO0CLRU 16

(half-word)

Address Description Reset

corresponds to PIO0 ... bit 7 to PIO7.

corresponds to PIO8 ... bit 7 to PIO15.

corresponds to PIO16 ... bit 7 to PIO23.

corresponds to PIO24 ... bit 7 to PIO31.

0x3FFF C01C fast GPIO output clear lower half-word register. Bit 0 in register

FIO0CLRL corresponds to PIO0 ... bit 15 to PIO15.

0x3FFF C01E fast GPIO output clear upper half-word register. Bit 0 in register

FIO0SETU corresponds to PIO16 ... bit 15 to PIO31.

value

0x00

0x0000

13.5 GPIO usage notes

13.5.1 Example 1: sequential accesses to IOSET and IOCLR affecting the same GPIO pin/bit

The state of the output configured GPIO pin is determined by writes into the pin’s port IOSET and IOCLR registers. The last of these accesses to register IOSET/IOCLR determines the final output of a pin.

In the case of a code:

IO0DIR = 0x0000 0080 ;pin PIO7 configured as output IO0CLR = 0x0000 0080 ;PIO7 goes LOW IO0SET = 0x0000 0080 ;PIO7 goes HIGH IO0CLR = 0x0000 0080 ;PIO7 goes LOW

Pin PIO7 is configured as an output (write to register IO0DIR). PIO7 output is then set LOW (first write to register IO0CLR). Short high pulse follows on PIO7 (write access to IO0SET), and the final write to register IO0CLR sets pin PIO7 back to LOW level.

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13.5.2 Example 2: an immediate output of 0s and 1s on a GPIO port

A write access to pins IOSET followed by a write to register IOCLR results in pins outputting 0s slightly later than pins outputting 1s. There are systems that can tolerate this delay of a valid output, but for some applications simultaneous output of a binary content (mixed 0s and 1s) within a group of pins on a single GPIO port is required. This can be accomplished by writing to the pins register IOPIN.

The following code preserves existing output on pins PIO[31:16] and PIO[7:0] and at the same time sets PIO[15:8] to 0xA5, regardless of the previous value of pins PIO[15:8]:

IO0PIN = (IO0PIN && 0xFFFF00FF) || 0x0000A500

The same outcome can be obtained using the fast pin access. Solution 1: using 32-bit (word) accessible fast GPIO registers

FIO0MASK = 0xFFFF00FF; FIO0PIN = 0x0000A500;

Solution 2: using 16-bit (half-word) accessible fast GPIO registers

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FIO0MASKL = 0x00FF; FIO0PINL = 0xA500;

Solution 3: using 8-bit (byte) accessible fast GPIO registers

FIO0PIN1 = 0xA5;

13.5.3 Writing to IOSET/IOCLR vs. IOPIN

A write to register IOSET/IOCLR allows easy change of the pin’s selected output pin(s) to HIGH/LOW level at a time. Only pin/bit(s) in the IOSET/IOCLR written with logic 1 is set to HIGH/LOW level, while pin/bit(s) written with logic 0 remain unaffected. However, by just writing to either IOSET or IOCLR register it is not possible to output arbitrary binary data containing a mixture of 0s and 1s on a GPIO pin instantaneously.

A write to register IOPIN enables instantaneous output of a desired conte nt on the parallel GPIO. Binary data written into register IOPIN affects all output configured pins of that parallel port: 0s in IOPIN produces LOW level pin outputs, and 1s in IOPIN produces HIGH level pin outputs. In order to change the output of only a group of pins, the application must logically AND readout from the IOPIN with the mask containing 0s in bits corresponding to pins that will be changed, and 1s for all others. Finally, this result has to be logically ORred with the desired content and stored back into register IOPIN. Example 2 above illustrates the output of 0xA5 on pins 15 to 8 while preserving all other output pins as they were before.

13.5.4 Output signal frequency considerations when using slow speed GPIO and enhanced GPIO registers

The enhanced features of the fast GPIO pins available on this MPT612 make GPIO pins more responsive to code that has the task of controlling them. In particular, software access to a GPIO pin is 3.5 times faster via the fast GPIO registers than it is when a set of slow speed registers is used. As a result of the increased access speed, the maximum output frequency of the digital pin is also increased 3.5 times. T his large increase in output

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frequency is not always obvious when a plain C code is used. To gain full benefit from the fast GPIO features, write the portion of the application handling the fast pin output in assembly code and execute in ARM mode.

The following example shows code in which the pin control section is written in assembly language for ARM. First, port 0 is configured as a slow port, and the program generates two pulses on PIO20. Then port 0 is configured as a fast port, and two pulses are generated on PIO16. This illustrates the difference between the fast and slow GPIO port output capabilities. Once this code is compiled in ARM mode, its execution from the on-chip Flash yields the best results when the MAM module is configured as described in

Section 8.8 “

independent of the MAM setup.

loop: b loop

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MAM usage notes” on page 18. Execution from the on-chip SRAM is

/*set port 0 to slow GPIO */ ldr r0,=0xe01fc1a0 /*register address--SCS register*/ mov r1,#0x0 /*set bit 0 to 0*/ str r1,[r0] /*enable slow port*/ ldr r1,=0xffffffff /* */ ldr r0,=0xe0028008 /*register address--IODIR*/ str r1,[r0] /*set port 0 to output*/ ldr r2,=0x00100000 /*select PIO20*/ ldr r0,=0xe0028004 /*register address--IOSET*/ ldr r1,=0xe002800C /*register address--IOCLR*/

/*generate 2 pulses using slow GPIO on PIO0*/ str r2,[r0] /*HIGH*/ str r2,[r1] /*LOW*/ str r2,[r0] /*HIGH*/ str r2,[r1] /*LOW*/

/*set port 0 to fast GPIO */ ldr r0,=0xe01fc1a0 /*register address--enable fast port*/ mov r1,#0x1 str r1,[r0] /*enable fast port0*/ ldr r1,=0xffffffff ldr r0,=0x3fffc000 /*direction of fast port0*/ str r1,[r0] ldr r0,=0x3fffc018 /*FIO0SET -- fast port0 register*/ ldr r1,=0x3fffc01c /*FIO0CLR0 -- fast port0 register*/ ldr r2,=0x00010000 /*select fast port 0.16 for toggle*/

/*generate 2 pulses on the fast port*/ str r2,[r0] str r2,[r1] str r2,[r0] str r2,[r1]

Figure 17 illustrates the above code executed by the MPT612 Flash memory. The PLL

generated f MEMCR = 2 and MEMTIM = 3, and APBDIV = 1 (PCLK = CCLK).

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= 60 MHz out of external f

CCLK

= 12 MHz. The MAM was fully enabled with

osc

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aaa-000580

Fig 17. Illustration of the fast and slow GPIO access and output showing a 3.5 increase of the pin output

frequency

14. Universal Asynchronous Receiver/Transmitter 0 (UART0)

14.1 Features

• 16 byte receive and transmit FIFOs

• Register locations conforming to ‘550 industry standard

• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes

• Built-in fractional baud rate generator with autobauding capabilities.

• Mechanism that enables software and hardware flow control implem entation

14.2 Pin description

Table 81: UART0 pin description

Pin Type Description

RXD0 input serial input: serial receive data TXD0 output serial output: serial transmit data

14.3 Register description

UART0 contains registers organized as shown in Table 82. The Divisor Latch Access Bit (DLAB) is contained in U0LCR[7] and enables access to the divisor latches.

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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

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Table 82: UAR T0 register map

Name Description Bit functions and addresses Access Reset

U0RBR receiver buffer register 8-bit read data RO n/a 0xE000 C000

U0THR transmit holding register 8-bit write data WO n/a 0xE000 C000

U0DLL divisor latch LSB 8-bit data R/W 0x01 0xE000 C000

U0DLM divisor latch MSB 8-bit data R/W 0x00 0xE000 C004

U0IER interrupt enable register - - - - - - ABTO

U0IIR interrupt ID register - - - - - - ABTOInt ABEOInt RO 0x01 0xE000 C008

U0FCR FIFO control register RX Trigger Level - - - TX FIFO

U0LCR line control register DLAB Break

U0LSR line status register RXFE TEMT THRE BI FE PE OE RDR RO 0x60 0xE000 C014 U0SCR scratch pad register 8-bit data R/W 0x00 0xE000 C01C U0ACR auto-baud control register - - - - - - ABTO

U0FDR fractional divider register Reserved[31:8] 0x10 0xE000 C028

U0TER Tx enable register TXEN - - - - - - - R/W 0x80 0xE000 C030

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

MSB LSB

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

- - - - - RX Line

FIFO Enable - - Interrupt Identification Interrupt

Parity Select Parity

Control

-----Auto

MULVAL DIVADDVAL

Enable

Status

Interrupt

Enable

Reset

Stop Bit

Select

Restart

[1]

value

ABEO

IntEn

THRE

Interrupt

Enable

RX FIFO

Reset

Word Length Select R/W 0x00 0xE000 C00C

IntClr

Mode Start

IntEn

RBR

Interrupt

Enable

Pending

FIFO

Enable

ABEO

IntClr

R/W 0x00 0xE000 C004

WO 0x00 0xE000 C008

R/W 0x00 0xE000 C020

NXP Semiconductors

Address

(DLAB=0)

(DLAB=1)

(DLAB=0)

MPT612 User manual

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14.3.1 UART0 Receiver buffer register (U0RBR - 0xE000 C000, when DLAB = 0, Read Only)

The U0RBR is the top byte of the UART0 Rx FIFO. The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest” received data bit. If the character received is less tha n 8 bits, the unused MSBs are padded with zeroes.

In order to access the U0RBR, the Divisor Latch Access Bit (DLAB) in U0LCR must be logic 0. The U0RBR is always read only.

Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (that is, the one that is read in the next read from RBR), the right app roach for fetching the valid pair of received byte and its status bits is first to read the content of register U0LSR, and then to read a byte from the U0RBR.

Table 83: UART0 Receiver buffer register (U0RBR - address 0xE000 C000, when DLAB = 0,

Bit Symbol Description Reset value

7:0 RBR UART0 receiver buffer register contains the oldest received byte

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read only) bit description

undefined

in the UART0 Rx FIFO

14.3.2 UART0 Transmit holding register (U0THR - 0xE000 C000, when DLAB = 0, write only)

The U0THR is the top byte of the UART0 Tx FIFO. The top byte is the newest character in the Tx FIFO and can be written via the bus interface. The LSB represents the first bit to transmit.

In order to access the U0THR, the Divisor Latch Access Bit (DLAB) in U0LCR must be logic 0. The U0THR is always write only.

T able 84: UART0 Transmit holding register (U0THR - address 0xE000 C000, when DLAB = 0,

write only) bit description

Bit Symbol Description Reset value

7:0 THR writing to UART0 transmit holding register stores data in UART0

transmit FIFO. Byte is sent when it reaches bottom of FIFO and when transmitter is available.

n/a

14.3.3 UART0 Divisor latch registers (U0DLL - 0xE000 C000 and U0DLM 0xE000 C004, when DLAB = 1)

The UART0 Divisor Latch is part of the UART0 Fractional Baud Rate Generator and holds the value used to divide the clock supplied by the fractional prescaler in order to produce the baud rate clock, which must be 16x the desired baud rate (Equation 1 on page 79 Registers U0DLL and U0DLM together form a 16-bit divisor where U0DLL contains the lower 8 bits of the divisor and U0DLM contains the higher 8 bits of the divisor . A 0x0000 value is treated like a 0x0001 value as division by zero is not allowed. In order to access the UART0 divisor latches, the Divisor Latch Access Bit (DLAB) in U0LCR must be logic

Details on how to select the right value for U0DLL and U0DLM can be found later in this user manual.

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UARTn

baudrate

PCLK

16 256 UnDLM UnDLL+ 1

DivAddVal

MulVal

---------------------------- -







----------------------------------------------------------------------------------------------------------------------------------

Table 85: UART0 Divisor latch LSB register (U0DLL - address 0xE000 C000, when

Bit Symbol Description Reset value

7:0 DLL UART0 divisor latch LSB register and U0DLM register determine

Table 86: UART0 Divisor latch MSB register (U0DLM - address 0xE000 C004, when

Bit Symbol Description Reset value

7:0 DLM UART0 divisor latch MSB register and U0DLL re gister determine

14.3.4 UART0 Fractional divider register (U0FDR - 0xE000 C028)

The UART0 fractional divider register (U0FDR) controls the clock pre-scaler for the baud rate generation and can be read and written at the user’s discretion. This pre-scaler takes the APB clock and generates an output clock according to the specified fractional requirements.

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DLAB = 1) bit description

0x01

baud rate of UART0

DLAB = 1) bit description

0x00

baud rate of UART0

Remark: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of register DLL must be 3 or greater.

Table 87: UARTn Fractional divider register (U0FDR - address 0xE000 C028,

U2FDR - 0xE007 8028, U3FDR - 0xE007 C028) bit description

Bit Function Value Description Reset

value

3:0 DIVADDVAL 0 baud rate generation pre-scaler divisor value. If logic 0,

fractional baud rate generator will not affect UARTn baud rate.

7:4 MUL VAL 1 baud rate pre-scaler multiplier value. Must be greater than or

equal to 1 for UARTn to operate properly, regardless of whether fractional baud rate generator is used or not.

31:8 - n/a reserved, user software must not write logic 1s to reserved

bits; value read from a reserved bit is not defined

This register controls the clock pre-scaler for baud rate generation. The register reset value keeps the fractional capabilities of UART0 disabled ensuring that UAR T0 is fully software and hardware compatible with UARTs not equipped with this feature.

The UART0 baud rate can be calculated as (n = 0):

(1)

Where PCLK is the peripheral clock, U0DLM and U0DLL are the standard UART0 baud rate divider registers, and DIVADDVAL and MULVAL are UART0 fractional baud rate generator-specific parameters.

The value of MULVAL and DIVADDVAL must comply with the following conditions:

• 0 < MULVAL  15

• 0  DIVADDVAL  15

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• DIVADDVAL< MULVAL

The value of U0FDR must not be modified while transmitting/receiving dat a or dat a can be lost or corrupted.

If register U0FDR value does not comply with these two requests, then the fractional divider output is undefined. If DIV ADDVAL is zero, then the fractional divider is disabled, and the clock is not divided.

14.3.4.1 Baud rate calculation

UART can operate with or without using the fractional divider. In real-life ap plication s, it is likely that the desired baud rate can be achieved using several different fractional divider settings. The following algorithm illustrates one way of finding a set of DLM, DLL, MULVAL, and DIVADDVAL values. Such a set of parameters yields a baud rate with a relative error of less than 1.1 % from that desired.

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Calculating UART

Baud Rate (BR)

PCLK,

= PCLK/(16 × BR)

est

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Pick another FR

the range [1.1, 1.9]

est

from

false

is an

est

integer?

= 1.5

est

= Int(PCLK/(16 × BR × FR

est

= PCLK/(16 × BR × DL

est

1.1 < FR

est

DIVADDVAL = table(FR

MULVAL = table(FR

DLM = DL

DLL = DL

false

< 1.9?

true

[15:8]

est

[7:0]

est

true

DIVADDVAL = 0

MULVAL = 1

))

est

)

est

)

End

aaa-000584

Fig 18. Algorithm for setting UART dividers

Table 88. Fractional divider setting look-up table

FR DivAddVal/

MulVal

FR DivAddVal/

MulVal

FR DivAddVal/

MulVal

FR DivAddVal/

MulVal

1.000 0/1 1.250 1/4 1.500 1/2 1.750 3/4

1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13

1.071 1/14 1.273 3/11 1.538 7/13 1.778 7/9

1.077 1/13 1.286 2/7 1.545 6/11 1.786 11/14

1.083 1/12 1.300 3/10 1.556 5/9 1.800 4/5

1.091 1/11 1.308 4/13 1.571 4/7 1.818 9/11

1.100 1/10 1.333 1/3 1.583 7/12 1.833 5/6

1.111 1/9 1.357 5/14 1.600 3/5 1.846 11/13

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Table 88. Fractional divider setting look-up table …continued

FR DivAddVal/

1.125 1/8 1.364 4/11 1.615 8/13 1.857 6/7

1.133 2/15 1.375 3/8 1.625 5/8 1.867 13/15

1.143 1/7 1.385 5/13 1.636 7/11 1.875 7/8

1.154 2/13 1.400 2/5 1.643 9/14 1.889 8/9

1.167 1/6 1.417 5/12 1.667 2/3 1.900 9/10

1.182 2/11 1.429 3/7 1.692 9/13 1.909 10/11

1.200 1/5 1.444 4/9 1.700 7/10 1.917 11/12

1.214 3/14 1.455 5/11 1.714 5/7 1.923 12/13

1.222 2/9 1.462 6/13 1.727 8/11 1.929 13/14

1.231 3/13 1.467 7/15 1.733 11/15 1.933 14/15

MulVal

FR DivAddVal/

MulVal

FR DivAddVal/

MulVal

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FR DivAddVal/

MulVal

Example 1: PCLK = 14.7456 MHz, BR = 9600: according to the provided algorithm DL

= PCLK / (16  BR) = 14.7456 MHz / (16  9600) = 96. Since this DL

is an integer

est

number, DIVADDVAL = 0, MULVAL = 1, DLM = 0, and DLL = 96.

Example 2: PCLK = 12 MHz, BR = 115200: according to the provided algorithm DL

PCLK / (16  BR) = 12 MHz / (16  115200) = 6.51. This DL and the next step is to estimate the FR parameter. Using an initial estimate of FR a new DL FR

est

= 4 is calculated and FR

est

is recalculated as FR

est

= 1.628 is within the specified range of 1.1 and 1.9, DIVADDVAL and MULVAL

is not an integer number

est

= 1.628. Since

est

values can be obtained from the attached look-up table. The closest value for FR

= 1.628 in the look-up Table 88 is FR = 1.625. It is equivalent

est

to DIVADDVAL = 5 and MULVAL = 8. Based on these findings, the suggested UART setup would be: DLM = 0, DLL = 4,

DIVADDVAL = 5, and MULVAL = 8. According to Equation 2 on page 89

, the UART baud rate is 115384 Bd. This rate has a relative error of 0.16 % from the originally specified value of 115200 Bd.

14.3.5 UART0 Interrupt enable register (U0IER - 0xE000 C004, when DLAB = 0)

The U0IER is used to enable UART0 interrupt sources.

Table 89. UART0 Interrupt enable register (U0IER - address 0xE000 C004, when DLAB = 0)

bit description

Bit Symbol Value Description Reset

value

0RBR

Interrupt Enable

1THRE

Interrupt Enable

0 disables RDA interrupts 1 enables RDA interrupts

0 disables THRE interrupts 1 enables THRE interrupts

U0IER[0] enables receive data available interrupt for UART0. Also controls the character receive time-out interrupt.

U0IER[1] enables THRE interrupt for UART0. Status can be read from U0LSR[5].

est

=1.5

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Table 89. UART0 Interrupt enable register (U0IER - address 0xE000 C004, when DLAB = 0)

Bit Symbol Value Description Reset

2RX Line

7:3 -

8 ABEOIntEn enables end of auto-baud interrupt 0

9 ABTOIntEn enables the auto-baud time-out interrupt. 0

31:10 -

bit description

Status Interrupt Enable

…continued

U0IER[2] enables the UART0 Rx line status interrupts.

Status of interrupt can be read from U0LSR[4:1]. 0 disables Rx line status interrupts 1 enables Rx line status interrupts

reserved, user software must not write logic 1s to

reserved bits; value read from a reserved bit is not

0 disables end of auto-baud interrupt 1 enables end of auto-baud interrupt

0 disables auto-baud time-out interrupt 1 enables auto-baud time-out interrupt

defined

reserved, user software must not write logic 1s to

reserved bits; value read from a reserved bit is not

defined

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value

n/a

14.3.6 UART0 Interrupt identification register (U0IIR - 0xE000 C008, read only)

The U0IIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during an U0IIR access. If an interrupt occurs during an U0IIR access, the interrupt is recorded for the next U0IIR access.

Table 90: UART0 Interrupt identification register (UOIIR - address 0xE000 C008, read only)

bit description

Bit Symbol Value Description Reset

0 Interrupt

Pending

0 at least one interrupt is pending 1 no pending interrupts

3:1 Interrupt

Identification

011 1 - Receive Line Status (RLS 010 2a - Receive Data Available (RDA) 1 10 2b - Character Time-out Indicator (CTI) 001 3 - THRE interrupt

5:4 - reserved, user software must not write logic 1s to reserved

7:6 FIFO Enable bits are equivalent to U0FCR[0] 0

note that U0IIR[0] is active LOW. Pen ding interrupt can be determined by evaluating U0IIR[3:1].

U0IER[3:1] identifies an interrupt corresponding to UART0 Rx FIFO. All other combinations of U0IER[3:1] not listed above are reserved (000,100,101,111).

bits; value read from a reserved bit is not defined

value

n/a

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Table 90: UART0 Interrupt identification register (UOIIR - address 0xE000 C008, read only)

Bit Symbol Value Description Reset

8 ABEOInt end of auto-baud interrupt. True if auto-baud has finished

9 ABTOInt auto-baud time-out interrupt. T rue if auto-baud has timed out

31:10 - reserved, user software must not write logic 1s to reserved

Interrupts are handled as described in Table 91. Given the status of U0IIR[3:0], an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt. In order to clear the interrupt before exiting the Interrupt Service Routine, the U0IIR must be read.

The UART0 RLS interrupt (U0IIR[3:1] = 011) is the highest priority interrupt and is set whenever any one of four error conditions occur on the UART0 Rx input: Overrun Error (OE), Parity Error (PE), Framing Error (FE) and Break Interrupt (BI). Th e UART0 Rx error condition that sets the interrupt can be observed via U0LSR[4:1]. The interrupt is cleared after an U0LSR read.

bit description

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…continued

value

successfully and interrupt is enabled.

and interrupt is enabled.

n/a

bits; value read from a reserved bit is not defined

The UART0 RDA interrupt (U0IIR[3:1] = 010) shares the second-level priority with the CTI interrupt (U0IIR[3:1] = 110). The RDA is activated when the UART0 Rx FIFO reaches the trigger level defined in U0FCR[7:6] and is reset when the UART0 Rx FIFO depth falls below the trigger level. When the RDA interrupt goes active, the CPU can read a block of data defined by the trigger level.

The CTI interrupt (U0IIR[3:1] = 1 10) is a second-level interrupt and is set when the UAR T0 Rx FIFO contains at least one character and no UART0 Rx FIFO activity has occurred in

3.5 to 4.5 character times. Any UART0 Rx FIFO activity (read or write of UART0 RSR) clears the interrupt. This interrupt is intended to flush the UART0 RBR after a message is received that is not a multiple of the trigger level size. For example, if a peripheral wished to send a 105 character message and the trigge r level was 10 characte rs, the CPU wou ld receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts (depending on the service routine) resulting in the transfer of the remaining 5 characters.

Table 91: UART0 interrupt handling

U0IIR[3:0] value

0001 - none none 0110 highest Rx line status/error OE

Priority Interrupt type Interrupt source Interrupt reset

[1]

[2]

or PE

[2]

or FE

[2]

or BI

[2]

U0LSR read

[2]

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Table 91: UART0 interrupt handling …continued

U0IIR[3:0] value

0100 second Rx data available Rx data available or trigger level reached in FIFO

1100 second character time-out

0010 third THRE THRE

Priority Interrupt type Interrupt source Interrupt reset

[1]

(U0FCR0 = 1)

minimum of one character in Rx FIFO and no

indication

[1] Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved. [2] For details see Section 14.3.9 on page 87 [3] For details see Section 14.3.1 on page 78 [4] For details see Section 14.3.6 on page 83 and Section 14.3.2 on page 78

character input or removed during a time period depending on how many characters are in FIFO and trigger level setting (3.5 to 4.5 character times).

exact time is: [(word length)  7

number of characters)  8 + 1] RCLKs

[2]

 2]  8 + [(trigger level 

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U0RBR read UART0 FIFO drops below trigger level

U0RBR read

U0IIR read (if source of interrupt) or THR write

[3]

[4]

The UART0 THRE interrupt (U0IIR[3:1] = 001) is a third-level interrupt and is activated when the UART0 THR FIFO is empty provided certain initialization conditions have been met. These initialization conditions are intended to give the UART0 THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start-up. The initialization conditions implement a one-character delay minus the Stop bit whenever THRE = 1 and there have not been at least two characters in the U0THR at one time since the last THRE = 1 event. This delay is provided to give the CPU time to write data to U0THR without a THRE interrupt to decode and service. If the UART0 THR FIFO has held two or more characters at one time and currently, the U0THR is empty, a THRE interrupt is set immediately. The THRE interrupt is reset when a U0THR write occurs or a read of the U0IIR occurs and the THRE is the highest interrupt (U0IIR[3:1] = 001).

14.3.7 UART0 FIFO Control register (U0FCR - 0xE000 C008)

The U0FCR controls the operation of the UART0 Rx and Tx FIFOs.

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Table 92. UART0 FIFO Control register (U0FCR - address 0xE000 C008) bit description

Bit Symbol Value Description Reset

0 FIFO Enable 0 UART0 FIFOs disabled. Must not be used in application. 0

1RX FIFO

2TX FIFO

5:3 - 0 reserved, user software must not write logic 1s to reserved

7:6 RX Trigger

Reset

Level

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1 active HIGH ena ble for both UART0 Rx and Tx FIFOs and

U0FCR[7:1] access. Must be set for correct UART0 operation.

Any transition on this bit automatically clears UART0 FIFOs. 0 no impact on either UART0 FIFO 0 1 writing a logic 1 to U0FCR[1] clears all bytes in UART0 Rx

FIFO and resets pointer logic. This bit is self-clearing. 0 no impact on either UART0 FIFO 0 1 writing a logic 1 to U0FCR[2] clears all bytes in UART0 Tx

FIFO and resets pointer logic. This bit is self-clearing.

bits; value read from a reserved bit is not defined

determine how many receiver UART0 FIFO characters must

be written before an interrupt is activated 00 trigger leve l 0 (1 character or 0x01) 01 trigger leve l 1 (4 characters or 0x04) 10 trigger leve l 2 (8 characters or 0x08) 11 trigger leve l 3 (14 characters or 0x0E)

value

n/a

14.3.8 UART0 Line control register (U0LCR - 0xE000 C00C)

The U0LCR determines the format of the data character that is to be transmitted or received.

Table 93: UART0 Line control register (U0LCR - address 0xE000 C00C) bit description

Bit Symbol Value Description Reset

1:0 Word Length

Select

2 Stop Bit Select 0 1 stop bit 0

3 Parity Enable 0 disable parity generation and checking 0

5:4 Parity Select 00 odd parity. Number of 1s in transmitted character and attached parity bit is odd. 0

6 Break Control 0 disable break transmission 0

7 Divisor Latch

Access Bit (DLAB)

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value

00 5-bit character length 0 01 6-bit character length 10 7-bit character length 11 8-bit character length

1 2 stop bits (1.5 if U0LCR[1:0] = 00)

1 ena ble parity gen eration and checking

01 even parity. Number of 1s in transmitted character and attached parity bit is even. 10 forced 1 stick parity 11 forced 0 stick parity

1 enable bre ak transmission. Output pin UART0 TXD is forced to logic 0 when

U0LCR[6] is active HIGH. 0 disable access to divisor latches 0 1 enable access to divisor latches

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14.3.9 UART0 Line status register (U0LSR - 0xE000 C014, read only)

The U0LSR is a read-only register that provides status information on the UART0 Tx and Rx blocks.

Table 94: UAR T0 Line status register (U0LSR - address 0xE000 C014, read only) bit description

Bit Symbol Value Description Reset value

0 Receiver Data

Ready (RDR)

1 Overrun Error

(OE)

2 Parity Error

(PE)

3 Framing Error

(FE)

4 Break Interrupt

(BI)

5 Transmitter

Holding Register Empty (THRE))

6 Transmitter

Empty (TEMT)

U0LSR0 set when U0RBR holds an unread character and is cleared when

UART0 RBR FIFO is empty 0 U0RBR is empty 1 U0RBR contains valid data

overrun error condition set when overrun occurs. An U0LSR read clears

U0LSR1. U0LSR1 is set when UART0 RSR has a new character assembled

and UART0 RBR FIFO is full. In this case, UART0 RBR FIFO is not

overwritten and character in UART0 RSR is lost. 0 overrun error status is inactive 1 overrun error status is active

if parity bit of received character is wrong state, a parity error occurs. An

U0LSR read clears U0LSR[2]. Time of parity error detection is dependent on

U0FCR[0].

Remark: Parity error is associated with character at top of UART0 RBR FIFO. 0 parity error status is inactive 1 parity error status is active

if stop bit of received character is logic 0, a framing error occurs. An U0LSR

read clears U0LSR[3]. Time of framing error detection is dependent on

U0FCR0. Upon detection of a framing error, Rx attempts to resynchronize to

data and assumes bad stop bit is early start bit. However, it cannot be

assumed that next received byte is correct even if there is no framing error.

Remark: Framing error is associated with character at top of UART0 RBR

FIFO. 0 framing error status is inactive 1 framing error status is active

if RXD0 is held in spacing state (all 0s) for one full character transmission

(start, data, parity, stop), a break interrupt occurs. Once break condition is

detected, receiver goes idle until RXD0 goes to marking state (all 1s). A

U0LSR read clears this status bit. Time of break detection is dependent on

U0FCR[0].

Remark: Break interrupt is associated with character at top of UART0 RBR

FIFO. 0 break interrupt status is inactive 1 break interrupt status is active

THRE is set immediately upon detection of an empty UART0 THR and is

cleared on a U0THR write 0 U0THR contains valid data 1 U0THR is empty

TEMT is set when both U0THR and U0TSR are empty; TEMT is cleared when

either U0TSR or U0THR contain valid data 0 U0THR and/or the U0TSR contains valid data 1 U0THR and the U0TSR are empty

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Table 94: UAR T0 Line status register (U0LSR - address 0xE000 C014, read only) bit description

Bit Symbol Value Description Reset value

7 Error in RX

FIFO (RXFE)

0 U0RBR contains no UART0 Rx errors or U0FCR[0] = 0 1 UART0 RBR contains at least one UART0 Rx error

U0LSR[7] is set when a character with Rx error such as framing error, parity

error or break interrupt, is loaded into U0RBR. This bit is cleared when

…continued

14.3.10 UART0 Scratch pad register (U0SCR - 0xE000 C01C)

The U0SCR has no effect on the UART0 operation. This register can be written and/or read at the user’s discretion. There is no provision in the interrupt interface that would indicate to the host that a read or write of the U0SCR has occurred.

Table 95: UAR T0 Scratch pad register (U0SCR - address 0xE000 C01C) bit description

Bit Symbol Description Reset value

7:0 Pad read/write byte 0x00

14.3.11 UART0 Auto-baud control register (U0ACR - 0xE000 C020)

The UART0 Auto-baud control register (U0ACR) controls the process of measuring the incoming clock/data rate for the baud rate generation and can be read and written at the user’s discretion.

Table 96. Auto-baud control register (U0ACR - 0xE000 C020) bit description

Bit Symbol Value Description Reset value

0 Start automatically cleared after auto-baud completion 0

0 auto-baud stop (auto-baud is not running) 1 auto-baud start (auto-baud is running). Auto-baud

run bit. Automatically cleared after auto-baud completion.

1 Mode auto-baud mode select bit 0

0 mode 0 1 mode 1

2 AutoRestart 0 no restart 0

1 restart in case of time-out (counter restarts at next

UART0 Rx falling edge)

7:3 - n/a reserved, user software must not write logic 1s to

reserved bits; value read from a reserved bit is not defined

8 ABEOIntClr end of auto-baud interrupt clear bit (write only

accessible). Writing a logic 1 clears corresponding interrupt in U0IIR. Writing a logic 0 has no impact.

9 ABTOIntClr auto-baud time-out interrupt clear bit (write only

accessible). Writing a logic 1 clears corresponding interrupt in U0IIR. Writing a logic 0 has no impact.

31:10 - n/a reserved, user software must not write logic 1s to

reserved bits; value read from a reserved bit is not defined

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ratemin

2P CLK

16 215

------------------------ -

UART0

baudrate

PCLK

16 2 databits paritybits stopbits++ +

----------------------------------------------------------------------------------------------------------- -

 ratemax

14.3.12 Auto-baud

The UART0 auto-baud function can be used to me asure the in coming baud rate base d on the ”AT" protocol (Hayes command). If enabled, the auto baud feature measures the bit time of the receive data stream and sets the divisor latch registers U0DLM and U0DLL accordingly.

Auto-baud is started by setting bit U0ACR Start. Auto-baud can be stopped by clearing bit U0ACR Start. Bit Start clears once auto-baud has finished, and reading the bit returns the status of auto-baud (pending/finished).

Two auto-baud measuring modes are available which can be selected by bit U0ACR Mode. In mode 0 the baud-rate is measured on two subsequent falling edges of pin UART0 Rx (the falling edge of the start bit and the falling edge of the least significant bit). In mode 1 the baud rate is measured between the falling edge and the subsequent rising edge of pin UART0 Rx (the length of the start bit).

If a time-out occurs (the rate measurement co un ter overflows), bit U0ACR AutoRestart can be used to restart the baud rate measurement automatically. If this bit is set the rate measurement restarts at the next falling edge of pin UART0 Rx.

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The auto-baud function can generate two interrupts:

• The U0IIR ABTOInt interrupt is set if the interrupt is enabled (U0IER ABToIntEn is set

and the auto-baud rate measurement counter overflows)

• The U0IIR ABEOInt interrupt is set if the interrupt is enabled (U0IER ABEOIntEn is set

and the auto-baud has completed successfully)

The auto-baud interrupts must be cleared by setting the corresponding U0ACR ABTOIntClr and ABEOIntEn bits.

Typically the fractional baud rate generator is disabled (DIVADDVAL = 0) during auto-baud. However, if the fractional baud rate generator is enabled (DIVADDVAL > 0), it is going to impact the measuring of pin UART0 Rx baud rate, but the value of register U0FDR is not going to be modified after rate measurement. Also, when auto-baud is used, any write to registers U0DLM and U0DLL must be done before re gister U0ACR write. The minimum and the maximum baud rates supported by UART0 are function of PCLK, number of data bits, stop-bits and parity bits.

14.3.13 UART0 Transmit enable register (U0TER - 0xE000 C030)

MPT612’s U0TER enables implementation of software flow control. When TXEn = 1, the UART0 transmitter sends data as long as it is available. When TXEn = 0, UART0 transmission stops.

(2)

Table 97

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describes how to use bit TXEn to achieve software flow control.

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Table 97: UART0 Transmit enable register (U0TER - address 0xE000 C030) bit description

Bit Symbol Description Reset

6:0 - reserved, user software must not write logic 1s to reserved bits; value

7 TXEN if logic 1, as it is after a reset, data written to THR is output on pin TXD

14.3.14 Auto-baud modes

When the software is expecting an AT command, it configures the UART0 with the expected character format and sets bit U0ACR Start. The initial values in the divisor latches U0DLM and U0DLM a re set to do no t care. Beca use of the ”A" or ” a" ASCII coding (”A" = 0x41, ”a" = 0x61), pin UART0 Rx sensed start bit and the LSB of the expected character are delimited by two falling edges. When bit U0ACR Start is set, the auto-baud protocol executes the following phase s:

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value

n/a

read from a reserved bit is not defined

1 when any preceding data is sent. If cleared to logic 0 while a character is being sent, transmission of that character is completed, no further characters are sent until this bit is set again. In other words, if bit is logic 0, it blocks transfer of characters from THR or Tx FIFO into transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character.

1. On setting bit U0ACR Start, the baud-rate measurement counter is reset and the UART0 U0RSR is reset. The U0RSR baud rate is switched to the highest rate.

2. A falling edge on pin UART0 Rx triggers the beginning of the start bit. The rate measuring counter starts counting PCLK cycles optionally pre-scaled by the fractional baud rate generator.

3. During receipt of the start bit, 16 pulses are generated on baud input RSR at the frequency of the (fractional baud rate pre-scaled) UART0 input clock, guaranteeing the start bit is stored in U0RSR.

4. During the receipt of the start bit (and the character LSB for mode = 0), the rate counter continues incrementing with the pre-scaled UART0 inpu t clock (PCLK).

5. If Mode = 0, then the rate counter stops on the next falling edge of pin UART0 Rx. If Mode = 1, then the rate counter stops on the next rising edge of pin UART0 Rx.

6. The rate counter is loaded into U0DLM/U0DLL and the baud rate is switched to normal operation. After setting the U0DLM/U0DLL, the end of auto-baud interrupt U0IIR ABEOInt is set, if enabled. The U0RSR continues receiving the remaining bits of the ”A/a" character.

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'A' (0x41) or 'a' (0x61)

start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop

UART0 RX

U0ACR start

rate counter

16xbaud_rate

a. Mode 0 (start bit and LSB are used for auto-baud)

'A' (0x41) or 'a' (0x61)

start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop

UART0 RX

start bit

U0ACR start

rate counter

LSB of 'A' or 'a' start bit

16 cycles16 cycles

LSB of 'A' or 'a'

aaa-000636

16xbaud_rate

16 cycles

b. Mode 1 (only start bit is used for auto-baud)

Fig 19. Autobaud mode 0 and mode 1 waveforms

14.4 Architecture

The architecture of UART0 is shown in block diagram Figure 20. The APB interface provides a communications link between the CPU or host and the

UART0. The UART0 receiver block, U0RX, monitors the serial input line, RXD0, for valid input.

The UART0 RX shift register (U0RSR) accepts valid characters via RXD0. After a valid character is assembled in the U0RSR, it is passed to the UART0 Rx buffer register FIFO to await access by the CPU or host via the generic host interface.

The UART0 transmitter block, U0TX, accep ts data written by the CPU or host and buffers the data in the UART0 TX Holding register FIFO (U0THR). The UART0 TX Shift register (U0TSR) reads the data stored in the U0THR and assembles the data to transmit via the serial output pin TXD0.

aaa-000582

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The UART0 Baud Rate Generator block, U0BRG, generates the timing enables used by the UART0 TX block. The U0BRG clock input source is the APB clock (PCLK). The main clock is divided down per the divisor specified in registers U0DLL and U0DLM and is a 16 oversample clock, NBAUDOUT.

The interrupt interface contains registers U0IER and U0IIR. The interrup t interface receives several one clock-wide enables from the U0TX and U0RX blocks.

Status information from the U0TX and U0RX is stored in the U0LSR. Control information for the U0TX and U0RX is stored in the U0LCR.

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U0INTR

INTERRUPT

U0IER

U0IIR

U0SCR

U0TX

U0THR U0TSR

U0BRG

U0DLL

U0DLM

U0RX

U0RBR U0RSR

U0FCR

U0LSR

U0LCR

NTXRDY

TXD0

NBAUDOUT

RCLK

NRXRDY

RXD0

PA[2:0]

PSEL

PSTB

PWRITE

PD[7:0]

PCLK

Fig 20. UART0 block di a gram

APB

INTERFACE

DDIS

aaa-000583

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15. Universal Asynchronous Receiver/Transmitter 1 (UART1)

15.1 Features

UART1 is identical to UART0 with the addition of a modem interface

•

• UART1 contains 16 byte receive and transmit FIFOs

• Register locations conform to ‘550 industry standard

• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes

• Fractional baud rate generator with auto-bauding capabilities is built in

• Mechanism enables software and hardwa re flow control implementation

• Standard modem interface signals are included, and flow control (auto-CTS/RTS) is

fully supported in hardware

15.2 Pin description

Table 98. UART1 pin description

Pin Type Description

RXD1 input serial input. Serial receive data. TXD1 output serial output. Serial transmit data. CTS1 input clear to send. Active LOW signal indicates if external modem is ready to accept transmitted data

DCD1 input data carrier detect. Active LOW signal indicates if external modem has established a

DSR1 input data set ready. Active LOW signal indicates if external modem is ready to establish a

DTR1 output data terminal ready. Active LOW signal indicates that UART1 is ready to establish connection with

RI1 input ring indicator. Active LOW signal indicates that telephone ringing signal is detected by modem. In

RTS1 output request to send. Active LOW signal indicates that UART1 wants to transmit data to external

via TXD1 from UART1. In normal operation of modem interface (U1MCR[4] = 0), complement value of this signal is stored in U1MSR[4]. If enabled (U1IER[3] = 1), state change information is stored in U1MSR[0] and is a source for a priority level 4 interrupt.

communication link with UART1 and data can be exchanged. In normal operation of modem interface (U1MCR[4]=0), complement value of this signal is stored in U1MSR[7]. If enabled (U1IER[3] = 1), state change information is stored in U1MSR3 and is a source for a priority level 4 interrupt.

communications link with UART1. In normal operation of modem interface (U1MCR[4] = 0), complement value of this signal is stored in U1MSR[5]. If enabled (U1IER[3] = 1), state change information is stored in U1MSR[1] and is a source for a priority level 4 interrupt.

external modem. Complement value of this signal is stored in U1MCR[0].

normal operation of modem interface (U1MCR[4] = 0), complement value of this signal is stored in U1MSR[6]. If enabled (U1IER[3] = 1), state change information is stored in U1MSR[2] and is a source for a priority level 4 interrupt.

modem. Complement value of this signal is stored in U1MCR[1].

15.3 Register description

UART1 contains registers organized as shown in Table 99. The Divisor Latch Access Bit (DLAB) is contained in U1LCR[7] and enables access to the divisor latches.

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Table 99. UART1 register map

Name Description Bit functions and addresses Access Reset

U1RBR Receiver Buffer register 8-bit read data RO n/a 0xE001 0000

U1THR Transmit Holding register 8-bit write data WO n/a 0xE001 0000

U1DLL Divisor Latch LSB 8-bit data R/W 0x01 0xE001 0000

U1DLM Divisor Latch MSB 8-bit data R/W 0x00 0xE001 0004

U1IER Interrupt Enable register - - - - - - ABTO

U1IIR Interrupt Identification register - - - - - - ABTO

U1FCR FIFO Control register RX Trigger Level - - - TX FIFO

U1LCR Line Control register DLAB Break

U1MCR Modem Control register CTSen RTSen - Loopback

U1LSR Line Status register RXFE TEMT THRE BI FE PE OE RDR RO 0x60 0xE001 0014 U1MSR Modem Status register DCD RI DSR CTS Delta

U1SCR Scratch Pad register 8-bit data R/W 0x00 0xE001 001C U1ACR Auto-baud Control register - - - - - - ABTO

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

MSB LSB

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

CTS

Interrupt

Enable

FIFO Enable - - Interrupt Identification Interrupt

--- - -Auto

- - - Modem

Parity Select Parity

Control

Mode

Select

IntEn

RX Line

Status

Interrupt

Enable

DCD

Interrupt

Enable

Reset

Stop Bit

Select

--RTS

Trailing

Edge RI

Restart

THRE

Interrupt

Enable

Int

RX FIFO

Reset

Word Length

Select

Control

Delta DSR

IntClr

Mode Start

ABEO

Int

RBR

Interrupt

Enable

ABEO

Int

Pending

FIFO

Enable

DTR

Control

Delta

CTS

ABEO

IntClr

[1]

value

R/W 0x00 0xE001 0004

RO 0x01 0xE001 0008

WO 0x00 0xE001 0008

R/W 0x00 0xE001 000C

R/W 0x00 0xE001 0010

RO 0x00 0xE001 0018

R/W 0x00 0xE001 0020

NXP Semiconductors

Address

(DLAB=0)

(DLAB=1)

(DLAB=0)

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Table 99. UART1 register map

Name Description Bit functions and addresses Access Reset

U1FDR Fractional Divider register reserved[31:8] R/W 0x10 0xE001 0028

U1TER TX Enable register TXEN - - - - - - - R/W 0x80 0xE001 0030

[1] Reset value reflects the data stored in used bits only. It does not include the content of reserved bits.

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

…continued

MSB LSB

MULVAL DIVADDVAL

value

[1]

NXP Semiconductors

Address

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15.3.1 UART1 Receiver buffer register (U1RBR - 0xE001 0000, when DLAB = 0 read only)

The U1RBR is the top byte of the UART1 Rx FIFO. The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest” received data bit. If the character received is less tha n 8 bits, the unused MSBs are padded with logic 0s.

The Divisor Latch Access Bit (DLAB) in U1LCR must be logic 0 to access the U1RBR. The U1RBR is always read only.

Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (that is, the one that is read in the next read from the RBR), the right approach for fetching the valid pair of received bytes and status bits is first to read the content of register U1LSR, and then to read a byte from the U1RBR.

Table 100. UART1 Receiver buffer register (U1RBR - address 0xE001 0000, when DLAB = 0

Bit Symbol Description Reset value

7:0 RBR UART1 receiver buffer register contains oldest received byte in

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read only) bit description

undefined

UART1 Rx FIFO

15.3.2 UART1 Transmitter holding register (U1THR - 0xE001 0000, when DLAB = 0 write only)

The U1THR is the top byte of the UART1 Tx FIFO. The top byte is the newest character in the Tx FIFO and can be written via the bus interface. The LSB represents the first bit to transmit.

The Divisor Latch Access Bit (DLAB) in U1LCR must be logic 0 to access the U1THR. The U1THR is always write only.

Table 101. UART1 Transmitter holding register (U1THR - address 0xE001 0000, when

DLAB = 0 write only) bit description

Bit Symbol Description Reset

value

7:0 THR writing to UART1 transmit holding register stores data in UART1 transmit

FIFO. Byte is sent when it reaches bottom of FIFO and when the transmitter is available.

n/a

15.3.3 UART1 Divisor latch registers 0 and 1 (U1DLL - 0xE001 0000 and U1DLM 0xE001 0004, when DLAB = 1)

The UART1 divisor latch is part of the UART1 fraction al baud rate generato r and holds the value used to divide the clock supplied by the fractional prescaler to produce the baud rate clock, which must be 16 the desired baud rate (Equation 4 on page 11 1 U1DLL and U1DLM together form a 16-bit divisor where U1DLL contains the lower 8 bits of the divisor and U1DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as division by zero is not allowed. The Divisor Latch Access Bit (DLAB) in U1LCR must be logic 1 to access the UART1 divisor latches.

). Registers

Details on how to select the right value for U1DLL and U1DLM can be found later on in this chapter.

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UARTn

baudrate

PCLK

16 256 UnDLM UnDLL+ 1

DivAddVal

MulVal

---------------------------- -







----------------------------------------------------------------------------------------------------------------------------------

T able 102. UART1 Divisor latch LSB register (U1DLL - address 0xE001 0000, when DLAB = 1)

Bit Symbol Description Reset value

7:0 DLLSB UART1 divisor latch LSB register and U1DLM register

Table 103. UART1 Divisor latch MSB register (U1DLM - address 0xE001 0004, when

Bit Symbol Description Reset value

7:0 DLMSB UART1 divisor latch MSB register and U1DLL register

15.3.4 UART1 Fractional divider register (U1FDR - 0xE001 0028)

The UART1 Fractional divider register (U1FDR) control s the clock pre -scaler for th e baud rate generation and can be read and written at the user’s discretion. This pre-scaler takes the APB clock and generates an output clock according to the specified fractional requirements.

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bit description

0x01

determines baud rate of UART1

DLAB = 1) bit description

0x00

determines baud rate of UART1

Remark: If the fractional divider is active (DIVADDVAL > 0) a nd DLM = 0, the value of the DLL register must be 3 or greater.

Table 104. UART1 Fractional divider register (U1FDR - addres s 0xE001 0028) bit description

Bit Function Value Description Reset

value

3:0 DIVADDVAL 0 baud rate generation pre-scaler divisor value. If logic 0,

fractional baud rate generator will not affect UARTn baud rate.

7:4 MULVAL 1 baud rate pre-scaler multiplier value. Must be greater than

or equal to 1 for UARTn to operate properly, regardless of whether fractional baud rate generator is used or not.

31:8 - n/a reserved, user software must not write logic 1s to reserved

bits; value read from a reserved bit is not defined

This register controls the clock pre-scaler for baud rate generation. The reset value of th e register keeps the fractional capabilities of UART1 disabled making sure that UART1 is fully software and hardware compatible with UARTs not equipped with this feature.

UART1 baud rate can be calculated as (n = 1):

(3)

Where PCLK is the peripheral clock, U1DLM and U1DLL are the standard UART1 baud rate divider registers, and DIVADDVAL and MULVAL are UART1 fractional baud rate generator-specific parameters.

The value of MULVAL and DIVADDVAL must comply with the following conditions:

• 0 < MULVAL  15

• 0  DIVADDVAL  15

• D IVADDVAL < MULVAL

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The value of the U1FDR must not be modified while transmitting/receiving data or data can be lost or corrupted.

If register U1FDR value does not comply to these two request s, then the fractional divider output is undefined. If DIVADDVAL is zero, then the fractional divider is disabled, and the clock is not divided.

15.3.4.1 Baud rate calculation

UART can operate with or without using the fractional divider. In real-life ap plication s, it is likely that the desired baud rate can be achieved using several different fractional divider settings. The following algorithm illustrates one way of finding a set of DLM, DLL, MULV AL, and DIVADDVAL values. Such set of parameters yields a baud rate with a relative error of less than 1.1 % from that desired.

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Calculating UART

Baud Rate (BR)

PCLK,

Pick another FR

the range [1.1, 1.9]

est

from

false

= PCLK/(16 × BR)

est

is an

est

integer?

= 1.5

est

= Int(PCLK/(16 × BR × FR

est

= PCLK/(16 × BR × DL

est

1.1 < FR

est

DIVADDVAL = table(FR

MULVAL = table(FR

false

< 1.9?

true

est

true

DIVADDVAL = 0

MULVAL = 1

))

est

)

est

)

DLM = DL

DLL = DL

End

est est

[15:8]

[7:0]

aaa-000584

Fig 21. Algorithm for setting UART dividers

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Table 105. Fractional divider setting look-up table

FR DivAddVal/

1.000 0/1 1.250 1/4 1.500 1/2 1.750 3/4

1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13

1.071 1/14 1.273 3/11 1.538 7/13 1.778 7/9

1.077 1/13 1.286 2/7 1.545 6/11 1.786 11/14

1.083 1/12 1.300 3/10 1.556 5/9 1.800 4/5

1.091 1/11 1.308 4/13 1.571 4/7 1.818 9/11

1.100 1/10 1.333 1/3 1.583 7/12 1.833 5/6

1.111 1/9 1.357 5/14 1.600 3/5 1.846 11/13

1.125 1/8 1.364 4/11 1.615 8/13 1.857 6/7

1.133 2/15 1.375 3/8 1.625 5/8 1.867 13/15

1.143 1/7 1.385 5/13 1.636 7/11 1.875 7/8

1.154 2/13 1.400 2/5 1.643 9/14 1.889 8/9

1.167 1/6 1.417 5/12 1.667 2/3 1.900 9/10

1.182 2/11 1.429 3/7 1.692 9/13 1.909 10/11

1.200 1/5 1.444 4/9 1.700 7/10 1.917 11/12

1.214 3/14 1.455 5/11 1.714 5/7 1.923 12/13

1.222 2/9 1.462 6/13 1.727 8/11 1.929 13/14

1.231 3/13 1.467 7/15 1.733 11/15 1.933 14/15

MulVal

FR DivAddVal/

MulVal

FR DivAddVal/

MulVal

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FR DivAddVal/

MulVal

Example 1: PCLK = 14.7456 MHz, BR = 9600: according to the provided algorithm

= PCLK / (16  BR) = 14.7456 MHz / (16  9600) = 96. Since this DL

est

is an integer

est

number, DIVADDVAL = 0, MULVAL = 1, DLM = 0, and DLL = 96.

Example 2: PCLK = 12 MHz, BR = 115200: according to the provided algorithm DL

PCLK / (16  BR) = 12 MHz / (16  115200) = 6.51. This DL and the next step is to estimate the FR parameter. Using an initial estimate of FR a new DL FR

est

= 4 is calculated and FR

est

is recalculated as FR

est

= 1.628 is within the specified range of 1.1 and 1.9, DIVADDVAL and MULVAL

is not an integer number

est

= 1.628. Since

est

values can be obtained from the attached look-up table. The closest value for FR

= 1.628 in the look-up Table 88 on page 81 is FR = 1.625. It is

est

equivalent to DIVADDVAL = 5 and MULVAL = 8. Based on these findings, the suggested UART setup is: DLM = 0, DLL = 4,

DIV ADDVAL = 5, and MUL VAL = 8. According to Equation 3 on page 98

the UART’s baud rate is 115384 Bd. This rate has a relative error of 0.16 % from the originally specified value of 115200 Bd.

15.3.5 UART1 Interrupt enable register (U1IER - 0xE001 0004, when DLAB = 0)

The U1IER is used to enable UART1 interrupt sources.

est

= 1.5,

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