NXP Semiconductors MPC8349E-mITX-GP User Manual

Freescale Semiconductor

Document Number: MPC8349EMITXGPUG

User’s Guide

MPC8349E-mITX-GP Reference
Design Platform User’s Guide

Rev. 0, 10/2006

The MPC8349E-mITX-GP reference design platform is a
system featuring the powerful PowerQUICC™ II Pro
processor, which includes a built-in security accelerator.
This low-cost, high-performance system solution consists of
a printed circuit board (PCB) assembly known as the
MPC8349E-mITX-GP Board, plus a board support package
(BSP), distributed in a CD image. This BSP enables fastes t
possible time-to-market for deve lopme nt or integration of
applications including media servers, network attached
storage devices, and next-generation small office home
office/small medium business gateways.

Section 1, “MPC8349E-mITX-GP Board,” describes the

board in terms of its hardware: the features, specifications,
block diagram, connectors, interface specification, and
hardware straps.

Section 2, “Getting Started,” describes the board settings and

physical connections needed to boot the
MPC8349E-mITX-GP board.

Section 3, “MPC8349E-mITX-GP Software,” describes the

software that is shipped with the platform.
Use this manual in conjunction with the following

documents:

• MPC8349E PowerQUICC™ II Pr o I ntegrated Host
Processor Family Reference Manual
(MPC8349ERM)

Contents

1. MPC8349E-mITX-GP Board . . . . . . . . . . . . . . . . . . . 2

2. Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3. MPC8349E-mITX-GP Software . . . . . . . . . . . . . . . . 34

4. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

WARNING

This is a class A product. In a domestic
environment this product may cause radio
interference in which case the user may be
required to take adequate measures.

NOTE

This equipment has been tested and found to
comply with the limits for a Class A digital
device, pursuant to Part 15 of the FCC Rules.
These limits are designed to provide
reasonable protection against harmful
interference when the equipment is operated
in a commercial environment. This
equipment generates, uses, and can radiate
radio frequency energy and, if not installed
and used in accordance with the instruction
manual, may cause harmful interference to
radio communications. Operation of this
equipment in a residential area is likely to
cause harmful interference in which case the
user will be required to correct the
interference at his own expense.

© Freescale Semiconductor, Inc., 2006. All rights reserved.

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MPC8349E-mITX-GP Board

• MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications
(MPC8349EEC)

• Hardware and Layout Design Considerations for DDR Memory Interfaces (AN2582)

1 MPC8349E-mITX-GP Board

This section presents the features and block diagram, specifications, and mechanical data for the
MPC8349E-mITX-GP board.

1.1 Features

This section presents the features, specification, and block diagram of the MPC8349E-mITX-GP board.
The features are as follows:

• CPU: Freescale MPC8349E running at 533/266 MHz (CPU/CSB (Coherent System Bus))

• Memory subsystem:
— 128 MByte unbuffered DIMM SDRAM that is expandable to 1 Gbyte
— 8 MByte Flash memory (one Macronix™ MX29LV640M Flash memory bankorone ESSI

EN29LV640 Flash memory bank)

• Interfaces:
— 10/100/1000 BaseT Ethernet ports:

– TSEC1, GMII interface: one 10/100/1000 BaseT RJ-45 with RJ-45 interface using V itesse™

VSC8201 single port 10/100/1000 BaseT PHY

— USB 2.0 host and OTG:

– USB2, ULPI interface: one USB2.0 type mini-AB receptacle connector, with SMSC™

USB3300 Hi-Speed USB host/device/OTG PHY

— PCI2: 32-bit PCI interface running at up to 66 MHz

– One 32-bit 3.3 V PCI slot connected to PCI-2

— ST M24256 Serial EEPROM

™

— Dallas

DS1339 RT C with battery holder

• Board connectors:
—2 × 10 ATX power supply connector
— RS-232 connectors

–1 × 9 pin DB9 receptacle
– JTAG/COP for debugging

— Form factor: Mini-ITX form factor (170 mm × 170 mm, or 6692 mils × 6692 mils)

• 6-layer Printed Circuit Board (4-layer signals, 2-layer power and ground)

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Figure 1 shows the MPC8349E-mITX-GP board block diagram.

32-Bit PCI Slot

33/66 MHz

PCI

ULPI1

MPC8349E-mITX-GP Board

USB PHY

8 Mbyte Flash

64 Mbyte ~ 1 Gbyte DDR

RTC EEPROM

Local Bus

DDR Bus

I2C

MPC8349E

RS-232 x 2

GMII

JTAG/COP

GbE PHY

Power

1 x GbE

Power

Figure 1. MPC8349E-mITX-GP Board Block Diagram

1.2 Board-Level Functions

The board-level functions discussed in this section are reset, interrupts, and clock distribution.

1.2.1 Reset and Reset Configurations

The MPC8349E-mITX-GP reset module generates a single reset to reset the MPC8349E and other
peripherals on the board. The reset unit provides power-on reset, hard reset, and soft reset signals in
compliance with the MPC8349E hardware specification.

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Figure 2 shows the reset circuitry.

SRESET

TRST

HRESET from COP

from COP

from COP

3.3 V
MAX811

MR

Push Button

GND

Figure 2. Reset Circuitry of the MPC8349E

PORESET

FLASH

to MPC8349E

SRESET

TRST

to MPC8349E

to MPC8349E

MPC8349E

10/100/1000 PHY

USB PHYs

• Hard reset is generated either by the COP/JTAG port or the MPC8349E.

• Power-on reset is generated by the Maxim MAX811 device. When MR is deasserted and 3.3 V is
ready , the MAX81 1 internal timeout guarantees a minimum reset active time of 150 ms before
PORESET is deasserted. This circuitry guarantees a 150 ms PORESET pulse width after 3.3 V
reaches the right voltage level, and this meets the specification of the PORESET input of
MPC834x.

• COP/JTAG port reset provides convenient hard-reset capability for a COP/JT AG controller. The
RESET line is available at the COP/JTAG port connector. The COP/JTAG controller can directly
generate the hard-reset signal by asserting this line low.

• Push button reset interfaces the MR

signal with a debounce capability to produce a manual master

reset of the processor card.

• Soft reset is generated by the COP/JT AG port. Assertion of SRESET causes the MPC8349E to
abort all current internal and external transactions and set most registers to their default values.

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1.2.2 External Interrupts

Figure 3 shows the external interrupt circuitry to the MPC8349E.

External Logic

MPC8349E-mITX-GP Board

GBE1_IRQ

RTC_IRQ

USB2_IRQ

PCI_INTA

PCI_INTB

Figure 3. MPC8349E Interrupt Circuitry

IRQ2

IRQ3

IRQ4

IRQ5

IRQ6

MPC8349E

Following are descriptions of the interrupt signals shown in Figure 3:

• PHY interrupt (GBE1_IRQ) and RT C interrupt (RTC_IRQ).The VSC8201 GBE PHY interrupt is
ORed with the DS1339 RTC interrupt and connected to IRQ2 of the MPC8349E. Therefore, the
system software can detect the status of the Ethernet link, the PHY internal status, and the R TC
status.

• PCI interrupt (PCI_INTA, PCI_INTB). The 32-bit PCI slot I N TA and INTB are connected to the
IRQ4 and IRQ5 of the MPC8349E, respectively.

• USB over current (USB2_IRQ) . The USB2 power s upply has an over current detection circuit and
generate an interrupt when the current limit reaches (2A) or a thermal shutdown or under voltage
lockout (UVLO) condition occurs. This interrupt pin generates an interrupt to IRQ3 of the
MPC8349E.

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1.2.3 Clock Distribution

Figure 4 and Table 1 show the clock distribution on the MPC8349E-mITX-GP board.

66.666 MHz

OSC

CLKIN

33/66 MHz

PCI_SYNC_OUT

GPL5

CFG_CLKIN_DIV

PCI
DIV

OCCR

2

32-bit PCI Slot

25 MHz

24 MHz
Crystal

OSC

USB3300

VSC8201

125 MHz

TSEC

System

PLL

MPC8349E

local bus

DLL

DDR
DLL

PCI_SYNC_IN

LCLKx

33 MHz to 133 MHz

Local Bus CLK

MCKx

MCKx

133 MHz

DDR SDRAM

CLK

32.768 KHz
Crystal

DS1339

GND GND

Figure 4. MPC8349E-mITX-GP Clock Scheme

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GND GND

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MPC8349E-mITX-GP Board

Table 1. Clock Distribution

Clock Frequency Module Generated by Description

66.666 MHz MPC8349E CLKIN 66.666 MHz oscillator The MPC834x uses CLKIN to generate the
PCI_SYNC_OUT clock signal, which is fed back
on the board through the PCI_SYNC_IN signal
to the internal system PLL. From the power-on
reset configuration, the CSB clock is generated
by the internal PLL and is fed to the e300 core
PLL for generating the e300 core clock. The
GPL5 (CFG_CLKIN_DIV) configuration input
selects whether CLKIN or CLKIN/2 is driven on
the PCI_SYNC_OUT signal. The GPL5 is tied to
jumper J22.D.

125 MHz MPC8349E TSEC VSC8201 For TSEC operation, a 125 MHz clock is

provided by the gigabit Ethernet PHY
(VSC8201) on the board.

133/166 MHz DDR SDRAM MPC8349E The DDR memory controller is configured to use

the 1:1 mode CSB to DDR clock for the DDR
interface. The local bus clock uses CCB/n clock,
where n is configured from the LCRR register.

25 MHz GBE PHY (VSC8201) 125 MHz oscillator The 25 MHz oscillator generates the clock for

the VSC8201

33/66 MHz PCI 32-bit slot MPC8349E The PCI module uses the PCI_SYNC_IN as its

clock source. The trace of the PCI_SYNC_IN/
PCI_SYNC_OUT signal is synchronized with all
the PCI signals of the PCI slots. The trace length
of the PCI_SYNC_IN/PCI_SYNC_OUT clock is

2.5 inches from the pin of the PowerQUICC II
Pro device to the PCI sockets.

24 MHz USB PHY2 (USB3300) 24 MHz crystal

32.768 KHz RTC (DS1339) 32.768 KHz crystal

1.2.4 DDR SDRAM Controller

MPC8349E uses DDR SDRAM as the system memory. The DDR interface uses the SSTL2 driver/receiver
and 2.5 V power. A Vr ef 2.5V/2 is needed for all SSTL2 receivers in the DDR interface. For details on
DDR timing design and termination, refer to the Fr eescale application note entitled Hardw ar e and Layout
Design Considerations for DDR Memory Interfaces (AN2582). The termination scheme uses one series
resistor (R
termination rail (V

The MPC8349E reads the DIMM SPD data using the DIMM SCL (clock) and the SDA (data) signals
through the I2C2 interface. Figure 5 shows the DDR SDRAM controller connection.

) from the MPC8349E to the memory and one termination resistor (RT) attached to the

S

). This approach is used in commodity PC motherboard designs.

TT

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MPC8349E-mITX-GP Board

MPC8349E

DDR

SDRAM

Controller

DQ[0:63]

DQM[0:7]

DQS[0:7]

A[0:13], BA[0,1],CTRL

MCK[0:3] pairs

MSYNC_OUT

MSYNC_IN

I2C– SCK2

I2C–SDA2

V

1.25 V

ref

Figure 5. DDR SDRAM Connection

2.5 V Input

VTT 1.25 V

V

Generator

ref

VTT

Generator

SDRAM

DIMM184

DDR

2.5 V Input

V

ref

1.2.5 Local Bus Controller

The MPC8349E local bus controller has a 32-bit LAD[0–31] address that consists of data multiplex bus
and control signals. The local bus speed is up to 133 MHz. T o interface with the standard memory device,
an address latch must provide the address signals. The LALE is used as the latchi ng signal. To reduce the
load of the high speed 32-bit local bus interface, there is a data buffer for all low-speed devices attached
to the memory controller. The on-board single bank 8-Mbyte Flash memory module is connected to the
local bus.

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Figure 6 shows the block diagram and connections for the local bus.

MPC834E

Local Bus

Controller

LCS0

LCS0

Boot Flash

Select

Jumpers

F1CS

MPC8349E-mITX-GP Board

LAD[0:31]

BADDR[27:29]

ALE

LBCTL

Control Signals

LSYNC_OUT

LSYN_IN

LCLK0

LCKE

LCLK1

LAD[8:31]

LAD[0:15]

Address

Latch

LE

Buffer

DIR

Data

OE

OE

GND

A[9:30]

D[0:15]

F1CS

Control

Flash Memory

A[21:0]

D[15:0]

CS

Control

MX29LV640M

Figure 6. Local Bus Connections

1.2.6 On-Board Flash Memory

Through the general-purpose chip-select machine (GPCM), the MPC8349E-mITX-GP provides a total of
8 Mbyte of 90 ns Flash memory using one chip-select signal. The Flash memory is used with the 16-bit
port size.

J22.E BOOT1 Boot Flash Backup Flash

Jumper Off 1 Reserved Reserved

Jumper On 0 U7 U4

The starting address for the Flash bank is 0xFE00_0000 to 0xFE7F_FFFF.

1.2.7 I2C

The MPC8349E has two I2C interfaces. On the MPC8349E-mITX-GP board, the MPC8349E acts as I2C
master for both I

Freescale Semiconductor 9

2

C buses (I2C1 and I2C2). I2C1 is connected to the M24256 serial EEPROM, and I2C2

MPC8349E-mITX-GP Reference Design Platform User’s Guide, Rev. 0

Table 2. Boot Flash Selection

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MPC8349E-mITX-GP Board

is connected to the DDR DIMM module SPD (serial presence detect) EEPROM, the two PCF8574 I2C
expanders, the DS1339 RTC (real time clock).

The M24256 serial EEPROM can be used to s tore the reset configuration word of the MPC8349E, as well
as storing the configuration registers values if boot sequencer of MPC8349E is enabled. If user wants to
load the reset configuration word from the I2C1 M24256 EEPROM, the jumper J22 should be set to
ABCDEFGH=01011110, with 1=jumper removed and 0=jumper installed. For more details on how to
program the reset configuration word value in I2C EEPROM and the boot sequencer mode, please refer to
the MPC8349ERM. The I2C address of the M24256 EEPROM on I 2C1 bus is 0x50.

The DDR SPD EEPROM is connected to the I2C2 of MPC 8349E. The bootload program optionally reads
the SPD EEPROM data to determine the DDR DIMM physical structure (e.g. number of rows and
columns), the DDR timings (e.g. CAS latency, re-fresh timing), and setup the configuration registers of
the MPC8349E DDR memory controller . The I2C address of the DDR SPD EEPROM on I2C2 bus is 0x51.

There are two PCF8574A I2C I/O expander on the MPC8349E-mITX-GP board to provide general
purpose I/O expansion via the I2C2 interface. The first PCF8574A (U8) has I2C2 address 0x38 and it is
able to control the Green LED (D1) and Yellow LED (D2), set the VSC8201 to powerdown mode. The bit
definition of this PCF8574A (U8) is defined as in Table 3.

Table 3. PCF8574A (U8) Bit Descriptions

PCF8574A (U8)

Bit[0..7]

0LED0Write only,

1 LED1 Write only,

2 VSC8201_PWN Write only,

3

4 LCD_EN Write only,

5 Not used — —

6 Not used — —

7 Not used — —

Name Read/Write Description

LED0 control

Reserved

read returns 1

read returns 1

read returns 1

Write only,

read returns 1 Reserved

read returns 1 Reserved

0: LED is on
1: LED is off

LED1 control

0: LED is on
1: LED is off

VSC8201 power down control
0: VSC8201 PHY is powerdown

1: VSC8201 PHY in normal mode

The second PCF8574A (U10) has I2C2 address 0x39 and it is able to detect the board revision number,
the PCI M66EN signal level and detect which Flash is currently used to boot. The bit definition of this
PCF8574A (U10) is defined as in Table 4.

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Table 4. PCF8574A (U10) Bit Descriptions

MPC8349E-mITX-GP Board

PCF8574A

(U10) bit[0..7]

0 REV1 Read only, write

1 REV0

2 Reserved Read only, write

3

4 MPCI_CLKRUN Read/Write

5 PCI_M66EN Read only, write

6 BOOT0 Read only, write

Name Read/Write Description

Read only, write

Reserved

Board revision number

has no effect

has no effect

has no effect Reserved

has no effect

has no effect

REV[0:1] definition
00: revision 0.0

01: revision 0.1
10: revision 1.0
11: reserved

Reserved for future use

Reserved

PCI M66EN Signal
0: PCI M66EN signal is low, indicates the PCI cards on PCI slot is

not 66 MHz capable

1: PCI M66EN signal is high, indicates the PCI cards on PCI slot is

66 MHz capable

Used to determine which Flash is used for boot Flash
0: Reserved

1: Flash 1 (U7) is the boot Flash

7 Not used — —

The DS1339 R TC is connected to I2C with address 0x68. The software running on PowerPC core can read
or write to the RTC through the I2C2 interface.

1.2.8 10/100/1000 BaseT Interface

On the MPC8349E-mITX-GP board, GMII mode is used on TSEC1 , which is connected to the on-board
10/100/1000 PHY (VSC8201). The TSEC I/O voltage is s et to 3. 3 V. The GMII (1000 BaseT) is a source
synchronous bus. For a transmit bus connection, it is synchronous to GTX_CLK from the TSEC module.
The receive bus connection is synchronous to RX_CLK generated from the PHY device. When the speed
is 10/100 BaseT (MII), both t ransmit and re ceive clocks ar e generated by the VSC8201 PHY device. The
MPC8349E MII management interface is connected to the VSC8201 only . Figure 7 shows the connection
between the MPC8349E TSEC1 to the VSC8201.

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