NXP Semiconductors MPC57xx Application Note
1 Introduction
Freescale's Qorivva MPC57xx devices are the latest
generation of Automotive microcontrollers (MCU) based on
the Power Architecture™ core. This generation is
manufactured in a 55 nm wafer processing flow (c55).
Previous generations of devices were manufactured in larger
geometry technologies.
In addition to being manufactured in a smaller technology, the
e200zx cores used in the c55 devices have been updated for
higher speeds, lower power, and better die size utilization
(equating to lower cost for the core itself). Many features of
the cores are selectable by the definition requirements of the
individual devices that use these cores. This document outlines
major differences in the e200zx cores based on the options
selected for devices in the MPC57xx family. While it lists the
differences and gives a basic summary of the feature, this
document does not fully explain the feature in detail. The core
reference manuals should be consulted for additional
information.
The table below shows the different technologies, as well as
the different types of cores that are used by the different
families of devices, starting with the first fully integrated
Power Architecture core with embedded nonvolatile flash
memory and peripherals (MPC555). There was an earlier
Automotive Power Architecture, the MPC505/MPC509,
however, it did not have integrated flash or peripherals.
Freescale Semiconductor
Document Number:AN4802
Application Note
Rev 0, 10/2013
Qorivva MPC57xx e200zx Core
Differences
c55 process migration
by:
Randy Dees
© 2013 Freescale Semiconductor, Inc.
Contents
1 Introduction................................................................1
1.1 MPC57xx core instantiations.........................2
2 Differences between MPC57xx e200zx
cores...........................................................................3
2.1 e200zx core execution options....................... 3
2.2 e200zx bus interface and memory
options........................................... ................ 5
2.3 e200zx debug options............. .......................7
A Revision history.......................... ............................ 10
Table 1. Automotive Power Architecture MCU technologies
Family Manufacturing
technology
Transistor geometry Cores used
MPC555 CDR1 350 nm
1
RCPU (Automotive RISC)
MPC56x Family CDR3 250 nm
2
Qorivva MPC55xx
Family
HiP7 120 nm e200z0, e200z1, e200z3, e200z6
Qorivva MPC56xx
Family
c90 90 nm e200z0, e200z3, e200z4, e200z6, e200z7
Qorivva MPC57xx
Family
c55 55 nm e200z0, e200z2, e200z4, e200z7
1. 0.35 micron
2. 0.25 micron
1.1 MPC57xx core instantiations
Many of the different devices in the MPC57xx family have a varying number of cores, including devices with different types
of cores. The following table shows the cores that are instantiated on the different devices in the family. In addition, it shows
the core that debuggers can access after reset with a blank flash (or when a valid reset configuration is not programmed into
the flash). The table also shows whether any of the cores has the option of enabling a lock-step core. On this generation of
MCUs, the lock-step core cannot be used as an independent core, it can only be enabled as a lock-step core. The lock-step
core can be disabled to save power, however, this is not a significant amount of power.
Table 2. MPC57xx core summary
Device Revision Core 0 Core 1 Core 2 Lock-Step core
1
MPC5726L 1
2
e200z215An3 — — —
MPC5744K 1
3
e200z420n3 — e200z225n3
4
Core 0 (e200z419)
MPC5744K 2
2
e200z410Dn3 — e200z225Bn3
4
Core 0 (e200z409)
MPC5744P 1
3
e200z4201n3 — — Core 0 (e200z419)
MPC5744P 2 e200z4251n3 — — Core 0 (e200z424)
MPC5746M 1.0/1.1
3
e200z420n3 e200z420n3 e200z425n3
4
Core 0 (e200z419)
MPC5746M 2 e200z410n3 e200z410n3 e200z425Bn3
4
Core 0 (e200z409)
Future device 1 1
3
e200z425n3 e200z425n3
4
— Core 0 (e200z424)
Future device 1 2 e200z425n3 e200z425n3
4
— Core 0 (e200z424)
MPC5748G 1 e200z4204n3
4
e200z4204n3 e200z210n3 —
MPC5775K 1/1.1
3
e200z4201n3 e200z7260n3 e200z7260n3 Core 0 (e200z419)
MPC5775K 2 e200z4201n3 e200z7260n3 e200z7260n3 Core 0 (e200z419)
Future device 2 1 e200z759n3
4
e200z759n3 — Core 1 (e200z758)
MPC5777M 1
3
e200z720n3 e200z720n3 e200z425Bn3
4
Core 0 (e200z719)
MPC5777M 2 e200z710n3 e200z710n3 e200z425Bn3
4
Core 0 (e200z709)
1. This column shows which core the lock-step core is associated with.
2. This device will not be supported by Freescale.
3. This revision is not intended for production.
Introduction
Qorivva MPC57xx e200zx Core Differences, Rev 0, 10/2013
2 Freescale Semiconductor, Inc.
4. Initial default boot core that executes code from the Boot Assist Flash (BAF). Debuggers have access to this core initially
as well.
2 Differences between MPC57xx e200zx cores
The second major generation of the e200zx cores has minor variations for different devices. The following sections show all
of the devices in the MPC57xx family and the variations of the cores used in each device (and version). The core options
have been divided into three sections:
• Core instruction set and execution options (signal processing instruction options, saturated math instructions, floating
point type options, instruction issue option, lock-step option etc.).
• Core bus interface options (memory protection options, end-to-end error correction code options, crossbar bus width,
local memory options, and cache options)
• Core debug options (Nexus class, timestamp option, trace port width, and whether it has the fixed JTAG Nexus register
access sequence)
The tables in the following sections are arranged by core complexity. The e200z210 is the "simplest" core (feature-wise) and
with the e200z759 being the most complex.
2.1 e200zx core execution options
The first set of options that are available to be integrated into the cores instantiated into a particular MCU directly affect the
cores, including what instructions are supported and how the instructions execute. These options are shown in the following
table, then each of the options is explained in more detail.
Table 3. e200zx cores instruction differences
Device
Revision
Instantiation
Core Name
Book E
Dual Issue
Lockstep
General Purpose Registers
Signal Processing
Saturation
Floating Point
e200z210 based cores
MPC5748G 1.0 Core 2 e200z210n3 No Single No 32x32 No No No
e200z215 based cores
MPC5726L 1.0 Core 01e200z215An3 No Single No 32x32 No No Scalar
e200z225 based cores
MPC5744K 1.0 Core 21e200z225n3 No Single No 32x32 LSP No Scalar
MPC5744K 2.0 Core 21e200z225Bn3 No Single No 32x32 LSP Yes Scalar
e200z410 based cores
MPC5746M 2.0 Core 0/1 e200z410n3 No Single Delayed 32x32 No Yes Scalar
MPC5744K 2.0 Core 0 e200z410Dn3 No Single Delayed 32x32 No Yes Scalar
Table continues on the next page...
Differences between MPC57xx e200zx cores
Qorivva MPC57xx e200zx Core Differences, Rev 0, 10/2013
Freescale Semiconductor, Inc. 3
Table 3. e200zx cores instruction differences (continued)
Device
Revision
Instantiation
Core Name
Book E
Dual Issue
Lockstep
General Purpose Registers
Signal Processing
Saturation
Floating Point
e200z420 based cores
MPC5744K 1.0 Core 0 e200z420n3 No Dual Delay
ver.
32x32 No No Scalar
MPC5746M 1.0/1.1 Core 0/1
MPC5744P 1.0 Core 0 e200z4201n3 No Dual Delay
ver.
32x32 No No Scalar
MPC5775K 1.0/1.1/
2.0
Core 0 e200z4201n3 No Dual Delay
ver.
32x32 No No Scalar
MPC5748G 1.0 Core
01/1
e200z4204n3 No Dual No 32x32 No No Scalar
e200z425 based cores
MPC5746M 1.0 Core 21e200z425n3 No Dual No 32x32 LSP No Scalar
Future device 1 1.0 Core
0/1
1
e200z425n3 No Dual Delayed 32x32 LSP No Scalar
Future device 1 2.0 Core
0/1
1
e200z425n3 No Dual Delayed 32x32 LSP Yes Scalar
MPC5777M 1.0 Core 21e200z425Bn3 No Dual No 32x32 LSP No Scalar
MPC5746M 2.0 Core 21e200z425Bn3 No Dual No 32x32 LSP Yes Scalar
MPC5777M 2.0
MPC5744P 2.0 Core 0 e200z4251n3 No Dual Delayed 32x32 LSP No Scalar
e200z710 based cores
MPC5777M 2.0 Core 0/1 e200z710n3 No Single Delayed 32x32 No Yes Scalar
e200z720 based cores
MPC5777M 1.0 Core 0/1 e200z720n3 No Dual Delayed 32x32 No No Scalar
e200z7260 based cores
MPC5775K 1.0/1.1/
2.0
Core 1/2 e200z7260n3 No Dual No 32x64 SPE2 No Vector
e200z759 based cores
Future device 2 1.0 Core
0/1
1
e200z759n3 Yes Dual Delayed 32x64 SPE1.1 No Vector
1. Initial boot core.
Book E Support - Previous e200z3 through e200z7 cores supported both the Power Architecture Book E instruction set and
a more size efficient Variable Length Encoded (VLE) instruction set. The previous e200z0 cores used on some of the
MPC5500 and MPC5600 devices supported only the VLE instruction set. Most of new MPC57xx devices support only the
VLE instruction set, however, there is at least one device planned in the future that will support the full Book E instruction
set.
Differences between MPC57xx e200zx cores
Qorivva MPC57xx e200zx Core Differences, Rev 0, 10/2013
4 Freescale Semiconductor, Inc.
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