NXP Semiconductors MMPF0100 Programming Instructions Manual

Freescale Semiconductor

Application Note

Rev. 3.0, 1/2014

AN4536

MMPF0100 OTP Programming Instructions

1 Introduction

This document provides a detailed description of the
One-Time Programmable (OTP) function of the MMPF0100. It
provides the system requirements and instructions to progr am
the fuses for a selected power-up configuration. All examples
assume the customer is using silicon revision P1.1 or higher.

Freescale analog ICs are manufactured using the
SMARTMOS process, a combinational BiCMOS
manufacturing flow that integrates precision analog, power
functions and dense CMOS logic together on a single
cost-effective die.

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 OTP Overview. . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.1 Power-up Configuration. . . . . . . . . . . . . . . . 2

2.2 OTP Programming Example. . . . . . . . . . . . 3

2.3 Try-Before-Buy Mode Example. . . . . . . . . . 8

2.4 OTP Registers Description . . . . . . . . . . . . 10

2.5 Fuse Programming and Error Correction Code

(ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3 Hardware Considerations . . . . . . . . . . . . . . . . 28

3.1 Programming the MMPF0100 on an Application

Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2 Isolating SCL/SDA. . . . . . . . . . . . . . . . . . . 29

3.3 Programming using the PF-Programmer . 30

3.4 Programming using a Generic Programmer33

4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5 Revision History . . . . . . . . . . . . . . . . . . . . . . . 35

© Freescale Semiconductor, Inc., 2014. All rights reserved.

OTP Overview

2 OTP Overview

The regulators in the MMPF0100 have been designed with flexibility and configurability to allow them to be adapted
for a wide variety of applications. One-T ime-Programma ble (OTP) fuses in the MMPF0100 are used to exercise this
flexibility. Key startup parameters and regulator configuration information can be programmed into the MMPF0100
to enable it to power the system. These parameters are:

• General: I2C slave address, PWRON pin configuration, regulator start-up sequence and timing,
RESETBMCU configuration

• Buck regulators: Output voltage, dual/single phase or independent mode configuration, switching
frequency, and soft start ramp rate

• Boost regulator and LDOs: Output voltage

MMPF0100 starts up based on the contents of the TBBOTP registers. The TBBOTP registers can be loaded from
different sources as shown in
non-programmed and programmed MMPF0100 devices. Once OTP programming is complete, TBBOTP can be
either loaded from the default values or from the OTP fuses.

The OTP block in the MMPF0100 also features a ‘Try-Before-Buy’ (TBB) mode which allows experimentation with
different voltag es an d se que nces of th e r egulator s. In t he TBB mo de, TBBOTP reg ister s are dire ctly wr itten to a nd
used for startup of the MMPF0100. Content s of the TBBOTP registers can be maint ained in the absence of the main
input supply, VIN, by using a coin cell at the LICELL pin.

Table 1. The default setting is hard-coded in the MMPF0100 and is available in all

2.1 Power-up Configuration

The PF0100 powers up based on the contents of the TBBOTP registers. Depen ding on cert ain pin and bit settings,
the TBBOTP registers are loaded from different sources as shown in

Table 1. Power-up Configuration Source and Conditions

Source Condition Power-Up Configuration

ROM VDDOTP = VCOREDIG

TBBOTP Registers VDDOTP = 0 V and TBB_POR = 1

OTP Fuses

Notes:

1. Pull-up VDDOTP to VCOREDIG with a 100 k resistor.

2. In MMPF0100, FUSE_POR1, FUSE_POR2 and FUSE_POR3 are XOR’ed into the FUSE_POR_XOR bit. The FUSE_POR_XOR has to be
1 for fuses to be loaded. This can be achieved by setting any one or all of the FUSE_PORx bits. In MMPF0100A, the XOR function is
removed. It is required to set all of the FUSE_PORx bits to be able to load the fuses.

VDDOTP = 0 V and
TBB_POR = 0 and FUSE_POR_XOR = 1

(1)

(2)

The TBBOTP registers serve as temporary storage for any of the following:

1. The values to be written to the fuses, or

2. The values read from the fuses, or

3. The values to start from during TBB development, or

4. The values read from the default configuration.

Table 1.

MMPF0100 starts up using the factory default settings
MMPF0100 starts up from current values of TBBOTP

registers. This is referred to as the 'Try-Before-Buy'
mode

The MMPF0100 starts up from the OTP fuse values

The TBBOTP registers are located within the Extended Page 1 of the MMPF0100 register map.

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OTP Overview

During a power-up, the TBBOTP registers behave as follows:

• The contents of the TBBOTP registers are initialized to zero when a valid VIN is first applied.

• The values that are then loaded in to the TBBOTP registers depend o n the setting of the VDDOTP pi n, and
on the value of the TBB_POR, and the FUSE_POR_XOR bits. Refer to

Table 1.

• If VDDOTP = VCOREDIG (1.5 V), the TBBOTP values are loaded from ROM.

• If VDDOTP = 0 V , TBB_POR = 0 and FUSE_POR_XOR = 1; the TBBOTP values are loaded from the fuses.

• If VDDOTP = 0, TBB_POR = 0 and FUSE_POR_XOR=0; the TBBOTP registers remain initialized at zero.

• The initial value of TBB_POR is always “0”, only when VDDOTP = 0 V and TBB_POR is set to “1”, are the
values from the TBBOTP registers maintained and not loaded from a different source.

The contents of the TBBOTP registers may be modified by I2C. To communicate with I2C, VIN must be valid and
VDDIO, to which SDA and SCL are pulled up, must be powered by a 1.7

V to 3.6 V supply. VIN or the coin cell
voltage must be valid to maintain the contents of the TBBOTP registers. To power on with the contents of the
TBBOTP registers, a valid turn-on event must oc cu r wi th the following conditions: a valid VIN, optional LICELL,
VDDOTP

= 0 V, TBB_POR = 1.

2.2 OTP Programming Example

The One-Time-Programmable memory is realized using fuses. The startup configuration can be programmed into
the MMPF0100 by changing the state of these fuses as required during the OTP programming process.

There are 10 banks of fuses with each bank consisting of 26 fuses. Of the 26 fuses in a bank, 20 are programmable
by the user. Th e remaining 6 are redundant fuses that allow impl ementation of Error Correction. An Err or Correction
Code within the MMPF0100 corrects single bit errors if they occur in the bank.

The following is an example of programming the MMPF0100 and MMPF0100A. MMPF0100A refers to the newer
silicon version of MMPF0100. Refer to the product Data Sheet for complete details.

Note that the programming voltage and time-delay during fuse programming is different between the two silicon
revisions. The programming voltage should have a tolerance of +/-3% and OTP programming should be done at
room temperature. For reliability reasons, do not OTP program a given part more than once.

Note: All code examples in this document represent a script using the KITPFPGMEVME and the associated GUI.
Command syntax may vary if the user utilizes a different tool for communication.

//--------------------------------------------------------------------------­// F0 - Sample Configuration
// Set VDDOTP = 0 V, PWRON = HIGH, LICELL = 3.0 V (Optional), VIN = VDDIO = 3.3 V
//---------------------------------------------------------------------------

WRITE_I2C:7F:01 // Access PF0100 EXT Page1

//[Extended Page 1 Registers: 0xA0 - 0xAF] ----------------------------------

WRITE_I2C:A0:2B // Sw1AB Voltage = 1.375 V
WRITE_I2C:A1:01 // Sw1AB Sequence = 1
WRITE_I2C:A2:05 // Sw1AB Freq = 2MHZ, Mode = Single phase
WRITE_I2C:A8:2B // Sw1c Voltage = 1.375 V
WRITE_I2C:A9:02 // Sw1c Sequence = 2
WRITE_I2C:AA:01 // Sw1c Freq = 2 MHZ
WRITE_I2C:AC:72 // Sw2 Voltage = 3.30 V

WRITE_I2C:AD:05 // Sw2 Sequence = 5
WRITE_I2C:AE:01 // Sw2 Freq = 2 MHZ

//[Extended Page 1 Registers: 0xB0 - 0xBF] ----------------------------------

WRITE_I2C:B0:2C // Sw3A Voltage = 1.500 V

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OTP Overview

WRITE_I2C:B1:03 // Sw3A Sequence = 3
WRITE_I2C:B2:05 // Sw3A Freq = 2 MHZ, Mode = Single phase
WRITE_I2C:B4:2C // Sw3B Voltage = 1.500 V
WRITE_I2C:B5:03 // Sw3B Sequence = 3
WRITE_I2C:B6:01 // Sw3B Freq = 2 MHZ
WRITE_I2C:B8:6F // Sw4 Voltage = 3.150 V
WRITE_I2C:B9:06 // Sw4 Sequence = 6
WRITE_I2C:BA:01 // Sw4 Freq = 2 MHZ
WRITE_I2C:BC:00 // Swbst Voltage = 5 V
WRITE_I2C:BD:0D // Swbst Sequence = 13

//[Extended Page 1 Registers: 0xC0 - 0xCF] ----------------------------------

WRITE_I2C:C0:06 // Vsnvs Voltage = 3 V
WRITE_I2C:C4:03 // Vsnvs Sequence = 3
WRITE_I2C:C8:0E // Vgen1 Voltage = 1.50 V
WRITE_I2C:C9:09 // Vgen1 Sequence = 9
WRITE_I2C:CC:0E // Vgen2 Voltage = 1.5 V
WRITE_I2C:CD:0A // Vgen2 Sequence = 10

//[Extended Page 1 Registers: 0xD0 - 0xDF] ----------------------------------

WRITE_I2C:D0:07 // Vgen3 Voltage = 2.5 V
WRITE_I2C:D1:0B // Vgen3 Sequence = 11
WRITE_I2C:D4:00 // Vgen4 Voltage = 1.8 V
WRITE_I2C:D5:07 // Vgen4 Sequence = 7
WRITE_I2C:D8:0A // Vgen5 Voltage = 2.8 V
WRITE_I2C:D9:0C // Vgen5 Sequence = 12
WRITE_I2C:DC:0F // Vgen6 Voltage = 3.3 V
WRITE_I2C:DD:08 // Vgen6 Sequence = 8

//[Extended Page 1 Registers: 0xE0 - 0xEF] ----------------------------------

WRITE_I2C:E0:0E // Power-up DVS = 1.5625 mV/us, SeqCLK = 2 ms, PWRON config = 0
WRITE_I2C:E1:0E // Power-up DVS = 1.5625 mV/us, SeqCLK = 2 ms, PWRON config = 0
WRITE_I2C:E2:0E // Power-up DVS = 1.5625 mV/us, SeqCLK = 2 ms, PWRON config = 0
WRITE_I2C:E8:00 // Power Good = Disabled

//[Extended Page 1 Registers: 0xF0 - 0xFF] ----------------------------------

WRITE_I2C:FF:08 // I2C Device Address = 0x08

//===========================================================================
// PROGRAMMING COMMANDS FOLLOW
//===========================================================================

WRITE_I2C:E4:02 // FUSE POR=1 (This Enables OTP Programming)
WRITE_I2C:E5:02 // FUSE POR=1 (This Enables OTP Programming)
WRITE_I2C:E6:02 // FUSE POR=1 (This Enables OTP Programming)

//---------------------------------------------------------------------------

WRITE_I2C:F0:1F // Enable ECC for fuse banks 1 to 5
WRITE_I2C:F1:1F // Enable ECC for fuse banks 6 to 10
WRITE_I2C:7F:02 // Access PF0100 EXT Page2

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WRITE_I2C:D0:1F // Set Auto ECC for fuse banks 1 to 5
WRITE_I2C:D1:1F // Set Auto ECC for fuse banks 6 to 10

//---------------------------------------------------------------------------

WRITE_I2C:F1:00 // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F2:00 // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F3:00 // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F4:00 // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F5:00 // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F6:00 // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F7:00 // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F8:00 // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F9:00 // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:FA:00 // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

//---------------------------------------------------------------------------

VPGM:ON // Turn ON 9.5 V supply for PF0100A. Turn ON 9.0 V supply for PF0100.

// VPGM:ON turns on supply to the VDDOTP pin

DELAY:500 // Adds 500 msec delay to allow VPGM time to ramp up

//--------------------------------------------------------------------------­// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
//--------------------------------------------------------------------------­// BANK 1
//---------------------------------------------------------------------------

WRITE_I2C:F1:03 // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F1:0B // Set Bank 1 ANTIFUSE_EN
DELAY:100 // Allow 100 ms for PF0100A. Use 50 ms for PF0100.
WRITE_I2C:F1:03 // Reset Bank 1 ANTIFUSE_EN
WRITE_I2C:F1:00 // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

//---------------------------------------------------------------------------

// BANK 2
//---------------------------------------------------------------------------

WRITE_I2C:F2:03 // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F2:0B // Set Bank 2 ANTIFUSE_EN
DELAY:100 // Allow 100 ms for PF0100A. Use 50 ms for PF0100.
WRITE_I2C:F2:03 // Reset Bank 2 ANTIFUSE_EN
WRITE_I2C:F2:00 // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

//--------------------------------------------------------------------------­// BANK 3
//---------------------------------------------------------------------------

WRITE_I2C:F3:03 // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F3:0B // Set Bank 3 ANTIFUSE_EN
DELAY:100 // Allow 100ms for PF0100A. Use 50 ms for PF0100.
WRITE_I2C:F3:03 // Reset Bank 3 ANTIFUSE_EN
WRITE_I2C:F3:00 // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

OTP Overview

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OTP Overview

//--------------------------------------------------------------------------­// BANK 4
//---------------------------------------------------------------------------

WRITE_I2C:F4:03 // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F4:0B // Set Bank 4 ANTIFUSE_EN
DELAY:100 // Allow 100ms for PF0100A. Use 50 ms for PF0100.
WRITE_I2C:F4:03 // Reset Bank 4 ANTIFUSE_EN
WRITE_I2C:F4:00 // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

//--------------------------------------------------------------------------­// BANK 5
//---------------------------------------------------------------------------

WRITE_I2C:F5:03 // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F5:0B // Set Bank 5 ANTIFUSE_EN
DELAY:100 // Allow 100 ms for PF0100A. Use 50 ms for PF0100.
WRITE_I2C:F5:03 // Reset Bank 5 ANTIFUSE_EN
WRITE_I2C:F5:00 // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

//--------------------------------------------------------------------------­// BANK 6
//---------------------------------------------------------------------------

WRITE_I2C:F6:03 // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F6:0B // Set Bank 6 ANTIFUSE_EN
DELAY:100 // Allow 100ms for PF0100A. Use 50 ms for PF0100.
WRITE_I2C:F6:03 // Reset Bank 6 ANTIFUSE_EN
WRITE_I2C:F6:00 // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

//--------------------------------------------------------------------------­// BANK 7
//---------------------------------------------------------------------------

WRITE_I2C:F7:03 // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F7:0B // Set Bank 7 ANTIFUSE_EN
DELAY:100 // Allow 100 ms for PF0100A. Use 50 ms for PF0100.
WRITE_I2C:F7:03 // Reset Bank 7 ANTIFUSE_EN
WRITE_I2C:F7:00 // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

//--------------------------------------------------------------------------­// BANK 8
//---------------------------------------------------------------------------

WRITE_I2C:F8:03 // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F8:0B // Set Bank 8 ANTIFUSE_EN
DELAY:100 // Allow 100 ms for PF0100A. Use 50 ms for PF0100.
WRITE_I2C:F8:03 // Reset Bank 8 ANTIFUSE_EN
WRITE_I2C:F8:00 // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

//--------------------------------------------------------------------------­// BANK 9
//---------------------------------------------------------------------------

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WRITE_I2C:F9:03 // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:F9:0B // Set Bank 9 ANTIFUSE_EN
DELAY:100 // Allow 100 ms for PF0100A. Use 50 ms for PF0100.
WRITE_I2C:F9:03 // Reset Bank 9 ANTIFUSE_EN
WRITE_I2C:F9:00 // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

//--------------------------------------------------------------------------­// BANK 10
//---------------------------------------------------------------------------

WRITE_I2C:FA:03 // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
WRITE_I2C:FA:0B // Set Bank 10 ANTIFUSE_EN
DELAY:100 // Allow 100 ms for PF0100A. Use 50 ms for PF0100.
WRITE_I2C:FA:03 // Reset Bank 10 ANTIFUSE_EN
WRITE_I2C:FA:00 // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits

//---------------------------------------------------------------------------

WRITE_I2C:D0:00 // Clear
WRITE_I2C:D1:00 // Clear

//---------------------------------------------------------------------------

VPGM:OFF // Turn off 8.5 V Boost Supply
DELAY:500 // Adds delay to allow VPGM to bleed off
PWRON:LOW // PWRON LOW to reload new OTP data
DELAY:500
PWRON:HIGH

OTP Overview

After OTP programming is complete by following the above steps, read the registers 0xA0 to 0xE8 in Extended Page
1 and compare to the required register values as in the script. Additionally, read the ECC Interrupt bit, OTP_ECCI
in register 0x0E. If there is an error in the programmed values or if the OTP_ECCI bit is set to 1, reject the part as
the programming process resulted in errors.

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OTP Overview

2.3 Try-Before-Buy Mode Example

As shown in Table 1, it is possible to start the MMPF0100 directly from the TBBOTP registers without actually
programming the part. Shown below is an example of the Try-Before-Buy mode.

Note: All code examples in this document represent a script using the KITPFPGMEVME and the associated GUI.
Command syntax may vary if the user utilizes a different tool for communication.

///--------------------------------------------------------------------------­// F0 – Sample Try-Before-Buy Configuration
// Set VDDOTP = 0 V, PWRON = HIGH, LICELL = 3.0 V (Optional), VIN = VDDIO = 3.3 V
//---------------------------------------------------------------------------

WRITE_I2C:7F:01 // Access PF0100 EXT Page1

//[Extended Page 1 Registers: 0xA0 - 0xAF] ----------------------------------

WRITE_I2C:A0:2B // Sw1AB Voltage = 1.375 V
WRITE_I2C:A1:01 // Sw1AB Sequence = 1
WRITE_I2C:A2:05 // Sw1AB Freq = 2 MHZ, Mode = Single phase
WRITE_I2C:A8:2B // Sw1c Voltage = 1.375 V
WRITE_I2C:A9:02 // Sw1c Sequence = 2
WRITE_I2C:AA:01 // Sw1c Freq = 2.0 MHZ
WRITE_I2C:AC:72 // Sw2 Voltage = 3.30 V
WRITE_I2C:AD:05 // Sw2 Sequence = 5
WRITE_I2C:AE:01 // Sw2 Freq = 2 MHZ

//[Extended Page 1 Registers: 0xB0 - 0xBF] ----------------------------------

WRITE_I2C:B0:2C // Sw3A Voltage = 1.500 V
WRITE_I2C:B1:03 // Sw3A Sequence = 3
WRITE_I2C:B2:05 // Sw3A Freq = 2 MHZ, Mode = Single phase
WRITE_I2C:B4:2C // Sw3B Voltage = 1.500 V
WRITE_I2C:B5:03 // Sw3B Sequence = 3
WRITE_I2C:B6:01 // Sw3B Freq = 2 MHZ
WRITE_I2C:B8:6F // Sw4 Voltage = 3.150 V
WRITE_I2C:B9:06 // Sw4 Sequence = 6
WRITE_I2C:BA:01 // Sw4 Freq = 2 MHZ
WRITE_I2C:BC:00 // Swbst Voltage = 5.0 V
WRITE_I2C:BD:0D // Swbst Sequence = 13

//[Extended Page 1 Registers: 0xC0 - 0xCF] ----------------------------------

WRITE_I2C:C0:06 // Vsnvs Voltage = 3.0 V
WRITE_I2C:C4:03 // Vsnvs Sequence = 3
WRITE_I2C:C8:0E // Vgen1 Voltage = 1.50 V
WRITE_I2C:C9:09 // Vgen1 Sequence = 9
WRITE_I2C:CC:0E // Vgen2 Voltage = 1.5 V
WRITE_I2C:CD:0A // Vgen2 Sequence = 10

//[Extended Page 1 Registers: 0xD0 - 0xDF] ----------------------------------

WRITE_I2C:D0:07 // Vgen3 Voltage = 2.5 V
WRITE_I2C:D1:0B // Vgen3 Sequence = 11

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WRITE_I2C:D4:00 // Vgen4 Voltage = 1.8 V
WRITE_I2C:D5:07 // Vgen4 Sequence = 7
WRITE_I2C:D8:0A // Vgen5 Voltage = 2.8 V
WRITE_I2C:D9:0C // Vgen5 Sequence = 12
WRITE_I2C:DC:0F // Vgen6 Voltage = 3.3 V
WRITE_I2C:DD:08 // Vgen6 Sequence = 8

//[Extended Page 1 Registers: 0xE0 - 0xEF] ----------------------------------

WRITE_I2C:E0:0E // Power-up DVS = 1.5625 mV/us, SeqCLK = 2 ms, PWRON config = 0
WRITE_I2C:E1:0E // Power-up DVS = 1.5625 mV/us, SeqCLK = 2 ms, PWRON config = 0
WRITE_I2C:E2:0E // Power-up DVS = 1.5625 mV/us, SeqCLK = 2 ms, PWRON config = 0
WRITE_I2C:E8:00 // Power Good = Disabled

//[Extended Page 1 Registers: 0xF0 - 0xFF] ----------------------------------

WRITE_I2C:FF:08 // I2C Device Address = 0x08

//===========================================================================
// TRY-BEFORE-BUY COMMANDS FOLLOW
//===========================================================================

WRITE_I2C:E4:80 // TBB POR=1 (This Enables TBB Mode)

//--------------------------------------------------------------------------­// BANK 9
//---------------------------------------------------------------------------

PWRON:LOW // PWRON LOW
DELAY:500

PWRON:HIGH // PWRON HIGH to Start PMIC from desired TBB Configuration

Optionally, PWRON on can be kept HIGH and VIN can be toggled when a valid LICELL is present.

OTP Overview

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OTP Overview

2.4 OTP Registers Description

There are ten banks with a total of 260 fuses, where each bank contains 26 fuses. Each fuse represents one bit of
the TBBOTP register map.
map.

Table 2. Bank 1

Fuses Register Name Register bits Description

5:0 OTP SW1AB VOLT SW1AB_VOLT[5:0] SW1AB power-up voltage
6– –RSVD
11:7 OTP SW1AB SEQ SW1AB_SEQ[4:0] SW1AB power-up sequence
13:12 OTP SW1AB CONFIG SW1AB_FREQ[1:0] SW1AB power-up frequency
15:14 OTP SW1AB CONFIG SW1AB_CONFIG[1:0] SW1A/B/C power-up configuration
18:16 OTP I2C ADDR I2C_SLV_ADDR[3:0] 3 LSBs of the slave address
19 OTP EN ECC0 EN_ECC_BANK1 Enable ECC for OTP fuse bank 1
25:20 – – ECC check bits for fuse bank 1

Table 3. Bank 2

Fuses Register Name Register bits Description

Table 2 to Table 11 show the banks, their fuses and the corresponding bit s in the register

5:0 OTP SW1C VOLT SW1C_VOLT[5:0] SW1C power-up voltage
6– –RSVD
11:7 OTP SW1C SEQ SW1C_SEQ[4:0] SW1C power-up sequence
13:12 OTP SW1C CONFIG SW1C_FREQ[1:0] SW1C power-up frequency
15:14 OTP SWBST VOLT SWBST[1:0] SWBST power-up voltage
18:16 – – RSVD
19 OTP EN ECC0 EN_ECC_BANK2 Enable ECC for OTP fuse bank 2
25:20 – – ECC check bits for fuse bank 2

Table 4. Bank 3

Fuses Register Name Register bits Description

6:0 OTP SW2 VOLT SW2_VOLT6:0] SW2 power-up voltage
11:7 OTP SW2 SEQ SW2_SEQ[4:0] SW2 power-up sequence
13:12 OTP SW2 CONFIG SW2_FREQ[1:0] SW2 power-up frequency
18:14 OTP SWBST SEQ SWBST_SEQ[4:0] SWBST power-up sequence
19 OTP EN ECC0 EN_ECC_BANK3 Enable ECC for OTP fuse bank 3
25:20 – – ECC check bits for fuse bank 3

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Table 5. Bank 4

Fuses Register Name Register bits Description

6:0 OTP SW3A VOLT SW3A_VOLT[6:0] SW3A power-up voltage
11:7 OTP SW3A SEQ SW3A_SEQ[4:0] SW3A power-up sequence
13:12 OTP SW3A CONFIG SW3A_FREQ[1:0] SW3A power-up frequency
15:14 OTP SW3A CONFIG SW3_CONFIG SW3A/B power-up configuration
18:16 – – RSVD
19 OTP EN ECC0 EN_ECC_BANK4 Enable ECC for OTP fuse bank 4
25:20 – – ECC check bits for fuse bank 4

Table 6. Bank 5

Fuses Register Name Register bits Description

6:0 OTP SW3B VOLT SW3B_VOLT[6:0] SW3B power-up voltage
11:7 OTP SW3B SEQ SW3B_SEQ[4:0] SW3B power-up sequence
13:12 OTP SW3B CONFIG SW3B_FREQ[1:0] SW3B power-up frequency
18:14 OTP VREFDDR SEQ VREFDDR_SEQ[4:0] VREFDDR power-up sequence
19 OTP EN ECC0 EN_ECC_BANK5 Enable ECC for OTP fuse bank 5
25:20 – – ECC check bits for fuse bank 5

OTP Overview

Table 7. Bank 6

Fuses Register Name Register bits Description

6:0 OTP SW 4 VOLT SW4_VOLT[6:0] SW4 power-up voltage
11:7 OTP SW 4 SEQ SW4_SEQ[4:0] SW4 power-up sequence
13:12 OTP SW 4 CONFIG SW4_FREQ[1:0] SW4 power-up frequency
14 OTP SW 4 CONFIG VTT SW4 tracking mode select
17:15 OTP VSNVS VOLT VSNVS_VOLT[2:0] VSNVS power-up voltage
18 – – RSVD
19 OTP EN ECC1 EN_ECC_BANK6 Enable ECC for OTP fuse bank 6
25:20 – – ECC check bits for fuse bank 6

Table 8. Bank 7

Fuses Register Name Register bits Description

3:0 OTP VGEN1 VOLT VGEN1_VOLT[3:0] VGEN1 power-up voltage
8:4 OTP VGEN1 SEQ VGEN1_SEQ[4:0] VGEN1 power-up sequence
12:9 OTP VGEN2 VOLT VGEN2_VOLT[3:0] VGEN2 power-up voltage
17:13 OTP VGEN2 SEQ VGEN2_SEQ[4:0] VGEN2 power-up sequence
18 – – RSVD
19 OTP EN ECC1 EN_ECC_BANK 7 Enable ECC for OTP fuse bank 7
25:20 – – ECC check bits for fuse bank 7

Freescale Semiconductor 11

AN4536 Application Note Rev. 2.0 1/2014