NXP Semiconductors MKW01Z128 Reference Manual

MKW01Z128

Sub 1 GHz Low Power Transceiver plus Microcontroller

Reference Manual

Document Number: MKW01xxRM

Rev. 3

04/2016

Audience. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi

Chapter 1
MKW01Z128 Introduction and Chip Configuration

1.1 KW01 family introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.3 General platform features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.4 MCU features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.5 RF transceiver features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.6 Software solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.7 System overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.7.1 Transceiver overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.7.2 MCU overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.7.2.1 Module functional categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.7.2.2 ARM Cortex-M0 core modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1.7.2.3 System modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

1.7.2.4 Memories and memory interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.7.2.5 Clock modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.7.2.6 Security and integrity module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.7.2.7 Analog modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1.7.2.8 Timer modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1.7.2.9 Radio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

1.7.2.10 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.7.2.11 Human-machine interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.7.2.12 System Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

Chapter 2
MKW01Z128 Pins and Connections

2.1 Device pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.2 Pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.3 Internal Functional Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Chapter 3 Signal Multiplexing and Signal Descriptions

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2 Signal Multiplexing Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2.1 Port control and interrupt module features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.2.2 Clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.2.3 Signal multiplexing contraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.3 Pin Assignments and Signal Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

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Chapter 4
System Considerations

4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.2 Power connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

4.3 System functional interconnects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.3.1 In-package Connections (SPI Channel and Status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.3.2 System Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.3.2.1 MCU Reset pin (pin 33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.3.2.2 Transceiver Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

4.3.2.3 MCU Control of Transceiver Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.3.3 External Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.4 System Clock Sources and Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

4.4.1 Additional Transceiver Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

4.4.2 Transceiver Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

4.4.2.1 Crystal Resonator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

4.4.2.2 Transceiver ClkOut Output (DIO5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

4.4.3 MCU Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

4.4.3.1 MCU External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

4.4.3.2 MCU External Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

4.4.3.3 MCU Internal Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

4.4.3.4 LPO 1 kHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

4.4.4 System Clock Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

4.4.4.1 Single crystal with ClkOut driving MCU EXTAL input . . . . . . . . . . . . . . . . . . . . . . . 4-12

4.4.4.2 Single Crystal with MCU Using Internal Clock Only . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

4.4.4.3 Dual Crystal Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

4.4.5 Debug Port Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

4.5 MKW01Z128 GPIO (Mixed I/O from Transceiver and MCU) . . . . . . . . . . . . . . . . . . . . . . . . 4-13

4.5.1 MCU GPIO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14

4.5.2 Transceiver DIOX Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14

4.6 Transceiver RF Configurations and External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15

4.6.1 RF Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15

4.6.2 Standard Output Power RF Configuration (Single, Bidirectional Port). . . . . . . . . . . . . . . 4-15

4.6.3 Higher Output Power RF Configuration (Dual Port with Optional External Power Amplifier)
4-16

4.6.4 Filter and Matching Network Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17

Chapter 5
Sub 1 GHz Transceiver Architecture Description

5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.2 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

5.3 Transceiver Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.4 Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2

5.5 Frequency Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.5.1 Reference Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

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5.5.2 CLKOUT Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.5.3 PLL Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.5.3.1 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.5.3.2 PLL Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.5.3.3 Carrier Frequency and Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.5.4 Lock Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

5.5.5 Lock Detect Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

5.6 Transmitter Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

5.6.1 Bit Rate Setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

5.6.2 FSK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5.6.3 OOK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5.6.4 Modulation Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5.6.5 Power Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

5.6.6 Over Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

5.7 Receiver Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

5.7.1 LNA - Single to Differential Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

5.7.2 Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

5.7.2.1 RssiThreshold Setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

5.7.2.2 AGC Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

5.7.3 Continuous-Time DAGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

5.7.4 Quadrature Mixer - ADCs - Decimators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

5.7.5 Channel Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

5.7.6 DC Cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

5.7.7 Complex Filter - OOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

5.7.8 RSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

5.7.9 Cordic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16

5.7.10 FSK Demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17

5.7.11 OOK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17

5.7.11.1 Optimizing the Floor Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18

5.7.11.2 Optimizing OOK Demodulator for Fast Fading Signals . . . . . . . . . . . . . . . . . . . . . . . 5-19

5.7.11.3 Alternative OOK Demodulator Threshold Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19

5.7.12 Bit Synchronizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19

5.7.13 Frequency Error Indicator (FEI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21

5.7.14 Automatic Frequency Correction (AFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22

5.7.15 Optimized Setup for Low Modulation Index Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22

5.7.16 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23

5.7.17 Timeout Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24

5.8 High Bit Rate Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24

5.8.1 500 kbps Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24

5.8.2 600 kbps Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24

Chapter 6
Transceiver Operating Modes

6.1 Basic Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

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6.2 Automatic Sequencer and Wake-Up Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

6.2.1 Transmitter Startup Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.2.2 TX Start Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2

6.2.3 Receiver Startup Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.2.4 RX Start Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

6.2.5 Optimized Frequency Hopping Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

6.3 Listen Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.3.1 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.3.2 Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

6.3.3 End of Cycle Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

6.3.4 RC Timer Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

6.4 AutoModes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

Chapter 7
Transceiver Digital Control and Communications

7.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.1.1 Data Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

7.2 Control Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

7.2.1 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2

7.2.2 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.2.2.1 Overview and Shift Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.2.2.2 Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

7.2.2.3 Interrupt Sources and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

7.2.2.4 FIFO Clearing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

7.2.3 Sync Word Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

7.2.3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

7.2.3.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6

7.2.4 Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6

7.2.5 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6

7.3 Digital IO Pins Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6

7.3.1 DIO Pins Mapping in Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7

7.3.2 DIO Pins Mapping in Packet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7

7.4 Continuous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8

7.4.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8

7.4.2 TX Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8

7.4.3 RX Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

7.5 Packet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

7.5.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

7.5.2 Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10

7.5.2.1 Fixed Length Packet Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10

7.5.2.2 Variable Length Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11

7.5.2.3 Unlimited Length Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12

7.5.3 TX Processing (without AES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12

7.5.4 RX Processing (without AES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13

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7.5.5 AES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14

7.5.5.1 TX Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14

7.5.5.2 RX Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14

7.5.6 Handling Large Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15

7.5.7 Packet Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15

7.5.7.1 Sync Word Based . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15

7.5.7.2 Address Based. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16

7.5.7.3 Length Based . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16

7.5.7.4 CRC Based . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16

7.5.8 DC-Free Data Mechanisms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17

7.5.8.1 Manchester Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17

7.5.8.2 Data Whitening. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18

7.6 Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18

7.7 Common Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21

7.8 Transmitter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25

7.9 Receiver Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26

7.10 IRQ and Pin Mapping Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29

7.11 Packet Engine Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32

7.12 Temperature Sensor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36

7.13 Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36

Chapter 8
MKW01Z128 Transceiver - MCU SPI Interface

8.1 SiP Level SPI Pin Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1

8.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

8.3 SPI System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2

8.3.1 SPI Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.3.1.1 Slave Select (SS or NSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.3.1.2 SPI Clock (SCK or SPSCK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.3.1.3 Master Out / Slave In (MOSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.3.1.4 Master In / Slave Out (MISO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.3.2 MKW0xxx SPI Transaction Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.3.3 MKW0xxx SPI Transaction Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

Appendix A
MKW01Z128 MCU Reference Manual

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Contents

About This Book

This manual details the MKW01, which is a highly-integrated, cost-effective, system-in-package (SIP),
sub-1 GHz wireless node solution with an FSK, GFSK, MSK, or OOK modulation-capable transceiver and
low-power Kinetis microcontroller . The highly integrated RF trans cei ver operates over a wide frequency
range including 315 MHz, 433 MHz, 470 MHz, 868 MHz, 915 MHz, 928 MHz, and 955 MHz in the
license-free Industrial, Scientific and Medical (ISM) frequency bands.

Audience

This manual is intended for system designers.

Revision History

The following table summarizes revisions to this document since the previous release (Rev 2.0).

Revision History

Location Revision

Chapter 1 • Corrected the package name from 56 LGA to 60-pin LGA

• Added the following paragraph in Section 1.7.1, “Transceiver overview
“The versatile RF Transceiver in the MKW01 can be configured to be compliant with
the relevant sections of numerous world-wide standards, including but not limited to:
ARIB-T108 and T67, FCC 15.231, 15.247 and 15.249, 802.15.4g, EN54-25 and ETSI
300 220.”

Chapter 2 • Updated Figure 2-1. MKW01Z128 pinout

• Updated Table 2-1. Pin Function Description

• Updated description of pin # 58 in Table 2-2 MKW01Z128 Internal Functional
Interconnects.

Chapter 3 • Updated Table 3-2 Reset State of PORTx_PCRn Register Bit Fields.

• Updated Table 3-3 MKW01 Pin Assignments and Signal Multiplexing.

Chapter 4 • Added a note related to CLKOUT in Idle mode to Section 4.3.3, “External Clock

Connections.

Chapter 5 • Added a note to Section 5.5.5, “Lock Detect Indicator.

• Added a figure to show Pout vs. Programmed Power to Section 5.6.5, “Power

Amplifiers.

• Updated the following sentence in Section 5.7.3, “Continuous-Time DAGC from
“The DAGC is enabled by setting RegTestDagc to 0x10“ to “The DAGC is enabled by
setting RegTestDagc to 0x20“.

• Added Table 5-6. Available DCC Cutoff Frequencies Expressed as Percentage of
RXBW (continued) to Section 5.7.6, “DC Cancellation.

• Added RSSI chart and the notes following the figure to Section 5.7.8, “RSSI.

Chapter 6 • Added a note related to CLKOUT in Idle mode to Section 6.3, “Listen Mode.
Chapter 7 • Updated Reset value of RegVersion (at address 0x10) from 0x22 to 0x 23 in T able 7-4.

Registers Summary. Also added a line for register RegTestTcxo at address 0x59.

• Added a line for register RegTestTcxo at address 0x59 in Table 7-11 Test Registers.
Also updated description of RegTestDagc (0x6F) register.

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Definitions, Acronyms, and Abbreviations

The following list defines the acronyms and abbreviations used in this document.
ACK Acknowledgement Frame
API Application Programming Interface
BB Baseband
CCA Clear Channel Assessment
CRC Cyclical Redundancy Check
DCD Differential Chip Decoding
DME Device Management Entity
FCS Frame Check Sequence
FFD Full Function Device
FFD-C Full Function Device Coordinator
FLI Frame Length Indicator
GTS Guaranteed Time Slot
HW Hardware
IRQ Interrupt Request
ISR Interrupt Service Routine
LO Local Oscillator
MAC Medium Access Control
MCPS MAC Common Part Sublayer
MCU Microcontroller Unit
MLME MAC Sublayer Management Entity
MSDU MAC Service Data Unit
NWK Network
PA Power Amplifier
PAN Personal Area Network
PANID PAN Identification
PHY PHYsical Layer
PIB PAN Information Base
PPDU PHY Protocol Data Unit
PSDU PHY Service Data Unit
RF Radio Frequency
RFD Reduced Function Device
SAP Service Access Point
SFD Start of Frame Delimiter

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SPI Serial Peripheral Interface
SSCS Service Specific Convergence Layer
SW Software
VCO Voltage Controlled Oscillator

References

The following sources were referenced to produce this book:

[1] IEEE 802.15.4 Standard
[2] Freescale

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Chapter 1 MKW01Z128 Introduction and Chip Configuration

Kinetis is the most scalable portfolio of low power, mixed-signal ARM®Cor tex™ MCUs in the industry.
Kinetis MCU families are peripheral- and software-compatible devices. Each family offers excellent
performance, memory and feature scalability with common peripherals, memory maps, and packages
providing easy migration both within and between families.

Kinetis MCUs are built from Freescale’ s innovative 90 nm thin film storage (TFS) flash technology with
unique FlexMemory. Kinetis MCU families combine the latest low-power innovations and high
performance, high precision mixed-signal capability with a broad range of connectivity, human-machine
interface, and safety & security peripherals.Kinetis MCUs are supported by a market-leading enablement
bundle from Freescale and numerous ARM 3rd party ecosystem partners.

Kinetis W-series devices all contain wireless connectivity options spanning across frequency bands and
standards.

T a ble 1-1. Kinetis W-Series devices

Family Frequency Band

KW0x Sub-Gigahertz
KW2x 2.4 GHz
KW3x Reserved

KW01 devices also have these features:

•Core:
— ARM Cortex-M0+ Cores delivering single-cycle access memories, 48 MHz CPU frequency
— Up to 16-channel DMA for peripheral and memory servicing with minimal CPU intervention
— Broad range of performance levels rated at maximum CPU frequencies starting at 48 MHz

• Ultra-low power:
— Multiple low power operating modes for optimizing peripheral activity and wakeup times for

extended battery life.

— Low–leakage wakeup unit, low power timer, and low power RTC for additional low power

flexibility

— Industry-leading fast wakeup times

• Memory: 16 KB RAM, 128 KB flash

• Mixed-signal analog:

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MKW01Z128 Introduction and Chip Configuration

— Fast, high precision 16-bit ADCs, 12-bit DACs, high speed comparators and an internal voltage

reference. Powerful signal conditioning, conversion and analysis capability with reduced
system cost

• Human Machine Interface (HMI):
— Capacitive Touch Sensing Interface with full low-power support and minimal current adder

when enabled

• Connectivity and Communications:
— UARTs with ISO7816, CEA709.1-B (LON), and IrDA support, I2C, and DSPI

• Reliability, Safety and Security:
— Hardware cyclic redundancy check engine for validating memory contents/ communication

data and increased system reliability

— Independent-clocked computer operating properly (COP) for protection against code runaway

in fail-safe applications

— External watchdog monitor

• Timing and Control:
— Programmable Interrupt Timer for RTOS task scheduler time base or trigger source for ADC

conversion and programmable delay block

•System:
— Wide operating voltage range from 1.8 V to 3.6 V with flash programmable down to 1.8 V with

fully functional flash and analog peripherals

— Ambient operating temperature ranges from –40°C to 85°C

1.1 KW01 family introduction

The KW01 family is the entry point into the Kinetis W-Series portfolio. The K01W is a single-chip
solution combining an ARM Cortex-M0+ microcontroller and a sub-GHz ISM band radio front-end
device.

Devices contain 128 KB of flash and 16 KB of SRAM in an 8 x 8 mm 60-pin LGA package. Standard
features include a rich suite of analog, communication, timing and control peripherals. Additionally,
flexible low-power capabilities and innovative FlexMemory help to solve many of the major pain points
for system implementation.

1.2 Ordering information

Table 1-2 lists the available devices in the MKW01 family.

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MKW01Z128 Introduction and Chip Configuration

Table 1-2. Devices in the MKW01 Family

Device

MKW01Z128CHN –40° to 85° C 60 LGA 16 KB RAM,

Operating Temp

Range (TA.)

Package Memory Options Description

The primary target market is communications for

128 KB flash

last mile metering, sub metering and associated
devices such as concentrators. The feature set
will also allow it to serve for wireless sensor
networks in building control and automation.

1.3 General platform features

• ARM Cortex-M0+ Core

• Sub-1 GHz in-package transceiver

• Multiple power saving modes

• 1.8 V to 3.6 V operating voltage with on-chip voltage regulators

• –40°C to +85°C temperature range

• Low external component count

• Supports single crystal (32 MHz typical) clock source operation or dual crystal operation

• Versatile software solutions

• 60-pin LGA (8x8 mm) Package

1.4 MCU features

•Core:
— ARM Cortex-M0+ 1.77 CoreMark/MHz from single-cycle access memories, 48 MHz CPU

frequency
— 4-channel DMA for peripheral and memory servicing with minimal CPU intervention
— CPU frequencies up to 48 MHz

• Ultra-low power:
— Multiple low power operating modes for optimizing peripheral activity and wakeup times for

extended battery life.
— Low–leakage wakeup unit and low power timer for time keeping function
— Industry-leading fast wakeup times

• Memory:
— 128 KB Flash, 16 KB RAM

• Mixed-signal analog:
— Fast, high precision 16-bit ADCs, and internal high speed comparators. Powerful signal

conditioning, conversion and analysis capability with reduced system cost

• Human Machine Interface (HMI):
— Capacitive Touch Sensing Interface with full low-power support and minimal current adder

when enabled

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MKW01Z128 Introduction and Chip Configuration

• Connectivity and Communications:
— Three UARTs, two SPIs, and two I2C

• Reliability, Safety and Security:
— Hardware cyclic redundancy check engine for validating memory contents/ communication

data and increased system reliability

— Independent-clocked computer operating properly (COP) for protection against code runaway

in fail-safe applications

• Timing and Control:
— Powerful timer modules that support general-purpose, PWM, and motor control functions
— Programmable Interrupt Timer for RTOS task scheduler time base or trigger source for ADC

conversion and programmable delay block

•System:
— Wide operating voltage range from 1.8 V to 3.6 V with flash programmable down to 1.8 V with

fully functional flash and analog peripherals

— Ambient operating temperature ranges from –40°C to 85°C

1.5 RF transceiver features

• High Sensitivity: down to –120 dBm at 1.2 kbps

• High Selectivity: 16-tap FIR Channel Filter

• Bullet-proof front end: IIP3 = –18 dBm, IIP2 = +35 dBm, 80 dB Blocking Immunity, no Image
Frequency response

• Low current: RX = 16 mA, 100 nA register retention

• Programmable Pout : –18 to +17 dBm in 1 dB steps

• Constant RF performance over voltage range of chip

• FSK bit rates up to 600 kbps

• Fully integrated synthesizer with a resolution of 61 Hz

• FSK, GFSK, MSK, GMSK and OOK modulations

• Built-in Bit Synchronizer performing Clock recovery

• Incoming Sync Word Recognition

• Automatic RF Sense with ultra-fast AFC

• Packet engine with CRC, AES-128 encryption and 66-byte FIFO

• Built-in temperature sensor and Low battery indicator

• 32 MHz (typical) crystal oscillator clock source

1.6 Software solutions

Freescale will support the MKW01Z128 platform with several software solutions:

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MKW01Z128 Introduction and Chip Configuration

• A radio utility GUI will be available that allows testing of various features and setting registers. A
firmware-based connectivity test will allow a limited set of testing controlled with a terminal
emulator on any computer.

• SMAC (Simple Media Access Controller) — This codebase provides simple communication and
test apps based on drivers/PHY utilities available as source code. This environment is useful for
hardware and RF debug, hardware standards certification, and developing proprietary applications.

• MAC/PHY (Media Access Control/Physical) for IEEE 802.15.4g/e — This release was developed
primarily for the ZigBee Alliance specified Home Energy Management Systems for the Japanese
application space.

• Additional software will be available through 3rd party providers.

1.7 System overview

Figure 1-1 shows a simplified block diagram of the MKW01.

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MKW01Z128 Introduction and Chip Configuration

Figure 1-1. MKW01 system level block diagram

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MKW01Z128 Introduction and Chip Configuration

1.7.1 Transceiver overview

The transceiver (see Figure 1-1) is a single-chip integrated circuit ideally suited for today's high
performance ISM band RF applications. Its advanced features set, including state of the art packet engine,
greatly simplifies system design while the high level of integration reduces the external RF component bill
of material (BOM) to a handful of passive de-coupling and matching components. It is intended for use as
a high-performance, low-cost FSK and OOK RF transceiver for robust, frequency agile, half-duplex
bidirectional RF links.

The MKW01 is intended for applications over a wide frequency range, including the 433 MHz and
868 MHz European and the 902–928 MHz North American and Japan ISM bands. Coupled with a link
budget in excess of 135 dB, the transceiver advanced system features include a 66 byte TX/RX FIFO,
configurable automatic packet handler, listen mode, temperature sensor and configurable DIOs which
greatly enhance system flexibility while at the same time significantly reducing MCU requirements. The
transceiver complies with both ETSI and FCC regulatory requirements.

The major RF communication parameters of the MKW0 1 transceiver are programmable and most can be
dynamically set. This feature offers the unique advantage of programmable narrow-band and wide-band
communication modes without the need to modify external components. The transceiver is also optimized
for low power consumption while offering high RF output power and channelized operation.

The versatile RF Transceiver in the MKW01 can be configured to be compliant with the relevant sections
of numerous world-wide standards, including but not limited to: FCC Part 15.247 and Part 15.249, ETSI
EN 300 220, ARIB STD-T108, IC RSS 210.

1.7.2 MCU overview

The in-package Kinetis L series 48 MHz MCU features an ARM Cortex M0+, 16 KB Ram and 128 KB
flash. The RF transceiver is controlled through the MCU SPI port which is dedicated to the RF device
interface. Two of the transceiver status IO lines are also directly connected to the MCU GPIO to monitor
the transceiver operation. In addition, the transceiver reset and additional status can be connected to the
MCU through external connections.

1.7.2.1 Module functional categories

The modules on this device are grouped into functional categories. The following sections describe the
modules assigned to each category in more detail.

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Table 1-3. Module functional categories

Module category Description

ARM Cortex-M0+ core

System • System integration module

• Power management and mode controllers — Multiple power modes available based on
run, wait, stop, and powerdown modes

• Low-leakage wakeup unit

• Miscellaneous control module

• Crossbar switch

• Peripheral bridge

• Direct memory access (DMA) controller with multiplexer to increase available DMA
requests

• External watchdog monitor

• Watchdog

Memories Internal memories include:

• Up to 128KB program flash memory

• Up to 16KB SRAM

Clocks • Multiple clock generation options available from internally- and externally-generated

clocks

• System oscillator from transceiver to provide clock source for the MCU

• 32 kHz RTC oscillator

Security • Cyclic Redundancy Check module for error detection

Analog • 16-bit analog-to-digital converter

• Internal Comparator with internal 6-bit DAC for reference

• 12-bit DAC with DMA support and two 16-bit buffers

Timers • Low Power Timer/PWM (TPM) modules

• One 6-channel TPM

• Two 2-channel TPMs

• 2-channel periodic interrupt timer

• Real-time clock

• Low-power timer

• System tick timer

Communications • 2x internal serial peripheral interface

• 2x inter-integrated circuit (I

•3x UART

Human-Machine Interfaces (HMI) • General purpose input/output controller

• Capacitive touch sense input interface enabled in hardware

2

C)

1.7.2.2 ARM Cortex-M0 core modules

The following core modules are available on this device.

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MKW01Z128 Introduction and Chip Configuration

Table 1-4. Core modules

Module Description

ARM Cortex-M0+ The ARM Cortex-M0+ is the newest member of the Cortex M Series of processors

targeting microcontroller applications focused on very cost sensitive, deterministic,
interrupt driven environments. The Cortex M0+ processor is based on the ARMv6
Architecture and Thumb®-2 ISA and is 100% instruction set compatible with its
predecessor, the Cortex-M0 core, and upward compatible to Cortex-M3 and M4 cores.

NVIC The ARMv6-M exception model and nested-vectored interrupt controller (NVIC) implement

a relocatable vector table supporting many external interrupts, a single non-maskable
interrupt (NMI), and priority levels.
The NVIC replaces shadow registers with equivalent system and simplified
programmability. The NVIC contains the address of the function to execute for a particular
handler. The address is fetched via the instruction port allowing parallel register stacking
and look-up. The first sixteen entries are allocated to ARM internal sources with the others
mapping to MCU-defined interrupts.

AWIC The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is to detect

asynchronous wake-up events in stop modes and signal to clock control logic to resume
system clocking. After clock restart, the NVIC observes the pending interrupt and performs
the normal interrupt or event processing.

Single-cycle I/O Port For high-speed, single-cycle access to peripherals, the Cortex-M0+ processor implements

a dedicated single-cycle I/O port.

Debug interfaces Most of this device's debug is based on the ARM CoreSight™ architecture. One debug

interface is supported:

• Serial Wire Debug (SWD)

1.7.2.3 System modules

The following system modules are available on this device.

Table 1-5. System modules

Module Description

System integration module (SIM) The SIM includes integration logic and several module configuration setti n gs.

System mode controller The SMC provides control and protection on entry and exit to each power mode, control

for the Power management controller (PMC), and reset entry and exit for the complete
MCU.

Power management controller

(PMC)

Low-leakage wakeup unit (LLWU) The LLWU module allows the device to wake from low leakage power modes (LLS and

Peripheral bridge The peripheral bridge converts the crossbar switch interface to an interface to access a

The PMC provides the user with multiple power options. Multiple modes are supported that
allow the user to optimize power consumption for the level of functionality needed. Includes
power-on-reset (POR) and integrated low voltage detect (LVD) with reset (brownout)
capability and selectable LVD trip points.

VLLS) through various internal peripheral and external pin sources.

majority of peripherals on the device.

DMA multiplexer (DMAMUX) The DMA multiplexer selects from many DMA requests down to 4 for the DMA controller.

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Table 1-5. System modules (continued)

Module Description

Direct memory access (DMA)

controller

Computer operating properly

watchdog (WDOG)

The DMA controller provides programmable channels with transfer control descriptors for
data movement via dual-address transfers for 8-, 16- and 32-bit data values.

The WDOG monitors internal system operation and forces a reset in case of failure. It can
run from an independent 1 kHz low power oscillator with a programmable refresh window
to detect deviations in program flow or system frequency.

1.7.2.4 Memories and memory interfaces

The following memories and memory interfaces are available on this device.

Table 1-6. Memories and memory interfaces

Module Description

Flash memory Program flash memory — up to 128 KB of the non-volatile flash memory that can

execute program code

Flash memory controller Manages the interface between the device and the on-chip flash memory.

SRAM Up to 16 KB internal system RAM.

1.7.2.5 Clock modules

The following clock modules are available on this device.

Table 1-7. Clock modules

Module Description

Multi-clock generator (MCG) The MCG , controlled by an internal or external (such as the CLKOUT from the transceiver)

reference oscillator, provides several clock sources for the MCU that include:

• Phase-locked loop (PLL). Voltage-controlled oscillator (VCO)

• Frequency-locked loop (FLL). Digitally-controlled oscillator (DCO)

• Internal reference clocks. Can be used as a clock source for other on-chip peripherals

System oscillator The system oscillator, in conjunction with an external crystal or resonator,

generates a reference clock for the MCU.

1.7.2.6 Security and integrity module

The following security and integrity module is available on this device.

Table 1-8. Security and integrity module

Module Description

Cyclic Redundancy Check (CRC) Hardware CRC generator circuit using 16-/32-bit shift register. Error detection for all single,

double, odd, and most multi-bit errors, programmable initial seed value, and optional
feature to transpose input data and CRC result via transpose register.

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1.7.2.7 Analog modules

The following analog modules are available on this device.

T ab le 1-9. Analog Modules

Module Description

MKW01Z128 Introduction and Chip Configuration

16-bit analog-to-digital converters

(ADC)

Internal analog comparators Compares two analog input voltages, one of which can be a reference provided by the

6-bit digital-to-analog converters

(DAC)

16-bit successive-approximation ADC

internal 6-bit DAC, across the full range of the supply voltage.
64-tap resistor ladder network which provides a selectable voltage reference for analog

comparator.

1.7.2.8 Timer modules

The following timer modules are available on this device.

Table 1-10. Timer modules

Module Description

Timer/PWM module (TPM) Selec table TPM clock mode

• Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128

• 16-bit free-running counter or modulo counter with counting be up or updown

• Six configurable channels for input capture, output compare, or edge-aligned PWM
mode

• Support the generation of an interrupt and/or DMA request per channel

• Support the generation of an interrupt and/or DMA request when the counter overflows

• Support selectable trigger input to optionally reset or cause the counter to start
incrementing.

• Support the generation of hardware triggers when the counter overflows and per

channel

Periodic interrupt timers (PIT) • Four general purpose interrupt timers

• Interrupt timers for triggering ADC conversions

• 32-bit counter resolution

• Clocked by system clock frequency

• DMA support

Low-power timer (LPTimer) • Selectable clock for prescaler/glitch filter of 1 kHz (internal LPO), 32.768 kHz (external

crystal), or internal reference clock

• Configurable Glitch Filter or Prescaler with 16-bit counter

• 16-bit time or pulse counter with compare

• Interrupt generated on Timer Compare

• Hardware trigger generated on Timer Compare

1.7.2.9 Radio

Table 1-11. Radio transceiver

Module Description

Sub-GHz transceiver • A highly integrated ISM band transceiver for FSK and OOK packet or continuous data.

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MKW01Z128 Introduction and Chip Configuration

1.7.2.10 Communication interfaces

The following wired communication interfaces are available on this device.

T able 1-12. Communication interfaces

Module Description

Internal serial peripheral interface

(SPI)

Inter-integrated circuit (I2C) Allows communication between a number of devices. Also supports the System

Universal asynchronous

receiver/transmitters (UART)

Synchronous serial bus for communication to an external device

Management Bus (SMBus) Specification, version 2.
Asynchronous serial bus communication interface with programmable 8- or 9-bit data

format

1.7.2.11 Human-machine interfaces

The following human-machine interfaces (HMI) are available on this device.

Table 1-13. HMI modules

Module Description

General purpose input/output

(GPIO)

Capacitive touch sense input (TSI) Contains up to 10 channel inputs for capacitive touch sensing applications. Operation is

All general purpose input or output (GPIO) pins are capable of interrupt and DMA request
generation. All GPIO pins have 5 V tolerance.

available in low-power modes via interrupts.

1.7.2.12 System Device Identification Register

The system device identification register contains device specific information factory programmed into the
in-package MCU die.

Table 1-14. Device-Specific Values

Field ID Value

FAMID 0001

SUBFAMID 0111

SERIESID 0001

SRAMSIZE 0101

REVID 0001

DIEID 01010
PINID 0010

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Chapter 2 MKW01Z128 Pins and Connections

2.1 Device pin assignment

Figure 2-1. MKW01Z128 pinout

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MKW01Z128 Pins and Connections

2.2 Pin definitions

Table 2-1 details the MKW01Z128 pinout and functionality.

Table 2-1. Pin Function Description (Sheet 1 of 5)

Pin # Pin Name Type Description Functionality

1 VREFH Input MCU high reference voltage for ADC
2 VREFL Input MCU low reference voltage for ADC
3 VSSA Power Input MCU ADC Ground Connect to ground
4 VSS Power Input MCU Ground Connect to ground
5 PTE16/ADC0_DP1/ADCO_

SE1/SPI0_PCS0/TPM/
UART2_TX

6 PTE17/ADC0_DM1/ADCO_

SE5a/SPI0_SCK/ TPM_
CLKIN1/UART2_RX/
LPTMR0_ALT3

7 PTE18/ADC0_DP2/ADC0_

SE2/SPI0_MOSI/I2C0_SDA/
SPI0_MISO

8 PTE19/ADC0_DM2/ ADC0_

SE6a/SPI0_MISO /I2C0_SCL/
SPI0_MOSI

9 PTE30/DAC0_OUT/

ADCO_SE23/ CMP0_IN4/
TPM0_CH3/TPM_CLKIN1

Digital Input /
Output

Digital Input /
Output

Digital Input /
Output

Digital Input /
Output

Digit-l Input /
Output

MCU Port E Bit 16 / ADC0 positive
differential analog channel input DP1/
ADC0 Single Ended analog channel input
SE1 / SPI module 0 PCS0 / TPM module
Clock In 0 / UART2_TX

MCU Port E Bit 17 / ADC0 negative
differential analog channel input DM1/
ADC0 Single Ended analog channel input
5a / SPI module 0 SCK / TPM module
Clock In 1 / UART2_RX / Low Power Timer
Module 0 ALT3

MCU Port E Bit 18 / ADC0 positive
differential analog channel input DP2/
ADC0 Single Ended analog channel input
2 / SPI module 0 MOSI / I2C0 Bus Data /
SPI module 0 MISO

MCU Port E Bit 19 / ADC0 negative
differential analog channel input DM2/
ADC0 Single Ended analog channel input
6a / SPI module 0 MISO / I2C0 Bus Clock /
SPI module 0 MOSI

MCU Port E Bit 30 / DAC0 Output/ ADC0
Single Ended analog channel input 23 /
Comparator 0 Analog Voltage Input 4/ TPM
Timer module 0 Channel 3 / TPM module
Clock In 1

10 PTA0/SWD_CLK/TSI0_CH1/

TPM0_CH5

11 PTA3/SWD_DIO/TSI0_CH4/

I2C1_SCL/TPM0_CH0

12 PTA4/NMI_b/TSI0_CH5/

I2C1_SDA/TPM0_CH1

2-2 Freescale Semiconductor, Inc.

Digital Input /
Output

Digital Input /
Output

Digital Input /
Output

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MCU Port A Bit 0 / Serial Wire Data Clock
/ Touch Screen Interface Channel 1/ TPM
module 0 Channel 5

MCU Port A Bit 3 / Serial Wire Data DIO /
Touch Screen Interface Channel 4 / I2C1
Bus Clock / TPM module 0 Channel 0

MCU Port A Bit 4/ / Non Maskable
Interrupt_ b/Touch Screen Interface
Channel 5 /I2C1 Bus Data / TPM module 0
Channel 1

MKW01Z128 Pins and Connections

Table 2-1. Pin Function Description (Sheet 2 of 5)

Pin # Pin Name Type Description Functionality

13 PTA2/TSI0_CH3/UART0_TX/

TPM2_CH1

Digital Input /
Output

MCU Port A Bit 2/Touch Screen Interface
Channel 3/UART module 0 Transmit / TPM
module 2 Channel 1

14 PTA1/TSI0_CH2/UART0_RX/

TPM2_CH0

Digital Input /
Output

MCU Port A Bit 1/Touch Screen Interface
Channel 2/UART module 0 Receive / TPM
module Channel 0

15 PTA18/EXTAL0/UART1_RX/

TPM_CLKIN0

16 PTA19/XTAL0/UART1_TX/

TPM_CLKIN1/LPTMR0_ALT1

Digital Input /
Output

Digital Input /
Output

MCU Port A Bit 18 / EXTAL0/ UART
module 1 Receive / TPM module Clock In 0

MCU Port A Bit 19 / XTAL0/ UAR T module
1 Transmit / TPM module Clock In 1
/Low Power Timer module 0 ALT1

17 PTB0/ADC0_SE8/TSI0_CH0/

LL WU_P5/I2C0_SCL/ TPM1_
CH0

Digital Input /
Output

MCU Port B Bit 0 / ADC0 Single Ended
analog channel input SE8 / Touch Screen
Interface Channel 0/ Low Leakage Wake
Up Port 5 / I2C0 Bus Clock / TPM module
1 Channel 0

18 PTB1/ADCO_SE9/TSI0_CH6/

I2C0_SDA/ TPM1_CH1

Digital Input /
Output

MCU Port B Bit 1 / ADC0 Single Ended
analog channel input SE9 / Touch Screen
Interface Channel 6 / I2C0 Bus Data / TPM
module 1 Channel 1

19 VDD Power Input MCU VDD supply input Connect to system VDD

supply
20 VSS Power Input MCU Gro und Connect to ground
21 PTB2/ADC0_SE12/TSI0_

CH7/I2C0_SCL/TPM2_CH0

Digital Input/
Output

MCU Port B Bit 2 / ADC0 Single Ended
analog channel input SE12 / T ouch Screen
Interface Channel 7 / I2C0 Bus Clock /
TPM Timer module 2 Channel 0

22 PTB17/TSI0_CH10/SPI1_

MISO/UART0_TX/TPM_
CLKIN1/SPI1_MOSI

23 PTC4/LLWU_P8/SPI0_PCS0/

UART1_TX/TPM0_CH3

Digital Input/
Output

Digital Input /
Output

MCU Port B Bit 17 / T ouch Screen Interface
Channel 10/SPI1 MOSI or MISO/UART0
TX / TPM timer clock

MCU Port C bit 4 / Low leakage Wake Up
port 8 / SPI0 Chip Select / UART1 TX /
TPM Timer module 0 channel 3

24 PTC1/ADC0_SE15/TSI0_

CH14/LLWU_P6/R TC_CLKIN/
I2C1_SCL/TPM0_CH0

Digital Input
Output /
Analog Input

MCU Port C Bit 1 /ADC0 Single Ended
analog channel input SE15/ Touch Screen
Interface Channel 14/ Low Leakage Wake
Up Port 6 / Real Time Counter Clock Input/
IC1 Bus Clock/ TPM module 0 Channel 0

25 PTC2/ADC0_SE11/TSI0_

CH15/I2C1_SDA/TPM0_CH1

Digital Input /
Output /
Analog Input

MCU Port C Bit 2 / ADC0 Single Ended
analog channel input SE11/ / T ouch Screen
Interface Channel 15 / I2C1 Bus Data /
TPM module 0 Channel 1

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MKW01Z128 Pins and Connections

Table 2-1. Pin Function Description (Sheet 3 of 5)

Pin # Pin Name Type Description Functionality

26 PTC3/LLWU_P7/UART1_RX/

TPM0_CH2/CLKOUTa

Digital Input /
Output

MCU Port C Bit 3 / Low Leakage Wake Up
Port 7 / UART module 1 Receive / TPM
module 0 Channel 2/ Clock OutA

27 PTD4/LLWU_P14/SPI1_

PCS0/UART2_RX/TPM0_
CH4

28 PTD5/ADC0_SE6b/SPI1_

SCK/UART2_TX/TPM0_CH5

29 PTD6/ADC0_SE7b/LLWU_

P15/SPI1_MOSI/UART0_RX/
SPI1_MISO

Digital Input /
Output

Digital Input /
Output /
Analog Input

Digital Input /
Output /
Analog Input

MCU Port D Bit 4 / Low Leak Wake Up Port
14/ SPI module 1 PCS0 / UART2 Receiver
input / TPM module 0 Channel 4

MCU Port D bit 5 / ADC0 Single Ended
analog channel input SE6b / SPI1 clock /
UART2 TX / TPM module 0 Channel 5

MCU Port D bit 6 / ADC0 Single Ended
analog channel input SE7b / Low leakage
Wake Up port 15 / SPI1 MOSI / UART0 RX

/ SPI module 1 MISO
30 NC No Connect
31 PTD7/SPI0_MISO/UART0_

TX/SPI1_MOSI

Digital Input/
Output

MCU Port D Bit 7 / SPI module 0 MISO /

UART module 0 Transmit / SPI module 1

MOSI
32 PTE0/SPI1_MISO/UART1_

TX/RTC_CLKOUT/CMP0_
OUT/ I2C1_SDA

Digital Input/
Output

MCU Port E Bit 0 / SPI module 1 MISO /

UART module 1 Transmit / Real Time

Counter Clock Output / Comparator 0

Analog voltage Output / I2C1 Bus Data
33 PT A20/RESETB Digital Input/

MCU Port A Bit 20/MCU RESET FTFA_FOPT[RESET_

Output

PIN_CFG] controls the
functionality of this pin.

34 PTE1 / SPI1_MOSI / UART1_

RX /SPI1_MISO / I2C1_SCL

Digital Input/
Output

MCU Port E Bit 1 / SPI module 1 MOSI /

UART module 1 RX / SPI1_MISO / I2C1_

SCL
35 VBAT2 (RF) Power Input Transceiver VDD Connect to system VDD

supply
36 GND/SCAN (RF) Power Input Transceiver Ground Connect to ground
37 RXTX (RF) Digital

Output

Transceiver RX / TX RF Switch Control

Output; high when in TX
38 GND_PA2 (RF) Power Input Transceiver RF Ground Connect to ground
39 RFIO (RF) RF Input /

Transceiver RF Input / Output

Output
40 GND_PA1 (RF) Power Input Transceiver RF Ground Connect to ground
41 PA_BOOST (RF) RF Output Transceiver Optional High-Power PA

Output

42 VR_PA (RF) Power

Output

Transceiver regulated output voltage for
VR_PA use.

De-coupling cap
suggested.

43 VBAT1 (RF) Power Input Transceiver VDD for RF circuitry Connect to system VDD

supply

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MKW01Z128 Pins and Connections

Table 2-1. Pin Function Description (Sheet 4 of 5)

Pin # Pin Name Type Description Functionality

44 VR_ANA (RF) Power

Output
45 VR_DIG (RF) Power

Output

Transceiver regulated output voltage for
analog circuitry.

Transceiver regulated output voltage for
digital circuitry.

Decouple to ground with
100 nF capacitor

Decouple to ground with
100 nF capacitor

46 XTA (RF) Xtal Osc Transceiver crystal reference oscillator Connect to 32 MHz

crystal and load capacitor

47 XTB (RF) Xtal Osc Transceiver crystal reference oscillator Connect to 32 MHz

crystal and load capacitor

48 RESET (RF) Digital Input Transceiver hardware reset input Typically driven from

MCU GPIO

49 DIO0/PTE2/SPI1_SCK Digital Input/

Output
50 DIO1/PTE3/SPI1_MISO/

SPI1_MOSI

Digital Input/

Output
51 DIO2 Digital Input/

Internally connected to Transceiver GPIO
bit 0 and MCU Port E bit 2 / SPI1 clock

Internally connected to Transceiver GPIO
bit 1 and MCU Port E bit 3 /SPI1 in or out

Transceiver GPIO Bit 2

MCU IO and Transceiver
IO connected onboard

MCU IO and Transceiver
IO connected onboard

Output
52 DIO3 Digital Input/

Transceiver GPIO Bit 3

Output
53 DIO4 Digital Input/

Transceiver GPIO Bit 4

Output
54 DIO5/CLKOUT Digital Input/

Output

Transceiver GPIO Bit 5 / ClkOut Commonly programmed

as ClkOut to supply MCU
clock; connect to Pin 15

PTA18/EXTAL0.
55 VDD Power Input MCU VDD supply Connect to VDD supply
56 VDDAD Power Input MCU Analog supply Connect to Analog

supply
57 MISO/PTC7/SPI0_MISO/

SPI0_MOSI

Digital Input/
Output

Internal SPI data connection from
Transceiver MISO bit 1 to MCU SPI0 (Port
C bit 7 )

• MCU IO and
Transceiver IO
connected onboard

• MCU IO must be
configured for this
connection

• SPI0 is dedicated to
radio interface; not for
application usage

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MKW01Z128 Pins and Connections

Table 2-1. Pin Function Description (Sheet 5 of 5)

Pin # Pin Name Type Description Functionality

58 NSS/PTD0/SPI0_PCS0 Digital Input/

Output

59 SCK/PTC5/SPI0_SCK Digital Input/

Output

60 MOSI/PTC6/SPI0_MOSI/

SPI0_MISO

Digital Input/
Output

Internal SPI select connection between
Transceiver NSS and MCU SPI0 (Port D bit

0)

Internal SPI clock connection between
Transceiver SCK and MCU SPI0 (port C bit

5)

Internal SPI data connection to Transceiver
MOSI bit 1 to MCU SPI0 (Port C bit 6 )

• MCU IO and
Transceiver IO
connected onboard

• MCU IO must be
configured for this
connection

• SPI0 is dedicated to
radio interface; not for
application usage

• MCU IO and
Transceiver IO
connected onboard

• MCU IO must be
configured for this
connection

• SPI0 is dedicated to
radio interface; not for
application usage

• MCU IO and
Transceiver IO
connected onboard

• MCU IO must be
configured for this
connection

• SPI0 is dedicated to
radio interface; not for
application usage

FLAG VSS Power input External package flag. Common VSS Connect to ground.

2.3 Internal Functional Interconnects

The MCU provides control to the transceiver through the SPI0 Port and receives status from the transceiver
from the DIOx pins. Certain interconnects between the devices are routed in the package. In addition, the
signals are brought out to external pads for monitoring, but only SPI1 is intended for applications usage.
SPI0 is dedicated to the radio interface and should not be used for applications.

Table 2-2. MKW01Z128 Internal Functional Interconnects

Pin # MCU Signal

49

DIO0/PTE2/SPI1_
SCK

50 DIO1/PTE3/SPI1_

MISO/SPI1_MOSI

Transceiver

Signal

DIO0 Transceiver DIO0 can be programmed to provide status to the MCU

DIO1 Transceiver DIO1 can be programmed to provide status to the MCU

Description

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MKW01Z128 Pins and Connections

Table 2-2. MKW01Z128 Internal Functional Interconnects

Pin # MCU Signal

57 MISO/PTC7/SPI0_

MISO/SPI0_MOSI

58 NSS/PTD0/SPI0_

PCS0
SCK/PTC5/SPI0_

59

SCK

60 MOSI/PTC6/SPI0_

MOSI/SPI0_MISO

• As shown in Table 2-2, the MCU SPI Port pin selection must be
configured by software by writing the corresponding port multiplex
control registers

• The transceiver DIO pins must be programmed to provide desired status

Transceiver

Signal

MISO SPI data from transceiver to MCU

NSS PTD0 programmed as SPI chip select

SCK SPI Clock

MOSI SPI data from MCU to transceiver

Description

NOTE

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