NXP Semiconductors MKL27Z128VFM4, MKL27Z256VMP4, MKL27Z256VFM4, MKL27Z128VLH4, MKL27Z256VLH4 Reference Manual

KL27 Sub-Family Reference Manual

Supports: MKL27Z128VFM4, MKL27Z256VFM4, MKL27Z128VFT4,

MKL27Z256VFT4, MKL27Z128VMP4, MKL27Z256VMP4,

MKL27Z128VLH4, MKL27Z256VLH4

Document Number: KL27P64M48SF6RM

Rev. 5, 01/2016

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Contents

Section number Title Page

Chapter 1

About This Document

1.1 Overview.......................................................................................................................................................................37

1.1.1 Purpose...........................................................................................................................................................37

1.1.2 Audience........................................................................................................................................................ 37

1.2 Conventions.................................................................................................................................................................. 37

1.2.1 Numbering systems........................................................................................................................................37

1.2.2 Typographic notation..................................................................................................................................... 38

1.2.3 Special terms.................................................................................................................................................. 38

Chapter 2

Introduction

2.1 Overview.......................................................................................................................................................................39

2.1.1 Sub-family introduction................................................................................................................................. 39

2.2 Module functional categories........................................................................................................................................40

2.2.1 ARM Cortex-M0+ core modules................................................................................................................... 41

2.2.2 System modules............................................................................................................................................. 41

2.2.3 Memories and memory interfaces..................................................................................................................42

2.2.4 Clocks.............................................................................................................................................................42

2.2.5 Security and integrity modules...................................................................................................................... 43

2.2.6 Analog modules............................................................................................................................................. 43

2.2.7 Timer modules............................................................................................................................................... 43

2.2.8 Communication interfaces............................................................................................................................. 44

2.2.9 Human-machine interfaces............................................................................................................................ 45

2.3 Module to module interconnects...................................................................................................................................45

2.3.1 Interconnection overview...............................................................................................................................45

2.3.2 Analog reference options............................................................................................................................... 47

Chapter 3

Core Overview

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3.1 ARM Cortex-M0+ core introduction............................................................................................................................49

3.1.1 Buses, interconnects, and interfaces.............................................................................................................. 49

3.1.2 System tick timer........................................................................................................................................... 49

3.1.3 Debug facilities.............................................................................................................................................. 49

3.1.4 Core privilege levels...................................................................................................................................... 50

3.2 Nested vectored interrupt controller (NVIC) ...............................................................................................................50

3.2.1 Interrupt priority levels.................................................................................................................................. 50

3.2.2 Non-maskable interrupt..................................................................................................................................50

3.2.3 Interrupt channel assignments........................................................................................................................50

3.3 AWIC introduction....................................................................................................................................................... 53

3.3.1 Wake-up sources............................................................................................................................................ 53

Chapter 4

Memory Map

4.1 Introduction...................................................................................................................................................................55

4.2 Flash memory............................................................................................................................................................... 55

4.2.1 Flash memory map.........................................................................................................................................55

4.2.2 Flash security................................................................................................................................................. 56

4.2.3 Flash modes....................................................................................................................................................56

4.2.4 Erase all flash contents...................................................................................................................................56

4.2.5 FTFA_FOPT register..................................................................................................................................... 57

4.3 SRAM........................................................................................................................................................................... 57

4.3.1 SRAM sizes....................................................................................................................................................57

4.3.2 SRAM ranges................................................................................................................................................. 57

4.3.3 SRAM retention in low power modes............................................................................................................58

4.4 System Register file......................................................................................................................................................58

4.5 System memory map.....................................................................................................................................................59

4.6 Bit Manipulation Engine...............................................................................................................................................60

4.7 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................60

4.7.1 Read-after-write sequence and required serialization of memory operations................................................60

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4.7.2 Peripheral bridge (AIPS-Lite) memory map..................................................................................................61

Chapter 5

Clock Distribution

5.1 Introduction...................................................................................................................................................................65

5.2 Programming model......................................................................................................................................................65

5.3 High-level device clocking diagram............................................................................................................................. 65

5.4 Clock definitions...........................................................................................................................................................66

5.4.1 Device clock summary...................................................................................................................................67

5.5 Internal clocking requirements..................................................................................................................................... 69

5.5.1 Clock divider values after reset......................................................................................................................70

5.5.2 VLPR mode clocking.....................................................................................................................................70

5.6 Clock gating..................................................................................................................................................................71

5.7 Module clocks...............................................................................................................................................................71

5.7.1 PMC 1-kHz LPO clock.................................................................................................................................. 72

5.7.2 COP clocking................................................................................................................................................. 72

5.7.3 RTC clocking................................................................................................................................................. 73

5.7.4 RTC_CLKOUT and CLKOUT32K clocking................................................................................................ 73

5.7.5 LPTMR clocking............................................................................................................................................74

5.7.6 TPM clocking.................................................................................................................................................75

5.7.7 USB FS device only controller clocking........................................................................................................75

5.7.8 LPUART clocking......................................................................................................................................... 76

5.7.9 FlexIO clocking..............................................................................................................................................77

5.7.10 I2S/SAI clocking............................................................................................................................................78

Chapter 6

Reset and Boot

6.1 Introduction...................................................................................................................................................................79

6.2 Reset..............................................................................................................................................................................79

6.2.1 Power-on reset (POR).................................................................................................................................... 80

6.2.2 System reset sources...................................................................................................................................... 80

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6.2.3 MCU resets.................................................................................................................................................... 83

6.2.4 RESET pin .................................................................................................................................................... 84

6.3 Boot...............................................................................................................................................................................84

6.3.1 Boot sources................................................................................................................................................... 85

6.3.2 FOPT boot options......................................................................................................................................... 85

6.3.3 Boot sequence................................................................................................................................................ 87

Chapter 7

Power Management

7.1 Introduction...................................................................................................................................................................89

7.2 Clocking modes............................................................................................................................................................ 89

7.2.1 Partial Stop..................................................................................................................................................... 89

7.2.2 DMA Wakeup................................................................................................................................................ 90

7.2.3 Compute Operation........................................................................................................................................ 91

7.2.4 Peripheral Doze..............................................................................................................................................92

7.2.5 Clock gating................................................................................................................................................... 93

7.3 Power modes.................................................................................................................................................................93

7.4 Entering and exiting power modes............................................................................................................................... 95

7.5 Module operation in low-power modes........................................................................................................................ 96

Chapter 8

Security

8.1 Introduction...................................................................................................................................................................101

8.1.1 Flash security................................................................................................................................................. 101

8.1.2 Security interactions with other modules.......................................................................................................101

Chapter 9

Debug

9.1 Introduction...................................................................................................................................................................103

9.2 Debug port pin descriptions..........................................................................................................................................103

9.3 SWD status and control registers..................................................................................................................................104

9.3.1 MDM-AP Control Register............................................................................................................................105

9.3.2 MDM-AP Status Register.............................................................................................................................. 106

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9.4 Debug resets..................................................................................................................................................................108

9.5 Micro Trace Buffer (MTB)...........................................................................................................................................108

9.6 Debug in low-power modes..........................................................................................................................................109

9.7 Debug and security....................................................................................................................................................... 110

Chapter 10

Pinouts and Packaging

10.1 Introduction...................................................................................................................................................................111

10.2 Signal multiplexing integration.................................................................................................................................... 111

10.2.1 Clock gating................................................................................................................................................... 112

10.2.2 Signal multiplexing constraints......................................................................................................................112

10.3 KL27 Signal Multiplexing and Pin Assignments......................................................................................................... 112

10.4 KL27 Family Pinouts....................................................................................................................................................115

10.5 Module Signal Description Tables................................................................................................................................118

10.5.1 Core modules................................................................................................................................................. 118

10.5.2 System modules............................................................................................................................................. 118

10.5.3 Clock modules................................................................................................................................................119

10.5.4 Analog............................................................................................................................................................119

10.5.5 Timer Modules...............................................................................................................................................120

10.5.6 Communication interfaces............................................................................................................................. 121

10.5.7 Human-machine interfaces (HMI).................................................................................................................124

Chapter 11

Port Control and Interrupts (PORT)

11.1 Chip-specific PORT information..................................................................................................................................125

11.2 Port control and interrupt summary..............................................................................................................................126

11.3 Introduction...................................................................................................................................................................127

11.4 Overview.......................................................................................................................................................................127

11.4.1 Features.......................................................................................................................................................... 127

11.4.2 Modes of operation........................................................................................................................................ 128

11.5 External signal description............................................................................................................................................129

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11.6 Detailed signal description............................................................................................................................................129

11.7 Memory map and register definition.............................................................................................................................129

11.7.1

11.7.2

11.7.3

11.7.4

11.8 Functional description...................................................................................................................................................139

11.8.1 Pin control......................................................................................................................................................139

11.8.2 Global pin control.......................................................................................................................................... 140

11.8.3 External interrupts..........................................................................................................................................140

Pin Control Register n (PORTx_PCRn).........................................................................................................135

Global Pin Control Low Register (PORTx_GPCLR)....................................................................................138

Global Pin Control High Register (PORTx_GPCHR)...................................................................................138

Interrupt Status Flag Register (PORTx_ISFR).............................................................................................. 139

Chapter 12

System Integration Module (SIM)

12.1 Chip-specific SIM information.....................................................................................................................................143

12.1.1 COP clocks.....................................................................................................................................................143

12.2 Introduction...................................................................................................................................................................143

12.2.1 Features.......................................................................................................................................................... 143

12.3 Memory map and register definition.............................................................................................................................144

12.3.1 System Options Register 1 (SIM_SOPT1).................................................................................................... 145

12.3.2 SOPT1 Configuration Register (SIM_SOPT1CFG)......................................................................................146

12.3.3 System Options Register 2 (SIM_SOPT2).................................................................................................... 148

12.3.4 System Options Register 4 (SIM_SOPT4).................................................................................................... 150

12.3.5 System Options Register 5 (SIM_SOPT5).................................................................................................... 151

12.3.6 System Options Register 7 (SIM_SOPT7).................................................................................................... 153

12.3.7 System Device Identification Register (SIM_SDID).....................................................................................154

12.3.8 System Clock Gating Control Register 4 (SIM_SCGC4)..............................................................................156

12.3.9 System Clock Gating Control Register 5 (SIM_SCGC5)..............................................................................158

12.3.10 System Clock Gating Control Register 6 (SIM_SCGC6)..............................................................................160

12.3.11 System Clock Gating Control Register 7 (SIM_SCGC7)..............................................................................162

12.3.12 System Clock Divider Register 1 (SIM_CLKDIV1).....................................................................................162

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12.3.13 Flash Configuration Register 1 (SIM_FCFG1)............................................................................................. 164

12.3.14 Flash Configuration Register 2 (SIM_FCFG2)............................................................................................. 165

12.3.15 Unique Identification Register Mid-High (SIM_UIDMH)............................................................................166

12.3.16 Unique Identification Register Mid Low (SIM_UIDML)............................................................................. 167

12.3.17 Unique Identification Register Low (SIM_UIDL)........................................................................................ 167

12.3.18 COP Control Register (SIM_COPC)............................................................................................................. 168

12.3.19 Service COP (SIM_SRVCOP).......................................................................................................................169

12.4 Functional description...................................................................................................................................................169

12.4.1 COP watchdog operation............................................................................................................................... 170

Chapter 13

Kinetis ROM Bootloader

13.1 Chip-Specific Information............................................................................................................................................173

13.2 Introduction...................................................................................................................................................................173

13.3 Functional Description..................................................................................................................................................175

13.3.1 Memory Maps................................................................................................................................................175

13.3.2 The Kinetis Bootloader Configuration Area (BCA)......................................................................................176

13.3.3 Start-up Process..............................................................................................................................................177

13.3.4 Clock Configuration.......................................................................................................................................179

13.3.5 Bootloader Entry Point...................................................................................................................................180

13.3.6 Bootloader Protocol....................................................................................................................................... 181

13.3.7 Bootloader Packet Types............................................................................................................................... 186

13.3.8 Bootloader Command API.............................................................................................................................193

13.3.9 Bootloader Exit state......................................................................................................................................208

13.4 Peripherals Supported...................................................................................................................................................209

13.4.1 I2C Peripheral................................................................................................................................................ 209

13.4.2 SPI Peripheral................................................................................................................................................ 211

13.4.3 USB peripheral...............................................................................................................................................213

13.5 Get/SetProperty Command Properties..........................................................................................................................217

13.5.1 Property Definitions.......................................................................................................................................218

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13.6 Kinetis Bootloader Status Error Codes.........................................................................................................................220

13.7 Bootloader errata...........................................................................................................................................................221

Chapter 14

System Mode Controller (SMC)

14.1 Chip-specific SMC information....................................................................................................................................223

14.2 Introduction...................................................................................................................................................................223

14.3 Modes of operation.......................................................................................................................................................223

14.4 Memory map and register descriptions.........................................................................................................................225

14.4.1 Power Mode Protection register (SMC_PMPROT).......................................................................................226

14.4.2 Power Mode Control register (SMC_PMCTRL)...........................................................................................227

14.4.3 Stop Control Register (SMC_STOPCTRL)...................................................................................................228

14.4.4 Power Mode Status register (SMC_PMSTAT)............................................................................................. 230

14.5 Functional description...................................................................................................................................................230

14.5.1 Power mode transitions..................................................................................................................................230

14.5.2 Power mode entry/exit sequencing................................................................................................................ 233

14.5.3 Run modes......................................................................................................................................................234

14.5.4 Wait modes.................................................................................................................................................... 236

14.5.5 Stop modes.....................................................................................................................................................237

14.5.6 Debug in low power modes........................................................................................................................... 240

Chapter 15

Power Management Controller (PMC)

15.1 Introduction...................................................................................................................................................................241

15.2 Features.........................................................................................................................................................................241

15.3 Low-voltage detect (LVD) system................................................................................................................................241

15.3.1 LVD reset operation.......................................................................................................................................242

15.3.2 LVD interrupt operation.................................................................................................................................242

15.3.3 Low-voltage warning (LVW) interrupt operation......................................................................................... 242

15.4 I/O retention..................................................................................................................................................................243

15.5 Memory map and register descriptions.........................................................................................................................243

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15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1).......................................................... 244

15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2).......................................................... 245

15.5.3 Regulator Status And Control register (PMC_REGSC)................................................................................246

Chapter 16

Miscellaneous Control Module (MCM)

16.1 Introduction...................................................................................................................................................................249

16.1.1 Features.......................................................................................................................................................... 249

16.2 Memory map/register descriptions............................................................................................................................... 249

16.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................250

16.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 250

16.2.3 Platform Control Register (MCM_PLACR)..................................................................................................251

16.2.4 Compute Operation Control Register (MCM_CPO)..................................................................................... 254

Chapter 17

Crossbar Switch Lite (AXBS-Lite)

17.1 Chip-specific AXBS-Lite information..........................................................................................................................257

17.1.1 Crossbar-light switch master assignments..................................................................................................... 257

17.1.2 Crossbar switch slave assignments................................................................................................................ 257

17.2 Introduction...................................................................................................................................................................257

17.2.1 Features.......................................................................................................................................................... 258

17.3 Memory Map / Register Definition...............................................................................................................................258

17.4 Functional Description..................................................................................................................................................258

17.4.1 General operation...........................................................................................................................................258

17.4.2 Arbitration......................................................................................................................................................259

17.5 Initialization/application information........................................................................................................................... 261

Chapter 18

Low-Leakage Wakeup Unit (LLWU)

18.1 LLWU interrupt............................................................................................................................................................263

18.1.1 Wake-up Sources........................................................................................................................................... 263

18.2 Introduction...................................................................................................................................................................264

18.2.1 Features.......................................................................................................................................................... 264

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18.2.2 Modes of operation........................................................................................................................................ 265

18.2.3 Block diagram................................................................................................................................................266

18.3 LLWU signal descriptions............................................................................................................................................267

18.4 Memory map/register definition...................................................................................................................................267

18.4.1 LLWU Pin Enable 1 register (LLWU_PE1)..................................................................................................268

18.4.2 LLWU Pin Enable 2 register (LLWU_PE2)..................................................................................................269

18.4.3 LLWU Pin Enable 3 register (LLWU_PE3)..................................................................................................270

18.4.4 LLWU Pin Enable 4 register (LLWU_PE4)..................................................................................................271

18.4.5 LLWU Module Enable register (LLWU_ME).............................................................................................. 272

18.4.6 LLWU Flag 1 register (LLWU_F1)...............................................................................................................274

18.4.7 LLWU Flag 2 register (LLWU_F2)...............................................................................................................276

18.4.8 LLWU Flag 3 register (LLWU_F3)...............................................................................................................277

18.4.9 LLWU Pin Filter 1 register (LLWU_FILT1)................................................................................................ 279

18.4.10 LLWU Pin Filter 2 register (LLWU_FILT2)................................................................................................ 280

18.5 Functional description...................................................................................................................................................281

18.5.1 LLS mode.......................................................................................................................................................282

18.5.2 VLLS modes.................................................................................................................................................. 282

18.5.3 Initialization................................................................................................................................................... 282

Chapter 19

Peripheral Bridge (AIPS-Lite)

19.1 Chip-specific AIPS-Lite information............................................................................................................................283

19.1.1 Number of peripheral bridges........................................................................................................................ 283

19.1.2 Memory maps................................................................................................................................................ 283

19.2 Introduction...................................................................................................................................................................283

19.2.1 Features.......................................................................................................................................................... 283

19.2.2 General operation...........................................................................................................................................284

19.3 Memory map/register definition...................................................................................................................................284

19.3.1 Master Privilege Register A (AIPS_MPRA)................................................................................................. 284

19.3.2

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Peripheral Access Control Register (AIPS_PACRn).....................................................................................286

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19.3.3

19.4 Functional description...................................................................................................................................................291

19.4.1 Access support............................................................................................................................................... 291

Peripheral Access Control Register (AIPS_n)............................................................................................... 0

Chapter 20

Direct Memory Access Multiplexer (DMAMUX)

20.1 Chip-specific DMAMUX information......................................................................................................................... 293

20.1.1 DMA MUX Request Sources........................................................................................................................ 293

20.1.2 DMA transfers via PIT trigger.......................................................................................................................295

20.2 Introduction...................................................................................................................................................................295

20.2.1 Overview........................................................................................................................................................295

20.2.2 Features.......................................................................................................................................................... 296

20.2.3 Modes of operation........................................................................................................................................ 296

20.3 External signal description............................................................................................................................................297

20.4 Memory map/register definition...................................................................................................................................297

20.4.1

20.5 Functional description...................................................................................................................................................298

20.5.1 DMA channels with periodic triggering capability........................................................................................299

20.5.2 DMA channels with no triggering capability.................................................................................................301

20.5.3 Always-enabled DMA sources...................................................................................................................... 301

20.6 Initialization/application information........................................................................................................................... 303

20.6.1 Reset...............................................................................................................................................................303

20.6.2 Enabling and configuring sources..................................................................................................................303

Channel Configuration register (DMAMUXx_CHCFGn)............................................................................ 297

Chapter 21

DMA Controller Module

21.1 Introduction...................................................................................................................................................................307

21.1.1 Overview........................................................................................................................................................307

21.1.2 Features.......................................................................................................................................................... 308

21.2 DMA Transfer Overview..............................................................................................................................................309

21.3 Memory Map/Register Definition.................................................................................................................................310

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21.3.1

21.3.2

21.3.3

21.3.4

21.4 Functional Description..................................................................................................................................................319

21.4.1 Transfer requests (Cycle-Steal and Continuous modes)................................................................................319

21.4.2 Channel initialization and startup.................................................................................................................. 320

21.4.3 Dual-Address Data Transfer Mode................................................................................................................321

21.4.4 Advanced Data Transfer Controls: Auto-Alignment.....................................................................................322

21.4.5 Termination....................................................................................................................................................323

Source Address Register (DMA_SARn)....................................................................................................... 311

Destination Address Register (DMA_DARn)............................................................................................... 312

DMA Status Register / Byte Count Register (DMA_DSR_BCRn)...............................................................313

DMA Control Register (DMA_DCRn)..........................................................................................................315

Chapter 22

Reset Control Module (RCM)

22.1 Introduction...................................................................................................................................................................325

22.2 Reset memory map and register descriptions............................................................................................................... 325

22.2.1 System Reset Status Register 0 (RCM_SRS0).............................................................................................. 326

22.2.2 System Reset Status Register 1 (RCM_SRS1).............................................................................................. 327

22.2.3 Reset Pin Filter Control register (RCM_RPFC)............................................................................................ 328

22.2.4 Reset Pin Filter Width register (RCM_RPFW)............................................................................................. 329

22.2.5 Force Mode Register (RCM_FM)..................................................................................................................331

22.2.6 Mode Register (RCM_MR)........................................................................................................................... 331

22.2.7 Sticky System Reset Status Register 0 (RCM_SSRS0).................................................................................332

22.2.8 Sticky System Reset Status Register 1 (RCM_SSRS1).................................................................................333

Chapter 23

Analog-to-Digital Converter (ADC)

23.1 Chip-specific ADC information....................................................................................................................................335

23.1.1 ADC instantiation information.......................................................................................................................335

23.1.2 DMA Support on ADC.................................................................................................................................. 335

23.1.3 ADC0 connections/channel assignment.........................................................................................................336

23.1.4 ADC analog supply and reference connections............................................................................................. 337

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23.1.5 Alternate clock............................................................................................................................................... 337

23.2 Introduction...................................................................................................................................................................338

23.2.1 Features.......................................................................................................................................................... 338

23.2.2 Block diagram................................................................................................................................................339

23.3 ADC signal descriptions...............................................................................................................................................340

23.3.1 Analog Power (VDDA)................................................................................................................................. 340

23.3.2 Analog Ground (VSSA).................................................................................................................................340

23.3.3 Voltage Reference Select...............................................................................................................................340

23.3.4 Analog Channel Inputs (ADx)....................................................................................................................... 341

23.3.5 Differential Analog Channel Inputs (DADx).................................................................................................341

23.4 Memory map and register definitions...........................................................................................................................341

23.4.1

23.4.2

23.4.3

23.4.4

23.4.5

23.4.6

23.4.7

23.4.8

23.4.9

23.4.10

23.4.11

23.4.12

23.4.13

23.4.14

ADC Status and Control Registers 1 (ADCx_SC1n).....................................................................................343

ADC Configuration Register 1 (ADCx_CFG1).............................................................................................346

ADC Configuration Register 2 (ADCx_CFG2).............................................................................................347

ADC Data Result Register (ADCx_Rn).........................................................................................................348

Compare Value Registers (ADCx_CVn)....................................................................................................... 350

Status and Control Register 2 (ADCx_SC2)..................................................................................................351

Status and Control Register 3 (ADCx_SC3)..................................................................................................353

ADC Offset Correction Register (ADCx_OFS).............................................................................................354

ADC Plus-Side Gain Register (ADCx_PG)...................................................................................................355

ADC Minus-Side Gain Register (ADCx_MG).............................................................................................. 355

ADC Plus-Side General Calibration Value Register (ADCx_CLPD)........................................................... 356

ADC Plus-Side General Calibration Value Register (ADCx_CLPS)............................................................357

ADC Plus-Side General Calibration Value Register (ADCx_CLP4)............................................................ 357

ADC Plus-Side General Calibration Value Register (ADCx_CLP3)............................................................ 358

23.4.15

23.4.16

23.4.17

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ADC Plus-Side General Calibration Value Register (ADCx_CLP2)............................................................ 358

ADC Plus-Side General Calibration Value Register (ADCx_CLP1)............................................................ 359

ADC Plus-Side General Calibration Value Register (ADCx_CLP0)............................................................ 359

ADC Minus-Side General Calibration Value Register (ADCx_CLMD).......................................................360

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23.4.19

23.4.20

23.4.21

23.4.22

23.4.23

23.4.24

23.5 Functional description...................................................................................................................................................363

23.5.1 Clock select and divide control......................................................................................................................364

23.5.2 Voltage reference selection............................................................................................................................365

23.5.3 Hardware trigger and channel selects............................................................................................................ 365

23.5.4 Conversion control.........................................................................................................................................366

23.5.5 Automatic compare function..........................................................................................................................374

23.5.6 Calibration function....................................................................................................................................... 375

23.5.7 User-defined offset function.......................................................................................................................... 377

ADC Minus-Side General Calibration Value Register (ADCx_CLMS)....................................................... 360

ADC Minus-Side General Calibration Value Register (ADCx_CLM4)....................................................... 361

ADC Minus-Side General Calibration Value Register (ADCx_CLM3)....................................................... 361

ADC Minus-Side General Calibration Value Register (ADCx_CLM2)....................................................... 362

ADC Minus-Side General Calibration Value Register (ADCx_CLM1)....................................................... 362

ADC Minus-Side General Calibration Value Register (ADCx_CLM0)....................................................... 363

23.5.8 Temperature sensor........................................................................................................................................378

23.5.9 MCU wait mode operation.............................................................................................................................379

23.5.10 MCU Normal Stop mode operation...............................................................................................................379

23.5.11 MCU Low-Power Stop mode operation........................................................................................................ 380

23.6 Initialization information..............................................................................................................................................381

23.6.1 ADC module initialization example.............................................................................................................. 381

23.7 Application information................................................................................................................................................383

23.7.1 External pins and routing............................................................................................................................... 383

23.7.2 Sources of error..............................................................................................................................................385

Chapter 24

Comparator (CMP)

24.1 Chip-specific CMP information....................................................................................................................................391

24.1.1 CMP instantiation information.......................................................................................................................391

24.1.2 CMP input connections..................................................................................................................................391

24.1.3 CMP external references................................................................................................................................392

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24.1.4 CMP trigger mode..........................................................................................................................................392

24.2 Introduction...................................................................................................................................................................393

24.2.1 CMP features..................................................................................................................................................393

24.2.2 6-bit DAC key features.................................................................................................................................. 394

24.2.3 ANMUX key features.................................................................................................................................... 394

24.2.4 CMP, DAC and ANMUX diagram................................................................................................................394

24.2.5 CMP block diagram....................................................................................................................................... 395

24.3 Memory map/register definitions..................................................................................................................................397

24.3.1

24.3.2

24.3.3

24.3.4

24.3.5

24.3.6

24.4 Functional description...................................................................................................................................................402

24.4.1 CMP functional modes...................................................................................................................................403

24.4.2 Power modes..................................................................................................................................................406

24.4.3 Startup and operation..................................................................................................................................... 407

24.4.4 Low-pass filter............................................................................................................................................... 408

24.5 CMP interrupts..............................................................................................................................................................410

24.6 DMA support................................................................................................................................................................410

24.7 CMP Asynchronous DMA support...............................................................................................................................410

CMP Control Register 0 (CMPx_CR0)......................................................................................................... 397

CMP Control Register 1 (CMPx_CR1)......................................................................................................... 398

CMP Filter Period Register (CMPx_FPR).....................................................................................................399

CMP Status and Control Register (CMPx_SCR)...........................................................................................400

DAC Control Register (CMPx_DACCR)......................................................................................................401

MUX Control Register (CMPx_MUXCR).................................................................................................... 401

24.8 Digital-to-analog converter...........................................................................................................................................411

24.9 DAC functional description..........................................................................................................................................411

24.9.1 Voltage reference source select......................................................................................................................411

24.10 DAC resets....................................................................................................................................................................412

24.11 DAC clocks...................................................................................................................................................................412

24.12 DAC interrupts..............................................................................................................................................................412

24.13 CMP Trigger Mode.......................................................................................................................................................412

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Chapter 25

12-bit Digital-to-Analog Converter (DAC)

25.1 Introduction...................................................................................................................................................................413

25.2 Features.........................................................................................................................................................................413

25.3 Block diagram...............................................................................................................................................................413

25.4 Memory map/register definition...................................................................................................................................414

25.4.1

25.4.2

25.4.3

25.4.4

25.4.5

25.4.6

25.5 Functional description...................................................................................................................................................419

25.5.1 DAC data buffer operation.............................................................................................................................419

25.5.2 DMA operation.............................................................................................................................................. 421

25.5.3 Resets............................................................................................................................................................. 421

25.5.4 Low-Power mode operation...........................................................................................................................421

DAC Data Low Register (DACx_DATnL)................................................................................................... 415

DAC Data High Register (DACx_DATnH).................................................................................................. 415

DAC Status Register (DACx_SR)................................................................................................................. 416

DAC Control Register (DACx_C0)............................................................................................................... 417

DAC Control Register 1 (DACx_C1)............................................................................................................ 418

DAC Control Register 2 (DACx_C2)............................................................................................................ 418

Chapter 26

Voltage Reference (VREFV1)

26.1 Introduction...................................................................................................................................................................423

26.1.1 Overview........................................................................................................................................................424

26.1.2 Features.......................................................................................................................................................... 424

26.1.3 Modes of Operation....................................................................................................................................... 424

26.1.4 VREF Signal Descriptions.............................................................................................................................425

26.2 Memory Map and Register Definition..........................................................................................................................425

26.2.1 VREF Trim Register (VREF_TRM)..............................................................................................................426

26.2.2 VREF Status and Control Register (VREF_SC)............................................................................................427

26.3 Functional Description..................................................................................................................................................428

26.3.1 Voltage Reference Disabled, SC[VREFEN] = 0........................................................................................... 428

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26.3.2 Voltage Reference Enabled, SC[VREFEN] = 1............................................................................................ 428

26.4 Internal voltage regulator..............................................................................................................................................430

26.5 Initialization/Application Information..........................................................................................................................430

Chapter 27

Multipurpose Clock Generator Lite (MCG_Lite)

27.1 Introduction ..................................................................................................................................................................433

27.1.1 Features ......................................................................................................................................................... 433

27.1.2 Block diagram ...............................................................................................................................................434

27.2 Memory map and register definition.............................................................................................................................434

27.2.1 MCG Control Register 1 (MCG_C1).............................................................................................................435

27.2.2 MCG Control Register 2 (MCG_C2).............................................................................................................436

27.2.3 MCG Status Register (MCG_S).................................................................................................................... 437

27.2.4 MCG Status and Control Register (MCG_SC)..............................................................................................437

27.2.5 MCG Miscellaneous Control Register (MCG_MC)......................................................................................438

27.3 Functional description...................................................................................................................................................439

27.3.1 Clock mode switching ...................................................................................................................................439

27.3.2 LIRC divider 1 .............................................................................................................................................. 440

27.3.3 LIRC divider 2 .............................................................................................................................................. 440

27.3.4 Enable LIRC in Stop mode ........................................................................................................................... 440

27.3.5 MCG-Lite in Low-power mode .................................................................................................................... 440

27.3.6 HIRC USB recovery ..................................................................................................................................... 441

Chapter 28

Oscillator (OSC)

28.1 Chip-specific OSC information.................................................................................................................................... 443

28.1.1 OSC modes of operation with MCG_Lite and RTC......................................................................................443

28.2 Introduction...................................................................................................................................................................443

28.3 Features and Modes...................................................................................................................................................... 443

28.4 Block Diagram..............................................................................................................................................................444

28.5 OSC Signal Descriptions.............................................................................................................................................. 445

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28.6 External Crystal / Resonator Connections....................................................................................................................445

28.7 External Clock Connections......................................................................................................................................... 447

28.8 Memory Map/Register Definitions...............................................................................................................................447

28.8.1 OSC Memory Map/Register Definition.........................................................................................................448

28.9 Functional Description..................................................................................................................................................449

28.9.1 OSC module states.........................................................................................................................................449

28.9.2 OSC module modes....................................................................................................................................... 451

28.9.3 Counter...........................................................................................................................................................453

28.9.4 Reference clock pin requirements..................................................................................................................453

28.10 Reset..............................................................................................................................................................................453

28.11 Low power modes operation.........................................................................................................................................454

28.12 Interrupts.......................................................................................................................................................................454

Chapter 29

Timer/PWM Module (TPM)

29.1 Chip-specific TPM information....................................................................................................................................455

29.1.1 TPM instantiation information.......................................................................................................................455

29.1.2 Clock options................................................................................................................................................. 456

29.1.3 Trigger options...............................................................................................................................................456

29.1.4 Global timebase..............................................................................................................................................457

29.1.5 TPM interrupts............................................................................................................................................... 457

29.2 Introduction...................................................................................................................................................................458

29.2.1 TPM Philosophy............................................................................................................................................ 458

29.2.2 Features.......................................................................................................................................................... 458

29.2.3 Modes of operation........................................................................................................................................ 459

29.2.4 Block diagram................................................................................................................................................459

29.3 TPM Signal Descriptions..............................................................................................................................................460

29.3.1 TPM_EXTCLK — TPM External Clock...................................................................................................... 460

29.3.2 TPM_CHn — TPM Channel (n) I/O Pin.......................................................................................................461

29.4 Memory Map and Register Definition..........................................................................................................................461

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29.4.1

29.4.2

29.4.3

29.4.4

29.4.5

29.4.6

29.4.7

29.4.8

29.5 Functional description...................................................................................................................................................474

29.5.1 Clock domains................................................................................................................................................474

29.5.2 Prescaler.........................................................................................................................................................475

29.5.3 Counter...........................................................................................................................................................475

29.5.4 Input Capture Mode....................................................................................................................................... 478

29.5.5 Output Compare Mode...................................................................................................................................479

Status and Control (TPMx_SC)..................................................................................................................... 463

Counter (TPMx_CNT)................................................................................................................................... 464

Modulo (TPMx_MOD)..................................................................................................................................465

Channel (n) Status and Control (TPMx_CnSC).............................................................................................466

Channel (n) Value (TPMx_CnV)...................................................................................................................468

Capture and Compare Status (TPMx_STATUS)...........................................................................................468

Channel Polarity (TPMx_POL)..................................................................................................................... 470

Configuration (TPMx_CONF).......................................................................................................................471

29.5.6 Edge-Aligned PWM (EPWM) Mode.............................................................................................................480

29.5.7 Center-Aligned PWM (CPWM) Mode..........................................................................................................482

29.5.8 Registers Updated from Write Buffers.......................................................................................................... 484

29.5.9 DMA.............................................................................................................................................................. 484

29.5.10 Output triggers............................................................................................................................................... 485

29.5.11 Reset Overview..............................................................................................................................................485

29.5.12 TPM Interrupts...............................................................................................................................................486

Chapter 30

Periodic Interrupt Timer (PIT)

30.1 Chip-specific PIT information......................................................................................................................................487

30.1.1 PIT/DMA periodic trigger assignments ........................................................................................................487

30.1.2 PIT/ADC triggers...........................................................................................................................................487

30.1.3 PIT/TPM triggers........................................................................................................................................... 487

30.1.4 PIT/DAC triggers...........................................................................................................................................487

30.2 Introduction...................................................................................................................................................................488

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30.2.1 Block diagram................................................................................................................................................488

30.2.2 Features.......................................................................................................................................................... 488

30.3 Signal description..........................................................................................................................................................489

30.4 Memory map/register description.................................................................................................................................489

30.4.1 PIT Module Control Register (PIT_MCR).................................................................................................... 490

30.4.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H)................................................................................. 491

30.4.3 PIT Lower Lifetime Timer Register (PIT_LTMR64L)................................................................................. 491

30.4.4

30.4.5

30.4.6

30.4.7

30.5 Functional description...................................................................................................................................................494

30.5.1 General operation...........................................................................................................................................494

30.5.2 Interrupts........................................................................................................................................................ 496

30.5.3 Chained timers............................................................................................................................................... 496

30.6 Initialization and application information.....................................................................................................................496

30.7 Example configuration for chained timers....................................................................................................................497

30.8 Example configuration for the lifetime timer............................................................................................................... 498

Timer Load Value Register (PIT_LDVALn).................................................................................................492

Current Timer Value Register (PIT_CVALn)............................................................................................... 492

Timer Control Register (PIT_TCTRLn)........................................................................................................493

Timer Flag Register (PIT_TFLGn)................................................................................................................494

Chapter 31

Low-Power Timer (LPTMR)

31.1 Chip-specific LPTMR information...............................................................................................................................501

31.1.1 LPTMR instantiation information..................................................................................................................501

31.1.2 LPTMR pulse counter input options..............................................................................................................501

31.1.3 LPTMR prescaler/glitch filter clocking options............................................................................................ 501

31.2 Introduction...................................................................................................................................................................502

31.2.1 Features.......................................................................................................................................................... 502

31.2.2 Modes of operation........................................................................................................................................ 503

31.3 LPTMR signal descriptions.......................................................................................................................................... 503

31.3.1 Detailed signal descriptions........................................................................................................................... 503

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31.4 Memory map and register definition.............................................................................................................................504

31.4.1

31.4.2

31.4.3

31.4.4

31.5 Functional description...................................................................................................................................................508

31.5.1 LPTMR power and reset................................................................................................................................508

31.5.2 LPTMR clocking............................................................................................................................................508

31.5.3 LPTMR prescaler/glitch filter........................................................................................................................509

31.5.4 LPTMR compare............................................................................................................................................510

31.5.5 LPTMR counter............................................................................................................................................. 510

31.5.6 LPTMR hardware trigger...............................................................................................................................511

31.5.7 LPTMR interrupt............................................................................................................................................511

Low Power Timer Control Status Register (LPTMRx_CSR)........................................................................504

Low Power Timer Prescale Register (LPTMRx_PSR)..................................................................................505

Low Power Timer Compare Register (LPTMRx_CMR)...............................................................................507

Low Power Timer Counter Register (LPTMRx_CNR)................................................................................. 507

Chapter 32

Real Time Clock (RTC)

32.1 Chip-specific RTC information.................................................................................................................................... 513

32.1.1 RTC Instantiation Information.......................................................................................................................513

32.1.2 RTC_CLKOUT options.................................................................................................................................513

32.2 Introduction...................................................................................................................................................................513

32.2.1 Features.......................................................................................................................................................... 513

32.2.2 Modes of operation........................................................................................................................................ 514

32.2.3 RTC signal descriptions.................................................................................................................................514

32.3 Register definition.........................................................................................................................................................514

32.3.1 RTC Time Seconds Register (RTC_TSR).....................................................................................................515

32.3.2 RTC Time Prescaler Register (RTC_TPR)....................................................................................................515

32.3.3 RTC Time Alarm Register (RTC_TAR)....................................................................................................... 516

32.3.4 RTC Time Compensation Register (RTC_TCR)...........................................................................................516

32.3.5 RTC Control Register (RTC_CR)..................................................................................................................518

32.3.6 RTC Status Register (RTC_SR).................................................................................................................... 520

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32.3.7 RTC Lock Register (RTC_LR)......................................................................................................................521

32.3.8 RTC Interrupt Enable Register (RTC_IER)...................................................................................................522

32.4 Functional description...................................................................................................................................................523

32.4.1 Power, clocking, and reset............................................................................................................................. 523

32.4.2 Time counter.................................................................................................................................................. 524

32.4.3 Compensation.................................................................................................................................................524

32.4.4 Time alarm..................................................................................................................................................... 525

32.4.5 Update mode.................................................................................................................................................. 525

32.4.6 Register lock.................................................................................................................................................. 526

32.4.7 Interrupt..........................................................................................................................................................526

Chapter 33

Universal Serial Bus (USB) FS Subsystem

33.1 Chip-specific USBFS information................................................................................................................................527

33.1.1 Universal Serial Bus (USB) FS Subsystem................................................................................................... 527

33.1.2 USB Wakeup..................................................................................................................................................527

33.1.3 USB Power Distribution................................................................................................................................ 528

33.1.4 USB power management............................................................................................................................... 530

33.2 Introduction...................................................................................................................................................................530

33.2.1 References......................................................................................................................................................530

33.2.2 USB................................................................................................................................................................531

33.2.3 USBFS Features.............................................................................................................................................532

33.3 Functional description...................................................................................................................................................532

33.3.1 Data Structures...............................................................................................................................................532

33.3.2 On-chip transceiver required external components........................................................................................532

33.4 Programmers interface..................................................................................................................................................534

33.4.1 Buffer Descriptor Table................................................................................................................................. 534

33.4.2 USB data transfers—Receive (Rx) and Transmit (Tx)..................................................................................535

33.4.3 Addressing BDT entries.................................................................................................................................536

33.4.4 Buffer Descriptors (BDs)...............................................................................................................................536

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33.4.5 USB transaction............................................................................................................................................. 539

33.5 Memory map/Register definitions................................................................................................................................ 541

33.5.1

33.5.2

33.5.3

33.5.4

33.5.5

33.5.6

33.5.7

33.5.8

33.5.9

33.5.10

33.5.11

33.5.12

33.5.13

33.5.14

Peripheral ID register (USBx_PERID).......................................................................................................... 543

Peripheral ID Complement register (USBx_IDCOMP).................................................................................543

Peripheral Revision register (USBx_REV)....................................................................................................544

Peripheral Additional Info register (USBx_ADDINFO)............................................................................... 544

Interrupt Status register (USBx_ISTAT)....................................................................................................... 545

Interrupt Enable register (USBx_INTEN)..................................................................................................... 546

Error Interrupt Status register (USBx_ERRSTAT)....................................................................................... 547

Error Interrupt Enable register (USBx_ERREN)...........................................................................................548

Status register (USBx_STAT)........................................................................................................................549

Control register (USBx_CTL)........................................................................................................................550

Address register (USBx_ADDR)...................................................................................................................551

BDT Page register 1 (USBx_BDTPAGE1)................................................................................................... 551

Frame Number register Low (USBx_FRMNUML).......................................................................................552

Frame Number register High (USBx_FRMNUMH)..................................................................................... 552

33.5.15

33.5.16

33.5.17

33.5.18

33.5.19

33.5.20

33.5.21

33.5.22

33.5.23

33.5.24

33.5.25

33.5.26

33.6 Device mode IRC48 operation......................................................................................................................................561

BDT Page Register 2 (USBx_BDTPAGE2)..................................................................................................553

BDT Page Register 3 (USBx_BDTPAGE3)..................................................................................................553

Endpoint Control register (USBx_ENDPTn).................................................................................................554

USB Control register (USBx_USBCTRL).................................................................................................... 555

USB OTG Observe register (USBx_OBSERVE)..........................................................................................555

USB OTG Control register (USBx_CONTROL).......................................................................................... 556

USB Transceiver Control register 0 (USBx_USBTRC0)..............................................................................557

Frame Adjust Register (USBx_USBFRMADJUST)..................................................................................... 558

USB Clock recovery control (USBx_CLK_RECOVER_CTRL)..................................................................558

IRC48M oscillator enable register (USBx_CLK_RECOVER_IRC_EN)..................................................... 559

Clock recovery combined interrupt enable (USBx_CLK_RECOVER_INT_EN)........................................ 560

Clock recovery separated interrupt status (USBx_CLK_RECOVER_INT_STATUS)................................ 561

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Chapter 34

USB Voltage Regulator (VREG)

34.1 Introduction...................................................................................................................................................................563

34.1.1 Overview........................................................................................................................................................563

34.1.2 Features.......................................................................................................................................................... 564

34.1.3 Modes of Operation....................................................................................................................................... 565

34.2 USB Voltage Regulator Module Signal Descriptions.................................................................................................. 565

Chapter 35

Serial Peripheral Interface (SPI)

35.1 Chip-specific SPI information...................................................................................................................................... 567

35.2 Introduction...................................................................................................................................................................567

35.2.1 Features.......................................................................................................................................................... 568

35.2.2 Modes of operation........................................................................................................................................ 568

35.2.3 Block diagrams.............................................................................................................................................. 569

35.3 External signal description............................................................................................................................................572

35.3.1 SPSCK — SPI Serial Clock...........................................................................................................................573

35.3.2 MOSI — Master Data Out, Slave Data In..................................................................................................... 573

35.3.3 MISO — Master Data In, Slave Data Out..................................................................................................... 573

35.3.4 SS — Slave Select..........................................................................................................................................573

35.4 Memory map/register definition...................................................................................................................................574

35.4.1

35.4.2

35.4.3

35.4.4

35.4.5

35.4.6

35.4.7

SPI Status Register (SPIx_S)......................................................................................................................... 574

SPI Baud Rate Register (SPIx_BR)............................................................................................................... 578

SPI Control Register 2 (SPIx_C2)................................................................................................................. 579

SPI Control Register 1 (SPIx_C1)................................................................................................................. 581

SPI Match Register low (SPIx_ML).............................................................................................................. 582

SPI match register high (SPIx_MH).............................................................................................................. 583

SPI Data Register low (SPIx_DL)................................................................................................................. 583

35.4.8

35.4.9

26 Freescale Semiconductor, Inc.

SPI data register high (SPIx_DH).................................................................................................................. 584

SPI clear interrupt register (SPIx_CI)............................................................................................................ 585

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35.4.10

35.5 Functional description...................................................................................................................................................588

35.5.1 General...........................................................................................................................................................588

35.5.2 Master mode...................................................................................................................................................588

35.5.3 Slave mode.....................................................................................................................................................590

35.5.4 SPI FIFO Mode..............................................................................................................................................591

35.5.5 SPI Transmission by DMA............................................................................................................................592

35.5.6 Data Transmission Length............................................................................................................................. 594

35.5.7 SPI clock formats...........................................................................................................................................595

35.5.8 SPI baud rate generation................................................................................................................................ 598

35.5.9 Special features.............................................................................................................................................. 598

35.5.10 Error conditions..............................................................................................................................................600

35.5.11 Low-power mode options.............................................................................................................................. 601

35.5.12 Reset...............................................................................................................................................................602

SPI control register 3 (SPIx_C3)....................................................................................................................586

35.5.13 Interrupts........................................................................................................................................................ 603

35.6 Initialization/application information........................................................................................................................... 605

35.6.1 Initialization sequence....................................................................................................................................605

35.6.2 Pseudo-Code Example................................................................................................................................... 606

Chapter 36

Inter-Integrated Circuit (I2C)

36.1 Chip-specific I2C information......................................................................................................................................611

36.1.1 I2C instantiation information.........................................................................................................................611

36.2 Introduction...................................................................................................................................................................611

36.2.1 Features.......................................................................................................................................................... 612

36.2.2 Modes of operation........................................................................................................................................ 612

36.2.3 Block diagram................................................................................................................................................613

36.3 I2C signal descriptions..................................................................................................................................................613

36.4 Memory map/register definition...................................................................................................................................614

36.4.1

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I2C Address Register 1 (I2Cx_A1)................................................................................................................615

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36.4.2

36.4.3

36.4.4

36.4.5

36.4.6

36.4.7

36.4.8

36.4.9

36.4.10

36.4.11

36.4.12

36.4.13

36.5 Functional description...................................................................................................................................................627

36.5.1 I2C protocol................................................................................................................................................... 627

I2C Frequency Divider register (I2Cx_F)......................................................................................................615

I2C Control Register 1 (I2Cx_C1).................................................................................................................616

I2C Status register (I2Cx_S).......................................................................................................................... 618

I2C Data I/O register (I2Cx_D)..................................................................................................................... 620

I2C Control Register 2 (I2Cx_C2).................................................................................................................620

I2C Programmable Input Glitch Filter Register (I2Cx_FLT)........................................................................ 621

I2C Range Address register (I2Cx_RA)........................................................................................................ 623

I2C SMBus Control and Status register (I2Cx_SMB)...................................................................................623

I2C Address Register 2 (I2Cx_A2)................................................................................................................625

I2C SCL Low Timeout Register High (I2Cx_SLTH)....................................................................................625

I2C SCL Low Timeout Register Low (I2Cx_SLTL).....................................................................................626

I2C Status register 2 (I2Cx_S2)..................................................................................................................... 626

36.5.2 10-bit address................................................................................................................................................. 632

36.5.3 Address matching...........................................................................................................................................634

36.5.4 System management bus specification.......................................................................................................... 635

36.5.5 Resets............................................................................................................................................................. 637

36.5.6 Interrupts........................................................................................................................................................ 637

36.5.7 Programmable input glitch filter....................................................................................................................640

36.5.8 Address matching wake-up............................................................................................................................640

36.5.9 DMA support................................................................................................................................................. 641

36.5.10 Double buffering mode.................................................................................................................................. 642

36.6 Initialization/application information........................................................................................................................... 643

Chapter 37

Low Power Universal asynchronous receiver/transmitter (LPUART)

37.1 Chip-specific LPUART information.............................................................................................................................647

37.1.1 LPUART0 and LPUART1 overview.............................................................................................................647

37.2 Introduction...................................................................................................................................................................647

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37.2.1 Features.......................................................................................................................................................... 647

37.2.2 Modes of operation........................................................................................................................................ 648

37.2.3 Signal Descriptions........................................................................................................................................ 649

37.2.4 Block diagram................................................................................................................................................649

37.3 Register definition.........................................................................................................................................................651

37.3.1

37.3.2

37.3.3

37.3.4

37.3.5

37.4 Functional description...................................................................................................................................................665

37.4.1 Baud rate generation...................................................................................................................................... 665

37.4.2 Transmitter functional description.................................................................................................................666

37.4.3 Receiver functional description..................................................................................................................... 668

37.4.4 Additional LPUART functions...................................................................................................................... 673

37.4.5 Interrupts and status flags.............................................................................................................................. 675

LPUART Baud Rate Register (LPUARTx_BAUD)......................................................................................652

LPUART Status Register (LPUARTx_STAT)..............................................................................................654

LPUART Control Register (LPUARTx_CTRL)........................................................................................... 658

LPUART Data Register (LPUARTx_DATA)............................................................................................... 663

LPUART Match Address Register (LPUARTx_MATCH)...........................................................................665

Chapter 38

Universal Asynchronous Receiver/Transmitter(UART)

38.1 Chip-specific UART information.................................................................................................................................677

38.1.1 UART2 Overview..........................................................................................................................................677

38.2 Introduction...................................................................................................................................................................677

38.2.1 Features.......................................................................................................................................................... 677

38.2.2 Modes of operation........................................................................................................................................ 679

38.3 UART signal descriptions.............................................................................................................................................680

38.3.1 Detailed signal descriptions........................................................................................................................... 680

38.4 Memory map and registers............................................................................................................................................680

38.4.1

38.4.2

38.4.3

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UART Baud Rate Registers: High (UARTx_BDH)...................................................................................... 682

UART Baud Rate Registers: Low (UARTx_BDL)....................................................................................... 683

UART Control Register 1 (UARTx_C1)....................................................................................................... 683

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38.4.4

38.4.5

38.4.6

38.4.7

38.4.8

38.4.9

38.4.10

38.4.11

38.4.12

38.4.13

38.4.14

38.4.15

38.4.16

38.4.17

UART Control Register 2 (UARTx_C2)....................................................................................................... 685

UART Status Register 1 (UARTx_S1).......................................................................................................... 687

UART Status Register 2 (UARTx_S2).......................................................................................................... 689

UART Control Register 3 (UARTx_C3)....................................................................................................... 691

UART Data Register (UARTx_D).................................................................................................................692

UART Match Address Registers 1 (UARTx_MA1)......................................................................................693

UART Match Address Registers 2 (UARTx_MA2)......................................................................................694

UART Control Register 4 (UARTx_C4)....................................................................................................... 694

UART Control Register 5 (UARTx_C5)....................................................................................................... 695

UART 7816 Control Register (UARTx_C7816)........................................................................................... 696

UART 7816 Interrupt Enable Register (UARTx_IE7816)............................................................................ 697

UART 7816 Interrupt Status Register (UARTx_IS7816)..............................................................................699

UART 7816 Wait Parameter Register (UARTx_WP7816)........................................................................... 701

UART 7816 Wait N Register (UARTx_WN7816)........................................................................................701

38.4.18

38.4.19

38.4.20

38.4.21

38.4.22

38.4.23

38.4.24

38.4.25

38.4.26

38.4.27

38.4.28

38.5 Functional description...................................................................................................................................................708

38.5.1 Transmitter.....................................................................................................................................................708

38.5.2 Receiver......................................................................................................................................................... 712

UART 7816 Wait FD Register (UARTx_WF7816)...................................................................................... 702

UART 7816 Error Threshold Register (UARTx_ET7816)............................................................................702

UART 7816 Transmit Length Register (UARTx_TL7816).......................................................................... 703

UART 7816 ATR Duration Timer Register A (UARTx_AP7816A_T0)......................................................703

UART 7816 ATR Duration Timer Register B (UARTx_AP7816B_T0)...................................................... 704

UART 7816 Wait Parameter Register A (UARTx_WP7816A_T0)..............................................................705

UART 7816 Wait Parameter Register A (UARTx_WP7816A_T1)..............................................................705

UART 7816 Wait Parameter Register B (UARTx_WP7816B_T0).............................................................. 706

UART 7816 Wait Parameter Register B (UARTx_WP7816B_T1).............................................................. 706

UART 7816 Wait and Guard Parameter Register (UARTx_WGP7816_T1)................................................707

UART 7816 Wait Parameter Register C (UARTx_WP7816C_T1).............................................................. 707

38.5.3 Baud rate generation...................................................................................................................................... 724

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Section number Title Page

38.5.4 Data format (non ISO-7816)..........................................................................................................................726

38.5.5 Single-wire operation.....................................................................................................................................729

38.5.6 Loop operation............................................................................................................................................... 729

38.5.7 ISO-7816/smartcard support..........................................................................................................................730

38.6 Reset..............................................................................................................................................................................735

38.7 System level interrupt sources......................................................................................................................................735

38.7.1 RXEDGIF description....................................................................................................................................736

38.8 DMA operation.............................................................................................................................................................737

38.9 Application information................................................................................................................................................738

38.9.1 ISO-7816 initialization sequence...................................................................................................................738

38.9.2 Initialization sequence (non ISO-7816)......................................................................................................... 739

38.9.3 Overrun (OR) flag implications..................................................................................................................... 740

38.9.4 Overrun NACK considerations......................................................................................................................741

38.9.5 Match address registers..................................................................................................................................742

38.9.6 Clearing 7816 wait timer (WT, BWT, CWT) interrupts................................................................................742

38.9.7 Legacy and reverse compatibility considerations.......................................................................................... 742

Chapter 39

FlexIO

39.1 Chip-specific FlexIO information.................................................................................................................................745

39.1.1 FlexIO Instantiation....................................................................................................................................... 745

39.1.2 FlexIO Trigger options...................................................................................................................................745

39.2 Introduction...................................................................................................................................................................746

39.2.1 Overview........................................................................................................................................................746

39.2.2 Features.......................................................................................................................................................... 746

39.2.3 Block Diagram............................................................................................................................................... 747

39.2.4 Modes of operation........................................................................................................................................ 747

39.2.5 FlexIO Signal Descriptions............................................................................................................................748

39.3 Memory Map and Registers..........................................................................................................................................748

39.3.1 Version ID Register (FLEXIO_VERID)....................................................................................................... 750

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Freescale Semiconductor, Inc. 31

Section number Title Page

39.3.2 Parameter Register (FLEXIO_PARAM).......................................................................................................751

39.3.3 FlexIO Control Register (FLEXIO_CTRL)...................................................................................................752

39.3.4 Shifter Status Register (FLEXIO_SHIFTSTAT)...........................................................................................753

39.3.5 Shifter Error Register (FLEXIO_SHIFTERR).............................................................................................. 754

39.3.6 Timer Status Register (FLEXIO_TIMSTAT)................................................................................................754

39.3.7 Shifter Status Interrupt Enable (FLEXIO_SHIFTSIEN)...............................................................................755

39.3.8 Shifter Error Interrupt Enable (FLEXIO_SHIFTEIEN)................................................................................ 756

39.3.9 Timer Interrupt Enable Register (FLEXIO_TIMIEN)...................................................................................756

39.3.10 Shifter Status DMA Enable (FLEXIO_SHIFTSDEN).................................................................................. 757

39.3.11

39.3.12

39.3.13

39.3.14

39.3.15

39.3.16

39.3.17

39.3.18

39.3.19

39.4 Functional description...................................................................................................................................................767

39.4.1 Shifter operation.............................................................................................................................................767

39.4.2 Timer operation..............................................................................................................................................769

39.4.3 Pin operation.................................................................................................................................................. 771

39.5 Application Information................................................................................................................................................772

Shifter Control N Register (FLEXIO_SHIFTCTLn).....................................................................................757

Shifter Configuration N Register (FLEXIO_SHIFTCFGn).......................................................................... 759

Shifter Buffer N Register (FLEXIO_SHIFTBUFn)...................................................................................... 760

Shifter Buffer N Bit Swapped Register (FLEXIO_SHIFTBUFBISn)...........................................................761

Shifter Buffer N Byte Swapped Register (FLEXIO_SHIFTBUFBYSn)...................................................... 761

Shifter Buffer N Bit Byte Swapped Register (FLEXIO_SHIFTBUFBBSn).................................................762

Timer Control N Register (FLEXIO_TIMCTLn)..........................................................................................762

Timer Configuration N Register (FLEXIO_TIMCFGn)............................................................................... 764

Timer Compare N Register (FLEXIO_TIMCMPn)...................................................................................... 766

39.5.1 UART Transmit............................................................................................................................................. 772

39.5.2 UART Receive...............................................................................................................................................773

39.5.3 SPI Master......................................................................................................................................................775

39.5.4 SPI Slave........................................................................................................................................................777

39.5.5 I2C Master......................................................................................................................................................779

39.5.6 I2S Master......................................................................................................................................................781

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32 Freescale Semiconductor, Inc.

Section number Title Page

39.5.7 I2S Slave........................................................................................................................................................ 782

Chapter 40

Synchronous Audio Interface (SAI)

40.1 Chip-specific I2S information.......................................................................................................................................785

40.1.1 Instantiation information................................................................................................................................785

40.1.2 I2S Interrupts..................................................................................................................................................785

40.1.3 I2S/SAI clocking............................................................................................................................................785

40.1.4 I2S/SAI operation in low power modes.........................................................................................................787

40.2 Introduction...................................................................................................................................................................788

40.2.1 Features.......................................................................................................................................................... 788

40.2.2 Block diagram................................................................................................................................................789

40.2.3 Modes of operation........................................................................................................................................ 789

40.3 External signals.............................................................................................................................................................790

40.4 Memory map and register definition.............................................................................................................................791

40.4.1

40.4.2

40.4.3

40.4.4

40.4.5

40.4.6

40.4.7

40.4.8

40.4.9

40.4.10

40.4.11

40.4.12

40.4.13

SAI Transmit Control Register (I2Sx_TCSR)............................................................................................... 792

SAI Transmit Configuration 2 Register (I2Sx_TCR2).................................................................................. 795

SAI Transmit Configuration 3 Register (I2Sx_TCR3).................................................................................. 796

SAI Transmit Configuration 4 Register (I2Sx_TCR4).................................................................................. 797

SAI Transmit Configuration 5 Register (I2Sx_TCR5).................................................................................. 799

SAI Transmit Data Register (I2Sx_TDRn)....................................................................................................800

SAI Transmit Mask Register (I2Sx_TMR)....................................................................................................800

SAI Receive Control Register (I2Sx_RCSR).................................................................................................801

SAI Receive Configuration 2 Register (I2Sx_RCR2)....................................................................................804

SAI Receive Configuration 3 Register (I2Sx_RCR3)....................................................................................806

SAI Receive Configuration 4 Register (I2Sx_RCR4)....................................................................................807

SAI Receive Configuration 5 Register (I2Sx_RCR5)....................................................................................809

SAI Receive Data Register (I2Sx_RDRn)..................................................................................................... 809

40.4.14

40.4.15

Freescale Semiconductor, Inc. 33

SAI Receive Mask Register (I2Sx_RMR)..................................................................................................... 810

SAI MCLK Control Register (I2Sx_MCR)................................................................................................... 811

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Section number Title Page

40.5 Functional description...................................................................................................................................................812

40.5.1 SAI clocking.................................................................................................................................................. 812

40.5.2 SAI resets....................................................................................................................................................... 814

40.5.3 Synchronous modes....................................................................................................................................... 815

40.5.4 Frame sync configuration...............................................................................................................................815

40.5.5 Data FIFO...................................................................................................................................................... 816

40.5.6 Word mask register........................................................................................................................................ 819

40.5.7 Interrupts and DMA requests.........................................................................................................................819

Chapter 41

General-Purpose Input/Output (GPIO)

41.1 Chip-specific GPIO information...................................................................................................................................821

41.1.1 GPIO instantiation information......................................................................................................................821

41.1.2 GPIO accessibility in the memory map......................................................................................................... 821

41.2 Introduction...................................................................................................................................................................822

41.2.1 Features.......................................................................................................................................................... 822

41.2.2 Modes of operation........................................................................................................................................ 822

41.2.3 GPIO signal descriptions............................................................................................................................... 822

41.3 Memory map and register definition.............................................................................................................................824

41.3.1

41.3.2

41.3.3

41.3.4

41.3.5

41.3.6

41.4 Functional description...................................................................................................................................................828

41.4.1 General-purpose input....................................................................................................................................828

41.4.2 General-purpose output..................................................................................................................................828

Port Data Output Register (GPIOx_PDOR)...................................................................................................825

Port Set Output Register (GPIOx_PSOR)......................................................................................................826

Port Clear Output Register (GPIOx_PCOR)..................................................................................................826

Port Toggle Output Register (GPIOx_PTOR)............................................................................................... 827

Port Data Input Register (GPIOx_PDIR).......................................................................................................827

Port Data Direction Register (GPIOx_PDDR)...............................................................................................828

Chapter 42

Bit Manipulation Engine (BME)

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34 Freescale Semiconductor, Inc.

Section number Title Page

42.1 Introduction...................................................................................................................................................................831

42.1.1 Overview........................................................................................................................................................832

42.1.2 Features.......................................................................................................................................................... 832

42.1.3 Modes of operation........................................................................................................................................ 833

42.2 Memory map and register definition.............................................................................................................................833

42.3 Functional description...................................................................................................................................................833

42.3.1 BME decorated stores.................................................................................................................................... 834

42.3.2 BME decorated loads.....................................................................................................................................841

42.3.3 Additional details on decorated addresses and GPIO accesses......................................................................847

42.4 Application information................................................................................................................................................848

Chapter 43

Micro Trace Buffer (MTB)

43.1 Introduction...................................................................................................................................................................851

43.1.1 Overview........................................................................................................................................................851

43.1.2 Features.......................................................................................................................................................... 854

43.1.3 Modes of operation........................................................................................................................................ 855

43.2 External signal description............................................................................................................................................855

43.3 Memory map and register definition.............................................................................................................................856

43.3.1 MTB_RAM Memory Map.............................................................................................................................856

43.3.2 MTB_DWT Memory Map.............................................................................................................................868

43.3.3 System ROM Memory Map...........................................................................................................................878

Chapter 44

Flash Memory Controller (FMC)

44.1 Introduction...................................................................................................................................................................883

44.1.1 Overview........................................................................................................................................................883

44.1.2 Features.......................................................................................................................................................... 883

44.2 Modes of operation.......................................................................................................................................................884

44.3 External signal description............................................................................................................................................884

44.4 Memory map and register descriptions.........................................................................................................................884

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Section number Title Page

44.5 Functional description...................................................................................................................................................884

Chapter 45

Flash Memory Module (FTFA)

45.1 Introduction...................................................................................................................................................................887

45.1.1 Features.......................................................................................................................................................... 887

45.1.2 Block Diagram............................................................................................................................................... 888

45.1.3 Glossary......................................................................................................................................................... 889

45.2 External Signal Description..........................................................................................................................................890

45.3 Memory Map and Registers..........................................................................................................................................890

45.3.1 Flash Configuration Field Description...........................................................................................................891

45.3.2 Program Flash IFR Map.................................................................................................................................891

45.3.3 Register Descriptions..................................................................................................................................... 892

45.4 Functional Description..................................................................................................................................................901

45.4.1 Flash Protection..............................................................................................................................................901

45.4.2 Interrupts........................................................................................................................................................ 902

45.4.3 Flash Operation in Low-Power Modes.......................................................................................................... 903

45.4.4 Functional Modes of Operation..................................................................................................................... 903

45.4.5 Flash Reads and Ignored Writes.................................................................................................................... 903

45.4.6 Read While Write (RWW).............................................................................................................................904

45.4.7 Flash Program and Erase................................................................................................................................904

45.4.8 Flash Command Operations...........................................................................................................................904

45.4.9 Margin Read Commands............................................................................................................................... 910

45.4.10 Flash Command Description..........................................................................................................................911

45.4.11 Security.......................................................................................................................................................... 927

45.4.12 Reset Sequence.............................................................................................................................................. 929

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Chapter 1
About This Document

1.1 Overview

1.1.1 Purpose

This document describes the features, architecture, and programming model of the
Freescale KL27 microcontroller.

1.1.2 Audience

A reference manual is primarily for system architects and software application developers
who are using or considering using a Freescale product in a system.

1.2 Conventions

1.2.1 Numbering systems

The following suffixes identify different numbering systems:

This suffix Identifies a

b Binary number. For example, the binary equivalent of the

number 5 is written 101b. In some cases, binary numbers are
shown with the prefix 0b.

d Decimal number. Decimal numbers are followed by this suffix

only when the possibility of confusion exists. In general,
decimal numbers are shown without a suffix.

h Hexadecimal number. For example, the hexadecimal

equivalent of the number 60 is written 3Ch. In some cases,
hexadecimal numbers are shown with the prefix 0x.

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Freescale Semiconductor, Inc. 37

Conventions

1.2.2 Typographic notation

The following typographic notation is used throughout this document:

Example Description

placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for

the titles of publications and for emphasis. Plain lowercase letters are also used as
placeholders for single letters and numbers.

code

SR[SCM] A mnemonic in brackets represents a named field in a register. This example refers to the

REVNO[6:4], XAD[7:0] Numbers in brackets and separated by a colon represent either:

Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction
mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type
is also used for example code. Instruction mnemonics and directives in text and tables are
shown in all caps; for example, BSR.

Scaling Mode (SCM) field in the Status Register (SR).

• A subset of a register's named field
For example, REVNO[6:4] refers to bits 6–4 that are part of the COREREV field that

occupies bits 6–0 of the REVNO register.

• A continuous range of individual signals of a bus
For example, XAD[7:0] refers to signals 7–0 of the XAD bus.

1.2.3 Special terms

The following terms have special meanings:

Term Meaning

asserted Refers to the state of a signal as follows:

• An active-high signal is asserted when high (1).

• An active-low signal is asserted when low (0).

deasserted Refers to the state of a signal as follows:

• An active-high signal is deasserted when low (0).
An active-low signal is deasserted when high (1).

•

In some cases, deasserted signals are described as negated.

reserved Refers to a memory space, register, or field that is either

reserved for future use or for which, when written to, the
module or chip behavior is unpredictable.

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Chapter 2
Introduction

2.1 Overview

Information found here provides an overview of the Kinetis L series of ARM® Cortex®­M0+ MCUs and KL27 product family. It also presents high-level descriptions of the
modules available on the devices covered by this document.

2.1.1 Sub-family introduction

The device is highly-integrated, market leading ultra low-power 32-bit microcontroller
based on the enhanced Cortex-M0+ (CM0+) core platform. The features of the family
derivatives are as follows.

• Core platform clock up to 48 MHz, bus clock up to 24 MHz

• Memory option is up to 256 KB flash and 32 KB RAM

• Wide operating voltage ranges from 1.71–3.6 V with fully functional flash program/
erase/read operations

• Multiple package options from 32-pin to 64-pin

• Ambient operating temperature ranges from –40 °C to 105 °C.

The family acts as an ultra low-power, cost-effective microcontroller to provide
developers an appropriate entry-level 32-bit solution. The family is the next-generation
MCU solution for low-cost, low-power, high-performance devices applications. It’s
valuable for cost-sensitive, portable applications requiring long battery life-time.

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Freescale Semiconductor, Inc. 39

Module functional categories

2.2 Module functional categories

The modules on this device are grouped into functional categories. Information found
here describes the modules assigned to each category in more detail.

Table 2-1. Module functional categories

Module category Description

ARM Cortex-M0+ core • 32-bit MCU core from ARM’s Cortex-M class, 1.77 CoreMark®/MHz from

single-cycle access memories, 48 MHz CPU frequency

System • System integration module

• Power management and mode controllers

• Multiple power modes available based on run, wait, stop, and power­down modes

• Miscellaneous control module

• Low-leakage wakeup unit

• Peripheral bridge

• Direct memory access (DMA) controller with multiplexer to increase available
DMA requests

• COP watchdog

Memories • Internal memories include:

• Up to 256 KB flash memory

• Up to 32 KB SRAM

• Up to 16 KB ROM

Clocks • Multiple clock generation options available from internally- and externally-

generated clocks

• MCG-Lite with 48MIRC and 8M/2M IRC for systems and CPU clock
sources.

• Low power 1 kHz RC oscillator for RTC and COP watchdog

• System oscillator to provide clock source for the MCU

Security • COP watchdog timer (COP)
Analog • 16-bit analog-to-digital converters with DMA supported and four muxed

differential pairs

• Comparator (CMP) with internal 6-bit digital-to-analog converter (DAC)

• 12-bit DAC with DMA support and two 16-bit data buffer

• High accuracy 1.2 V voltage reference to provide a stable reference for ADC

Timers • One 6-channel TPM

• Two 2-channel TPMs

• 2-channel periodic interrupt timer

• Real time clock

• Low-power timer

• System tick timer

Communications • Two 16-bit serial peripheral interface

• USB controller with built-in FS transceiver

• USB voltage regulator

• Two inter-integrated circuit (I2C) modules

• Two low power UART modules and one UART module

• One FlexIO

Human-Machine Interfaces (HMI) • General purpose input/output controller

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Chapter 2 Introduction

2.2.1 ARM Cortex-M0+ core modules

The following core modules are available on this device.

Table 2-2. Core modules

Module Description

ARM Cortex-M0+ The ARM Cortex-M0+ is the newest member of the Cortex M Series of processors

targeting microcontroller applications focused on very cost sensitive, deterministic,
interrupt driven environments. The Cortex M0+ processor is based on the ARMv6
Architecture and Thumb®-2 ISA and is 100% instruction set compatible with its
predecessor, the Cortex-M0 core, and upward compatible to Cortex-M3 and M4
cores.

NVIC The ARMv6-M exception model and nested-vectored interrupt controller (NVIC)

implement a relocatable vector table supporting many external interrupts, a single
non-maskable interrupt (NMI), and priority levels.

The NVIC replaces shadow registers with equivalent system and simplified
programmability. The NVIC contains the address of the function to execute for a
particular handler. The address is fetched via the instruction port allowing parallel
register stacking and look-up. The first sixteen entries are allocated to ARM
internal sources with the others mapping to MCU-defined interrupts.

AWIC The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is

to detect asynchronous wake-up events in stop modes and signal to clock control
logic to resume system clocking. After clock restart, the NVIC observes the
pending interrupt and performs the normal interrupt or event processing.

Single-cycle I/O Port For high-speed, single-cycle access to peripherals, the Cortex-M0+ processor

implements a dedicated single-cycle I/O port.

Debug interfaces Most of this device's debug is based on the ARM CoreSight™ architecture. One

debug interface is supported:

• Serial Wire Debug (SWD)

2.2.2 System modules

The following system modules are available on this device.

Table 2-3. System modules

Module Description

System integration module (SIM) The SIM includes integration logic and several module configuration settings.
System mode controller (SMC) The SMC provides control and protection on entry and exit to each power mode,

control for the power management controller (PMC), and reset entry and exit for
the complete MCU.

Power management controller (PMC) The PMC provides the user with multiple power options. Multiple modes are

supported that allow the user to optimize power consumption for the level of
functionality needed. Includes power-on-reset (POR) and integrated low voltage
detect (LVD) with reset (brownout) capability and selectable LVD trip points.

Table continues on the next page...

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Module functional categories

Table 2-3. System modules (continued)

Module Description

Miscellaneous control module (MCM) The MCM includes integration logic and details.
Crossbar switch lite (AXBS-Lite) The AXBS connects bus masters and bus slaves, allowing all bus masters to

access different bus slaves simultaneously and providing arbitration among the bus
masters when they access the same slave.

Low-leakage wakeup unit (LLWU) The LLWU module allows the device to wake from low leakage power modes (LLS

and VLLS) through various internal peripheral and external pin sources.

Peripheral bridge (AIPS-Lite) The peripheral bridge converts the crossbar switch interface to an interface to

access a majority of peripherals on the device.

DMA multiplexer (DMAMUX) The DMA multiplexer selects from many DMA requests down to 4 for the DMA

controller.

Direct memory access (DMA) controller The DMA controller provides programmable channels with transfer control

descriptors for data movement via dual-address transfers for 8-, 16- and 32-bit
data values.

Computer operating properly watchdog
(WDOG)

The WDOG monitors internal system operation and forces a reset in case of
failure. It can run from an independent 1 kHz low power oscillator, 8/2 MHz internal
oscillator or external crystal oscillator with a programmable refresh window to
detect deviations in program flow or system frequency.

2.2.3 Memories and memory interfaces

The following memories and memory interfaces are available on this device.

Table 2-4. Memories and memory interfaces

Module Description

Flash memory Program flash memory — up to 256 KB of the non-volatile flash memory that can

execute program code.

Flash memory controller Manages the interface between the device and the on-chip flash memory.
SRAM Up to 32 KB internal system RAM.
ROM 16 KB ROM.

2.2.4 Clocks

The following clock modules are available on this device.

Table 2-5. Clock modules

Module Description

Multipurpose Clock Generator Lite
(MCG-Lite)

System oscillator (OSC) The system oscillator, in conjunction with an external crystal or resonator,

MCG Lite module containing a 48 MHz and an 8 or 2 MHz internal reference clock

source.

generates a reference clock for the MCU.

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Chapter 2 Introduction

2.2.5 Security and integrity modules

The following security and integrity modules are available on this device:

Table 2-6. Security and integrity modules

Module Description

Watchdog timer (WDOG) Watchdog timer keeps a watch on the system functioning and resets it in case of

its failure.

2.2.6 Analog modules

The following analog modules are available on this device:

Table 2-7. Analog modules

Module Description

Analog-to-digital converters (ADC) 16-bit successive-approximation ADC module.
Analog comparators One comparator that compares two analog input voltages across the full range of

the supply voltage and can trigger an ADC acquisition, TPM update, or CPU

interrupt.

6-bit digital-to-analog converters (DAC) 64-tap resistor ladder network which provides a selectable voltage reference for

comparator.

Voltage reference (VREF) Supplies an accurate voltage output that is trimmable in 0.5 mV steps. The VREF

can be used in medical applications, such as glucose meters, to provide a

reference voltage to biosensors or as a reference to analog peripherals, such as

the ADC, DAC, or CMP.

12-bit digital-to-analog converters (DAC) Low-power general-purpose DAC, whose output can be placed on an external pin

or set as one of the inputs to the analog comparator or ADC.

2.2.7 Timer modules

The following timer modules are available on this device:

Table 2-8. Timer modules

Module Description

Timer/PWM module (TPM) • Selectable TPM clock mode

• Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128

• 16-bit free-running counter or modulo counter with counting be up or up­down

• configurable channels for input capture, output compare, edge-aligned PWM
mode, or center-aligned PWM mode

Table continues on the next page...

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Module functional categories

Table 2-8. Timer modules (continued)

Module Description

• Support the generation of an interrupt and/or DMA request per channel

• Support the generation of an interrupt and/or DMA request when the counter
overflows

• Support selectable trigger input to optionally reset or cause the counter to
start incrementing.

• Support the generation of hardware triggers when the counter overflows and
per channel

Periodic interrupt timers (PIT) • One general purpose interrupt timer

• Interrupt timers for triggering ADC conversions

• 32-bit counter resolution

• Clocked by bus clock frequency

• DMA support

Low power timer (LPTMR) • 16-bit time counter or pulse counter with compare

• Configurable clock source for prescaler/glitch filter

• Configurable input source for pulse counter

Real Time Clock (RTC) • 32-bit seconds counter with roll-over protection and 32-bit alarm

• Software selectable clock sources for input to prescaler with programmable
16-bit prescaler

• XOSC 32.678 kHz nominal

• LPO (~1 kHz)

• External RTC_CLKIN

2.2.8 Communication interfaces

The following communication interfaces are available on this device:

Table 2-9. Communication modules

Module Description

USB controller with built-in FS
transceiver

USB voltage regulator Up to 5 V regulator input typically provided by USB VBUS power with 3.3 V

Serial peripheral interface (SPI) Synchronous serial bus for communication to an external device
Inter-integrated circuit (I2C) Allows communication between a number of devices. Also supports the System

Universal asynchronous receiver/
transmitters (UART) and (LPUART)

I2S The I2S is a full-duplex, serial port that allows the chip to communicate with a

FlexIO The FlexIO module is capable of supporting a wide range of protocols including,

Dual-role USB controller that supports a full-speed (FS) device. The module
complies with the USB 2.0 specification.

regulated output that powers on-chip USB subsystem, capable of sourcing 120 mA
to external board components.

Management Bus (SMBus) Specification, version 2.
Two low power UART modules that retains functional in stop modes. One UART

module does not work in stop mode.

variety of serial devices, such as standard codecs, digital signal processors
(DSPs), microprocessors, peripherals, and audio codecs that implement the inter­IC sound bus (I2S) and the Intel® AC97 standards

but not limited to--UART, I2C, SPI, I2S, Camera IF, LCD RGB, PWM / Waveform
generation. The module can remain functional in VLPS mode provided the clock it
is using remains enabled.

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Chapter 2 Introduction

2.2.9 Human-machine interfaces

The following human-machine interfaces (HMI) are available on this device:

Table 2-10. HMI modules

Module Description

General purpose input/output (GPIO) Some general purpose input or output (GPIO) pins are capable of interrupt and

DMA request generation.

2.3 Module to module interconnects

2.3.1 Interconnection overview

The following table lists the module to module interconnections for this device.

Table 2-11. Module-to-module interconnects

Peripheral Signal — to

Peripheral

TPM1 CH0F, CH1F to ADC

(Trigger)

LPTMR Hardware

trigger

TPMx TOF to ADC

PIT CHx TIF0, TIF1 to ADC

RTC ALARM or

SECONDS

to ADC

(Trigger)

(Trigger)

(Trigger)

to ADC

(Trigger)

Use Case Control Comment

ADC

Triggering (A

AND B)

ADC

Triggering (A

or B)
ADC

Triggering (A

or B)
ADC

Triggering (A

or B)
ADC

Triggering (A

or B)

SIM_SOPT7[ADC0ALTTRGEN] = 0 Ch0 is A, and Ch1 is

B, selecting this

ADC trigger is for

supporting A and B

triggering. In Stop
and VLPS modes,
the second trigger

must be set to >10

µs after the first

SIM_SOPT7[ADC0TRGSEL] and
SIM_SOPT7[ADC0PRETRGSEL]
to select A or B

SIM_SOPT7[ADC0TRGSEL],
SIM_SOPT7[ADC0PRETRGSEL]
to select A or B

SIM_SOPT7[ADC0TRGSEL],
SIM_SOPT7[ADC0PRETRGSEL]
to select A or B

SIM_SOPT7[ADC0TRGSEL],
SIM_SOPT7[ADC0PRETRGSEL]
to select A or B

trigger

—

—

—

—

Table continues on the next page...

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Module to module interconnects

Table 2-11. Module-to-module interconnects (continued)

Peripheral Signal — to

Peripheral

EXTRG_IN EXTRG_IN to ADC

(Trigger)

CMP0 CMP0_OUT to ADC

(Trigger)

CMP0 CMP0_OUT to LPTMR_ALT0Count CMP

CMP0 CMP0_OUT to TPM1 CH0 Input capture SIM_SOPT4[TPM1CH0SRC] —
CMP0 CMP0_OUT to TPM2 CH0 Input capture SIM_SOPT4[TPM2CH0SRC] —
CMP0 CMP0_OUT to LPUART0_RXIR interface SIM_SOPT5[LPUART0RXSRC] Uses for IR interface

CMP0 CMP0_OUT to LPUART1_RXIR Interface SIM_SOPT5[LPUART1RXSRC] Uses for IR interface

LPTMR Hardware

trigger

LPTMR Hardware

trigger

TPMx TOF to TPMx TPM Trigger

TPM1 Timebase to TPMx TPM Global

PIT CHx TIF0, TIF1 to TPMx TPM Trigger

RTC ALARM or

SECONDS

EXTRG_IN EXTRG_IN to TPMx TPM Trigger

CMP0 CMP0_OUT to TPMx TPM Trigger

LPUART0 LPUART0_TXto Modulated by

LPUART0 LPUART0_TXto Modulated by

LPUART1 LPUART1_TXto Modulated by

LPUART1 LPUART1_TXto Modulated by

PIT TIF0 to DAC Advance

to CMPx Low power

to TPMx TPM Trigger

to TPMx TPM Trigger

TPM1 CH0

TPM2 CH0

TPM1 CH0

TPM2 CH0

Use Case Control Comment

ADC

Triggering (A

or B)
ADC

Triggering (A

or B)

events

triggering of

the

comparator

input

input

timebase

input

input

input

input

input

LPUART

modulation

LPUART

modulation

LPUART

modulation

LPUART

modulation

DAC FIFO

SIM_SOPT7[ADC0TRGSEL],
SIM_SOPT7[ADC0PRETRGSEL]
to select A or B

SIM_SOPT7[ADC0TRGSEL],
SIM_SOPT7[ADC0PRETRGSEL]
to select A or B

LPTMR_CSR[TPS] —

CMP_CR1[TRIGM] —

TPMx_CONF[TRGSEL] (4-bit field) —

TPMx_CONF[TRGSEL] (4-bit field) —

TPMx_CONF[GTBEEN] —

TPMx_CONF[TRGSEL] (4-bit field) If PIT is triggering

the TPM, the TPM

clock must be faster

TPMx_CONF[TRGSEL] (4-bit field) —

TPMx_CONF[TRGSEL] (4-bit field) —

TPMx_CONF[TRGSEL] (4-bit field) —

SIM_SOPT5[LPUART0TXSRC] Uses for IR interface

SIM_SOPT5[LPUART0TXSRC] Uses for IR interface

SIM_SOPT5[LPUART1TXSRC] Uses for IR interface

SIM_SOPT5[LPUART1TXSRC] Uses for IR interface

DAC HWTRG Select —

—

—

than Bus clock.

Table continues on the next page...

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46 Freescale Semiconductor, Inc.

Chapter 2 Introduction

Table 2-11. Module-to-module interconnects (continued)

Peripheral Signal — to

Peripheral

PIT TIF0 to DMA CH0 DMA HW

PIT TIF1 to DMA CH1 DMA HW

Use Case Control Comment

DMA MUX register option —

Trigger

DMA MUX register option —

Trigger

Table 2-12. Module-to-FlexIO interconnects

Peripheral Signal — to

Peripheral

LPTMR Hardware

trigger

TPMx TOF to FlexIO Trigger input FlexIO_TIMCTLn[TRGSEL] (4-bit

PIT CHx TIF0, TIF1 to FlexIO Trigger input FlexIO_TIMCTLn[TRGSEL] (4-bit

RTC ALARM or

SECONDS

EXTRG_IN EXTRG_IN to FlexIO Trigger input FlexIO_TIMCTLn[TRGSEL] (4-bit

CMP0 CMP0_OUT to FlexIO Trigger input FlexIO_TIMCTLn[TRGSEL] (4-bit

to FlexIO Trigger input FlexIO_TIMCTLn[TRGSEL] (4-bit

to FlexIO Trigger input FlexIO_TIMCTLn[TRGSEL] (4-bit

Use Case Control Comment

field)

field)

field)

field)

field)

field)

—

—

If PIT is triggering

the FlexIO, the

FlexIO clock must be

faster than Bus

clock.

—

—

—

2.3.2 Analog reference options

Several analog blocks have selectable reference voltages as shown in the below table .
These options allow analog peripherals to share or have separate analog references. Care
should be taken when selecting analog references to avoid cross talk noise.

Table 2-13. Analog reference options

Module Reference option Comment/ Reference selection

16-bit SAR ADC 1 - VREFH or 1.2V VREF_OUT

2 - VDDA

3 - Reserved

12-bit DAC 1 - VREFH or 1.2V VREF_OUT

2 - VDDA

CMP with 6-bit DAC Vin1 - VREFH or 1.2V VREF_OUT

Vin2 - VDD

1

1

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Selected by ADCx_SC2[REFSEL]

Selected by DACx_C0[DACRFS] bit

Selected by CMPx_DACCR[VRSEL]

Module to module interconnects

1. Use this option for the best ADC operation.

VREFH pin can be used as filter capacitor pin for high
precision 1.2V VREF_OUT. When 1.2V VREF is enabled,
VREFH is 1.2V VREF_OUT. Also, when 1.2V VREF module
is enabled, adding supply to VREFH pad, which is a dedicated

1.2 VREF_OUT pad, from external is prohibited. If ADC or
DAC needs another reference voltage not equal to 1.2V at same
time, second reference VDDA or VDD is required to be
selected.

NOTE

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48 Freescale Semiconductor, Inc.

Chapter 3
Core Overview

3.1 ARM Cortex-M0+ core introduction

The enhanced ARM Cortex M0+ is the member of the Cortex-M Series of processors
targeting microcontroller cores focused on very cost sensitive, low power applications. It
has a single 32-bit AMBA AHB-Lite interface and includes an NVIC component. It also
has hardware debug functionality including support for simple program trace capability.
The processor supports the ARMv6-M instruction set (Thumb) architecture including all
but three 16-bit Thumb opcodes (52 total) plus seven 32-bit instructions. It is upward
compatible with other Cortex-M profile processors.

3.1.1 Buses, interconnects, and interfaces

The ARM Cortex-M0+ core has two bus interfaces:

• Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to
peripherals and all system memory, which includes flash memory and RAM
Single 32-bit I/O port bus interfacing to the GPIO with 1-cycle loads and stores

•

3.1.2 System tick timer

The CLKSOURCE field in SysTick Control and Status register selects either the core
clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock (when
CLKSOURCE = 0). Because the timing reference is a variable frequency, the TENMS
field in the SysTick Calibration Value Register is always 0.

3.1.3 Debug facilities

This device supports standard ARM 2-pin SWD debug port.

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Nested vectored interrupt controller (NVIC)

3.1.4 Core privilege levels

The core on this device is implemented with both privileged and unprivileged levels. The
ARM documentation uses different terms than this document to distinguish between
privilege levels.

If you see this term... it also means this term...

Privileged Supervisor
Unprivileged or user User

3.2

Nested vectored interrupt controller (NVIC)

3.2.1 Interrupt priority levels

This device supports four priority levels for interrupts. Therefore, in the NVIC, each
source in the IPR registers contains two bits. For example, IPR0 is shown below:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

W

R

IRQ3

0 0 0 0 0 0

IRQ2

0 0 0 0 0 0

IRQ1

0 0 0 0 0 0

IRQ0

0 0 0 0 0 0

3.2.2 Non-maskable interrupt

The non-maskable interrupt request to the NVIC is controlled by the external NMI signal.
The pin the NMI signal is multiplexed on, must be configured for the NMI function to
generate the non-maskable interrupt request.

3.2.3 Interrupt channel assignments

The interrupt vector assignments are defined in the following table.

• Vector number — the value stored on the stack when an interrupt is serviced.

• IRQ number — non-core interrupt source count, which is the vector number minus

16.

The IRQ number is used within ARM's NVIC documentation.

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Chapter 3 Core Overview

NOTE

The NVIC wake-up sources in the following table support only
down to VLPS.

Table 3-2. Interrupt vector assignments

Address Vector IRQ

0x0000_0000 0 — — ARM core Initial stack pointer
0x0000_0004 1 — — ARM core Initial program counter
0x0000_0008 2 — — ARM core Non-maskable interrupt (NMI)
0x0000_000C 3 — — ARM core Hard fault
0x0000_0010 4 — — — —
0x0000_0014 5 — — — —
0x0000_0018 6 — — — —
0x0000_001C 7 — — — —
0x0000_0020 8 — — — —
0x0000_0024 9 — — — —
0x0000_0028 10 — — — —
0x0000_002C 11 — — ARM core Supervisor call (SVCall)
0x0000_0030 12 — — — —
0x0000_0034 13 — — — —
0x0000_0038 14 — — ARM core Pendable request for system service

0x0000_003C 15 — — ARM core System tick timer (SysTick)

Non-Core Vectors

0x0000_0040 16 0 0 DMA DMA channel 0 transfer complete and error
0x0000_0044 17 1 0 DMA DMA channel 1 transfer complete and error
0x0000_0048 18 2 0 DMA DMA channel 2 transfer complete and error
0x0000_004C 19 3 0 DMA DMA channel 3 transfer complete and error
0x0000_0050 20 4 1 — —
0x0000_0054 21 5 1 FTFA Command complete and read collision
0x0000_0058 22 6 1 PMC Low-voltage detect, low-voltage warning
0x0000_005C 23 7 1 LLWU Low Leakage Wakeup
0x0000_0060 24 8 2 I2C0 Status and Timeout and wakeup flags
0x0000_0064 25 9 2 I2C1 Status and Timeout and wakeup flags
0x0000_0068 26 10 2 SPI0 Single interrupt vector for all sources
0x0000_006C 27 11 2 SPI1 Single interrupt vector for all sources
0x0000_0070 28 12 3 LPUART0 Status and error
0x0000_0074 29 13 3 LPUART1 Status and error
0x0000_0078 30 14 3 UART2 or FlexIO Status and error—

1

NVIC

IPR

register

number

ARM core system handler vectors

Source module Source description

2

(PendableSrvReq)

Table continues on the next page...

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Nested vectored interrupt controller (NVIC)

Table 3-2. Interrupt vector assignments (continued)

Address Vector IRQ

0x0000_007C 31 15 3 ADC0 Conversion complete
0x0000_0080 32 16 4 CMP0 Rising or falling edge of comparator output
0x0000_0084 33 17 4 TPM0 Overflow or channel interrupt
0x0000_0088 34 18 4 TPM1 Overflow or channel interrupt
0x0000_008C 35 19 4 TPM2 Overflow or channel interrupt
0x0000_0090 36 20 5 RTC Alarm interrupt
0x0000_0094 37 21 5 RTC Seconds interrupt
0x0000_0098 38 22 5 PIT Single interrupt vector for all channels
0x0000_009C 39 23 5 I2S0 Single interrupt vector for all sources
0x0000_00A0 40 24 6 USB —
0x0000_00A4 41 25 6 DAC0 —
0x0000_00A8 42 26 6 — —
0x0000_00AC 43 27 6 — —
0x0000_00B0 44 28 7 LPTMR0 LP Timer compare match
0x0000_00B4 45 29 7 — —
0x0000_00B8 46 30 7 Port control module Pin detect (Port A)
0x0000_00BC 47 31 7 Port control module Pin detect (Single interrupt vector for Port C,

1

NVIC

IPR

register

number

Source module Source description

2

Port D)

1. Indicates the NVIC's interrupt source number.

2. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4

3.2.3.1 Determining the bitfield and register location for configuring a particular interrupt

Suppose you need to configure the SPI0 interrupt. The following table is an excerpt of the
SPI0 row from Interrupt priority levels.

Table 3-3. Interrupt vector assignments

Address Vector IRQ

0x0000_0068 26 10 2 SPI0 Single interrupt vector for all sources

1. Indicates the NVIC's interrupt source number.

2. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4.

• The NVIC registers you would use to configure the interrupt are:

1

NVIC IPR

register

number

Source module Source description

2

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Chapter 3 Core Overview

• NVICIPR2

• To determine the particular IRQ's field location within these particular registers:

• NVICIPR2 field starting location = 8 * (IRQ mod 4) + 6 = 22

Since the NVICIPR fields are 2-bit wide (4 priority levels), the NVICIPR2 field
range is 22–23.

Therefore, the following field locations are used to configure the SPI0 interrupts:

• NVICIPR2[23:22]

3.3 AWIC introduction

The primary function of the AWIC block is to detect asynchronous wake-up events in
stop modes and signal to clock control logic to resume system clocking. After clock
restart, the NVIC observes the pending interrupt and performs the normal interrupt or
event processing.

3.3.1 Wake-up sources

The device uses the following internal and external inputs to the AWIC module.

Table 3-4. AWIC stop wake-up sources

Wake-up source Description

Available system resets RESET pin when LPO is its clock source
Low-voltage detect Power management controller—functional in Stop mode
Low-voltage warning Power management controller—functional in Stop mode
Pin interrupts Port control module—any enabled pin interrupt is capable of waking the system
ADC The ADC is functional when using internal clock source or external crystal clock
CMP0 Interrupt in normal or trigger mode
I2C Address match wakeup
LPUART0 , LPUART1 Any enabled interrupt can be a source as long as the module remains clocked
UART2 Active edge on RXD
RTC Alarm or seconds interrupt
NMI NMI pin
TPMx Any enabled interrupt can be a source as long as the module remains clocked
LPTMR Any enabled interrupt can be a source as long as the module remains clocked
SPIx Slave mode interrupt
FlexIO Any enabled interrupt can be a source as long as the module remains clocked

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AWIC introduction

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54 Freescale Semiconductor, Inc.

Chapter 4
Memory Map

4.1 Introduction

This device contains various memories and memory-mapped peripherals which are
located in a 4 GB memory space.

This chapter describes the memory and peripheral locations within that memory space.

4.2 Flash memory

The devices covered in this document contain 2 program flash blocks consisting of 1 KB
sectors.

The amounts of flash memory for the devices covered in this document are:

Table 4-1. KL27 Flash Memory Size

Device Flash Memory (KB) Block 0 (P-Flash) address

range

MKL27Z128VMP4,

MKL27Z128VLH4,

MKL27Z128VFM4,

MKL27Z128VFT4

MKL27Z256VMP4,

MKL27Z256VLH4,

MKL27Z256VFM4,

MKL27Z256VFT4

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128 0x0000_0000 – 0x0000_FFFF 0x0001_0000 – 0x0001_FFFF

256 0x0000_0000 – 0x0001_FFFF 0x0002_0000 – 0x0003_FFFF

Block 1 (P-Flash) address

range

Flash

Flash configur

ation field

Flash base address

Flash memory base address

Registers

Flash memory

4.2.1 Flash memory map

The flash memory and the flash registers are located at different base addresses as shown
in the figure found here.

The base address for each is specified in System memory map.

Figure 4-1. Flash memory map

The on-chip flash memory is implemented in a portion of the allocated Flash range to
form a contiguous block in the memory map beginning at address 0x0000_0000. See

Flash memory for details of supported ranges.

Access to the flash memory ranges outside the amount of flash on the device causes the
bus cycle to be terminated with an error followed by the appropriate response in the
requesting bus master.

4.2.2 Flash security

For information on how flash security is implemented on this device, see Security.

4.2.3 Flash modes

The flash memory chapter defines two modes of operation: NVM normal and NVM
special modes. On this device, the flash memory only operates in NVM normal mode. All
references to NVM special mode must be ignored.

4.2.4 Erase all flash contents

In addition to software, the entire flash memory may be erased external to the flash
memory via the SW-DP debug port by setting MDM-AP CONTROL[0]. MDM-AP
STATUS[0] is set to indicate the mass erase command has been accepted. MDM-AP
STATUS[0] is cleared when the mass erase completes.

56 Freescale Semiconductor, Inc.

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Chapter 4 Memory Map

4.2.5 FTFA_FOPT register

The flash memory's FTFA_FOPT register allows the user to customize the operation of
the MCU at boot time. See FOPT boot options for details of its definition.

4.3

SRAM

4.3.1 SRAM sizes

This device contains SRAM which could be accessed by bus masters through the cross­bar switch. The amount of SRAM for the devices covered in this document is shown in
the following table.

Table 4-2. KL27 SRAM memory size

Device SRAM

MKL27Z128VFM4 32 KB
MKL27Z256VFM4 32 KB

MKL27Z128VFT4 32 KB

MKL27Z256VFT4 32 KB
MKL27Z128VMP4 32 KB
MKL27Z256VMP4 32 KB

MKL27Z128VLH4 32 KB
MKL27Z256VLH4 32 KB

4.3.2 SRAM ranges

The on-chip SRAM is split into two ranges, 1/4 is allocated SRAM_L and 3/4 is allocated
to SRAM_U.

The on-chip RAM is implemented such that the SRAM_L and SRAM_U ranges form a
contiguous block in the memory map. As such:

• SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending
address.
SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning

•
address.

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SRAM_U

0x2000_0000

SRAM size *(1/4)

SRAM_L

0x1FFF_FFFF

SRAM size * (3/4)

0x2000_0000 – SRAM_size/4

0x2000_0000 + SRAM_size*(3/4) - 1

System Register file

Valid address ranges for SRAM_L and SRAM_U are then defined as:

• SRAM_L = [0x2000_0000–(SRAM_size/4)] to 0x1FFF_FFFF

• SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size*(3/4))-1]

This is illustrated in the following figure.

Figure 4-2. SRAM blocks memory map

For example, for a device containing 16 KB of SRAM, the ranges are:

• SRAM_L: 0x1FFF_F000 – 0x1FFF_FFFF
SRAM_U: 0x2000_0000 – 0x2000_2FFF

•

4.3.3 SRAM retention in low power modes

The SRAM is retained down to VLLS3 mode. In VLLS1 and VLLS0, no SRAM is
retained.

4.4 System Register file

This device includes a 32-byte register file that is powered in all power modes.

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Chapter 4 Memory Map

Also, it retains contents during low-voltage detect (LVD) events and is only reset during
a power-on reset.

4.5 System memory map

The table found here shows the high-level device memory map.

Table 4-3. System memory map

System 32-bit address range Destination slave Access

0x0000_0000–0x07FF_FFFF

0x0800_0000–0x1BFF_FFFF Reserved —
0x1C00_0000 – 0x1C00_3FFF Boot ROM All masters
0x1C00_4000 – 0x1FFF_DFFF Reserved —
0x1FFF_E000–0x1FFF_FFFF
0x2000_0000–0x2000_5FFF
0x2000_6000–0x3FFF_FFFF Reserved –
0x4000_0000–0x4007_FFFF AIPS Peripherals Cortex-M0+ core &

0x4008_0000–0x400F_EFFF Reserved –
0x400F_F000–0x400F_FFFF General-purpose input/output (GPIO) Cortex-M0+ core &

0x4010_0000–0x43FF_FFFF Reserved –
0x4400_0000–0x5FFF_FFFF Bit Manipulation Engine (BME) access to AIPS Peripherals for

0x6000_0000–0xDFFF_FFFF Reserved –
0xE000_0000–0xE00F_FFFF Private Peripherals Cortex-M0+ core
0xE010_0000–0xEFFF_FFFF Reserved –
0xF000_0000–0xF000_0FFF Micro Trace Buffer (MTB) registers Cortex-M0+ core
0xF000_1000–0xF000_1FFF MTB Data Watchpoint and Trace (MTBDWT) registers Cortex-M0+ core
0xF000_2000–0xF000_2FFF ROM table Cortex-M0+ core
0xF000_3000–0xF000_3FFF Miscellaneous Control Module (MCM) Cortex-M0+ core
0xF000_4000–0xF7FF_FFFF Reserved –
0xF800_0000–0xFFFF_FFFF IOPORT: GPIO (single cycle) Cortex-M0+ core

1

, 2

2

Program flash and read-only data
(Includes exception vectors in first 192 bytes)

SRAM_L: Lower SRAM All masters
SRAM_U: Upper SRAM All masters

slots 0-127

3

All masters

DMA

DMA

Cortex-M0+ core

1. The program flash always begins at 0x0000_0000 but the end of implemented flash varies depending on the amount of
flash implemented for a particular device. See Flash memory for details.

2. This range varies depending on SRAM sizes. See SRAM sizes for details.

3. Includes BME operations to GPIO at slot 15 (based at 0x4000_F000).

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Bit Manipulation Engine

4.6 Bit Manipulation Engine

The Bit Manipulation Engine (BME) provides hardware support for atomic read-modify­write memory operations to the peripheral address space.

By combining the basic load and store instruction support in the Cortex-M instruction set
architecture with the concept of decorated storage provided by the BME, the resulting
implementation provides a robust and efficient read-modify-write capability to this class
of ultra low-end microcontrollers. See the Bit Manipulation Engine Block Guide (BME)
for a detailed description of BME functionality.

4.7 Peripheral bridge (AIPS-Lite) memory map

The peripheral memory map is accessible via one slave port on the crossbar in the
0x4000_0000–0x400F_FFFF region. The device implements one peripheral bridge that
defines a 1024 KB address space.

The three regions associated with this space are:

• A 128 KB region, partitioned as 32 spaces, each 4 KB in size and reserved for on­platform peripheral devices. The AIPS controller generates unique module enables
for all 32 spaces.

• A 384 KB region, partitioned as 96 spaces, each 4 KB in size and reserved for off­platform modules. The AIPS controller generates unique module enables for all 96
spaces.

• The last slot is a 4 KB region beginning at 0x400F_F000 for accessing the GPIO
module. The GPIO slot (slot 128) is an alias of slot 15. This block is also directly
interfaced to the core and provides direct access without incurring wait states
associated with accesses via the AIPS controller.

Modules that are disabled via their clock gate control bits in the SIM registers disable the
associated AIPS slots. Access to any address within an unimplemented or disabled
peripheral bridge slot results in a transfer error termination.

For programming model accesses via the peripheral bridges, there is generally only a
small range within the 4 KB slots that is implemented. Accessing an address that is not
implemented in the peripheral results in a transfer error termination.

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Chapter 4 Memory Map

4.7.1 Read-after-write sequence and required serialization of
memory operations

In some situations, a write to a peripheral must be completed fully before a subsequent
action can occur. Examples of such situations include:

• Exiting an interrupt service routine (ISR)

• Changing a mode

• Configuring a function

In these situations, the application software must perform a read-after-write sequence to
guarantee the required serialization of the memory operations:

1. Write the peripheral register.

2. Read the written peripheral register to verify the write.

3. Continue with subsequent operations.

4.7.2 Peripheral bridge (AIPS-Lite) memory map

Table 4-4. Peripheral bridge 0 slot assignments

System 32-bit base address Slot

number

0x4000_0000 0 —
0x4000_1000 1 —
0x4000_2000 2 —
0x4000_3000 3 —
0x4000_4000 4 —
0x4000_5000 5 —
0x4000_6000 6 —
0x4000_7000 7 —
0x4000_8000 8 DMA controller
0x4000_9000 9 —
0x4000_A000 10 —

0x4000_B000 11 —
0x4000_C000 12 —
0x4000_D000 13 —
0x4000_E000 14 —
0x4000_F000 15 GPIO controller (aliased to 0x400F_F000)

0x4001_0000 16 —

0x4001_1000 17 —

0x4001_2000 18 —

0x4001_3000 19 —

0x4001_4000 20 —

Module

Table continues on the next page...

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Peripheral bridge (AIPS-Lite) memory map

Table 4-4. Peripheral bridge 0 slot assignments (continued)

System 32-bit base address Slot

number

0x4001_5000 21 —

0x4001_6000 22 —

0x4001_7000 23 —

0x4001_8000 24 —

0x4001_9000 25 —
0x4001_A000 26 —
0x4001_B000 27 —
0x4001_C000 28 —
0x4001_D000 29 —
0x4001_E000 30 —
0x4001_F000 31 —

0x4002_0000 32 Flash memory

0x4002_1000 33 DMA channel mutiplexer 0

0x4002_2000 34 —

0x4002_3000 35 —

0x4002_4000 36 —

0x4002_5000 37 —

0x4002_6000 38 —

0x4002_7000 39 —

0x4002_8000 40 —

0x4002_9000 41 —
0x4002_A000 42 —
0x4002_B000 43 —
0x4002_C000 44 —
0x4002_D000 45 —
0x4002_E000 46 —
0x4002_F000 47 I2S0

0x4003_0000 48 —

0x4003_1000 49 —

0x4003_2000 50 —

0x4003_3000 51 —

0x4003_4000 52 —

0x4003_5000 53 —

0x4003_6000 54 —

0x4003_7000 55 Periodic interrupt timers (PIT)

0x4003_8000 56 Timer/PWM (LPTPM) 0

0x4003_9000 57 Timer/PWM (LPTPM) 1
0x4003_A000 58 Timer/PWM (LPTPM) 2
0x4003_B000 59 Analog-to-digital converter 0(ADC0)

Module

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Chapter 4 Memory Map

Table 4-4. Peripheral bridge 0 slot assignments (continued)

System 32-bit base address Slot

number

0x4003_C000 60 —
0x4003_D000 61 Real Time Clock (RTC)
0x4003_E000 62 —
0x4003_F000 63 DAC0

0x4004_0000 64 Low-power timer (LPTMR)

0x4004_1000 65 System register file

0x4004_2000 66 —

0x4004_3000 67 —

0x4004_4000 68 —

0x4004_5000 69 —

0x4004_6000 70 —

0x4004_7000 71 SIM low-power logic

0x4004_8000 72 System integration module (SIM)

0x4004_9000 73 Port A multiplexing control
0x4004_A000 74 Port B multiplexing control
0x4004_B000 75 Port C multiplexing control
0x4004_C000 76 Port D multiplexing control
0x4004_D000 77 Port E multiplexing control
0x4004_E000 78 —
0x4004_F000 79 —

0x4005_0000 80 —

0x4005_1000 81 —

0x4005_2000 82 —

0x4005_3000 83 —

0x4005_4000 84 LPUART0

0x4005_5000 85 LPUART1

0x4005_6000 86 —

0x4005_7000 87 —

0x4005_8000 88 —

0x4005_9000 89 —
0x4005_A000 90 —
0x4005_B000 91 —
0x4005_C000 92 —
0x4005_D000 93 —
0x4005_E000 94
0x4005_F000 95 FlexIO

0x4006_0000 96 —

0x4006_1000 97 —

0x4006_2000 98 —

Module

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Peripheral bridge (AIPS-Lite) memory map

Table 4-4. Peripheral bridge 0 slot assignments (continued)

System 32-bit base address Slot

number

0x4006_3000 99 —

0x4006_4000 100 Multi-purpose clock Generator Lite (MCG_Lite)

0x4006_5000 101 System oscillator (OSC)

0x4006_6000 102 I2C0

0x4006_7000 103 I2C1

0x4006_8000 104 —

0x4006_9000 105 —
0x4006_A000 106 —
0x4006_B000 107 —
0x4006_C000 108 UART2
0x4006_D000 109 —
0x4006_E000 110 —
0x4006_F000 111 —

0x4007_0000 112 —

0x4007_1000 113 —

0x4007_2000 114 USB FS

0x4007_3000 115 Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC)

0x4007_4000 116 Voltage reference (VREF)

0x4007_5000 117 —

0x4007_6000 118 SPI0

0x4007_7000 119 SPI1

0x4007_8000 120 —

0x4007_9000 121 —
0x4007_A000 122 —
0x4007_B000 123 —
0x4007_C000 124 Low-leakage wakeup unit (LLWU)
0x4007_D000 125 Power management controller (PMC)
0x4007_E000 126 System mode controller (SMC)
0x4007_F000 127 Reset control module (RCM)
0x400F_F000 128 GPIO controller

Module

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Chapter 5
Clock Distribution

5.1 Introduction

This chapter presents the clock architecture for the device, the overview of the clocks and
includes a terminology section.

The Cortex M0+ resides within a synchronous core platform, where the processor and
bus masters, flash memory, and peripheral clocks can be configured independently. The
clock distribution figure shows how clocks from the lite version of Multi Clock
Generation (MCG-Lite) and OSC module are distributed to the microcontroller’s other
function units. Some modules in the microcontroller have selectable clock input.

5.2 Programming model

The selection and multiplexing of system clock sources is controlled and programmed via
the Clock Generation Module. The setting of clock dividers and module clock gating for
the system are programmed via the SIM module. Refer to the MCG_Lite and SIM
sections for detailed register and bit descriptions.

5.3 High-level device clocking diagram

The following system oscillator, MCG_Lite, and SIM module registers control the
multiplexers, dividers, and clock gates shown in the following figure:

OSC MCG-Lite SIM

Multiplexers MCG_Cx MCG_Cx SIM_SOPT1, SIM_SOPT2
Dividers — MCG_Cx SIM_CLKDIVx
Clock gates OSC_CR MCG_C1 SIM_SCGCx

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Freescale Semiconductor, Inc. 65

MCG_Lite

OUTDIV1

Core/Platform/System clock

IRC48M

OUTDIV4

Bus/Flash clock

EXTAL0

XTAL0

System oscillator

CLKGEN

CLKS

MCGIRCLK

ERCLK32K

OSC32KCLK

XTAL_CLK

OSCERCLK

OSC
logic

Clock options for
some peripherals
(see note)

Note1: See subsequent sections for details on where these clocks are used.

PMC logic

PMC

LPO

OSCCLK

CG

CG

CG

CG — Clock gate

8MHz/
2MHz
IRC

8MHz

2MHz

IRC8M

Clock options for
some peripherals
(see note)

RTC_CLKOUT

RTC

RTC_CKLIN

1Hz

IRCS

USB_EN

Counter logic

USB

IRC_TRIMs

Note2: 48Mhz clock (IRC48M) control register is defined in either USB or MCG_Lite. In case USB is not
available, IRC48M will be controlled by IRC_TRIMs in MCG_Lite module
Note3: FCRDIV support divider ratio 1,2,4,8,16, 32, 64, 128. LIRC_DIV2 provides the futher divide
down for MCGIRCLK.
Note4: OSC32KCLK is only available when external crystal is in 30KHz - 40KHz range.

MCGOUTCLK

FCRDIV

MCGPCLK

CG

LIRC_DIV2

Clock definitions

Figure 5-1. Clocking diagram

5.4 Clock definitions

The following table describes the clocks in the previous block diagram.

Core clock MCGOUTCLK divided by OUTDIV1

Clock name Description

Clocks the ARM Cortex-M0+ core.

Platform clock MCGOUTCLK divided by OUTDIV1

Clocks the crossbar switch and NVIC.

System clock MCGOUTCLK divided by OUTDIV1

Clocks the bus masters directly .

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Table continues on the next page...

Chapter 5 Clock Distribution

Clock name Description

Bus clock System clock divided by OUTDIV4.

Clocks the bus slaves and peripherals.

Flash clock Flash memory clock

On this device, it is the same as Bus clock.

MCGOUTCLK MCG_Lite output of either IRC48M, IRC8M, MCG_Lite's

external reference clock that sources the core, system, bus,

and flash clock.
MCGIRCLK IRC8M/2M internal reference clock divided by lirc_div2
MCGPCLK MCG_Lite output of the fast (IRC48M) internal reference

clock. This clock may clock some modules. In addition, this

clock is used for LPUART0, LPUART1 and TPM modules
OSCCLK System oscillator output of the internal oscillator or sourced

directly from EXTAL. Used as MCG_Lite's external reference

clock.
OSCERCLK System oscillator output sourced from OSCCLK that may

clock some on-chip modules
OSC32KCLK System oscillator 32 kHz output
ERCLK32K Clock source for some modules that is chosen as

OSC32KCLK or RTC_CLKIN or LPO
LPO PMC 1 kHz output

5.4.1 Device clock summary

The following table provides more information regarding the on-chip clocks.

Table 5-1. Clock summary

Clock name Run mode

clock frequency

MCGOUTCLK Up to 48 MHz Up to 8 MHz MCG_Lite In all stop modes

MCGPCLK Up to 48 MHz N/A MCG_Lite MCG_Lite and USB

Core clock Up to 48 MHz Up to 4 MHz MCGOUTCLK clock

Platform clock Up to 48 MHz Up to 4 MHz MCGOUTCLK clock

System clock Up to 48 MHz Up to 4 MHz MCGOUTCLK clock

Bus clock Up to 24 MHz Up to 1 MHz

VLPR mode
clock frequency

1

Table continues on the next page...

Clock source Clock is disabled

divider

divider

divider
MCGOUTCLK clock

divider

when…

except for partial stop
modes.

clock controls are not
enabled and in all stop
modes except for partial
stop modes.

In all wait and stop
modes

In all stop modes

In all stop modes and
Compute Operation

In all stop modes
except for partial

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Clock definitions

Table 5-1. Clock summary (continued)

Clock name Run mode

clock frequency

SWD Clock Up to 24 MHz Up to 1 MHz SWD_CLK pin In all stop modes
Flash clock Up to 24 MHz Up to 1 MHz in EXT

Internal reference

(MCGIRCLK)

External reference

(OSCERCLK)

External reference

32kHz

(ERCLK32K)

RTC_CLKOUT RTC 1Hz,

CLKOUT32K 32K 32K ERCLK32K SIM_SOPT1[OSC3

LPO 1 kHz 1 kHz PMC in VLLS0

TPM clock Up to 48 MHz Up to 8 MHz MCGIRCLK,

LPUART0 clock Up to 48 MHz Up to 8 MHz MCGIRCLK,

8/2MHz LIRC 8/2MHz LIRC MCG_Lite MCG_C1[IRCLKEN]

Up to 48 MHz (bypass),
30–40 kHz
or 3-32Mhz(crystal)

30–40 kHz 30–40 kHz System OSC

OSCERCLK

VLPR mode
clock frequency

and LIRC

Up to 16 MHz (bypass),
30–40 kHz
(low-range crystal)
or 3-16Mhz (high range

crystal)

RTC 1Hz,
OSCERCLK

Clock source Clock is disabled

when…

STOP2 mode, and
Compute Operation

MCGOUTCLK clock
divider

System OSC System OSC's

or RTC_CLKIN
or LPO

RTC 1Hz,
OSCERCLK

MCGPCLK,
OSCERCLK

MCGPCLK,
OSCERCLK

In all stop modes
except for partial
STOP2 mode

cleared,
Stop/VLPS mode and

MCG_C1[IREFSTEN]
cleared, or

VLLS mode

OSC_CR[ERCLKEN]
cleared, or

Stop mode and
OSC_CR[EREFSTEN]
cleared

or VLLS0 and oscillator
not in external clock
mode.

System OSC's
OSC_CR[ERCLKEN]
cleared

and RTC's
RTC_CR[OSCE]
cleared

or VLLS0 and oscillator
not in external clock
mode.

Clock is disabled in
VLLSx modes

2KOUT] not configured
to drive ERCLK32K out.

SIM_SOPT2[TPMSRC
]=00 selected clock
source disabled

SIM_SOPT2[LPUART0
SRC]=00 selected clock
source disabled

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Table 5-1. Clock summary (continued)

Chapter 5 Clock Distribution

Clock name Run mode

clock frequency

LPUART1 clock Up to 48 MHz Up to 8 MHz MCGIRCLK,

FlexIO clock Up to 48 MHz Up to 8 MHz MCGIRCLK,

USB FS clock 48 MHz N/A MCGPCLK,

I2S master clock Up to 25 MHz Up to 16 MHz System clock,

1. If in LIRC mode, where clocking is derived from the fast internal reference clock, the Bus clock and flash clock frequency
needs to be limited to 1Mhz if executing from flash.

VLPR mode
clock frequency

Clock source Clock is disabled

when…

SIM_SOPT2[LPUART1
MCGPCLK,
OSCERCLK

MCGPCLK,
OSCERCLK

USB_CLKIN

OSCERCLK,
MCGIRCLK ,
MCGPCLK,

SRC]=00 selected clock

source disabled

SIM_SOPT2[FLEXIOS

RC]=00 selected clock

source disabled

USB FS is disabled

I2S is disabled

5.5 Internal clocking requirements

The clock dividers are programmed via the SIM_CLKDIV1 register. The following
requirements must be met when configuring the clocks for this device:

• The core, platform, and system clock are programmable from a divide-by-1 through
divide-by-16 setting. The core, platform, and system clock frequencies must be 48
MHz or slower.
The frequency of bus clock and flash clock is divided by the system clock and is

•
programmable from a divide-by-1 through divide-by-8 setting. The bus clock and
flash clock must be programmed to 24 MHz or slower.

• MCGPCLK is used for peripheral which is fixed to 48 MHz.

• MCGIRCLK is also one of peripheral clock sources which is from IRC8M and can
be divided down by a divider.

The following is a common clock configuration for this device:

Clock Max. Frequency

Core clock 48 MHz
Platform clock 48 MHz
System clock 48 MHz
Bus clock 24 MHz
Flash clock 24 MHz

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Internal clocking requirements

Clock Max. Frequency

MCGIRCLK 8 MHz
MCGPCLK 48 MHz

5.5.1 Clock divider values after reset

Each clock divider is programmed via the CLKDIV1 registers of the SIM module. Two
bits in the flash memory's FTFA_FOPT register control the reset value of the core clock,
system clock, bus clock, and flash clock dividers as shown in the table given below:

FTFA_FOPT [4,0] Core/system clock Bus/Flash clock Execution Mode

00 0x7 (divide by 8) 0x1 (divide by 2) VLPR
01 0x3 (divide by 4) 0x1 (divide by 2) VLPR
10 0x1 (divide by 2) 0x1 (divide by 2) RUN
11 0x0 (divide by 1) 0x1 (divide by 2) RUN

This gives the user flexibility in selecting between a lower frequency, low-power boot
option and higher frequency, higher power during and after reset.

The flash erased state defaults to fast clocking mode, since these bits reside in flash,
which is logic 1 in the flash erased state. To enable a lower power boot option, program
the appropriate bits in FTFA_FOPT. During the reset sequence, if either of the control
bits is cleared, the system is in a slower clock configuration. Upon any system reset, the
clock dividers return to this configurable reset state.

The default reset clock for core/system clock is 8 MHz from IRC8M.

5.5.2 VLPR mode clocking

The clock dividers cannot be changed while in VLPR mode. These dividers must be
programmed prior to entering VLPR mode to guarantee operation. Maximum frequency
limitations for VLPR mode is as follows :

• the core/system clocks are less than or equal to 4 MHz, and
the bus and flash clocks are less than or equal to 1 MHz

•

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Chapter 5 Clock Distribution

5.6 Clock gating

The clock to each module can be individually gated on and off using bits of the SCGCx
registers of the SIM module. These bits are cleared after any reset, which disables the
clock to the corresponding module to conserve power. Prior to initializing a module, set
the corresponding bit in the SCGCx register to enable the clock. Before turning off the
clock, make sure to disable the module.

Any bus access to a peripheral that has its clock disabled generates an error termination.

5.7 Module clocks

The following table summarizes the clocks associated with each module.

Table 5-2. Module clocks

Module Bus interface clock Internal clocks I/O interface clocks

Core modules

ARM Cortex-M0+ core Platform clock Core clock —

NVIC Platform clock — —

DAP Platform clock — SWD_CLK

System modules

DMA System clock — —

DMA Mux Bus clock — —

Port control Bus clock — —

Crossbar Switch Platform clock — —

Peripheral bridges System clock Bus clock —

LLWU, PMC, SIM, RCM Bus clock LPO —

Mode controller Bus clock — —

MCM Platform clock — —

COP watchdog Bus clock LPO, Bus Clock, MCGIRCLK,

OSCERCLK

Clocks

MCG_Lite Bus clock MCGOUTCLK, MCGPCLK,

MCGIRCLK, OSCERCLK,

ERCLK32K

OSC Bus clock OSCERCLK —

Memory and memory interfaces

Flash Controller Platform clock Flash clock —

Flash memory Flash clock — —

Analog

—

—

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Module clocks

Table 5-2. Module clocks (continued)

Module Bus interface clock Internal clocks I/O interface clocks

ADC Bus clock OSCERCLK —
CMP Bus clock — —
DAC Bus clock — —

Internal Voltage Reference

(VREF)

TPM Bus clock TPM clock TPM_CLKIN0, TPM_CLKIN1

PIT Bus clock — —

LPTMR Bus clock LPO, OSCERCLK,

RTC Bus clock ERCLK32K RTC_CLKOUT, RTC_CLKIN

USB FS (Device Only) System clock USB FS clock —

SPI0 Bus clock — SPI0_SCK
SPI1 System clock — SPI1_SCK

I2C0 System Clock — I2C0_SCL
I2C1 System Clock — I2C1_SCL

LPUART0, LPUART1 Bus clock LPUART0 clock

UART2 Bus clock — —

FlexIO Bus clock FlexIO clock —

I2S Bus clock I2S master clock I2S_TX_BCLK,

GPIO Platform clock — —

Bus clock — —

Timers

MCGPCLK, ERCLK32K

Communication interfaces

LPUART1 clock

Human-machine interfaces

—

—

I2S_RX_BCLK

5.7.1 PMC 1-kHz LPO clock

The Power Management Controller (PMC) generates a 1-kHz clock that is enabled in all
modes of operation, including all low-power modes except VLLS0. This 1-kHz source is
commonly referred to as LPO clock or 1-kHz LPO clock.

5.7.2 COP clocking

The COP may be clocked from four clock sources as shown in the following figure.

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72 Freescale Semiconductor, Inc.

SIM_COPC[COPCLKSEL]

COP clock

Bus clock

LPO

OSCERCLK

MCGIRCLK

00
01

1

0

11

Figure 5-2. COP clock generation

SIM_SOPT1[OSC32KSEL]

OSC32KCLK

RTC_CLKIN

LPO

ERCLK32K

(to RTC)

00

11

1

0

5.7.3 RTC clocking

The RTC module can be clocked as shown in the following figure.

NOTE

The chosen clock must remain enabled if the RTC is to
continue operating in all required low-power modes.

Chapter 5 Clock Distribution

Figure 5-3. RTC clock generation

5.7.4 RTC_CLKOUT and CLKOUT32K clocking

When the RTC is enabled and the port control module selects the RTC_CLKOUT
function, the RTC_CLKOUT signal, controlled from SIM_SOPT2[RTCCLKOUTSEL],
outputs a 1 Hz or 32 kHz output derived from RTC oscillator as shown below and can be
configured to drive to external pins via pin control configuration for the associated pin. It
is also possible to drive CLKOUT32K on the same pins as controlled by

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SIM_SOPT2[RTCCLKOUTSEL]

RTC_CLKOUT

RTC 1Hz clock

OSCERCLK

RTC_CLKIN]

SIM_SOPT1[OSC32KOUT]

PTE0/CLKOUT32K

Pad
interface

PTE26/CLKOUT32K

Pad
interface

SIM_SOPT1[OSC32KSEL]

OSC32KCLK

ERCLK32K

00

10

1

0

10

01

Other
modules

Other
modules

LPO

11

Module clocks

SIM_SOPT1[OSC32KOUT] on the selected RTC_CLKOUT pins in all modes of
operation (including LLS/VLLS and System Reset), overriding the existing pin mux
configuration for that pin.

Figure 5-4. RTC_CLKOUT and CLKOUT32K generation

5.7.5 LPTMR clocking

The prescaler and glitch filters in each of the LPTMRx modules can be clocked as shown
in the following figure.

The chosen clock must remain enabled if the LPTMRx is to
continue operating in all required low-power modes.

NOTE

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74 Freescale Semiconductor, Inc.

LPTMRx_PSR[PCS]

LPTMRx prescaler/glitch
f

ilt

er clock

MCGIRCLK

OSCERCLK

ERCLK32K

LPO

SIM_SOPT1[OSC32KSEL]

OSC32KCLK

RTC_CLKIN

LPO

11

10

00

00

01

10

11

SIM_SOPT2[TPMSRC]

TPM clock

MCGIRCLK

OSCERCLK

MCGPCLK

11

10

01

Chapter 5 Clock Distribution

Figure 5-5. LPTMRx prescaler/glitch filter clock generation

5.7.6 TPM clocking

The counter for the TPM modules has a selectable clock as shown in the following figure.

NOTE

The chosen clock must remain enabled if the TPMx is to
continue operating in all required low-power modes.

Figure 5-6. TPM clock generation

5.7.7 USB FS device only controller clocking

The USB FS controller is a bus master attached to the crossbar switch. As such, its clock
is connected to the system clock.

Freescale Semiconductor, Inc. 75

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USB 48MHz

SIM_SOPT2[USBSRC]

MCGPCLK

Module clocks

NOTE

For the USB FS controller to operate, the minimum system
clock frequency is 20 MHz.

The USB controller also requires a 48 MHz clock. The clock source options are shown
below.

Figure 5-7. USB 48 MHz clock source

5.7.8 LPUART clocking

The LPUART0 and LPUART1 have a selectable clock as shown in the following figure.
UART2 module operates from the bus clock.

NOTE

The chosen clock must remain enabled if the LPUART0 and
LPUART1 is to continue operating in all required low-power
modes.

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76 Freescale Semiconductor, Inc.

LPUART0 clock

MCGPCLK

SIM_SOPT2[LPUART0SRC]

MCGIRCLK

OSCERCLK

11

10

0

1

LPUART1 clock

MCGPCLK

SIM_SOPT2[LPUART1SRC]

MCGIRCLK

OSCERCLK

01

10

1

1

FlexIO clock

MCGPCLK

SIM_SOPT2[FLEXIOSRC]

MCGIRCLK

OSCERCLK

01

10

1

1

Chapter 5 Clock Distribution

5.7.9 FlexIO clocking

The FlexIO module has a selectable clock as shown in the following figure.

Figure 5-8. LPUART0 and LPUART1 clock generation

NOTE

The chosen clock must remain enabled if the FlexIO is to
continue operating in all required low-power modes.

Freescale Semiconductor, Inc. 77

Figure 5-9. FlexIO clock generation

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

1

0

11

01

10

00

OSCERCLK

MCGPCLK

System Clock

I2Sx_MCR[MOE]

MCLK

MCLK_OUT

MCLK_IN

11

01

10

00

Bus Clock

[MSEL]

Bit

Clock

Divider

1

0

BCLK_IN

I2S/SAI

BCLK_OUT

[BCD]

BCLK

I2Sx_MCR[MICS]

Clock Generation

[DIV]

I2Sx_TCR2/RCR2

Direction
Control

Pad Interface Logic

MCGIRCLK

Module clocks

5.7.10 I2S/SAI clocking

The audio master clock (MCLK) is used to generate the bit clock when the receiver or
transmitter is configured for an internally generated bit clock. The audio master clock can
also be output to or input from a pin. The transmitter and receiver have the same audio
master clock inputs.

Each SAI peripheral can control the input clock selection, pin direction and divide ratio
of one audio master clock.

The I2S/SAI transmitter and receiver support asynchronous bit clocks (BCLKs) that can
be generated internally from the audio master clock or supplied externally. The module
also supports the option for synchronous operation between the receiver and transmitter.

The transmitter and receiver can independently select between the bus clock and the
audio master clock to generate the bit clock.

The MCLK and BCLK source options appear in the following figure.

Figure 5-10. I2S/SAI clock generation

78 Freescale Semiconductor, Inc.

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Chapter 6
Reset and Boot

6.1 Introduction

The reset sources supported in this MCU are listed in the table found here.

Table 6-1. Reset sources

Reset sources Description

POR reset • Power-on reset (POR)

System resets • External pin reset (PIN)

• Low-voltage detect (LVD)

• Computer operating properly (COP) watchdog reset

• Low leakage wakeup (LLWU) reset

• Stop mode acknowledge error (SACKERR)

• Software reset (SW)

• Lockup reset (LOCKUP)

• MDM DAP system reset

Debug reset • Debug reset

Each of the system reset sources has an associated bit in the System Reset Status (SRS)
registers. See the Reset Control Module for register details.

The MCU can exit and reset in functional mode where the CPU is executing code
(default) or the CPU is in a debug halted state. There are several boot options that can be
configured. See Boot information for more details.

6.2 Reset

The information found here discusses basic reset mechanisms and sources.
Some modules that cause resets can be configured to cause interrupts instead. Consult the

individual peripheral chapters for more information.

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Reset

6.2.1 Power-on reset (POR)

When power is initially applied to the MCU or when the supply voltage drops below the
power-on reset re-arm voltage level (V

), the POR circuit causes a POR reset

POR

condition.
As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has

risen above the LVD low threshold (V

). The POR and LVD fields in the Reset

LVDL

Status Register are set following a POR.

6.2.2 System reset sources

Resetting the MCU provides a way to start processing from a known set of initial
conditions. System reset begins with the on-chip regulator in full regulation and system
clocking generation from an internal reference. When the processor exits reset, it
performs the following:

• Reads the start SP (SP_main) from vector-table offset 0
Reads the start program counter (PC) from vector-table offset 4

•

• Link register (LR) is set to 0xFFFF_FFFF.

The on-chip peripheral modules are disabled and the non-analog I/O pins are initially
configured as disabled. The pins with analog functions assigned to them default to their
analog function after reset.

During and following a reset, the SWD pins have their associated input pins configured
as:

• SWD_CLK in pulldown (PD)

• SWD_DIO in pullup (PU)

6.2.2.1 External pin reset (

RESET)

This pin is open drain and has an internal pullup device. Asserting RESET wakes the
device from any mode.

The RESET pin can be disabled by programming RESET_PIN_CFG option bit to 0.
When this option is selected, there could be a short period of contention during a POR
ramp where the device drives the pin-out low prior to establishing the setting of this
option and releasing the reset function on the pin.

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Chapter 6 Reset and Boot

6.2.2.1.1 RESET pin filter

The RESET pin filter supports filtering from both the 1 kHz LPO clock and the bus
clock. RCM_RPFC[RSTFLTSS], RCM_RPFC[RSTFLTSRW], and
RCM_RPFW[RSTFLTSEL] control this functionality; see the RCM chapter. The filters
are asynchronously reset by Chip POR. The reset value for each filter assumes the
RESET pin is negated.

For all stop modes where LPO clock is still active (Stop, VLPS, LLS, VLLS3, and
VLLS1), the only filtering option is the LPO-based digital filter. The filtering logic either
switches to bypass operation or has continued filtering operation depending on the
filtering mode selected. When entering VLLS0, the RESET pin filter is disabled and
bypassed.

The LPO filter has a fixed filter value of 3. Due to a synchronizer on the input data, there
is also some associated latency (2 cycles). As a result, 5 cycles are required to complete a
transition from low to high or high to low.

6.2.2.2 Low-voltage detect (LVD)

The chip includes a system for managing low-voltage conditions to protect memory
contents and control MCU system states during supply voltage variations. The system
consists of a power-on reset (POR) circuit and an LVD circuit with a user-selectable trip
voltage. The LVD system is always enabled in Normal Run, Wait, or Stop mode. The
LVD system is disabled when entering VLPx, LLS, or VLLSx modes.

The LVD can be configured to generate a reset upon detection of a low-voltage condition
by setting PMC_LVDSC1[LVDRE] to 1. The low-voltage detection threshold is
determined by PMC_LVDSC1[LVDV]. After an LVD reset has occurred, the LVD
system holds the MCU in reset until the supply voltage has risen above the low voltage
detection threshold. RCM_SRS0[LVD] is set following either an LVD reset or POR.

6.2.2.3 Computer operating properly (COP) watchdog timer

The computer operating properly (COP) watchdog timer (WDOG) monitors the operation
of the system by expecting periodic communication from the software. This
communication is generally known as servicing (or refreshing) the COP watchdog. If this
periodic refreshing does not occur, the watchdog issues a system reset. The COP reset
causes RCM_SRS0[WDOG] to set.

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Reset

6.2.2.4 Low leakage wakeup (LLWU)

The LLWU module provides the means for a number of external pins to wake the MCU
from low leakage power modes. The LLWU module is functional only in low leakage
power modes. In VLLSx modes, all enabled inputs to the LLWU can generate a system
reset.

After a system reset, the LLWU retains the flags indicating the input source of the last
wakeup until the user clears them.

NOTE

Some flags are cleared in the LLWU and some flags are
required to be cleared in the peripheral module. Refer to the
individual peripheral chapters for more information.

6.2.2.5 Stop mode acknowledge error (SACKERR)

This reset is generated if the core attempts to enter Stop mode or Compute Operation, but
not all modules acknowledge Stop mode within 1025 cycles of the 1 kHz LPO clock.

A module might not acknowledge the entry to Stop mode if an error condition occurs.
The error can be caused by a failure of an external clock input to a module.

6.2.2.6 Software reset (SW)

The SYSRESETREQ field in the NVIC Application Interrupt and Reset Control register
can be set to force a software reset on the device. (See ARM's NVIC documentation for
the full description of the register fields, especially the VECTKEY field requirements.)
Setting SYSRESETREQ generates a software reset request. This reset forces a system
reset of all major components except for the debug module. A software reset causes
RCM_SRS1[SW] to set.

6.2.2.7 Lockup reset (LOCKUP)

The LOCKUP gives immediate indication of seriously errant kernel software. This is the
result of the core being locked because of an unrecoverable exception following the
activation of the processor’s built in system state protection hardware.

The LOCKUP condition causes a system reset and also causes RCM_SRS1[LOCKUP] to
set.

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Chapter 6 Reset and Boot

6.2.2.8 MDM-AP system reset request

Set the System Reset Request field in the MDM-AP control register to initiate a system
reset. This is the primary method for resets via the SWD interface. The system reset is
held until this field is cleared.

Set the Core Hold Reset field in the MDM-AP control register to hold the core in reset as
the rest of the chip comes out of system reset.

6.2.3 MCU resets

A variety of resets are generated by the MCU to reset different modules.

6.2.3.1 POR Only

The POR Only reset asserts on the POR reset source only. It resets the PMC.
The POR Only reset also causes all other reset types to occur.

6.2.3.2 Chip POR not VLLS

The Chip POR not VLLS reset asserts on POR and LVD reset sources. It resets parts of
the SMC and SIM. It also resets the LPTMR.

The Chip POR not VLLS reset also causes these resets to occur: Chip POR, Chip Reset
not VLLS, and Chip Reset (including Early Chip Reset).

6.2.3.3 Chip POR

The Chip POR asserts on POR, LVD, and VLLS Wakeup reset sources. It resets the
Reset Pin Filter registers and parts of the SIM and MCG-Lite.

The Chip POR also causes the Chip Reset (including Early Chip Reset) to occur.

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Boot

6.2.3.4 Chip Reset not VLLS

The Chip Reset not VLLS reset asserts on all reset sources except a VLLS Wakeup that
does not occur via the RESET pin. It resets parts of the SMC, LLWU, and other modules
that remain powered during VLLS mode.

The Chip Reset not VLLS reset also causes the Chip Reset (including Early Chip Reset)
to occur.

6.2.3.5 Early Chip Reset

The Early Chip Reset asserts on all reset sources. It resets only the flash memory module.
It negates before flash memory initialization begins ("earlier" than when the Chip Reset
negates).

6.2.3.6 Chip Reset

Chip Reset asserts on all reset sources and only negates after flash initialization has
completed and the RESET pin has also negated. It resets the remaining modules (the
modules not reset by other reset types).

6.2.4 RESET pin

For all reset sources except a VLLS Wakeup that does not occur via the RESET pin, the
RESET pin is driven low by the MCU for at least 128 bus clock cycles and until flash
initialization has completed.

After flash initialization has completed, the RESET pin is released, and the internal Chip
Reset negates after the RESET pin is pulled high. Keeping the RESET pin asserted
externally delays the negation of the internal Chip Reset.

The RESET pin can be disabled by programming FTFA_FOPT[RESET_PIN_CFG]
option bit to 0 (See Table 6-2). When this option is selected, there could be a short period
of contention during a POR ramp where the device drives the pinout low prior to
establishing the setting of this option and releasing the reset function on the pin.

6.3 Boot

The information found here describes the boot sequence, including sources and options.

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Chapter 6 Reset and Boot

Some configuration information such as clock trim values stored in factory programmed
flash locations is autoloaded.

6.3.1 Boot sources

The CM0+ core adds support for a programmable Vector Table Offset Register (VTOR)
to relocate the exception vector table. This device supports booting from:

• internal flash

• ROM

This device supports booting from internal flash with the reset vectors located at
addresses 0x0 (initial SP_main), 0x4 (initial PC).

The device is also able to boot from ROM. The ROM start address is from 0x1C00_0000.
When boot from ROM, it remaps all vector fetch to ROM base address. ROM code start
pointer locates in ROM vector table which address is 0x1C00_0000 where stack pointer
is offset 0x0 and reset vector is offset 0x4. Vector table and stack pointer are valid out of
reset. RCM mode register is cleared by software when Boot ROM completes, this
disables remapping of vector fetches. Boot source can change between reset, but is
always known before core reset negation. NMI input is disabled to platform when
booting from ROM. See FOPT section and Reset Control Module for more detail options.

The boot options can be overridden by using RCM_FM[2:1] and RCM_MR[2:1] which
can be written by software. The boot source remains set until the next System Reset or
software can write logic one to clear one or both of the mode bits.

6.3.2 FOPT boot options

The Flash Option (FOPT) register in the Flash Memory module (FTFA_FOPT) allows
the user to customize the operation of the MCU at boot time. The register contains read­only bits that are loaded from the NVM's option byte in the flash configuration field. The
default setting for all values in the FTFA_FOPT register is logic 1 since it is copied from
the option byte residing in flash, which has all bits as logic 1 in the flash erased state. To
configure for alternate settings, program the appropriate bits in the NVM option byte.
The new settings will take effect on subsequent POR, VLLSx recoveries, and any system
reset. For more details on programming the option byte, see the flash memory chapter.

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Boot

The MCU uses FTFA_FOPT to configure the device at reset as shown in the following
table. An FTFA_FOPT value of 0x00 is invalid and will be ignored. The FOPT register is
written to 0xFF if the contents of the Flash nonvolatile option are 0x00.

Table 6-2. Flash Option Register (FTFA_FOPT) definition

Bit

Num

7-6 BOOTSRC_SEL Boot Source Selection: these bits select the boot sources if boot pin option bit

5 FAST_INIT Selects initialization speed on POR, VLLSx, and any system reset.

3 RESET_PIN_CFG Enables/disables control for the RESET pin.

2 NMI_DIS Enables/disables control for the NMI function.

1 BOOTPIN_OPT External pin selects boot options

4,0 LPBOOT Controls the reset value of OUTDIV1 value in SIM_CLKDIV1 register, and the state of the

Field Value Definition

BOOTPIN_OPT = 1
00 Boot from Flash
01 Reserved
10 Boot from ROM
11 Boot from ROM

0 Slower initialization: The flash initialization will be slower with the benefit of

reduced average current during this time. The duration of the recovery will be
controlled by the clock divider selection determined by the LPBOOT setting.

1 Fast Initialization: The flash has faster recoveries at the expense of higher current

during these times.

0 RESET pin is disabled following a POR and cannot be enabled as reset function.

When this option is selected, there could be a short period of contention during a
POR ramp where the device drives the pinout low prior to establishing the setting
of this option and releasing the reset function on the pin.

This bit is preserved through system resets and low-power modes. When RESET
pin function is disabled, it cannot be used as a source for low-power mode wake­up.

NOTE:

1 RESET_b pin is dedicated. The port is configured as open drain and pullup

enabled.

0 NMI interrupts are always blocked. The associated pin continues to default to NMI

pin controls with internal pullup enabled. When NMI pin function is disabled, it
cannot be used as a source for low-power mode wake-up.

1 NMI_b pin/interrupts reset default to enabled.

0 Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot

config function which is muxed with NMI pin. RESET pin must be enabled when
this option is selected.

1 Boot source configured by FOPT[7:6] ( BOOTSRC_SEL) bits

RUNM register in SMC_PMCTRL. Larger divide value selections produce lower average
power consumption during POR, VLLSx recoveries and reset sequencing and after reset
exit. The recovery times are also extended if the FAST_INIT option is not selected.

When the reset pin has been disabled and security has been enabled by
means of the FSEC register, a mass erase can be performed only by
setting both the Mass Erase and System Reset Request fields in the
MDM-AP register.

1

Table continues on the next page...

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Table 6-2. Flash Option Register (FTFA_FOPT) definition

(continued)

Chapter 6 Reset and Boot

Bit

Num

1. Refer to Clock divider values after reset and RCM_FM, RCM_MR in the Reset Control Module (RCM) for details.

Field Value Definition

00 Core and system clock divider (OUTDIV1) is 0x7 (divide by 8). Device is configured

for VLPR mode on exit from reset.

01 Core and system clock divider (OUTDIV1) is 0x3 (divide by 4). Device is configured

for VLPR mode on exit from reset.

10 Core and system clock divider (OUTDIV1) is 0x1 (divide by 2). Device is configured

for RUN mode on exit from reset.

11 Core and system clock divider (OUTDIV1) is 0x0 (divide by 1). Device is configured

for RUN mode on exit from reset.

6.3.3 Boot sequence

At power up, the on-chip regulator holds the system in a POR state until the input supply
exceeds the POR threshold. The system continues to be held in this static state until the
internally regulated supplies have reached a safe operating voltage as determined by the
LVD. The Reset Controller logic then controls a sequence to exit reset.

1. A system reset is held on internal logic, the RESET pin is driven out low, and the
MCG-Lite is enabled in its default clocking mode.

2. Required clocks are enabled (system clock, flash clock, and any bus clocks that do
not have clock gate control reset to disabled).
The system reset on internal logic continues to be held, but the Flash Controller is

3.
released from reset and begins initialization operation while the Reset Control logic
continues to drive the

RESET pin out low.

4. Early in reset sequencing, the NVM option byte is read and stored to the FOPT
register of the Flash Memory module (FTFA_FOPT). If the bits associated with
FTFA_FOPT[LPBOOT] are programmed for an alternate clock divider reset value,
the system/core clock is switched to a slower clock speed. If
FTFA_FOPT[FAST_INIT] is programmed clear, the flash initialization switches to
slower clock resulting longer recovery times.
When flash Initialization completes, the

5.

RESET pin is released. If RESET continues
to be asserted (an indication of a slow rise time on the RESET pin or external drive
in low), the system continues to be held in reset. Once the RESET pin is detected
high, the core clock is enabled and the system is released from reset.

6. When the system exits reset, the processor sets up the stack, program counter (PC),
and link register (LR). The processor reads the start SP (SP_main) from vector-table
offset 0. The core reads the start PC from vector-table offset 4. LR is set to
0xFFFF_FFFF. The next sequence of events depends on the NMI/BOOTCFG0 input

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Boot

and FTFA_FOPT[NMI_DIS] and FTFA_FOPT[BOOTSRC_SEL] and
FTFA_FOPT[BOOTPIN_OPT] as well as RCM_FM[FORCEROM] and
RCM_MR[BOOTROM](See Table 6-2 and RCM block guide) :

• If the NMI/BOOTCFG0 input is high or the NMI function is disabled in
FTFA_FOPT, the CPU begins execution at the PC location.

• If the NMI/BOOTCFG0 input is low, the NMI function is enabled in
FTFA_FOPT, and FTFA_FOPT[BOOTPIN_OPT] = 1, this results in an NMI
interrupt. The processor executes an Exception Entry and reads the NMI
interrupt handler address from vector-table offset 8. The CPU begins execution
at the NMI interrupt handler.

• When FTFA_FOPT[BOOTPIN_OPT] = 0, it forces boot from ROM if NMI/
BOOTCFG0 pin set to 0.

NOTE

If the NMI function is not required, either for an interrupt or
wake up source, it is recommended that the NMI function be
disabled by clearing NMI_DIS in the FOPT register.

Subsequent system resets follow this same reset flow.

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Chapter 7
Power Management

7.1 Introduction

Information about the various chip power modes and functionality of the individual
modules in these modes can be found here.

See AN4503: Power Management for Kinetis and ColdFire+ MCUs for further details on
power management techniques.

7.2 Clocking modes

Information found here describes the various clocking modes supported on this device.

7.2.1 Partial Stop

Partial Stop is a clocking option that can be taken instead of entering Stop mode and is
configured in the SMC Stop Control Register (SMC_STOPCTRL). The Stop mode is
only partially entered, which leaves some additional functionality alive at the expense of
higher power consumption. Partial Stop can be entered from either Run mode or VLP
Run mode.

When configured for PSTOP2, only the core and system clocks are gated and the bus
clock remains active. The bus masters and bus slaves clocked by the system clock enter
Stop mode, but the bus slaves clocked by bus clock remain in Run (or VLP Run) mode.
The clock generators in the MCG and the on-chip regulator in the PMC also remain in
Run (or VLP Run) mode. Exit from PSTOP2 can be initiated by a reset, an asynchronous
interrupt from a bus master or bus slave clocked by the system clock, or a synchronous
interrupt from a bus slave clocked by the bus clock. If configured, a DMA request (using
the asynchronous DMA wakeup) can also be used to exit Partial Stop for the duration of a
DMA transfer before the device is transitioned back into PSTOP2.

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Clocking modes

When configured for PSTOP1, both the system clock and bus clock are gated. All bus
masters and bus slaves enter Stop mode, but the clock generators in the MCG and the on­chip regulator in the PMC remain in Run (or VLP Run) mode. Exit from PSTOP1 can be
initiated by a reset or an asynchronous interrupt from a bus master or bus slave. If
configured, an asynchronous DMA request can also be used to exit Partial Stop for the
duration of a DMA transfer before the device is transitioned back into PSTOP1.

PSTOP1 is functionally similar to Stop mode, but offers faster wake-up at the expense of
higher power consumption. Another benefit is that it keeps all of the MCG clocks
enabled, which can be useful for some of the asynchronous peripherals that can remain
functional in Stop modes.

7.2.2 DMA Wakeup

The DMA can be configured to wake the device on a DMA request whenever it is placed
in Stop mode. The wake-up is configured per DMA channel and is supported in Compute
Operation, PSTOP, STOP, and VLPS low power modes.

When a DMA wake-up is detected in PSTOP, STOP or VLPS then the device will initiate
a normal exit from the low power mode. This can include restoring the on-chip regulator
and internal power switches, enabling the clock generators in the MCG, enabling the
system and bus clocks (but not the core clock) and negating the stop mode signal to the
bus masters and bus slaves. The only difference is that the CPU will remain in the low
power mode with the CPU clock disabled.

During Compute Operation, a DMA wake-up will initiate a normal exit from Compute
Operation. This includes enabling the clocks and negating the stop mode signal to the bus
masters and bus slaves. The core clock always remains enabled during Compute
Operation.

Since the DMA wakeup will enable the clocks and negate the stop mode signals to all bus
masters and slaves, software needs to ensure that bus masters and slaves that are not
involved with the DMA wake-up and transfer remain in a known state. That can be
accomplished by disabling the modules before entry into the low power mode or by
setting the Doze enable bit in selected modules.

Once the DMA request that initiated the wake-up negates and the DMA completes the
current transfer, the device will transition back to the original low-power mode. This
includes requesting all non-CPU bus masters to enter Stop mode and then requesting bus
slaves to enter Stop mode. In STOP and VLPS modes the MCG and PMC would then
also enter their appropriate modes.

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Chapter 7 Power Management

NOTE

If the requested DMA transfer cannot cause the DMA request
to negate then the device will remain in a higher power state
until the low power mode is fully exited.

An enabled DMA wake-up can cause an aborted entry into the low power mode, if the
DMA request asserts during the stop mode entry sequence (or reentry if the request
asserts during a DMA wakeup) and can cause the SMC to assert its Stop Abort flag. Once
the DMA wake-up completes, entry into the low power mode will restart.

An interrupt that occurs during a DMA wake-up will cause an immediate exit from the
low power mode (this is optional for Compute Operation) without impacting the DMA
transfer.

A DMA wake-up can be generated by either a synchronous DMA request or an
asynchronous DMA request. Not all peripherals can generate an asynchronous DMA
request in stop modes, although in general if a peripheral can generate synchronous DMA
requests and also supports asynchronous interrupts in stop modes, then it can generate an
asynchronous DMA request.

7.2.3 Compute Operation

Compute Operation is an execution or compute-only mode of operation that keeps the
CPU enabled with full access to the SRAM and Flash read port, but places all other bus
masters and bus slaves into their stop mode. Compute Operation can be enabled in either
Run mode or VLP Run mode.

NOTE

Do not enter any Stop mode without first exiting Compute
Operation.

Because Compute Operation reuses the Stop mode logic (including the staged entry with
bus masters disabled before bus slaves), any bus master or bus slave that can remain
functional in Stop mode also remains functional in Compute Operation, including
generation of asynchronous interrupts and DMA requests. When enabling Compute
Operation in Run mode, module functionality for bus masters and slaves is the equivalent
of STOP mode. When enabling Compute Operation in VLP Run mode, module
functionality for bus masters and slaves is the equivalent of VLPS mode. The MCG,
PMC, SRAM, and Flash read port are not affected by Compute Operation, although the
Flash register interface is disabled.

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Clocking modes

During Compute Operation, the AIPS peripheral space is disabled and attempted accesses
generate bus errors. The private peripheral space remains accessible during Compute
Operation, including the MCM, NVIC, IOPORT, and SysTick. Although access to the
GPIO registers via the IOPORT is supported, the GPIO Port Data Input registers do not
return valid data since clocks are disabled to the Port Control and Interrupt modules. By
writing to the GPIO Port Data Output registers, it is possible to control those GPIO ports
that are configured as output pins.

Compute Operation is controlled by the CPO register in the MCM (MCM_CPO), which
is only accessible to the CPU. Setting or clearing MCM_CPO[CPOREQ] initiates entry
or exit into Compute Operation. Compute Operation can also be configured to exit
automatically on detection of an interrupt, which is required in order to service most
interrupts. Only the core system interrupts (exceptions, including NMI and SysTick) and
any edge-sensitive interrupts can be serviced without exiting Compute Operation.

• When entering Compute Operation, the CPOACK status field in the CPO register of
MCM module (MCM_CPO[CPOACK]) indicates when entry has completed.

• When exiting Compute Operation in Run mode, MCM_CPO[CPOACK] negates
immediately.

• When exiting Compute Operation in VLP Run mode, the exit is delayed to allow the
PMC to handle the change in power consumption. This delay means that
MCM_CPO[CPOACK] is polled to determine when the AIPS peripheral space can
be accessed without generating a bus error.

The DMA wake-up is also supported during Compute Operation and causes
MCM_CPO[CPOACK] to clear and the AIPS peripheral space to be accessible for the
duration of the DMA wakeup. At the completion of the DMA wake-up, the device
transitions back into Compute Operation.

7.2.4 Peripheral Doze

Several peripherals support a Peripheral Doze mode, where a register bit can be used to
disable the peripheral for the duration of a low-power mode. The flash memory can also
be placed in a low-power state during Peripheral Doze via a register bit in the SIM.

Peripheral Doze is defined to include all of the modes of operation listed below.

• The CPU is in Wait mode.
The CPU is in Stop mode, including the entry sequence and for the duration of a

•
DMA wakeup.

• The CPU is in Compute Operation, including the entry sequence and for the duration
of a DMA wakeup.

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Chapter 7 Power Management

Peripheral Doze can therefore be used to disable selected bus masters or slaves for the
duration of WAIT or VLPW mode. It can also be used to disable selected bus slaves
immediately on entry into any stop mode (or Compute Operation), instead of waiting for
the bus masters to acknowledge the entry as part of the stop entry sequence. Finally, it
can be used to disable selected bus masters or slaves that should remain inactive during a
DMA wakeup.

If the flash memory is not being accessed during WAIT and PSTOP modes, then the
Flash Doze mode can be used to reduce power consumption, at the expense of a slightly
longer wake-up when executing code and vectors from flash. It can also be used to reduce
power consumption during Compute Operation when executing code and vectors from
SRAM.

7.2.5 Clock gating

To conserve power, the clocks to most modules can be turned off using the SCGCx
registers in the SIM module. The bits of these registers are cleared after any reset, which
disables the clock to the corresponding module. Prior to initializing a module, set the
corresponding bit in the SCGCx register to enable the clock. Before turning off the clock,
make sure to disable the module. For more details, see the Clock Distribution and SIM
chapters.

7.3 Power modes

The Power Management Controller (PMC) provides multiple power options to allow the
user to optimize power consumption for the level of functionality needed.

Depending on the stop requirements of the user application, a variety of stop modes are
available that provide state retention, partial power-down or full power-down of certain
logic and/or memory. I/O states are held in all modes of operation. The following table
compares the various power modes available.

For each run mode, there is a corresponding Wait and Stop mode. Wait modes are similar
to ARM Sleep modes. Stop modes (VLPS, STOP) are similar to ARM Sleep Deep mode.
The Very Low Power Run (VLPR) operating mode can drastically reduce runtime power
when the maximum bus frequency is not required to handle the application needs.

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Power modes

The three primary modes of operation are Run, Wait, and Stop. The WFI instruction
invokes both Wait and Stop modes for the chip. The primary modes are augmented in a
number of ways to provide lower power based on application needs.

Table 7-1. Chip power modes

Chip mode Description Core mode Normal

recovery

method

Normal Run Allows maximum performance of chip.

• Default mode out of reset

• On-chip voltage regulator is on.

Normal Wait -

via WFI

Normal Stop -

via WFI

VLPR (Very

Low-Power Run)

VLPW (Very

Low-Power

Wait) -via WFI

VLPS (Very

Low-Power

Stop)-via WFI

LLS (Low-

Leakage Stop)

Allows peripherals to function while the core is in Sleep mode,
reducing power.

• NVIC remains sensitive to interrupts

• Peripherals continue to be clocked.

Places chip in static state. Lowest power mode that retains all registers
while maintaining LVD protection.

• NVIC is disabled.

• AWIC is used to wake up from interrupt.

• Peripheral clocks are stopped.

On-chip voltage regulator is in a low-power mode that supplies only
enough power to run the chip at a reduced frequency. Only MCG-Lite
modes LIRC and EXT can be used in VLPR.

• Reduced frequency Flash access mode (1 MHz)

• LVD off

• In LIRC clock mode, only the internal reference oscillator
(LIRC8M) is available to provide a low power nominal 4 MHz
source for the core with the nominal bus and flash clock required
to be <1 MHz

• Alternatively, EXT clock mode can be used with an external
clock or the crystal oscillator providing the clock source.

Same as VLPR but with the core in Sleep mode to further reduce
power.

• NVIC remains sensitive to interrupts (CPU clk = ON).

• On-chip voltage regulator is in a low-power mode that supplies
only enough power to run the chip at a reduced frequency.

Places chip in static state with LVD operation off. Lowest power mode
with ADC and pin interrupts functional.

• Peripheral clocks are stopped, but OSC, LPTMR, RTC, CMP can
be used.

• UART, LPUART and TPM can optionally be enabled if their clock
source is enabled.

• NVIC is disabled (CPU clk = OFF); AWIC is used to wake up
from interrupt.

• On-chip voltage regulator is in a low-power mode that supplies
only enough power to run the chip at a reduced frequency.

• All SRAM is operating (content retained and I/O states held).

State retention power mode

• Most peripherals are in state retention mode (with clocks
stopped), but OSC, LLWU,LPTMR, RTC, CMP can be used.

• NVIC is disabled; LLWU is used to wake up.

Table continues on the next page...

Run —

Sleep Interrupt

Sleep Deep Interrupt

Run —

Sleep Interrupt

Sleep Deep Interrupt

Sleep Deep Wake-up

Interrupt

1

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Chapter 7 Power Management

Table 7-1. Chip power modes (continued)

Chip mode Description Core mode Normal

recovery

method

VLLS3 (Very

Low-Leakage

Stop3)

VLLS1 (Very

Low-Leakage

Stop1)

VLLS0 (Very

Low-Leakage

Stop 0)

NOTE:

• All SRAM is operating (content retained and I/O states held).

• Most peripherals are disabled (with clocks stopped), but OSC,
LLWU, LPTMR, RTC, CMP can be used.

• NVIC is disabled; LLWU is used to wake up.

• SRAM_U and SRAM_L remain powered on (content retained
and I/O states held).

• Most peripherals are disabled (with clocks stopped), but OSC,
LLWU, LPTMR, RTC, CMP can be used.

• NVIC is disabled; LLWU is used to wake up.

• All of SRAM_U and SRAM_L are powered off.

• The 32-byte system register file remains powered for customer­critical data

• Most peripherals are disabled (with clocks stopped), but LLWU,
LPTMR, RTC can be used.

• NVIC is disabled; LLWU is used to wake up.

• All of SRAM_U and SRAM_L are powered off.

• The 32-byte system register file remains powered for customer­critical data

• LPO disabled, optional POR brown-out detection

The LLWU interrupt must not be masked by
the interrupt controller to avoid a scenario
where the system does not fully exit stop
mode on an LLS recovery

Sleep Deep Wake-up Reset

Sleep Deep Wake-up Reset

Sleep Deep Wake-up Reset

2

2

2

1. Resumes Normal Run mode operation by executing the LLWU interrupt service routine.

2. Follows the reset flow with the LLWU interrupt flag set for the NVIC.

7.4 Entering and exiting power modes

The WFI instruction invokes wait and stop modes for the chip. The processor exits the
low-power mode via an interrupt.

For LLS and VLLS modes, the wake-up sources are limited to LLWU generated wake­ups,NMI_b pin, or RESET_b pin assertions. When the NMI_b pin or RESET_b pin have
been disabled through associated FTFA_FOPT settings, then these pins are ignored as
wakeup sources. The wake-up flow from VLLSx is always through reset.

NOTE

The WFE instruction can have the side effect of entering a low­power mode, but that is not its intended usage. See ARM
documentation for more on the WFE instruction.

On VLLS recoveries, the I/O pins continue to be held in a static state after code execution
begins, allowing software to reconfigure the system before unlocking the I/O. RAM is
retained in VLLS3 only.

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Module operation in low-power modes

7.5 Module operation in low-power modes

The table found here illustrates the functionality of each module while the chip is in each
of the low power modes.

The standard behavior is shown with some exceptions for Compute Operation (CPO) and
Partial Stop2 (PSTOP2).

Debug modules are discussed separately; see Debug in low-power modes. Number
ratings (such as 4 MHz and 1 Mbit/s) represent the maximum frequencies or maximum
data rates per mode. Following is list of terms also used in the table.

• FF = Full functionality. In VLPR and VLPW, the system frequency is limited, but if
a module does not have a limitation in its functionality, it is still listed as FF.

• Async operation = Fully functional with alternate clock source, provided the selected
clock source remains enabled

• static = Module register states and associated memories are retained.

• powered = Memory is powered to retain contents.

• low power = Memory is powered to retain contents in a lower power state

• OFF = Modules are powered off; module is in reset state upon wake-up. For clocks,
OFF means disabled.

• wakeup = Modules can serve as a wake-up source for the chip.

Table 7-2. Module operation in low power modes

Modules VLPR VLPW Stop VLPS LLS VLLSx

Core modules

NVIC FF FF static static static OFF

System modules

Mode Controller FF FF FF FF FF FF

1

LLWU
Regulator low power low power ON low power low power low power in

LVD disabled disabled ON disabled disabled disabled
Brown-out

Detection

DMA FF

static static static static FF FF

VLLS3, OFF in

ON ON ON ON ON ON in VLLS1/3,

FF Async operation Async operation static OFF

Async operation

in CPO

Table continues on the next page...

2

VLLS0/1

optionally

disabled in

VLLS0

3

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Chapter 7 Power Management

Table 7-2. Module operation in low power modes (continued)

Modules VLPR VLPW Stop VLPS LLS VLLSx

COP watchdog FF

static in CPO

1kHz LPO ON ON ON ON ON ON in VLLS1/3,

System
oscillator (OSC)

MCG_Lite 4 MHz 4 MHz static -

Core clock 4 MHz max OFF OFF OFF OFF OFF
Platform clock 4 MHz max 4 MHz max OFF OFF OFF OFF
System clock 4 MHz max

Bus clock 1 MHz max

Flash 1 MHz max

SRAM_U and
SRAM_L

System Register
File

USB FS static static static static static OFF
USB Voltage

Regulator
LPUART0,

LPUART1

OSCERCLK

max of 16MHz

crystal

OFF in CPO

OFF in CPO

access - no

program

No register

access in CPO

low power low power low power low power low power low power in

powered powered powered powered powered powered

optional optional optional optional optional optional

1 Mbit/s

Async operation

in CPO

FF Optional work

with clock

source enabled

in stop mode

FF in PSTOP2

Clocks

OSCERCLK

max of 16MHz

crystal

4 MHz max OFF OFF OFF OFF

1 MHz max OFF

Memory and memory interfaces

low power low power low power OFF OFF

Communication interfaces

1 Mbit/s Async operation

OSCERCLK

optional

MCGIRCLK

optional

24 MHz max in

PSTOP2 from

RUN

1 MHz max in
PSTOP2 from

VLPR

FF in PSTOP2

Optional work

with clock

source enabled

in stop mode

OSCERCLK

max of 16MHz

crystal

static -

MCGIRCLK

optional

OFF OFF OFF

Async operation static OFF

static OFF

OSCERCLK

max of 16MHz

crystal

static - no clock

output

OFF in VLLS0

OSCERCLK

max of 16MHz

crystal in

VLLS1/3, OFF in

VLLS0

VLLS3, OFF in

VLLS0/1

OFF

Table continues on the next page...

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Module operation in low-power modes

Table 7-2. Module operation in low power modes (continued)

Modules VLPR VLPW Stop VLPS LLS VLLSx

UART2 62.5 kbit/s

static, wakeup

on edge in CPO

SPI0 (without
FIFO)

master mode

500 kbit/s,

slave mode 250

kbit/s

static, slave

mode receive in

CPO

SPI1 (with FIFO) master mode 2

Mbit/s,

slave mode 1

Mbit/s

static, slave

mode receive in

CPO

I2C0 100 kbit/s

static, address
match wakeup

in CPO

I2C1 100 kbit/s

static, address
match wakeup

in CPO

I2S FF

Async operation

in CPO

FlexIO FF FF FF FF static OFF

TPM FF

Async operation

in CPO

PIT FF

static in CPO

LPTMR FF FF Async operation

RTC FF

Async operation

in CPO

16-bit ADC FF FF ADC internal

62.5 kbit/s static, wakeup
on edge

static, wakeup

on edge

static OFF

FF in PSTOP2

master mode

500 kbit/s,

slave mode 250

static, slave

mode receive

FF in PSTOP2

static, slave

mode receive

static OFF

kbit/s

master mode 2

Mbit/s,

static, slave

mode receive

static, slave

mode receive

static OFF

slave mode 1

Mbit/s

100 kbit/s static, address

match wakeup

100 kbit/s static, address

match wakeup

FF Async operation

static, address

static OFF

match wakeup

static, address

static OFF

match wakeup

Async operation static OFF

FF in PSTOP2

Timers

FF Async operation

Async operation static OFF

FF in PSTOP2

FF static static static OFF

Async operation Async operation Async

FF in PSTOP2

FF Async operation

Async operation Async operation Async

FF in PSTOP2

Analog

clock only

ADC internal

clock only

static OFF

FF in PSTOP2

Table continues on the next page...

operation

operation

4

5

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Chapter 7 Power Management

Table 7-2. Module operation in low power modes (continued)

Modules VLPR VLPW Stop VLPS LLS VLLSx

ADC internal

clock only in

CPO

6

CMP

6-bit DAC FF

12-bit DAC FF

Internal Voltage
Reference
(VREF)

GPIO FF

FF

HS or LS

compare in CPO

static in CPO

static in CPO

FF

static in CPO

IOPORT write

only in CPO

FF HS or LS

compare

FF in PSTOP2

FF static

FF in PSTOP2

FF static

FF in PSTOP2

FF static

FF in PSTOP2

Human-machine interfaces

FF static output,

wakeup input

FF in PSTOP2

HS or LS

compare

static static static, OFF in

static static static, OFF in

static static static, OFF in

static output,

wakeup input

LS compare LS compare in

VLLS1/3, OFF in

static, pins

latched

VLLS0

VLLS0

VLLS0

VLLS0

OFF, pins

latched

1. Using the LLWU module, the external pins available for this chip do not require the associated peripheral function to be
enabled. It only requires the function controlling the pin (GPIO or peripheral) to be configured as an input to allow a
transition to occur to the LLWU.

2. Since LPO clock source is disabled, filters will be bypassed during VLLS0.

3. STOPCTRL[PORPO] in the SMC module controls this option.

4. LPO clock source is not available in VLLS0. Also, to use system OSC in VLLS0 it must be configured for bypass (external
clock) operation. Pulse counting is available in all modes.

5. In VLLS0 the only clocking option is from RTC_CLKIN.

6. CMP in stop or VLPS supports high speed or low speed external pin to pin or external pin to DAC compares. CMP in LLS
or VLLSx only supports low speed external pin to pin or external pin to DAC compares.

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Module operation in low-power modes

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100 Freescale Semiconductor, Inc.