NXP Semiconductors MKL27Z128VFM4, MKL27Z256VMP4, MKL27Z256VFM4, MKL27Z128VLH4, MKL27Z256VLH4 Reference Manual

KL27 Sub-Family Reference Manual

Supports: MKL27Z128VFM4, MKL27Z256VFM4, MKL27Z128VFT4,

MKL27Z256VFT4, MKL27Z128VMP4, MKL27Z256VMP4,

MKL27Z128VLH4, MKL27Z256VLH4

Document Number: KL27P64M48SF6RM

Rev. 5, 01/2016

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Contents

Section number Title Page

Chapter 1

About This Document

1.1 Overview.......................................................................................................................................................................37

1.1.1 Purpose...........................................................................................................................................................37

1.1.2 Audience........................................................................................................................................................ 37

1.2 Conventions.................................................................................................................................................................. 37

1.2.1 Numbering systems........................................................................................................................................37

1.2.2 Typographic notation..................................................................................................................................... 38

1.2.3 Special terms.................................................................................................................................................. 38

Chapter 2

Introduction

2.1 Overview.......................................................................................................................................................................39

2.1.1 Sub-family introduction................................................................................................................................. 39

2.2 Module functional categories........................................................................................................................................40

2.2.1 ARM Cortex-M0+ core modules................................................................................................................... 41

2.2.2 System modules............................................................................................................................................. 41

2.2.3 Memories and memory interfaces..................................................................................................................42

2.2.4 Clocks.............................................................................................................................................................42

2.2.5 Security and integrity modules...................................................................................................................... 43

2.2.6 Analog modules............................................................................................................................................. 43

2.2.7 Timer modules............................................................................................................................................... 43

2.2.8 Communication interfaces............................................................................................................................. 44

2.2.9 Human-machine interfaces............................................................................................................................ 45

2.3 Module to module interconnects...................................................................................................................................45

2.3.1 Interconnection overview...............................................................................................................................45

2.3.2 Analog reference options............................................................................................................................... 47

Chapter 3

Core Overview

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3.1 ARM Cortex-M0+ core introduction............................................................................................................................49

3.1.1 Buses, interconnects, and interfaces.............................................................................................................. 49

3.1.2 System tick timer........................................................................................................................................... 49

3.1.3 Debug facilities.............................................................................................................................................. 49

3.1.4 Core privilege levels...................................................................................................................................... 50

3.2 Nested vectored interrupt controller (NVIC) ...............................................................................................................50

3.2.1 Interrupt priority levels.................................................................................................................................. 50

3.2.2 Non-maskable interrupt..................................................................................................................................50

3.2.3 Interrupt channel assignments........................................................................................................................50

3.3 AWIC introduction....................................................................................................................................................... 53

3.3.1 Wake-up sources............................................................................................................................................ 53

Chapter 4

Memory Map

4.1 Introduction...................................................................................................................................................................55

4.2 Flash memory............................................................................................................................................................... 55

4.2.1 Flash memory map.........................................................................................................................................55

4.2.2 Flash security................................................................................................................................................. 56

4.2.3 Flash modes....................................................................................................................................................56

4.2.4 Erase all flash contents...................................................................................................................................56

4.2.5 FTFA_FOPT register..................................................................................................................................... 57

4.3 SRAM........................................................................................................................................................................... 57

4.3.1 SRAM sizes....................................................................................................................................................57

4.3.2 SRAM ranges................................................................................................................................................. 57

4.3.3 SRAM retention in low power modes............................................................................................................58

4.4 System Register file......................................................................................................................................................58

4.5 System memory map.....................................................................................................................................................59

4.6 Bit Manipulation Engine...............................................................................................................................................60

4.7 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................60

4.7.1 Read-after-write sequence and required serialization of memory operations................................................60

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4.7.2 Peripheral bridge (AIPS-Lite) memory map..................................................................................................61

Chapter 5

Clock Distribution

5.1 Introduction...................................................................................................................................................................65

5.2 Programming model......................................................................................................................................................65

5.3 High-level device clocking diagram............................................................................................................................. 65

5.4 Clock definitions...........................................................................................................................................................66

5.4.1 Device clock summary...................................................................................................................................67

5.5 Internal clocking requirements..................................................................................................................................... 69

5.5.1 Clock divider values after reset......................................................................................................................70

5.5.2 VLPR mode clocking.....................................................................................................................................70

5.6 Clock gating..................................................................................................................................................................71

5.7 Module clocks...............................................................................................................................................................71

5.7.1 PMC 1-kHz LPO clock.................................................................................................................................. 72

5.7.2 COP clocking................................................................................................................................................. 72

5.7.3 RTC clocking................................................................................................................................................. 73

5.7.4 RTC_CLKOUT and CLKOUT32K clocking................................................................................................ 73

5.7.5 LPTMR clocking............................................................................................................................................74

5.7.6 TPM clocking.................................................................................................................................................75

5.7.7 USB FS device only controller clocking........................................................................................................75

5.7.8 LPUART clocking......................................................................................................................................... 76

5.7.9 FlexIO clocking..............................................................................................................................................77

5.7.10 I2S/SAI clocking............................................................................................................................................78

Chapter 6

Reset and Boot

6.1 Introduction...................................................................................................................................................................79

6.2 Reset..............................................................................................................................................................................79

6.2.1 Power-on reset (POR).................................................................................................................................... 80

6.2.2 System reset sources...................................................................................................................................... 80

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6.2.3 MCU resets.................................................................................................................................................... 83

6.2.4 RESET pin .................................................................................................................................................... 84

6.3 Boot...............................................................................................................................................................................84

6.3.1 Boot sources................................................................................................................................................... 85

6.3.2 FOPT boot options......................................................................................................................................... 85

6.3.3 Boot sequence................................................................................................................................................ 87

Chapter 7

Power Management

7.1 Introduction...................................................................................................................................................................89

7.2 Clocking modes............................................................................................................................................................ 89

7.2.1 Partial Stop..................................................................................................................................................... 89

7.2.2 DMA Wakeup................................................................................................................................................ 90

7.2.3 Compute Operation........................................................................................................................................ 91

7.2.4 Peripheral Doze..............................................................................................................................................92

7.2.5 Clock gating................................................................................................................................................... 93

7.3 Power modes.................................................................................................................................................................93

7.4 Entering and exiting power modes............................................................................................................................... 95

7.5 Module operation in low-power modes........................................................................................................................ 96

Chapter 8

Security

8.1 Introduction...................................................................................................................................................................101

8.1.1 Flash security................................................................................................................................................. 101

8.1.2 Security interactions with other modules.......................................................................................................101

Chapter 9

Debug

9.1 Introduction...................................................................................................................................................................103

9.2 Debug port pin descriptions..........................................................................................................................................103

9.3 SWD status and control registers..................................................................................................................................104

9.3.1 MDM-AP Control Register............................................................................................................................105

9.3.2 MDM-AP Status Register.............................................................................................................................. 106

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9.4 Debug resets..................................................................................................................................................................108

9.5 Micro Trace Buffer (MTB)...........................................................................................................................................108

9.6 Debug in low-power modes..........................................................................................................................................109

9.7 Debug and security....................................................................................................................................................... 110

Chapter 10

Pinouts and Packaging

10.1 Introduction...................................................................................................................................................................111

10.2 Signal multiplexing integration.................................................................................................................................... 111

10.2.1 Clock gating................................................................................................................................................... 112

10.2.2 Signal multiplexing constraints......................................................................................................................112

10.3 KL27 Signal Multiplexing and Pin Assignments......................................................................................................... 112

10.4 KL27 Family Pinouts....................................................................................................................................................115

10.5 Module Signal Description Tables................................................................................................................................118

10.5.1 Core modules................................................................................................................................................. 118

10.5.2 System modules............................................................................................................................................. 118

10.5.3 Clock modules................................................................................................................................................119

10.5.4 Analog............................................................................................................................................................119

10.5.5 Timer Modules...............................................................................................................................................120

10.5.6 Communication interfaces............................................................................................................................. 121

10.5.7 Human-machine interfaces (HMI).................................................................................................................124

Chapter 11

Port Control and Interrupts (PORT)

11.1 Chip-specific PORT information..................................................................................................................................125

11.2 Port control and interrupt summary..............................................................................................................................126

11.3 Introduction...................................................................................................................................................................127

11.4 Overview.......................................................................................................................................................................127

11.4.1 Features.......................................................................................................................................................... 127

11.4.2 Modes of operation........................................................................................................................................ 128

11.5 External signal description............................................................................................................................................129

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11.6 Detailed signal description............................................................................................................................................129

11.7 Memory map and register definition.............................................................................................................................129

11.7.1

11.7.2

11.7.3

11.7.4

11.8 Functional description...................................................................................................................................................139

11.8.1 Pin control......................................................................................................................................................139

11.8.2 Global pin control.......................................................................................................................................... 140

11.8.3 External interrupts..........................................................................................................................................140

Pin Control Register n (PORTx_PCRn).........................................................................................................135

Global Pin Control Low Register (PORTx_GPCLR)....................................................................................138

Global Pin Control High Register (PORTx_GPCHR)...................................................................................138

Interrupt Status Flag Register (PORTx_ISFR).............................................................................................. 139

Chapter 12

System Integration Module (SIM)

12.1 Chip-specific SIM information.....................................................................................................................................143

12.1.1 COP clocks.....................................................................................................................................................143

12.2 Introduction...................................................................................................................................................................143

12.2.1 Features.......................................................................................................................................................... 143

12.3 Memory map and register definition.............................................................................................................................144

12.3.1 System Options Register 1 (SIM_SOPT1).................................................................................................... 145

12.3.2 SOPT1 Configuration Register (SIM_SOPT1CFG)......................................................................................146

12.3.3 System Options Register 2 (SIM_SOPT2).................................................................................................... 148

12.3.4 System Options Register 4 (SIM_SOPT4).................................................................................................... 150

12.3.5 System Options Register 5 (SIM_SOPT5).................................................................................................... 151

12.3.6 System Options Register 7 (SIM_SOPT7).................................................................................................... 153

12.3.7 System Device Identification Register (SIM_SDID).....................................................................................154

12.3.8 System Clock Gating Control Register 4 (SIM_SCGC4)..............................................................................156

12.3.9 System Clock Gating Control Register 5 (SIM_SCGC5)..............................................................................158

12.3.10 System Clock Gating Control Register 6 (SIM_SCGC6)..............................................................................160

12.3.11 System Clock Gating Control Register 7 (SIM_SCGC7)..............................................................................162

12.3.12 System Clock Divider Register 1 (SIM_CLKDIV1).....................................................................................162

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12.3.13 Flash Configuration Register 1 (SIM_FCFG1)............................................................................................. 164

12.3.14 Flash Configuration Register 2 (SIM_FCFG2)............................................................................................. 165

12.3.15 Unique Identification Register Mid-High (SIM_UIDMH)............................................................................166

12.3.16 Unique Identification Register Mid Low (SIM_UIDML)............................................................................. 167

12.3.17 Unique Identification Register Low (SIM_UIDL)........................................................................................ 167

12.3.18 COP Control Register (SIM_COPC)............................................................................................................. 168

12.3.19 Service COP (SIM_SRVCOP).......................................................................................................................169

12.4 Functional description...................................................................................................................................................169

12.4.1 COP watchdog operation............................................................................................................................... 170

Chapter 13

Kinetis ROM Bootloader

13.1 Chip-Specific Information............................................................................................................................................173

13.2 Introduction...................................................................................................................................................................173

13.3 Functional Description..................................................................................................................................................175

13.3.1 Memory Maps................................................................................................................................................175

13.3.2 The Kinetis Bootloader Configuration Area (BCA)......................................................................................176

13.3.3 Start-up Process..............................................................................................................................................177

13.3.4 Clock Configuration.......................................................................................................................................179

13.3.5 Bootloader Entry Point...................................................................................................................................180

13.3.6 Bootloader Protocol....................................................................................................................................... 181

13.3.7 Bootloader Packet Types............................................................................................................................... 186

13.3.8 Bootloader Command API.............................................................................................................................193

13.3.9 Bootloader Exit state......................................................................................................................................208

13.4 Peripherals Supported...................................................................................................................................................209

13.4.1 I2C Peripheral................................................................................................................................................ 209

13.4.2 SPI Peripheral................................................................................................................................................ 211

13.4.3 USB peripheral...............................................................................................................................................213

13.5 Get/SetProperty Command Properties..........................................................................................................................217

13.5.1 Property Definitions.......................................................................................................................................218

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13.6 Kinetis Bootloader Status Error Codes.........................................................................................................................220

13.7 Bootloader errata...........................................................................................................................................................221

Chapter 14

System Mode Controller (SMC)

14.1 Chip-specific SMC information....................................................................................................................................223

14.2 Introduction...................................................................................................................................................................223

14.3 Modes of operation.......................................................................................................................................................223

14.4 Memory map and register descriptions.........................................................................................................................225

14.4.1 Power Mode Protection register (SMC_PMPROT).......................................................................................226

14.4.2 Power Mode Control register (SMC_PMCTRL)...........................................................................................227

14.4.3 Stop Control Register (SMC_STOPCTRL)...................................................................................................228

14.4.4 Power Mode Status register (SMC_PMSTAT)............................................................................................. 230

14.5 Functional description...................................................................................................................................................230

14.5.1 Power mode transitions..................................................................................................................................230

14.5.2 Power mode entry/exit sequencing................................................................................................................ 233

14.5.3 Run modes......................................................................................................................................................234

14.5.4 Wait modes.................................................................................................................................................... 236

14.5.5 Stop modes.....................................................................................................................................................237

14.5.6 Debug in low power modes........................................................................................................................... 240

Chapter 15

Power Management Controller (PMC)

15.1 Introduction...................................................................................................................................................................241

15.2 Features.........................................................................................................................................................................241

15.3 Low-voltage detect (LVD) system................................................................................................................................241

15.3.1 LVD reset operation.......................................................................................................................................242

15.3.2 LVD interrupt operation.................................................................................................................................242

15.3.3 Low-voltage warning (LVW) interrupt operation......................................................................................... 242

15.4 I/O retention..................................................................................................................................................................243

15.5 Memory map and register descriptions.........................................................................................................................243

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15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1).......................................................... 244

15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2).......................................................... 245

15.5.3 Regulator Status And Control register (PMC_REGSC)................................................................................246

Chapter 16

Miscellaneous Control Module (MCM)

16.1 Introduction...................................................................................................................................................................249

16.1.1 Features.......................................................................................................................................................... 249

16.2 Memory map/register descriptions............................................................................................................................... 249

16.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................250

16.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 250

16.2.3 Platform Control Register (MCM_PLACR)..................................................................................................251

16.2.4 Compute Operation Control Register (MCM_CPO)..................................................................................... 254

Chapter 17

Crossbar Switch Lite (AXBS-Lite)

17.1 Chip-specific AXBS-Lite information..........................................................................................................................257

17.1.1 Crossbar-light switch master assignments..................................................................................................... 257

17.1.2 Crossbar switch slave assignments................................................................................................................ 257

17.2 Introduction...................................................................................................................................................................257

17.2.1 Features.......................................................................................................................................................... 258

17.3 Memory Map / Register Definition...............................................................................................................................258

17.4 Functional Description..................................................................................................................................................258

17.4.1 General operation...........................................................................................................................................258

17.4.2 Arbitration......................................................................................................................................................259

17.5 Initialization/application information........................................................................................................................... 261

Chapter 18

Low-Leakage Wakeup Unit (LLWU)

18.1 LLWU interrupt............................................................................................................................................................263

18.1.1 Wake-up Sources........................................................................................................................................... 263

18.2 Introduction...................................................................................................................................................................264

18.2.1 Features.......................................................................................................................................................... 264

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18.2.2 Modes of operation........................................................................................................................................ 265

18.2.3 Block diagram................................................................................................................................................266

18.3 LLWU signal descriptions............................................................................................................................................267

18.4 Memory map/register definition...................................................................................................................................267

18.4.1 LLWU Pin Enable 1 register (LLWU_PE1)..................................................................................................268

18.4.2 LLWU Pin Enable 2 register (LLWU_PE2)..................................................................................................269

18.4.3 LLWU Pin Enable 3 register (LLWU_PE3)..................................................................................................270

18.4.4 LLWU Pin Enable 4 register (LLWU_PE4)..................................................................................................271

18.4.5 LLWU Module Enable register (LLWU_ME).............................................................................................. 272

18.4.6 LLWU Flag 1 register (LLWU_F1)...............................................................................................................274

18.4.7 LLWU Flag 2 register (LLWU_F2)...............................................................................................................276

18.4.8 LLWU Flag 3 register (LLWU_F3)...............................................................................................................277

18.4.9 LLWU Pin Filter 1 register (LLWU_FILT1)................................................................................................ 279

18.4.10 LLWU Pin Filter 2 register (LLWU_FILT2)................................................................................................ 280

18.5 Functional description...................................................................................................................................................281

18.5.1 LLS mode.......................................................................................................................................................282

18.5.2 VLLS modes.................................................................................................................................................. 282

18.5.3 Initialization................................................................................................................................................... 282

Chapter 19

Peripheral Bridge (AIPS-Lite)

19.1 Chip-specific AIPS-Lite information............................................................................................................................283

19.1.1 Number of peripheral bridges........................................................................................................................ 283

19.1.2 Memory maps................................................................................................................................................ 283

19.2 Introduction...................................................................................................................................................................283

19.2.1 Features.......................................................................................................................................................... 283

19.2.2 General operation...........................................................................................................................................284

19.3 Memory map/register definition...................................................................................................................................284

19.3.1 Master Privilege Register A (AIPS_MPRA)................................................................................................. 284

19.3.2

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Peripheral Access Control Register (AIPS_PACRn).....................................................................................286

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19.3.3

19.4 Functional description...................................................................................................................................................291

19.4.1 Access support............................................................................................................................................... 291

Peripheral Access Control Register (AIPS_n)............................................................................................... 0

Chapter 20

Direct Memory Access Multiplexer (DMAMUX)

20.1 Chip-specific DMAMUX information......................................................................................................................... 293

20.1.1 DMA MUX Request Sources........................................................................................................................ 293

20.1.2 DMA transfers via PIT trigger.......................................................................................................................295

20.2 Introduction...................................................................................................................................................................295

20.2.1 Overview........................................................................................................................................................295

20.2.2 Features.......................................................................................................................................................... 296

20.2.3 Modes of operation........................................................................................................................................ 296

20.3 External signal description............................................................................................................................................297

20.4 Memory map/register definition...................................................................................................................................297

20.4.1

20.5 Functional description...................................................................................................................................................298

20.5.1 DMA channels with periodic triggering capability........................................................................................299

20.5.2 DMA channels with no triggering capability.................................................................................................301

20.5.3 Always-enabled DMA sources...................................................................................................................... 301

20.6 Initialization/application information........................................................................................................................... 303

20.6.1 Reset...............................................................................................................................................................303

20.6.2 Enabling and configuring sources..................................................................................................................303

Channel Configuration register (DMAMUXx_CHCFGn)............................................................................ 297

Chapter 21

DMA Controller Module

21.1 Introduction...................................................................................................................................................................307

21.1.1 Overview........................................................................................................................................................307

21.1.2 Features.......................................................................................................................................................... 308

21.2 DMA Transfer Overview..............................................................................................................................................309

21.3 Memory Map/Register Definition.................................................................................................................................310

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21.3.1

21.3.2

21.3.3

21.3.4

21.4 Functional Description..................................................................................................................................................319

21.4.1 Transfer requests (Cycle-Steal and Continuous modes)................................................................................319

21.4.2 Channel initialization and startup.................................................................................................................. 320

21.4.3 Dual-Address Data Transfer Mode................................................................................................................321

21.4.4 Advanced Data Transfer Controls: Auto-Alignment.....................................................................................322

21.4.5 Termination....................................................................................................................................................323

Source Address Register (DMA_SARn)....................................................................................................... 311

Destination Address Register (DMA_DARn)............................................................................................... 312

DMA Status Register / Byte Count Register (DMA_DSR_BCRn)...............................................................313

DMA Control Register (DMA_DCRn)..........................................................................................................315

Chapter 22

Reset Control Module (RCM)

22.1 Introduction...................................................................................................................................................................325

22.2 Reset memory map and register descriptions............................................................................................................... 325

22.2.1 System Reset Status Register 0 (RCM_SRS0).............................................................................................. 326

22.2.2 System Reset Status Register 1 (RCM_SRS1).............................................................................................. 327

22.2.3 Reset Pin Filter Control register (RCM_RPFC)............................................................................................ 328

22.2.4 Reset Pin Filter Width register (RCM_RPFW)............................................................................................. 329

22.2.5 Force Mode Register (RCM_FM)..................................................................................................................331

22.2.6 Mode Register (RCM_MR)........................................................................................................................... 331

22.2.7 Sticky System Reset Status Register 0 (RCM_SSRS0).................................................................................332

22.2.8 Sticky System Reset Status Register 1 (RCM_SSRS1).................................................................................333

Chapter 23

Analog-to-Digital Converter (ADC)

23.1 Chip-specific ADC information....................................................................................................................................335

23.1.1 ADC instantiation information.......................................................................................................................335

23.1.2 DMA Support on ADC.................................................................................................................................. 335

23.1.3 ADC0 connections/channel assignment.........................................................................................................336

23.1.4 ADC analog supply and reference connections............................................................................................. 337

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23.1.5 Alternate clock............................................................................................................................................... 337

23.2 Introduction...................................................................................................................................................................338

23.2.1 Features.......................................................................................................................................................... 338

23.2.2 Block diagram................................................................................................................................................339

23.3 ADC signal descriptions...............................................................................................................................................340

23.3.1 Analog Power (VDDA)................................................................................................................................. 340

23.3.2 Analog Ground (VSSA).................................................................................................................................340

23.3.3 Voltage Reference Select...............................................................................................................................340

23.3.4 Analog Channel Inputs (ADx)....................................................................................................................... 341

23.3.5 Differential Analog Channel Inputs (DADx).................................................................................................341

23.4 Memory map and register definitions...........................................................................................................................341

23.4.1

23.4.2

23.4.3

23.4.4

23.4.5

23.4.6

23.4.7

23.4.8

23.4.9

23.4.10

23.4.11

23.4.12

23.4.13

23.4.14

ADC Status and Control Registers 1 (ADCx_SC1n).....................................................................................343

ADC Configuration Register 1 (ADCx_CFG1).............................................................................................346

ADC Configuration Register 2 (ADCx_CFG2).............................................................................................347

ADC Data Result Register (ADCx_Rn).........................................................................................................348

Compare Value Registers (ADCx_CVn)....................................................................................................... 350

Status and Control Register 2 (ADCx_SC2)..................................................................................................351

Status and Control Register 3 (ADCx_SC3)..................................................................................................353

ADC Offset Correction Register (ADCx_OFS).............................................................................................354

ADC Plus-Side Gain Register (ADCx_PG)...................................................................................................355

ADC Minus-Side Gain Register (ADCx_MG).............................................................................................. 355

ADC Plus-Side General Calibration Value Register (ADCx_CLPD)........................................................... 356

ADC Plus-Side General Calibration Value Register (ADCx_CLPS)............................................................357

ADC Plus-Side General Calibration Value Register (ADCx_CLP4)............................................................ 357

ADC Plus-Side General Calibration Value Register (ADCx_CLP3)............................................................ 358

23.4.15

23.4.16

23.4.17

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ADC Plus-Side General Calibration Value Register (ADCx_CLP2)............................................................ 358

ADC Plus-Side General Calibration Value Register (ADCx_CLP1)............................................................ 359

ADC Plus-Side General Calibration Value Register (ADCx_CLP0)............................................................ 359

ADC Minus-Side General Calibration Value Register (ADCx_CLMD).......................................................360

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23.4.19

23.4.20

23.4.21

23.4.22

23.4.23

23.4.24

23.5 Functional description...................................................................................................................................................363

23.5.1 Clock select and divide control......................................................................................................................364

23.5.2 Voltage reference selection............................................................................................................................365

23.5.3 Hardware trigger and channel selects............................................................................................................ 365

23.5.4 Conversion control.........................................................................................................................................366

23.5.5 Automatic compare function..........................................................................................................................374

23.5.6 Calibration function....................................................................................................................................... 375

23.5.7 User-defined offset function.......................................................................................................................... 377

ADC Minus-Side General Calibration Value Register (ADCx_CLMS)....................................................... 360

ADC Minus-Side General Calibration Value Register (ADCx_CLM4)....................................................... 361

ADC Minus-Side General Calibration Value Register (ADCx_CLM3)....................................................... 361

ADC Minus-Side General Calibration Value Register (ADCx_CLM2)....................................................... 362

ADC Minus-Side General Calibration Value Register (ADCx_CLM1)....................................................... 362

ADC Minus-Side General Calibration Value Register (ADCx_CLM0)....................................................... 363

23.5.8 Temperature sensor........................................................................................................................................378

23.5.9 MCU wait mode operation.............................................................................................................................379

23.5.10 MCU Normal Stop mode operation...............................................................................................................379

23.5.11 MCU Low-Power Stop mode operation........................................................................................................ 380

23.6 Initialization information..............................................................................................................................................381

23.6.1 ADC module initialization example.............................................................................................................. 381

23.7 Application information................................................................................................................................................383

23.7.1 External pins and routing............................................................................................................................... 383

23.7.2 Sources of error..............................................................................................................................................385

Chapter 24

Comparator (CMP)

24.1 Chip-specific CMP information....................................................................................................................................391

24.1.1 CMP instantiation information.......................................................................................................................391

24.1.2 CMP input connections..................................................................................................................................391

24.1.3 CMP external references................................................................................................................................392

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24.1.4 CMP trigger mode..........................................................................................................................................392

24.2 Introduction...................................................................................................................................................................393

24.2.1 CMP features..................................................................................................................................................393

24.2.2 6-bit DAC key features.................................................................................................................................. 394

24.2.3 ANMUX key features.................................................................................................................................... 394

24.2.4 CMP, DAC and ANMUX diagram................................................................................................................394

24.2.5 CMP block diagram....................................................................................................................................... 395

24.3 Memory map/register definitions..................................................................................................................................397

24.3.1

24.3.2

24.3.3

24.3.4

24.3.5

24.3.6

24.4 Functional description...................................................................................................................................................402

24.4.1 CMP functional modes...................................................................................................................................403

24.4.2 Power modes..................................................................................................................................................406

24.4.3 Startup and operation..................................................................................................................................... 407

24.4.4 Low-pass filter............................................................................................................................................... 408

24.5 CMP interrupts..............................................................................................................................................................410

24.6 DMA support................................................................................................................................................................410

24.7 CMP Asynchronous DMA support...............................................................................................................................410

CMP Control Register 0 (CMPx_CR0)......................................................................................................... 397

CMP Control Register 1 (CMPx_CR1)......................................................................................................... 398

CMP Filter Period Register (CMPx_FPR).....................................................................................................399

CMP Status and Control Register (CMPx_SCR)...........................................................................................400

DAC Control Register (CMPx_DACCR)......................................................................................................401

MUX Control Register (CMPx_MUXCR).................................................................................................... 401

24.8 Digital-to-analog converter...........................................................................................................................................411

24.9 DAC functional description..........................................................................................................................................411

24.9.1 Voltage reference source select......................................................................................................................411

24.10 DAC resets....................................................................................................................................................................412

24.11 DAC clocks...................................................................................................................................................................412

24.12 DAC interrupts..............................................................................................................................................................412

24.13 CMP Trigger Mode.......................................................................................................................................................412

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Chapter 25

12-bit Digital-to-Analog Converter (DAC)

25.1 Introduction...................................................................................................................................................................413

25.2 Features.........................................................................................................................................................................413

25.3 Block diagram...............................................................................................................................................................413

25.4 Memory map/register definition...................................................................................................................................414

25.4.1

25.4.2

25.4.3

25.4.4

25.4.5

25.4.6

25.5 Functional description...................................................................................................................................................419

25.5.1 DAC data buffer operation.............................................................................................................................419

25.5.2 DMA operation.............................................................................................................................................. 421

25.5.3 Resets............................................................................................................................................................. 421

25.5.4 Low-Power mode operation...........................................................................................................................421

DAC Data Low Register (DACx_DATnL)................................................................................................... 415

DAC Data High Register (DACx_DATnH).................................................................................................. 415

DAC Status Register (DACx_SR)................................................................................................................. 416

DAC Control Register (DACx_C0)............................................................................................................... 417

DAC Control Register 1 (DACx_C1)............................................................................................................ 418

DAC Control Register 2 (DACx_C2)............................................................................................................ 418

Chapter 26

Voltage Reference (VREFV1)

26.1 Introduction...................................................................................................................................................................423

26.1.1 Overview........................................................................................................................................................424

26.1.2 Features.......................................................................................................................................................... 424

26.1.3 Modes of Operation....................................................................................................................................... 424

26.1.4 VREF Signal Descriptions.............................................................................................................................425

26.2 Memory Map and Register Definition..........................................................................................................................425

26.2.1 VREF Trim Register (VREF_TRM)..............................................................................................................426

26.2.2 VREF Status and Control Register (VREF_SC)............................................................................................427

26.3 Functional Description..................................................................................................................................................428

26.3.1 Voltage Reference Disabled, SC[VREFEN] = 0........................................................................................... 428

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26.3.2 Voltage Reference Enabled, SC[VREFEN] = 1............................................................................................ 428

26.4 Internal voltage regulator..............................................................................................................................................430

26.5 Initialization/Application Information..........................................................................................................................430

Chapter 27

Multipurpose Clock Generator Lite (MCG_Lite)

27.1 Introduction ..................................................................................................................................................................433

27.1.1 Features ......................................................................................................................................................... 433

27.1.2 Block diagram ...............................................................................................................................................434

27.2 Memory map and register definition.............................................................................................................................434

27.2.1 MCG Control Register 1 (MCG_C1).............................................................................................................435

27.2.2 MCG Control Register 2 (MCG_C2).............................................................................................................436

27.2.3 MCG Status Register (MCG_S).................................................................................................................... 437

27.2.4 MCG Status and Control Register (MCG_SC)..............................................................................................437

27.2.5 MCG Miscellaneous Control Register (MCG_MC)......................................................................................438

27.3 Functional description...................................................................................................................................................439

27.3.1 Clock mode switching ...................................................................................................................................439

27.3.2 LIRC divider 1 .............................................................................................................................................. 440

27.3.3 LIRC divider 2 .............................................................................................................................................. 440

27.3.4 Enable LIRC in Stop mode ........................................................................................................................... 440

27.3.5 MCG-Lite in Low-power mode .................................................................................................................... 440

27.3.6 HIRC USB recovery ..................................................................................................................................... 441

Chapter 28

Oscillator (OSC)

28.1 Chip-specific OSC information.................................................................................................................................... 443

28.1.1 OSC modes of operation with MCG_Lite and RTC......................................................................................443

28.2 Introduction...................................................................................................................................................................443

28.3 Features and Modes...................................................................................................................................................... 443

28.4 Block Diagram..............................................................................................................................................................444

28.5 OSC Signal Descriptions.............................................................................................................................................. 445

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28.6 External Crystal / Resonator Connections....................................................................................................................445

28.7 External Clock Connections......................................................................................................................................... 447

28.8 Memory Map/Register Definitions...............................................................................................................................447

28.8.1 OSC Memory Map/Register Definition.........................................................................................................448

28.9 Functional Description..................................................................................................................................................449

28.9.1 OSC module states.........................................................................................................................................449

28.9.2 OSC module modes....................................................................................................................................... 451

28.9.3 Counter...........................................................................................................................................................453

28.9.4 Reference clock pin requirements..................................................................................................................453

28.10 Reset..............................................................................................................................................................................453

28.11 Low power modes operation.........................................................................................................................................454

28.12 Interrupts.......................................................................................................................................................................454

Chapter 29

Timer/PWM Module (TPM)

29.1 Chip-specific TPM information....................................................................................................................................455

29.1.1 TPM instantiation information.......................................................................................................................455

29.1.2 Clock options................................................................................................................................................. 456

29.1.3 Trigger options...............................................................................................................................................456

29.1.4 Global timebase..............................................................................................................................................457

29.1.5 TPM interrupts............................................................................................................................................... 457

29.2 Introduction...................................................................................................................................................................458

29.2.1 TPM Philosophy............................................................................................................................................ 458

29.2.2 Features.......................................................................................................................................................... 458

29.2.3 Modes of operation........................................................................................................................................ 459

29.2.4 Block diagram................................................................................................................................................459

29.3 TPM Signal Descriptions..............................................................................................................................................460

29.3.1 TPM_EXTCLK — TPM External Clock...................................................................................................... 460

29.3.2 TPM_CHn — TPM Channel (n) I/O Pin.......................................................................................................461

29.4 Memory Map and Register Definition..........................................................................................................................461

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29.4.1

29.4.2

29.4.3

29.4.4

29.4.5

29.4.6

29.4.7

29.4.8

29.5 Functional description...................................................................................................................................................474

29.5.1 Clock domains................................................................................................................................................474

29.5.2 Prescaler.........................................................................................................................................................475

29.5.3 Counter...........................................................................................................................................................475

29.5.4 Input Capture Mode....................................................................................................................................... 478

29.5.5 Output Compare Mode...................................................................................................................................479

Status and Control (TPMx_SC)..................................................................................................................... 463

Counter (TPMx_CNT)................................................................................................................................... 464

Modulo (TPMx_MOD)..................................................................................................................................465

Channel (n) Status and Control (TPMx_CnSC).............................................................................................466

Channel (n) Value (TPMx_CnV)...................................................................................................................468

Capture and Compare Status (TPMx_STATUS)...........................................................................................468

Channel Polarity (TPMx_POL)..................................................................................................................... 470

Configuration (TPMx_CONF).......................................................................................................................471

29.5.6 Edge-Aligned PWM (EPWM) Mode.............................................................................................................480

29.5.7 Center-Aligned PWM (CPWM) Mode..........................................................................................................482

29.5.8 Registers Updated from Write Buffers.......................................................................................................... 484

29.5.9 DMA.............................................................................................................................................................. 484

29.5.10 Output triggers............................................................................................................................................... 485

29.5.11 Reset Overview..............................................................................................................................................485

29.5.12 TPM Interrupts...............................................................................................................................................486

Chapter 30

Periodic Interrupt Timer (PIT)

30.1 Chip-specific PIT information......................................................................................................................................487

30.1.1 PIT/DMA periodic trigger assignments ........................................................................................................487

30.1.2 PIT/ADC triggers...........................................................................................................................................487

30.1.3 PIT/TPM triggers........................................................................................................................................... 487

30.1.4 PIT/DAC triggers...........................................................................................................................................487

30.2 Introduction...................................................................................................................................................................488

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30.2.1 Block diagram................................................................................................................................................488

30.2.2 Features.......................................................................................................................................................... 488

30.3 Signal description..........................................................................................................................................................489

30.4 Memory map/register description.................................................................................................................................489

30.4.1 PIT Module Control Register (PIT_MCR).................................................................................................... 490

30.4.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H)................................................................................. 491

30.4.3 PIT Lower Lifetime Timer Register (PIT_LTMR64L)................................................................................. 491

30.4.4

30.4.5

30.4.6

30.4.7

30.5 Functional description...................................................................................................................................................494

30.5.1 General operation...........................................................................................................................................494

30.5.2 Interrupts........................................................................................................................................................ 496

30.5.3 Chained timers............................................................................................................................................... 496

30.6 Initialization and application information.....................................................................................................................496

30.7 Example configuration for chained timers....................................................................................................................497

30.8 Example configuration for the lifetime timer............................................................................................................... 498

Timer Load Value Register (PIT_LDVALn).................................................................................................492

Current Timer Value Register (PIT_CVALn)............................................................................................... 492

Timer Control Register (PIT_TCTRLn)........................................................................................................493

Timer Flag Register (PIT_TFLGn)................................................................................................................494

Chapter 31

Low-Power Timer (LPTMR)

31.1 Chip-specific LPTMR information...............................................................................................................................501

31.1.1 LPTMR instantiation information..................................................................................................................501

31.1.2 LPTMR pulse counter input options..............................................................................................................501

31.1.3 LPTMR prescaler/glitch filter clocking options............................................................................................ 501

31.2 Introduction...................................................................................................................................................................502

31.2.1 Features.......................................................................................................................................................... 502

31.2.2 Modes of operation........................................................................................................................................ 503

31.3 LPTMR signal descriptions.......................................................................................................................................... 503

31.3.1 Detailed signal descriptions........................................................................................................................... 503

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31.4 Memory map and register definition.............................................................................................................................504

31.4.1

31.4.2

31.4.3

31.4.4

31.5 Functional description...................................................................................................................................................508

31.5.1 LPTMR power and reset................................................................................................................................508

31.5.2 LPTMR clocking............................................................................................................................................508

31.5.3 LPTMR prescaler/glitch filter........................................................................................................................509

31.5.4 LPTMR compare............................................................................................................................................510

31.5.5 LPTMR counter............................................................................................................................................. 510

31.5.6 LPTMR hardware trigger...............................................................................................................................511

31.5.7 LPTMR interrupt............................................................................................................................................511

Low Power Timer Control Status Register (LPTMRx_CSR)........................................................................504

Low Power Timer Prescale Register (LPTMRx_PSR)..................................................................................505

Low Power Timer Compare Register (LPTMRx_CMR)...............................................................................507

Low Power Timer Counter Register (LPTMRx_CNR)................................................................................. 507

Chapter 32

Real Time Clock (RTC)

32.1 Chip-specific RTC information.................................................................................................................................... 513

32.1.1 RTC Instantiation Information.......................................................................................................................513

32.1.2 RTC_CLKOUT options.................................................................................................................................513

32.2 Introduction...................................................................................................................................................................513

32.2.1 Features.......................................................................................................................................................... 513

32.2.2 Modes of operation........................................................................................................................................ 514

32.2.3 RTC signal descriptions.................................................................................................................................514

32.3 Register definition.........................................................................................................................................................514

32.3.1 RTC Time Seconds Register (RTC_TSR).....................................................................................................515

32.3.2 RTC Time Prescaler Register (RTC_TPR)....................................................................................................515

32.3.3 RTC Time Alarm Register (RTC_TAR)....................................................................................................... 516

32.3.4 RTC Time Compensation Register (RTC_TCR)...........................................................................................516

32.3.5 RTC Control Register (RTC_CR)..................................................................................................................518

32.3.6 RTC Status Register (RTC_SR).................................................................................................................... 520

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32.3.7 RTC Lock Register (RTC_LR)......................................................................................................................521

32.3.8 RTC Interrupt Enable Register (RTC_IER)...................................................................................................522

32.4 Functional description...................................................................................................................................................523

32.4.1 Power, clocking, and reset............................................................................................................................. 523

32.4.2 Time counter.................................................................................................................................................. 524

32.4.3 Compensation.................................................................................................................................................524

32.4.4 Time alarm..................................................................................................................................................... 525

32.4.5 Update mode.................................................................................................................................................. 525

32.4.6 Register lock.................................................................................................................................................. 526

32.4.7 Interrupt..........................................................................................................................................................526

Chapter 33

Universal Serial Bus (USB) FS Subsystem

33.1 Chip-specific USBFS information................................................................................................................................527

33.1.1 Universal Serial Bus (USB) FS Subsystem................................................................................................... 527

33.1.2 USB Wakeup..................................................................................................................................................527

33.1.3 USB Power Distribution................................................................................................................................ 528

33.1.4 USB power management............................................................................................................................... 530

33.2 Introduction...................................................................................................................................................................530

33.2.1 References......................................................................................................................................................530

33.2.2 USB................................................................................................................................................................531

33.2.3 USBFS Features.............................................................................................................................................532

33.3 Functional description...................................................................................................................................................532

33.3.1 Data Structures...............................................................................................................................................532

33.3.2 On-chip transceiver required external components........................................................................................532

33.4 Programmers interface..................................................................................................................................................534

33.4.1 Buffer Descriptor Table................................................................................................................................. 534

33.4.2 USB data transfers—Receive (Rx) and Transmit (Tx)..................................................................................535

33.4.3 Addressing BDT entries.................................................................................................................................536

33.4.4 Buffer Descriptors (BDs)...............................................................................................................................536

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33.4.5 USB transaction............................................................................................................................................. 539

33.5 Memory map/Register definitions................................................................................................................................ 541

33.5.1

33.5.2

33.5.3

33.5.4

33.5.5

33.5.6

33.5.7

33.5.8

33.5.9

33.5.10

33.5.11

33.5.12

33.5.13

33.5.14

Peripheral ID register (USBx_PERID).......................................................................................................... 543

Peripheral ID Complement register (USBx_IDCOMP).................................................................................543

Peripheral Revision register (USBx_REV)....................................................................................................544

Peripheral Additional Info register (USBx_ADDINFO)............................................................................... 544

Interrupt Status register (USBx_ISTAT)....................................................................................................... 545

Interrupt Enable register (USBx_INTEN)..................................................................................................... 546

Error Interrupt Status register (USBx_ERRSTAT)....................................................................................... 547

Error Interrupt Enable register (USBx_ERREN)...........................................................................................548

Status register (USBx_STAT)........................................................................................................................549

Control register (USBx_CTL)........................................................................................................................550

Address register (USBx_ADDR)...................................................................................................................551

BDT Page register 1 (USBx_BDTPAGE1)................................................................................................... 551

Frame Number register Low (USBx_FRMNUML).......................................................................................552

Frame Number register High (USBx_FRMNUMH)..................................................................................... 552

33.5.15

33.5.16

33.5.17

33.5.18

33.5.19

33.5.20

33.5.21

33.5.22

33.5.23

33.5.24

33.5.25

33.5.26

33.6 Device mode IRC48 operation......................................................................................................................................561

BDT Page Register 2 (USBx_BDTPAGE2)..................................................................................................553

BDT Page Register 3 (USBx_BDTPAGE3)..................................................................................................553

Endpoint Control register (USBx_ENDPTn).................................................................................................554

USB Control register (USBx_USBCTRL).................................................................................................... 555

USB OTG Observe register (USBx_OBSERVE)..........................................................................................555

USB OTG Control register (USBx_CONTROL).......................................................................................... 556

USB Transceiver Control register 0 (USBx_USBTRC0)..............................................................................557

Frame Adjust Register (USBx_USBFRMADJUST)..................................................................................... 558

USB Clock recovery control (USBx_CLK_RECOVER_CTRL)..................................................................558

IRC48M oscillator enable register (USBx_CLK_RECOVER_IRC_EN)..................................................... 559

Clock recovery combined interrupt enable (USBx_CLK_RECOVER_INT_EN)........................................ 560

Clock recovery separated interrupt status (USBx_CLK_RECOVER_INT_STATUS)................................ 561

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Chapter 34

USB Voltage Regulator (VREG)

34.1 Introduction...................................................................................................................................................................563

34.1.1 Overview........................................................................................................................................................563

34.1.2 Features.......................................................................................................................................................... 564

34.1.3 Modes of Operation....................................................................................................................................... 565

34.2 USB Voltage Regulator Module Signal Descriptions.................................................................................................. 565

Chapter 35

Serial Peripheral Interface (SPI)

35.1 Chip-specific SPI information...................................................................................................................................... 567

35.2 Introduction...................................................................................................................................................................567

35.2.1 Features.......................................................................................................................................................... 568

35.2.2 Modes of operation........................................................................................................................................ 568

35.2.3 Block diagrams.............................................................................................................................................. 569

35.3 External signal description............................................................................................................................................572

35.3.1 SPSCK — SPI Serial Clock...........................................................................................................................573

35.3.2 MOSI — Master Data Out, Slave Data In..................................................................................................... 573

35.3.3 MISO — Master Data In, Slave Data Out..................................................................................................... 573

35.3.4 SS — Slave Select..........................................................................................................................................573

35.4 Memory map/register definition...................................................................................................................................574

35.4.1

35.4.2

35.4.3

35.4.4

35.4.5

35.4.6

35.4.7

SPI Status Register (SPIx_S)......................................................................................................................... 574

SPI Baud Rate Register (SPIx_BR)............................................................................................................... 578

SPI Control Register 2 (SPIx_C2)................................................................................................................. 579

SPI Control Register 1 (SPIx_C1)................................................................................................................. 581

SPI Match Register low (SPIx_ML).............................................................................................................. 582

SPI match register high (SPIx_MH).............................................................................................................. 583

SPI Data Register low (SPIx_DL)................................................................................................................. 583

35.4.8

35.4.9

26 Freescale Semiconductor, Inc.

SPI data register high (SPIx_DH).................................................................................................................. 584

SPI clear interrupt register (SPIx_CI)............................................................................................................ 585

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35.4.10

35.5 Functional description...................................................................................................................................................588

35.5.1 General...........................................................................................................................................................588

35.5.2 Master mode...................................................................................................................................................588

35.5.3 Slave mode.....................................................................................................................................................590

35.5.4 SPI FIFO Mode..............................................................................................................................................591

35.5.5 SPI Transmission by DMA............................................................................................................................592

35.5.6 Data Transmission Length............................................................................................................................. 594

35.5.7 SPI clock formats...........................................................................................................................................595

35.5.8 SPI baud rate generation................................................................................................................................ 598

35.5.9 Special features.............................................................................................................................................. 598

35.5.10 Error conditions..............................................................................................................................................600

35.5.11 Low-power mode options.............................................................................................................................. 601

35.5.12 Reset...............................................................................................................................................................602

SPI control register 3 (SPIx_C3)....................................................................................................................586

35.5.13 Interrupts........................................................................................................................................................ 603

35.6 Initialization/application information........................................................................................................................... 605

35.6.1 Initialization sequence....................................................................................................................................605

35.6.2 Pseudo-Code Example................................................................................................................................... 606

Chapter 36

Inter-Integrated Circuit (I2C)

36.1 Chip-specific I2C information......................................................................................................................................611

36.1.1 I2C instantiation information.........................................................................................................................611

36.2 Introduction...................................................................................................................................................................611

36.2.1 Features.......................................................................................................................................................... 612

36.2.2 Modes of operation........................................................................................................................................ 612

36.2.3 Block diagram................................................................................................................................................613

36.3 I2C signal descriptions..................................................................................................................................................613

36.4 Memory map/register definition...................................................................................................................................614

36.4.1

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I2C Address Register 1 (I2Cx_A1)................................................................................................................615

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36.4.2

36.4.3

36.4.4

36.4.5

36.4.6

36.4.7

36.4.8

36.4.9

36.4.10

36.4.11

36.4.12

36.4.13

36.5 Functional description...................................................................................................................................................627

36.5.1 I2C protocol................................................................................................................................................... 627

I2C Frequency Divider register (I2Cx_F)......................................................................................................615

I2C Control Register 1 (I2Cx_C1).................................................................................................................616

I2C Status register (I2Cx_S).......................................................................................................................... 618

I2C Data I/O register (I2Cx_D)..................................................................................................................... 620

I2C Control Register 2 (I2Cx_C2).................................................................................................................620

I2C Programmable Input Glitch Filter Register (I2Cx_FLT)........................................................................ 621

I2C Range Address register (I2Cx_RA)........................................................................................................ 623

I2C SMBus Control and Status register (I2Cx_SMB)...................................................................................623

I2C Address Register 2 (I2Cx_A2)................................................................................................................625

I2C SCL Low Timeout Register High (I2Cx_SLTH)....................................................................................625

I2C SCL Low Timeout Register Low (I2Cx_SLTL).....................................................................................626

I2C Status register 2 (I2Cx_S2)..................................................................................................................... 626

36.5.2 10-bit address................................................................................................................................................. 632

36.5.3 Address matching...........................................................................................................................................634

36.5.4 System management bus specification.......................................................................................................... 635

36.5.5 Resets............................................................................................................................................................. 637

36.5.6 Interrupts........................................................................................................................................................ 637

36.5.7 Programmable input glitch filter....................................................................................................................640

36.5.8 Address matching wake-up............................................................................................................................640

36.5.9 DMA support................................................................................................................................................. 641

36.5.10 Double buffering mode.................................................................................................................................. 642

36.6 Initialization/application information........................................................................................................................... 643

Chapter 37

Low Power Universal asynchronous receiver/transmitter (LPUART)

37.1 Chip-specific LPUART information.............................................................................................................................647

37.1.1 LPUART0 and LPUART1 overview.............................................................................................................647

37.2 Introduction...................................................................................................................................................................647

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37.2.1 Features.......................................................................................................................................................... 647

37.2.2 Modes of operation........................................................................................................................................ 648

37.2.3 Signal Descriptions........................................................................................................................................ 649

37.2.4 Block diagram................................................................................................................................................649

37.3 Register definition.........................................................................................................................................................651

37.3.1

37.3.2

37.3.3

37.3.4

37.3.5

37.4 Functional description...................................................................................................................................................665

37.4.1 Baud rate generation...................................................................................................................................... 665

37.4.2 Transmitter functional description.................................................................................................................666

37.4.3 Receiver functional description..................................................................................................................... 668

37.4.4 Additional LPUART functions...................................................................................................................... 673

37.4.5 Interrupts and status flags.............................................................................................................................. 675

LPUART Baud Rate Register (LPUARTx_BAUD)......................................................................................652

LPUART Status Register (LPUARTx_STAT)..............................................................................................654

LPUART Control Register (LPUARTx_CTRL)........................................................................................... 658

LPUART Data Register (LPUARTx_DATA)............................................................................................... 663

LPUART Match Address Register (LPUARTx_MATCH)...........................................................................665

Chapter 38

Universal Asynchronous Receiver/Transmitter(UART)

38.1 Chip-specific UART information.................................................................................................................................677

38.1.1 UART2 Overview..........................................................................................................................................677

38.2 Introduction...................................................................................................................................................................677

38.2.1 Features.......................................................................................................................................................... 677

38.2.2 Modes of operation........................................................................................................................................ 679

38.3 UART signal descriptions.............................................................................................................................................680

38.3.1 Detailed signal descriptions........................................................................................................................... 680

38.4 Memory map and registers............................................................................................................................................680

38.4.1

38.4.2

38.4.3

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UART Baud Rate Registers: High (UARTx_BDH)...................................................................................... 682

UART Baud Rate Registers: Low (UARTx_BDL)....................................................................................... 683

UART Control Register 1 (UARTx_C1)....................................................................................................... 683

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38.4.4

38.4.5

38.4.6

38.4.7

38.4.8

38.4.9

38.4.10

38.4.11

38.4.12

38.4.13

38.4.14

38.4.15

38.4.16

38.4.17

UART Control Register 2 (UARTx_C2)....................................................................................................... 685

UART Status Register 1 (UARTx_S1).......................................................................................................... 687

UART Status Register 2 (UARTx_S2).......................................................................................................... 689

UART Control Register 3 (UARTx_C3)....................................................................................................... 691

UART Data Register (UARTx_D).................................................................................................................692

UART Match Address Registers 1 (UARTx_MA1)......................................................................................693

UART Match Address Registers 2 (UARTx_MA2)......................................................................................694

UART Control Register 4 (UARTx_C4)....................................................................................................... 694

UART Control Register 5 (UARTx_C5)....................................................................................................... 695

UART 7816 Control Register (UARTx_C7816)........................................................................................... 696

UART 7816 Interrupt Enable Register (UARTx_IE7816)............................................................................ 697

UART 7816 Interrupt Status Register (UARTx_IS7816)..............................................................................699

UART 7816 Wait Parameter Register (UARTx_WP7816)........................................................................... 701

UART 7816 Wait N Register (UARTx_WN7816)........................................................................................701

38.4.18

38.4.19

38.4.20

38.4.21

38.4.22

38.4.23

38.4.24

38.4.25

38.4.26

38.4.27

38.4.28

38.5 Functional description...................................................................................................................................................708

38.5.1 Transmitter.....................................................................................................................................................708

38.5.2 Receiver......................................................................................................................................................... 712

UART 7816 Wait FD Register (UARTx_WF7816)...................................................................................... 702

UART 7816 Error Threshold Register (UARTx_ET7816)............................................................................702

UART 7816 Transmit Length Register (UARTx_TL7816).......................................................................... 703

UART 7816 ATR Duration Timer Register A (UARTx_AP7816A_T0)......................................................703

UART 7816 ATR Duration Timer Register B (UARTx_AP7816B_T0)...................................................... 704

UART 7816 Wait Parameter Register A (UARTx_WP7816A_T0)..............................................................705

UART 7816 Wait Parameter Register A (UARTx_WP7816A_T1)..............................................................705

UART 7816 Wait Parameter Register B (UARTx_WP7816B_T0).............................................................. 706

UART 7816 Wait Parameter Register B (UARTx_WP7816B_T1).............................................................. 706

UART 7816 Wait and Guard Parameter Register (UARTx_WGP7816_T1)................................................707

UART 7816 Wait Parameter Register C (UARTx_WP7816C_T1).............................................................. 707

38.5.3 Baud rate generation...................................................................................................................................... 724

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

30 Freescale Semiconductor, Inc.