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NXP Semiconductors MKL04Z16VFM4, MKL04Z32VLC4, MKL04Z32VFM4, MKL04Z16VLF4, MKL04Z32VLF4 Reference Manual

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Page 1
KL04 Sub-Family Reference Manual
Supports: MKL04Z8VFK4, MKL04Z16VFK4, MKL04Z32VFK4,
MKL04Z8VLC4, MKL04Z16VLC4, MKL04Z32VLC4, MKL04Z8VFM4,
MKL04Z16VFM4, MKL04Z32VFM4, MKL04Z16VLF4, and
MKL04Z32VLF4
Document Number: KL04P48M48SF1RM
Rev. 3.1, November 2012
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KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012
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Contents
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................29
1.1.1 Purpose.........................................................................................................................................................29
1.1.2 Audience......................................................................................................................................................29
1.2 Conventions..................................................................................................................................................................29
1.2.1 Numbering systems......................................................................................................................................29
1.2.2 Typographic notation...................................................................................................................................30
1.2.3 Special terms................................................................................................................................................30
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................31
2.2 Kinetis L Series.............................................................................................................................................................31
2.3 KL04 Sub-Family Introduction.....................................................................................................................................34
2.4 Module functional categories........................................................................................................................................35
2.4.1 ARM® Cortex™-M0+ Core Modules.........................................................................................................35
2.4.2 System Modules...........................................................................................................................................36
2.4.3 Memories and Memory Interfaces...............................................................................................................37
2.4.4 Clocks...........................................................................................................................................................37
2.4.5 Security and Integrity modules....................................................................................................................37
2.4.6 Analog modules...........................................................................................................................................38
2.4.7 Timer modules.............................................................................................................................................38
2.4.8 Communication interfaces...........................................................................................................................39
2.4.9 Human-machine interfaces..........................................................................................................................39
2.5 Orderable part numbers.................................................................................................................................................39
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................41
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3.2 Module to Module Interconnects..................................................................................................................................41
3.2.1 Module to Module Interconnects.................................................................................................................41
3.2.2 Analog reference options.............................................................................................................................43
3.3 Core Modules................................................................................................................................................................44
3.3.1 ARM Cortex-M0+ Core Configuration.......................................................................................................44
3.3.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................46
3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration............................................................50
3.4 System Modules............................................................................................................................................................51
3.4.1 SIM Configuration.......................................................................................................................................51
3.4.2 System Mode Controller (SMC) Configuration...........................................................................................52
3.4.3 PMC Configuration......................................................................................................................................52
3.4.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................53
3.4.5 MCM Configuration....................................................................................................................................55
3.4.6 Crossbar-Light Switch Configuration..........................................................................................................56
3.4.7 Peripheral Bridge Configuration..................................................................................................................57
3.4.8 DMA request multiplexer configuration......................................................................................................58
3.4.9 DMA Controller Configuration...................................................................................................................61
3.4.10 Computer Operating Properly (COP) Watchdog Configuration..................................................................61
3.5 Clock Modules..............................................................................................................................................................64
3.5.1 MCG Configuration.....................................................................................................................................64
3.5.2 OSC Configuration......................................................................................................................................65
3.6 Memories and Memory Interfaces................................................................................................................................66
3.6.1 Flash Memory Configuration.......................................................................................................................66
3.6.2 Flash Memory Controller Configuration.....................................................................................................68
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3.6.3 SRAM Configuration...................................................................................................................................69
3.7 Analog...........................................................................................................................................................................71
3.7.1 12-bit SAR ADC Configuration..................................................................................................................71
3.7.2 CMP Configuration......................................................................................................................................75
3.8 Timers...........................................................................................................................................................................77
3.8.1 Timer/PWM Module Configuration............................................................................................................77
3.8.2 PIT Configuration........................................................................................................................................79
3.8.3 Low-power timer configuration...................................................................................................................81
3.8.4 RTC configuration.......................................................................................................................................82
3.9 Communication interfaces............................................................................................................................................84
3.9.1 SPI configuration.........................................................................................................................................84
3.9.2 I2C Configuration........................................................................................................................................85
3.9.3 UART Configuration...................................................................................................................................85
3.10 Human-machine interfaces (HMI)................................................................................................................................87
3.10.1 GPIO Configuration.....................................................................................................................................87
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................91
4.2 System memory map.....................................................................................................................................................91
4.3 Flash Memory Map.......................................................................................................................................................92
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................92
4.4 SRAM memory map.....................................................................................................................................................93
4.5 Bit Manipulation Engine...............................................................................................................................................93
4.6 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................94
4.6.1 Read-after-write sequence and required serialization of memory operations..............................................94
4.6.2 Peripheral Bridge (AIPS-Lite) Memory Map..............................................................................................95
4.6.3 Modules Restricted Access in User Mode...................................................................................................98
4.7 Private Peripheral Bus (PPB) memory map..................................................................................................................98
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Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................101
5.2 Programming model......................................................................................................................................................101
5.3 High-Level device clocking diagram............................................................................................................................101
5.4 Clock definitions...........................................................................................................................................................102
5.4.1 Device clock summary.................................................................................................................................103
5.5 Internal clocking requirements.....................................................................................................................................105
5.5.1 Clock divider values after reset....................................................................................................................105
5.5.2 VLPR mode clocking...................................................................................................................................106
5.6 Clock Gating.................................................................................................................................................................106
5.7 Module clocks...............................................................................................................................................................106
5.7.1 PMC 1-kHz LPO clock................................................................................................................................107
5.7.2 COP clocking...............................................................................................................................................108
5.7.3 RTC clocking...............................................................................................................................................108
5.7.4 LPTMR clocking..........................................................................................................................................109
5.7.5 TPM clocking...............................................................................................................................................109
5.7.6 UART clocking............................................................................................................................................110
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................111
6.2 Reset..............................................................................................................................................................................111
6.2.1 Power-on reset (POR)..................................................................................................................................112
6.2.2 System reset sources....................................................................................................................................112
6.2.3 MCU Resets.................................................................................................................................................115
6.2.4 Reset Pin .....................................................................................................................................................116
6.2.5 Debug resets.................................................................................................................................................117
6.3 Boot...............................................................................................................................................................................118
6.3.1 Boot sources.................................................................................................................................................118
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6.3.2 FOPT boot options.......................................................................................................................................118
6.3.3 Boot sequence..............................................................................................................................................119
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................121
7.2 Clocking Modes............................................................................................................................................................121
7.2.1 Partial Stop...................................................................................................................................................121
7.2.2 DMA Wakeup..............................................................................................................................................122
7.2.3 Compute Operation......................................................................................................................................123
7.2.4 Peripheral Doze............................................................................................................................................124
7.2.5 Clock Gating................................................................................................................................................125
7.3 Power modes.................................................................................................................................................................125
7.4 Entering and exiting power modes...............................................................................................................................127
7.5 Module Operation in Low Power Modes......................................................................................................................127
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................131
8.2 Flash Security...............................................................................................................................................................131
8.3 Security Interactions with other Modules.....................................................................................................................131
8.3.1 Security Interactions with Debug.................................................................................................................132
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................133
9.2 Debug Port Pin Descriptions.........................................................................................................................................133
9.3 SWD status and control registers..................................................................................................................................134
9.3.1 MDM-AP Control Register..........................................................................................................................135
9.3.2 MDM-AP Status Register............................................................................................................................136
9.4 Debug Resets................................................................................................................................................................138
9.5 Micro Trace Buffer (MTB)...........................................................................................................................................139
9.6 Debug in Low Power Modes........................................................................................................................................139
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9.7 Debug & Security.........................................................................................................................................................139
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................141
10.2 Signal Multiplexing Integration....................................................................................................................................141
10.2.1 Port control and interrupt module features..................................................................................................142
10.2.2 Clock gating.................................................................................................................................................143
10.2.3 Signal multiplexing constraints....................................................................................................................143
10.3 Pinout............................................................................................................................................................................143
10.3.1 KL04 signal multiplexing and pin assignments...........................................................................................143
10.3.2 KL04 Pinouts...............................................................................................................................................145
10.4 Module Signal Description Tables................................................................................................................................149
10.4.1 Core Modules...............................................................................................................................................149
10.4.2 System Modules...........................................................................................................................................150
10.4.3 Clock Modules.............................................................................................................................................150
10.4.4 Memories and Memory Interfaces...............................................................................................................150
10.4.5 Analog..........................................................................................................................................................150
10.4.6 Timer Modules.............................................................................................................................................151
10.4.7 Communication Interfaces...........................................................................................................................152
10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................152
Chapter 11
Port control and interrupts (PORT)
11.1 Introduction...................................................................................................................................................................153
11.2 Overview.......................................................................................................................................................................153
11.2.1 Features........................................................................................................................................................153
11.2.2 Modes of operation......................................................................................................................................154
11.3 External signal description............................................................................................................................................154
11.4 Detailed signal description............................................................................................................................................155
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11.5 Memory map and register definition.............................................................................................................................155
11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................158
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................160
11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................161
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................161
11.6 Functional description...................................................................................................................................................162
11.6.1 Pin control....................................................................................................................................................162
11.6.2 Global pin control........................................................................................................................................163
11.6.3 External interrupts........................................................................................................................................163
Chapter 12
System integration module (SIM)
12.1 Introduction...................................................................................................................................................................165
12.1.1 Features........................................................................................................................................................165
12.2 Memory map and register definition.............................................................................................................................165
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................167
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................167
12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................168
12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................170
12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................171
12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................172
12.2.7 System Device Identification Register (SIM_SDID)...................................................................................174
12.2.8 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................176
12.2.9 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................177
12.2.10 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................179
12.2.11 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................180
12.2.12 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................181
12.2.13 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................183
12.2.14 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................184
12.2.15 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................185
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12.2.16 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................185
12.2.17 Unique Identification Register Low (SIM_UIDL)......................................................................................186
12.2.18 COP Control Register (SIM_COPC)...........................................................................................................186
12.2.19 Service COP Register (SIM_SRVCOP)......................................................................................................187
12.3 Functional description...................................................................................................................................................188
Chapter 13
System Mode Controller (SMC)
13.1 Introduction...................................................................................................................................................................189
13.2 Modes of operation.......................................................................................................................................................189
13.3 Memory map and register descriptions.........................................................................................................................191
13.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................191
13.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................193
13.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................194
13.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................195
13.4 Functional description...................................................................................................................................................196
13.4.1 Power mode transitions................................................................................................................................196
13.4.2 Power mode entry/exit sequencing..............................................................................................................199
13.4.3 Run modes....................................................................................................................................................201
13.4.4 Wait modes..................................................................................................................................................203
13.4.5 Stop modes...................................................................................................................................................204
13.4.6 Debug in low power modes.........................................................................................................................207
Chapter 14
Power Management Controller (PMC)
14.1 Introduction...................................................................................................................................................................209
14.2 Features.........................................................................................................................................................................209
14.3 Low-voltage detect (LVD) system................................................................................................................................209
14.3.1 LVD reset operation.....................................................................................................................................210
14.3.2 LVD interrupt operation...............................................................................................................................210
14.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................210
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14.4 I/O retention..................................................................................................................................................................211
14.5 Memory map and register descriptions.........................................................................................................................211
14.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................212
14.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................213
14.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................214
Chapter 15
Low-Leakage Wakeup Unit (LLWU)
15.1 Introduction...................................................................................................................................................................217
15.1.1 Features........................................................................................................................................................217
15.1.2 Modes of operation......................................................................................................................................218
15.1.3 Block diagram..............................................................................................................................................219
15.2 LLWU signal descriptions............................................................................................................................................220
15.3 Memory map/register definition...................................................................................................................................220
15.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................221
15.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................222
15.3.3 LLWU Module Enable register (LLWU_ME)............................................................................................223
15.3.4 LLWU Flag 1 register (LLWU_F1).............................................................................................................225
15.3.5 LLWU Flag 3 register (LLWU_F3).............................................................................................................226
15.3.6 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................228
15.3.7 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................229
15.4 Functional description...................................................................................................................................................230
15.4.1 LLS mode.....................................................................................................................................................231
15.4.2 VLLS modes................................................................................................................................................231
15.4.3 Initialization.................................................................................................................................................231
Chapter 16
Reset Control Module (RCM)
16.1 Introduction...................................................................................................................................................................233
16.2 Reset memory map and register descriptions...............................................................................................................233
16.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................233
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16.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................235
16.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................236
16.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................237
Chapter 17
Bit Manipulation Engine (BME)
17.1 Introduction...................................................................................................................................................................239
17.1.1 Overview......................................................................................................................................................240
17.1.2 Features........................................................................................................................................................240
17.1.3 Modes of Operation.....................................................................................................................................241
17.2 External Signal Description..........................................................................................................................................241
17.3 Memory Map and Register Definition..........................................................................................................................242
17.4 Functional Description..................................................................................................................................................242
17.4.1 BME Decorated Stores.................................................................................................................................242
17.4.2 BME Decorated Loads.................................................................................................................................248
17.4.3 Additional Details on Decorated Addresses and GPIO Accesses................................................................255
17.5 Application Information................................................................................................................................................256
Chapter 18
Miscellaneous Control Module (MCM)
18.1 Introduction...................................................................................................................................................................259
18.1.1 Features........................................................................................................................................................259
18.2 Memory map/register descriptions...............................................................................................................................259
18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................260
18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................261
18.2.3 Platform Control Register (MCM_PLACR)................................................................................................261
18.2.4 Compute Operation Control Register (MCM_CPO)...................................................................................264
Chapter 19
Micro Trace Buffer (MTB)
19.1 Introduction...................................................................................................................................................................267
19.1.1 Overview......................................................................................................................................................267
19.1.2 Features........................................................................................................................................................270
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19.1.3 Modes of Operation.....................................................................................................................................271
19.2 External Signal Description..........................................................................................................................................271
19.3 Memory Map and Register Definition..........................................................................................................................272
19.3.1 MTB_RAM Memory Map...........................................................................................................................272
19.3.2 MTB_DWT Memory Map...........................................................................................................................285
19.3.3 System ROM Memory Map.........................................................................................................................295
Chapter 20
Crossbar Switch Lite (AXBS-Lite)
20.1 Introduction...................................................................................................................................................................301
20.1.1 Features........................................................................................................................................................301
20.2 Memory Map / Register Definition...............................................................................................................................301
20.3 Functional Description..................................................................................................................................................302
20.3.1 General operation.........................................................................................................................................302
20.3.2 Arbitration....................................................................................................................................................303
20.4 Initialization/application information...........................................................................................................................304
Chapter 21
Peripheral Bridge (AIPS-Lite)
21.1 Introduction...................................................................................................................................................................305
21.1.1 Features........................................................................................................................................................305
21.1.2 General operation.........................................................................................................................................305
21.2 Functional description...................................................................................................................................................306
21.2.1 Access support.............................................................................................................................................306
Chapter 22
Direct Memory Access Multiplexer (DMAMUX)
22.1 Introduction...................................................................................................................................................................307
22.1.1 Overview......................................................................................................................................................307
22.1.2 Features........................................................................................................................................................308
22.1.3 Modes of operation......................................................................................................................................308
22.2 External signal description............................................................................................................................................309
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22.3 Memory map/register definition...................................................................................................................................309
22.3.1 Channel Configuration register (DMAMUXx_CHCFGn)..........................................................................309
22.4 Functional description...................................................................................................................................................310
22.4.1 DMA channels with periodic triggering capability......................................................................................311
22.4.2 DMA channels with no triggering capability...............................................................................................313
22.4.3 Always-enabled DMA sources....................................................................................................................313
22.5 Initialization/application information...........................................................................................................................314
22.5.1 Reset.............................................................................................................................................................314
22.5.2 Enabling and configuring sources................................................................................................................314
Chapter 23
DMA Controller Module
23.1 Introduction...................................................................................................................................................................319
23.1.1 Overview......................................................................................................................................................319
23.1.2 Features........................................................................................................................................................320
23.2 DMA Transfer Overview..............................................................................................................................................321
23.3 Memory Map and Registers..........................................................................................................................................322
23.3.1 Source Address Register (DMA_SARn).....................................................................................................323
23.3.2 Destination Address Register (DMA_DARn).............................................................................................324
23.3.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn).............................................................325
23.3.4 DMA Control Register (DMA_DCRn)........................................................................................................327
23.4 Functional Description..................................................................................................................................................331
23.4.1 Transfer Requests (Cycle-Steal and Continuous Modes)............................................................................331
23.4.2 Channel Initialization and Startup................................................................................................................331
23.4.3 Dual-Address Data Transfer Mode..............................................................................................................333
23.4.4 Advanced Data Transfer Controls: Auto-Alignment...................................................................................334
23.4.5 Termination..................................................................................................................................................335
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Chapter 24
Multipurpose Clock Generator (MCG)
24.1 Introduction...................................................................................................................................................................337
24.1.1 Features........................................................................................................................................................337
24.1.2 Modes of Operation.....................................................................................................................................339
24.2 External Signal Description..........................................................................................................................................340
24.3 Memory Map/Register Definition.................................................................................................................................340
24.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................340
24.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................342
24.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................343
24.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................343
24.3.5 MCG Control 6 Register (MCG_C6)...........................................................................................................345
24.3.6 MCG Status Register (MCG_S)..................................................................................................................345
24.3.7 MCG Status and Control Register (MCG_SC)............................................................................................346
24.3.8 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................348
24.3.9 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................348
24.4 Functional Description..................................................................................................................................................348
24.4.1 MCG mode state diagram............................................................................................................................348
24.4.2 Low Power Bit Usage..................................................................................................................................352
24.4.3 MCG Internal Reference Clocks..................................................................................................................352
24.4.4 External Reference Clock............................................................................................................................353
24.4.5 MCG Fixed frequency clock .......................................................................................................................353
24.4.6 MCG Auto TRIM (ATM)............................................................................................................................353
24.5 Initialization / Application information........................................................................................................................355
24.5.1 MCG module initialization sequence...........................................................................................................355
24.5.2 Using a 32.768 kHz reference......................................................................................................................357
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24.5.3 MCG mode switching..................................................................................................................................358
Chapter 25
Oscillator (OSC)
25.1 Introduction...................................................................................................................................................................365
25.2 Features and Modes......................................................................................................................................................365
25.3 Block Diagram..............................................................................................................................................................366
25.4 OSC Signal Descriptions..............................................................................................................................................366
25.5 External Crystal / Resonator Connections....................................................................................................................367
25.6 External Clock Connections.........................................................................................................................................368
25.7 Memory Map/Register Definitions...............................................................................................................................369
25.7.1 OSC Memory Map/Register Definition.......................................................................................................369
25.8 Functional Description..................................................................................................................................................370
25.8.1 OSC Module States......................................................................................................................................370
25.8.2 OSC Module Modes.....................................................................................................................................372
25.8.3 Counter.........................................................................................................................................................373
25.8.4 Reference Clock Pin Requirements.............................................................................................................373
25.9 Reset..............................................................................................................................................................................374
25.10 Low Power Modes Operation.......................................................................................................................................374
25.11 Interrupts.......................................................................................................................................................................374
Chapter 26
Flash Memory Controller (FMC)
26.1 Introduction...................................................................................................................................................................375
26.1.1 Overview......................................................................................................................................................375
26.1.2 Features........................................................................................................................................................375
26.2 Modes of operation.......................................................................................................................................................376
26.3 External signal description............................................................................................................................................376
26.4 Memory map and register descriptions.........................................................................................................................376
26.5 Functional description...................................................................................................................................................376
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Chapter 27
Flash Memory Module (FTFA)
27.1 Introduction...................................................................................................................................................................379
27.1.1 Features........................................................................................................................................................380
27.1.2 Block Diagram.............................................................................................................................................380
27.1.3 Glossary.......................................................................................................................................................381
27.2 External Signal Description..........................................................................................................................................382
27.3 Memory Map and Registers..........................................................................................................................................382
27.3.1 Flash Configuration Field Description.........................................................................................................382
27.3.2 Program Flash IFR Map...............................................................................................................................383
27.3.3 Register Descriptions...................................................................................................................................384
27.4 Functional Description..................................................................................................................................................392
27.4.1 Flash Protection............................................................................................................................................393
27.4.2 Interrupts......................................................................................................................................................393
27.4.3 Flash Operation in Low-Power Modes........................................................................................................394
27.4.4 Functional Modes of Operation...................................................................................................................394
27.4.5 Flash Reads and Ignored Writes..................................................................................................................394
27.4.6 Read While Write (RWW)...........................................................................................................................395
27.4.7 Flash Program and Erase..............................................................................................................................395
27.4.8 Flash Command Operations.........................................................................................................................395
27.4.9 Margin Read Commands.............................................................................................................................400
27.4.10 Flash Command Description........................................................................................................................401
27.4.11 Security........................................................................................................................................................414
27.4.12 Reset Sequence............................................................................................................................................416
Chapter 28
Analog-to-Digital Converter (ADC)
28.1 Introduction...................................................................................................................................................................417
28.1.1 Features........................................................................................................................................................417
28.1.2 Block diagram..............................................................................................................................................418
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28.2 ADC Signal Descriptions..............................................................................................................................................419
28.2.1 Analog Power (VDDA)...............................................................................................................................420
28.2.2 Analog Ground (VSSA)...............................................................................................................................420
28.2.3 Voltage Reference Select.............................................................................................................................420
28.2.4 Analog Channel Inputs (ADx).....................................................................................................................421
28.3 Register definition.........................................................................................................................................................421
28.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)...................................................................................422
28.3.2 ADC Configuration Register 1 (ADCx_CFG1)...........................................................................................425
28.3.3 ADC Configuration Register 2 (ADCx_CFG2)...........................................................................................427
28.3.4 ADC Data Result Register (ADCx_Rn).......................................................................................................428
28.3.5 Compare Value Registers (ADCx_CVn).....................................................................................................429
28.3.6 Status and Control Register 2 (ADCx_SC2)................................................................................................430
28.3.7 Status and Control Register 3 (ADCx_SC3)................................................................................................432
28.3.8 ADC Offset Correction Register (ADCx_OFS)...........................................................................................433
28.3.9 ADC Plus-Side Gain Register (ADCx_PG).................................................................................................434
28.3.10 ADC Plus-Side General Calibration Value Register (ADCx_CLPD).........................................................434
28.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)..........................................................435
28.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)..........................................................435
28.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)..........................................................436
28.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP2)..........................................................436
28.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP1)..........................................................437
28.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP0)..........................................................437
28.4 Functional description...................................................................................................................................................438
28.4.1 Clock select and divide control....................................................................................................................438
28.4.2 Voltage reference selection..........................................................................................................................439
28.4.3 Hardware trigger and channel selects..........................................................................................................439
28.4.4 Conversion control.......................................................................................................................................440
28.4.5 Automatic compare function........................................................................................................................447
28.4.6 Calibration function.....................................................................................................................................449
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28.4.7 User-defined offset function........................................................................................................................450
28.4.8 Temperature sensor......................................................................................................................................451
28.4.9 MCU wait mode operation...........................................................................................................................452
28.4.10 MCU Normal Stop mode operation.............................................................................................................452
28.4.11 MCU Low-Power Stop mode operation......................................................................................................453
28.5 Initialization information..............................................................................................................................................454
28.5.1 ADC module initialization example............................................................................................................454
28.6 Application information................................................................................................................................................456
28.6.1 External pins and routing.............................................................................................................................456
28.6.2 Sources of error............................................................................................................................................458
Chapter 29
Comparator (CMP)
29.1 Introduction...................................................................................................................................................................463
29.2 CMP features................................................................................................................................................................463
29.3 6-bit DAC key features.................................................................................................................................................464
29.4 ANMUX key features...................................................................................................................................................465
29.5 CMP, DAC and ANMUX diagram...............................................................................................................................465
29.6 CMP block diagram......................................................................................................................................................466
29.7 Memory map/register definitions..................................................................................................................................468
29.7.1 CMP Control Register 0 (CMPx_CR0).......................................................................................................468
29.7.2 CMP Control Register 1 (CMPx_CR1).......................................................................................................469
29.7.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................471
29.7.4 CMP Status and Control Register (CMPx_SCR).........................................................................................471
29.7.5 DAC Control Register (CMPx_DACCR)....................................................................................................472
29.7.6 MUX Control Register (CMPx_MUXCR)..................................................................................................473
29.8 Functional description...................................................................................................................................................474
29.8.1 CMP functional modes.................................................................................................................................474
29.8.2 Power modes................................................................................................................................................483
29.8.3 Startup and operation...................................................................................................................................484
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29.8.4 Low-pass filter.............................................................................................................................................484
29.9 CMP interrupts..............................................................................................................................................................487
29.10 DMA support................................................................................................................................................................487
29.11 CMP Asyncrhonous DMA support...............................................................................................................................487
29.12 Digital-to-analog converter...........................................................................................................................................488
29.13 DAC functional description..........................................................................................................................................488
29.13.1 Voltage reference source select....................................................................................................................488
29.14 DAC resets....................................................................................................................................................................489
29.15 DAC clocks...................................................................................................................................................................489
29.16 DAC interrupts..............................................................................................................................................................489
29.17 CMP Trigger Mode.......................................................................................................................................................489
Chapter 30
Timer/PWM Module (TPM)
30.1 Introduction...................................................................................................................................................................491
30.1.1 TPM Philosophy..........................................................................................................................................491
30.1.2 Features........................................................................................................................................................491
30.1.3 Modes of Operation.....................................................................................................................................492
30.1.4 Block Diagram.............................................................................................................................................492
30.2 TPM Signal Descriptions..............................................................................................................................................493
30.2.1 TPM_EXTCLK — TPM External Clock....................................................................................................493
30.2.2 TPM_CHn — TPM Channel (n) I/O Pin.....................................................................................................494
30.3 Memory Map and Register Definition..........................................................................................................................494
30.3.1 Status and Control (TPMx_SC)...................................................................................................................496
30.3.2 Counter (TPMx_CNT).................................................................................................................................497
30.3.3 Modulo (TPMx_MOD)................................................................................................................................498
30.3.4 Channel (n) Status and Control (TPMx_CnSC)...........................................................................................499
30.3.5 Channel (n) Value (TPMx_CnV).................................................................................................................501
30.3.6 Capture and Compare Status (TPMx_STATUS).........................................................................................501
30.3.7 Configuration (TPMx_CONF).....................................................................................................................503
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30.4 Functional Description..................................................................................................................................................505
30.4.1 Clock Domains.............................................................................................................................................505
30.4.2 Prescaler.......................................................................................................................................................506
30.4.3 Counter.........................................................................................................................................................506
30.4.4 Input Capture Mode.....................................................................................................................................508
30.4.5 Output Compare Mode.................................................................................................................................509
30.4.6 Edge-Aligned PWM (EPWM) Mode...........................................................................................................510
30.4.7 Center-Aligned PWM (CPWM) Mode........................................................................................................512
30.4.8 Registers Updated from Write Buffers........................................................................................................514
30.4.9 DMA............................................................................................................................................................514
30.4.10 Reset Overview............................................................................................................................................515
30.4.11 TPM Interrupts.............................................................................................................................................515
Chapter 31
Periodic Interrupt Timer (PIT-RTI)
31.1 Introduction...................................................................................................................................................................517
31.1.1 Block diagram..............................................................................................................................................517
31.1.2 Features........................................................................................................................................................518
31.2 Signal description..........................................................................................................................................................518
31.3 Memory map/register description.................................................................................................................................519
31.3.1 PIT Module Control Register (PIT_MCR)..................................................................................................519
31.3.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H)...............................................................................521
31.3.3 PIT Lower Lifetime Timer Register (PIT_LTMR64L)...............................................................................521
31.3.4 Timer Load Value Register (PIT_LDVALn)...............................................................................................522
31.3.5 Current Timer Value Register (PIT_CVALn).............................................................................................522
31.3.6 Timer Control Register (PIT_TCTRLn)......................................................................................................523
31.3.7 Timer Flag Register (PIT_TFLGn)..............................................................................................................524
31.4 Functional description...................................................................................................................................................524
31.4.1 General operation.........................................................................................................................................524
31.4.2 Interrupts......................................................................................................................................................526
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31.4.3 Chained timers.............................................................................................................................................526
31.5 Initialization and application information.....................................................................................................................526
31.6 Example configuration for chained timers....................................................................................................................527
31.7 Example configuration for the lifetime timer...............................................................................................................528
Chapter 32
Low-Power Timer (LPTMR)
32.1 Introduction...................................................................................................................................................................531
32.1.1 Features........................................................................................................................................................531
32.1.2 Modes of operation......................................................................................................................................531
32.2 LPTMR signal descriptions..........................................................................................................................................532
32.2.1 Detailed signal descriptions.........................................................................................................................532
32.3 Memory map and register definition.............................................................................................................................532
32.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)......................................................................533
32.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)................................................................................534
32.3.3 Low Power Timer Compare Register (LPTMRx_CMR).............................................................................536
32.3.4 Low Power Timer Counter Register (LPTMRx_CNR)...............................................................................536
32.4 Functional description...................................................................................................................................................537
32.4.1 LPTMR power and reset..............................................................................................................................537
32.4.2 LPTMR clocking..........................................................................................................................................537
32.4.3 LPTMR prescaler/glitch filter......................................................................................................................537
32.4.4 LPTMR compare..........................................................................................................................................539
32.4.5 LPTMR counter...........................................................................................................................................539
32.4.6 LPTMR hardware trigger.............................................................................................................................540
32.4.7 LPTMR interrupt..........................................................................................................................................540
Chapter 33
Real Time Clock (RTC)
33.1 Introduction...................................................................................................................................................................541
33.1.1 Features........................................................................................................................................................541
33.1.2 Modes of operation......................................................................................................................................541
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33.1.3 RTC Signal Descriptions.............................................................................................................................541
33.2 Register definition.........................................................................................................................................................542
33.2.1 RTC Time Seconds Register (RTC_TSR)...................................................................................................543
33.2.2 RTC Time Prescaler Register (RTC_TPR)..................................................................................................543
33.2.3 RTC Time Alarm Register (RTC_TAR).....................................................................................................544
33.2.4 RTC Time Compensation Register (RTC_TCR).........................................................................................544
33.2.5 RTC Control Register (RTC_CR)................................................................................................................545
33.2.6 RTC Status Register (RTC_SR)..................................................................................................................547
33.2.7 RTC Lock Register (RTC_LR)....................................................................................................................548
33.2.8 RTC Interrupt Enable Register (RTC_IER).................................................................................................549
33.3 Functional description...................................................................................................................................................550
33.3.1 Power, clocking, and reset...........................................................................................................................550
33.3.2 Time counter................................................................................................................................................551
33.3.3 Compensation...............................................................................................................................................551
33.3.4 Time alarm...................................................................................................................................................552
33.3.5 Update mode................................................................................................................................................552
33.3.6 Register lock................................................................................................................................................553
33.3.7 Interrupt........................................................................................................................................................553
Chapter 34
Serial Peripheral Interface (SPI)
34.1 Introduction...................................................................................................................................................................555
34.1.1 Features........................................................................................................................................................555
34.1.2 Modes of Operation.....................................................................................................................................556
34.1.3 Block Diagrams............................................................................................................................................557
34.2 External Signal Description..........................................................................................................................................559
34.2.1 SPSCK — SPI Serial Clock.........................................................................................................................559
34.2.2 MOSI — Master Data Out, Slave Data In...................................................................................................560
34.2.3 MISO — Master Data In, Slave Data Out...................................................................................................560
34.2.4 SS — Slave Select........................................................................................................................................560
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34.3 Memory Map and Register Descriptions......................................................................................................................561
34.3.1 SPI control register 1 (SPIx_C1)..................................................................................................................561
34.3.2 SPI control register 2 (SPIx_C2)..................................................................................................................563
34.3.3 SPI baud rate register (SPIx_BR).................................................................................................................564
34.3.4 SPI status register (SPIx_S).........................................................................................................................565
34.3.5 SPI data register (SPIx_D)...........................................................................................................................566
34.3.6 SPI match register (SPIx_M).......................................................................................................................567
34.4 Functional Description..................................................................................................................................................568
34.4.1 General.........................................................................................................................................................568
34.4.2 Master Mode................................................................................................................................................568
34.4.3 Slave Mode..................................................................................................................................................570
34.4.4 SPI Transmission by DMA..........................................................................................................................571
34.4.5 SPI Clock Formats.......................................................................................................................................573
34.4.6 SPI Baud Rate Generation...........................................................................................................................576
34.4.7 Special Features...........................................................................................................................................576
34.4.8 Error Conditions...........................................................................................................................................578
34.4.9 Low Power Mode Options...........................................................................................................................579
34.4.10 Reset.............................................................................................................................................................580
34.4.11 Interrupts......................................................................................................................................................581
34.5 Initialization/Application Information..........................................................................................................................582
34.5.1 Initialization Sequence.................................................................................................................................582
34.5.2 Pseudo-Code Example.................................................................................................................................583
Chapter 35
Inter-Integrated Circuit (I2C)
35.1 Introduction...................................................................................................................................................................587
35.1.1 Features........................................................................................................................................................587
35.1.2 Modes of operation......................................................................................................................................588
35.1.3 Block diagram..............................................................................................................................................588
35.2 I2C signal descriptions..................................................................................................................................................589
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35.3 Memory map and register descriptions.........................................................................................................................589
35.3.1 I2C Address Register 1 (I2Cx_A1)..............................................................................................................590
35.3.2 I2C Frequency Divider register (I2Cx_F)....................................................................................................591
35.3.3 I2C Control Register 1 (I2Cx_C1)...............................................................................................................592
35.3.4 I2C Status register (I2Cx_S)........................................................................................................................593
35.3.5 I2C Data I/O register (I2Cx_D)...................................................................................................................595
35.3.6 I2C Control Register 2 (I2Cx_C2)...............................................................................................................596
35.3.7 I2C Programmable Input Glitch Filter register (I2Cx_FLT).......................................................................597
35.3.8 I2C Range Address register (I2Cx_RA)......................................................................................................598
35.3.9 I2C SMBus Control and Status register (I2Cx_SMB).................................................................................599
35.3.10 I2C Address Register 2 (I2Cx_A2)..............................................................................................................600
35.3.11 I2C SCL Low Timeout Register High (I2Cx_SLTH)..................................................................................601
35.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL)...................................................................................601
35.4 Functional description...................................................................................................................................................601
35.4.1 I2C protocol.................................................................................................................................................601
35.4.2 10-bit address...............................................................................................................................................607
35.4.3 Address matching.........................................................................................................................................608
35.4.4 System management bus specification........................................................................................................609
35.4.5 Resets...........................................................................................................................................................612
35.4.6 Interrupts......................................................................................................................................................612
35.4.7 Programmable input glitch filter..................................................................................................................614
35.4.8 Address matching wakeup...........................................................................................................................615
35.4.9 DMA support...............................................................................................................................................615
35.5 Initialization/application information...........................................................................................................................616
Chapter 36
Universal Asynchronous Receiver/Transmitter (UART0)
36.1 Introduction...................................................................................................................................................................619
36.1.1 Features........................................................................................................................................................619
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36.1.2 Modes of operation......................................................................................................................................620
36.1.3 Block diagram..............................................................................................................................................620
36.2 Register definition.........................................................................................................................................................622
36.2.1 UART Baud Rate Register High (UARTx_BDH).......................................................................................623
36.2.2 UART Baud Rate Register Low (UARTx_BDL)........................................................................................624
36.2.3 UART Control Register 1 (UARTx_C1).....................................................................................................624
36.2.4 UART Control Register 2 (UARTx_C2).....................................................................................................626
36.2.5 UART Status Register 1 (UARTx_S1)........................................................................................................627
36.2.6 UART Status Register 2 (UARTx_S2)........................................................................................................629
36.2.7 UART Control Register 3 (UARTx_C3).....................................................................................................631
36.2.8 UART Data Register (UARTx_D)...............................................................................................................632
36.2.9 UART Match Address Registers 1 (UARTx_MA1)....................................................................................633
36.2.10 UART Match Address Registers 2 (UARTx_MA2)....................................................................................634
36.2.11 UART Control Register 4 (UARTx_C4).....................................................................................................634
36.2.12 UART Control Register 5 (UARTx_C5).....................................................................................................635
36.3 Functional description...................................................................................................................................................636
36.3.1 Baud rate generation....................................................................................................................................636
36.3.2 Transmitter functional description...............................................................................................................636
36.3.3 Receiver functional description...................................................................................................................638
36.3.4 Additional UART functions.........................................................................................................................641
36.3.5 Interrupts and status flags............................................................................................................................643
Chapter 37
General-Purpose Input/Output (GPIO)
37.1 Introduction...................................................................................................................................................................645
37.1.1 Features........................................................................................................................................................645
37.1.2 Modes of operation......................................................................................................................................645
37.1.3 GPIO signal descriptions.............................................................................................................................646
37.2 Memory map and register definition.............................................................................................................................647
37.2.1 Port Data Output Register (GPIOx_PDOR).................................................................................................648
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37.2.2 Port Set Output Register (GPIOx_PSOR)....................................................................................................649
37.2.3 Port Clear Output Register (GPIOx_PCOR)................................................................................................649
37.2.4 Port Toggle Output Register (GPIOx_PTOR).............................................................................................650
37.2.5 Port Data Input Register (GPIOx_PDIR).....................................................................................................650
37.2.6 Port Data Direction Register (GPIOx_PDDR).............................................................................................651
37.3 FGPIO memory map and register definition................................................................................................................651
37.3.1 Port Data Output Register (FGPIOx_PDOR)..............................................................................................652
37.3.2 Port Set Output Register (FGPIOx_PSOR).................................................................................................652
37.3.3 Port Clear Output Register (FGPIOx_PCOR).............................................................................................653
37.3.4 Port Toggle Output Register (FGPIOx_PTOR)...........................................................................................653
37.3.5 Port Data Input Register (FGPIOx_PDIR)...................................................................................................654
37.3.6 Port Data Direction Register (FGPIOx_PDDR)..........................................................................................654
37.4 Functional description...................................................................................................................................................655
37.4.1 General-purpose input..................................................................................................................................655
37.4.2 General-purpose output................................................................................................................................655
37.4.3 IOPORT.......................................................................................................................................................655
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Chapter 1 About This Document
1.1

Overview

1.1.1 Purpose

This document describes the features, architecture, and programming model of the Freescale KL04 microcontroller.

1.1.2 Audience

This document is primarily for system architects and software application developers who are using or considering using the KL04KL02 microcontroller in a system.
1.2

Conventions

1.2.1 Numbering systems

The following suffixes identify different numbering systems:
This suffix Identifies a
b Binary number. For example, the binary equivalent of the
number 5 is written 101b. In some cases, binary numbers are shown with the prefix 0b.
d Decimal number. Decimal numbers are followed by this suffix
only when the possibility of confusion exists. In general, decimal numbers are shown without a suffix.
h Hexadecimal number. For example, the hexadecimal
equivalent of the number 60 is written 3Ch. In some cases, hexadecimal numbers are shown with the prefix 0x.
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Conventions

1.2.2 Typographic notation

The following typographic notation is used throughout this document:
Example Description
placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for
the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers.
code
SR[SCM] A mnemonic in brackets represents a named field in a register. This example refers to the
REVNO[6:4], XAD[7:0] Numbers in brackets and separated by a colon represent either:
Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type is also used for example code. Instruction mnemonics and directives in text and tables are shown in all caps; for example, BSR.
Scaling Mode (SCM) field in the Status Register (SR).
• A subset of a register's named field For example, REVNO[6:4] refers to bits 6–4 that are part of the COREREV field that
occupies bits 6–0 of the REVNO register.
• A continuous range of individual signals of a bus For example, XAD[7:0] refers to signals 7–0 of the XAD bus.

1.2.3 Special terms

The following terms have special meanings:
Term Meaning
asserted Refers to the state of a signal as follows:
• An active-high signal is asserted when high (1).
• An active-low signal is asserted when low (0).
deasserted Refers to the state of a signal as follows:
• An active-high signal is deasserted when low (0).
• An active-low signal is deasserted when high (1).
In some cases, deasserted signals are described as negated.
reserved Refers to a memory space, register, or field that is either
reserved for future use or for which, when written to, the module or chip behavior is unpredictable.
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Chapter 2 Introduction

2.1 Overview

This chapter provides an overview of the Kinetis L series of ARM® Cortex™-M0+ MCUs and KL04 product family. It also presents high-level descriptions of the modules available on the devices covered by this document.

2.2 Kinetis L Series

The Kinetis L series is the most scalable portfolio of ultra low-power, mixed-signal ARM Cortex-M0+ MCUs in the industry. The portfolio includes 5 MCU families that offer a broad range of memory, peripheral and package options. Kinetis L Series families share common peripherals and pin-counts allowing developers to migrate easily within an MCU family or between MCU families to take advantage of more memory or feature integration. This scalability allows developers to standardize on the Kinetis L Series for their end product platforms, maximising hardware and software reuse and reducing time­to-market.
Features common to all Kinetis L series families include:
• 48 MHz ARM Cortex-M0+ core
• High-speed 12/16-bit analog-to-digital converters
• 12-bit digital-to-analog converters for all series except for KLx4/KLx2 family
• High-speed analog comparators
• Low-power touch sensing with wake-up on touch from reduced power states for all series except for KLx4/KLx2 family
• Powerful timers for a broad range of applications including motor control
• Low power focused serial communication interfaces such as low power UART, SPI, I2C etc.
• Single power supply: 1.71V - 3.6V with multiple low-power modes support single operation temperature: -40 ~ 105 °C (exclude CSP package)
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KL2x Family
KL1x Family
KL0x Family
KL3x Family
Family
Program
Flash
Packages Key Features
Low power Mixed signal USB Segment LCD
KL4x Family
8-32KB
32-256KB
32-256KB
64-256KB
128-256KB
16-48pin
32-80pin
32-121pin
64-121pin
64-121pin
Kinetis L Series
Kinetis L series MCU families combine the latest low-power innovations with precision mixed-signal capability and a broad range of communication, connectivity, and human­machine interface peripherals. Each MCU family is supported by a market-leading enablement bundle from Freescale and numerous ARM 3rd party ecosystem partners. The KL0x family is the entry-point to the Kinetis L series and is pin compatible with the 8-bit S08PT family. The KL1x/2x/3x/4x families are compatible with each other and their equivalent ARM Cortex-M4 Kinetis K series families - K10/20/30/40.
All Kinetis L series families include a powerful array of analog, communication and timing and control peripherals with the level of feature integration increasing with flash memory size and the pin count. Features within the Kinetis L series families include:
Figure 2-1. Kinetis L series families of MCU portfolio
• Core and Architecture:
• ARM Cortex-M0+ Core running up to 48 MHz with zero wait state execution from memories
• Single-cycle access to I/O: Up to 50 percent faster than standard I/O, improves reaction time to external events allowing bit banging and software protocol emulation
• Two-stage pipeline: Reduced number of cycles per instruction (CPI), enabling faster branch instruction and ISR entry, and reducing power consumption
• Excellent code density vs. 8-bit and 16-bit MCUs - reduces flash size, system cost and power consumption
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Chapter 2 Introduction
• Optimized access to program memory: Accesses on alternate cycles reduces power consumption
• 100 percent compatible with ARM Cortex-M0 and a subset ARM Cortex­M3/M4: Reuse existing compilers and debug tools
• Simplified architecture: 56 instructions and 17 registers enables easy programming and efficient packaging of 8/16/32-bit data in memory
• Linear 4 GB address space removes the need for paging/banking, reducing software complexity
• ARM third-party ecosystem support: Software and tools to help minimize development time/cost
• Micro Trace Buffer: Lightweight trace solution allows fast bug identification and correction
• BME: Bit manipulation engine reduces code size and cycles for bit oriented operations to peripheral registers eliminating traditional methods where the core would need to perform read-modify-write operations.
• Up to 4-channel DMA for peripheral and memory servicing with minimal CPU intervention (feature not available on KL02 family)
• Ultra low-power:
• Extreme dynamic efficiency: 32-bit ARM Cortex-M0+ core combined with Freescale 90 nm thin film storage flash technology delivers 50% energy savings per Coremark versus the closest 8/16-bit competitive solution
• Multiple flexible low-power modes, including new operation clocking option which reduces dynamic power by shutting off bus and system clocks for lowest power core processing. Peripherals with an alternate asynchronous clock source can continue operation.
• UART, SPI, I2C, ADC, DAC, TPM, LPT, and DMA support low-power mode operation without waking up the core
• Memory:
• Scalable memory footprints from 8 KB flash / 1 KB SRAM to 256 KB flash / 32 KB SRAM
• Embedded 64 B cache memory for optimizing bus bandwidth and flash execution performance (32 B cache on KL02 family)
• Mixed-signal analog:
• Fast, high precision 16-, or 12-bit ADC with optional differential pairs, 12-bit DAC, high speed comparators. Powerful signal conditioning, conversion and analysis capability with reduced system cost (12-bit DAC not available on KL02 family)
• Human Machine Interface (HMI):
• Optional capacitive Touch Sensing Interface with full low-power support and minimal current adder when enabled
• Segment LCD controller
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Page 34

KL04 Sub-Family Introduction

• Connectivity and Communications:
• Up to three UARTs, all UARTs support DMA transfers, and can trigger when data on bus is detected, UART0 supports 4x to 32x over sampling ratio. Asynchronous transmit and receive operation for operating in STOP/VLPS modes.
• Up to two SPIs
• Up to two I2Cs
• Full-speed USB OTG controller with on-chip transceiver
• 5 V to 3.3 V USB on-chip regulator
• Up to one I2S
• Reliability, Safety and Security:
• Internal watchdog with independent clock source
• Timing and Control:
• Powerful timer modules which support general purpose, PWM, and motor control functions
• Periodic Interrupt Timer for RTOS task scheduler time base or trigger source for ADC conversion and timer modules
• System:
• GPIO with pin interrupt functionality
• Wide operating voltage range from 1.71 V to 3.6 V with flash programmable down to 1.71 V with fully functional flash and analog peripherals
• Ambient operating temperature ranges from -40 °C to 105 °C
2.3 KL04 Sub-Family Introduction
The device is highly-integrated, market leading ultra low power 32-bit microcontroller based on the enhanced Cortex-M0+ (CM0+) core platform. The family derivatives feature:
• Core platform clock up to 48 MHz, bus clock up to 24 MHz
• Memory option is up to 32 KB Flash and 4 KB RAM
• Wide operating voltage ranges from 1.71V to 3.6V with full functional Flash program/erase/read operations
• Multiple package options from 24-pin to 48-pin
• Ambient operating temperature ranges from –40 °C to 105 °C
The family acts as an ultra low power, cost effective microcontroller to provide developers an appropriate entry-level 32-bit solution. The family is next generation MCU solution for low cost, low power, high performance devices applications. It’s valuable for cost-sensitive, portable applications requiring long battery life-time.
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Chapter 2 Introduction

2.4 Module functional categories

The modules on this device are grouped into functional categories. The following sections describe the modules assigned to each category in more detail.
Table 2-1. Module functional categories
Module category Description
ARM Cortex-M0+ core • 32-bit MCU core from ARM’s Cortex-M class, 1.77 CoreMark®/MHz from
single-cycle access memories, 48 MHz CPU frequency
System • System integration module
• Power management and mode controllers
• Multiple power modes available based on run, wait, stop, and power­down modes
• Miscellaneous control module
• Low-leakage wakeup unit
• Peripheral bridge
• Direct memory access (DMA) controller with multiplexer to increase available DMA requests
• COP watchdog
Memories • Internal memories include:
• Up to 32 KB flash memory
• up to 4 KB SRAM
Clocks • Multiple clock generation options available from internally- and externally-
generated clocks
• MCG module with FLL for systems and CPU clock sources
• Low power 1 kHz RC oscillator for RTC and COP watchdog
• System oscillator to provide clock source for the MCU
Security • COP watchdog timer (COP) Analog • 12-bit analog-to-digital converters with DMA supported
• Comparator (CMP) with internal 6-bit digital-to-analog converter (DAC)
Timers • One 6-channel TPM
• One 2-channel TPM
• 2-channel periodic interrupt timer
• Real time clock
• Low-power timer
• System tick timer
Communications • One8-bit serial peripheral interface
• One inter-integrated circuit (I2C) module
• One low power UART module
Human-Machine Interfaces (HMI) • General purpose input/output controller

2.4.1 ARM® Cortex™-M0+ Core Modules

The following core modules are available on this device.
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Module functional categories
Table 2-2. Core modules
Module Description
ARM® Cortex™-M0+ The ARM® Cortex™-M0+ is the newest member of the Cortex M Series of
processors targeting microcontroller applications focused on very cost sensitive, deterministic, interrupt driven environments. The Cortex M0+ processor is based on the ARMv6 Architecture and Thumb®-2 ISA and is 100% instruction set compatible with its predecessor, the Cortex-M0 core, and upward compatible to Cortex-M3 and M4 cores.
NVIC The ARMv6-M exception model and nested-vectored interrupt controller (NVIC)
implement a relocatable vector table supporting many external interrupts, a single non-maskable interrupt (NMI), and priority levels.
The NVIC replaces shadow registers with equivalent system and simplified programmability. The NVIC contains the address of the function to execute for a particular handler. The address is fetched via the instruction port allowing parallel register stacking and look-up. The first sixteen entries are allocated to ARM internal sources with the others mapping to MCU-defined interrupts.
AWIC The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is
to detect asynchronous wake-up events in stop modes and signal to clock control logic to resume system clocking. After clock restart, the NVIC observes the pending interrupt and performs the normal interrupt or event processing.
Single-cycle I/O Port For high-speed, single-cycle access to peripherals, the Cortex-M0+ processor
implements a dedicated single-cycle I/O port.
Debug interfaces Most of this device's debug is based on the ARM CoreSight™ architecture. One
debug interface is supported:
• Serial Wire Debug (SWD)

2.4.2 System Modules

The following system modules are available on this device.
Table 2-3. System modules
Module Description
System integration module (SIM) The SIM includes integration logic and several module configuration settings. System mode controller The SMC provides control and protection on entry and exit to each power mode,
control for the Power management controller (PMC), and reset entry and exit for the complete MCU.
Power management controller (PMC) The PMC provides the user with multiple power options. Multiple modes are
supported that allow the user to optimize power consumption for the level of functionality needed. Includes power-on-reset (POR) and integrated low voltage
detect (LVD) with reset (brownout) capability and selectable LVD trip points.
Miscellaneous control module (MCM) The MCM includes integration logic and details. Crossbar switch (XBS) The XBS connects bus masters and bus slaves, allowing all bus masters to access
different bus slaves simultaneously and providing arbitration among the bus
masters when they access the same slave.
Low-leakage wakeup unit (LLWU) The LLWU module allows the device to wake from low leakage power modes (LLS
and VLLS) through various internal peripheral and external pin sources.
Table continues on the next page...
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Chapter 2 Introduction
Table 2-3. System modules (continued)
Module Description
Peripheral bridge The peripheral bridge converts the crossbar switch interface to an interface to
access a majority of peripherals on the device.
DMA multiplexer (DMAMUX) The DMA multiplexer selects from many DMA requests down to 4 for the DMA
controller.
Direct memory access (DMA) controller The DMA controller provides programmable channels with transfer control
descriptors for data movement via dual-address transfers for 8-, 16- and 32-bit
data values.
Computer operating properly watchdog (WDOG)
The WDOG monitors internal system operation and forces a reset in case of
failure. It can run from an independent 1 kHz low power oscillator with a
programmable refresh window to detect deviations in program flow or system
frequency.

2.4.3 Memories and Memory Interfaces

The following memories and memory interfaces are available on this device.
Table 2-4. Memories and memory interfaces
Module Description
Flash memory Program flash memory — up to 32 KB of the non-volatile flash memory that can
execute program code
Flash memory controller Manages the interface between the device and the on-chip flash memory. SRAM Up to 4 KB internal system RAM.

2.4.4 Clocks

The following clock modules are available on this device.
Table 2-5. Clock modules
Module Description
Multipurpose Clock Generator (MCG) MCG module containing a frequency-locked-loop (FLL) controlled by internal or
external reference oscillator.
System oscillator The system oscillator, in conjunction with an external crystal or resonator,
generates a reference clock for the MCU.

2.4.5 Security and Integrity modules

The following security and integrity modules are available on this device:
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Module functional categories
Table 2-6. Security and integrity modules
Module Description
Watchdog Timer (WDOG) Watchdog Timer keeps a watch on the system functioning and resets it in case of
its failure.

2.4.6 Analog modules

The following analog modules are available on this device:
Table 2-7. Analog modules
Module Description
Analog-to-digital converters (ADC) 12-bit successive-approximation ADC module. Analog comparators One comparator that compares two analog input voltages across the full range of
the supply voltage and can trigger an ADC acquisition, TPM update, or CPU
interrupt.
6-bit digital-to-analog converters (DAC) 64-tap resistor ladder network which provides a selectable voltage reference for
comparator.

2.4.7 Timer modules

The following timer modules are available on this device:
Table 2-8. Timer modules
Module Description
Timer/PWM module (TPM) • Selectable TPM clock mode
• Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128
• 16-bit free-running counter or modulo counter with counting be up or up­down
• Six configurable channels for input capture, output compare, or edge-aligned PWM mode
• Support the generation of an interrupt and/or DMA request per channel
• Support the generation of an interrupt and/or DMA request when the counter overflows
• Support selectable trigger input to optionally reset or cause the counter to start incrementing.
• Support the generation of hardware triggers when the counter overflows and per channel
Periodic interrupt timers (PIT) • One general purpose interrupt timer
• Interrupt timers for triggering ADC conversions
• 32-bit counter resolution
• Clocked by bus clock frequency
• DMA support
Table continues on the next page...
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Table 2-8. Timer modules (continued)
Module Description
Low power timer (LPTMR) • 16-bit time counter or pulse counter with compare
• Configurable clock source for prescaler/glitch filter
• Configurable input source for pulse counter
Real-time counter (RTC) • 16-bit up-counter
• 16-bit modulo match limit
• Software controllable periodic interrupt on match
• Software selectable clock sources for input to prescaler with programmable 16-bit prescaler
• XOSC 32.678 kHz nominal
• LPO (~1 kHz)
• External RTC_CLKIN

2.4.8 Communication interfaces

The following communication interfaces are available on this device:
Chapter 2 Introduction
Table 2-9. Communication modules
Module Description
Serial peripheral interface (SPI) Synchronous serial bus for communication to an external device Inter-integrated circuit (I2C) Allows communication between a number of devices. Also supports the System
Management Bus (SMBus) Specification, version 2.
Universal asynchronous receiver/ transmitters (UART)
One low power UART module that retains functional in stop modes.

2.4.9 Human-machine interfaces

The following human-machine interfaces (HMI) are available on this device:
Table 2-10. HMI modules
Module Description
General purpose input/output (GPIO) Some general purpose input or output (GPIO) pins are capable of interrupt and
DMA request generation.

2.5 Orderable part numbers

The following table summarizes the part numbers of the devices covered by this document.
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Orderable part numbers
Table 2-11. Orderable part numbers summary
Freescale part number CPU
frequency
MKL04Z8VFK4 48 MHz 24 QFN 8 KB 1 KB -40 to 105 °C MKL04Z16VFK4 48 MHz 24 QFN 16 KB 2 KB -40 to 105 °C MKL04Z32VFK4 48 MHz 24 QFN 32 KB 4 KB -40 to 105 °C
MKL04Z8VLC4 48 MHz 32 LQFP 8 KB 1 KB -40 to 105 °C MKL04Z16VLC4 48 MHz 32 LQFP 16 KB 2 KB -40 to 105 °C MKL04Z32VLC4 48 MHz 32 LQFP 32 KB 4 KB -40 to 105 °C
MKL04Z8VFM4 48 MHz 32 QFN 8 KB 1 KB -40 to 105 °C MKL04Z16VFM4 48 MHz 32 QFN 16 KB 2 KB -40 to 105 °C MKL04Z32VFM4 48 MHz 32 QFN 32 KB 4 KB -40 to 105 °C
MKL04Z16VLF4 48 MHz 48 LQFP 16 KB 2 KB -40 to 105 °C MKL04Z32VLF4 48 MHz 48 LQFP 32 KB 4 KB -40 to 105 °C
Pin count Package Total flash
memory
RAM Temperature range
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Chapter 3 Chip Configuration

3.1 Introduction

This chapter provides details on the individual modules of the microcontroller. It includes:
• Module block diagrams showing immediate connections within the device
• Specific module-to-module interactions not necessarily discussed in the individual module chapters
• Links for more information
3.2

Module to Module Interconnects

3.2.1 Module to Module Interconnects

The below table captures the module to module interconnections for this device.
Table 3-1. Module to Module Interconnects
Peripheral Signal — to Peripheral Use Case Control Comment
TPM1 CH0F, CH1F to ADC (Trigger) ADC Triggering
(A AND B)
Table continues on the next page...
SOPT7_ADCAL
TTRGEN = 0
Ch0 is A, and
Ch1 is B,
selecting this
ADC trigger is
for supporting A
and B triggering.
In Stop and
VLPS modes,
the second
trigger must be
set to >10us after the first
trigger
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Module to Module Interconnects
Table 3-1. Module to Module Interconnects (continued)
Peripheral Signal — to Peripheral Use Case Control Comment
LPTMR Hardware trigger to ADC (Trigger) ADC Triggering
(A or B)
TPMx TOF to ADC (Trigger) ADC Triggering
(A or B)
PIT CHx TIF0, TIF1 to ADC (Trigger) ADC Triggering
(A or B)
RTC ALARM or
SECONDS
EXTRG_IN EXTRG_IN to ADC (Trigger) ADC Triggering
CMP0 CMP0_OUT to ADC (Trigger) ADC Triggering
CMP0 CMP0_OUT to LPTMR_ALT0 Count CMP
CMP0 CMP0_OUT to TPM1 CH0 Input capture SOPT4_TPM1C
CMP0 CMP0_OUT to UART0_RX IR interface SOPT5_UART0
LPTMR Hardware trigger to CMPx Low power
LPTMR Hardware trigger to TPMx TPM Trigger
TPMx TOF to TPMx TPM Trigger
to ADC (Trigger) ADC Triggering
(A or B)
(A or B)
(Aor B)
events
triggering of the
comparator
input
input
SOPT7_ADC0T
RGSEL (4 bit
field), ADC0PRETRG SEL to select A
or B
SOPT7_ADC0T
RGSEL (4 bit
field),
SOPT7_ADC0P
RETRGSEL to
select A or B
SOPT7_ADC0T
RGSEL (4 bit
field), ADC0PRETRG SEL to select A
or B
SOPT7_ADC0T
RGSEL (4 bit
field) ADC0PRETRG SEL to select A
or B
SOPT7_ADC0T
RGSEL (4 bit
field) ADC0PRETRG SEL to select A
or B
SOPT7_ADC0T
RGSEL (4 bit
field) ADC0PRETRG SEL to select A
or B
LPTMR_CSR[T
PS]
H0SRC
RXSRC
CMP_CR1[TRIG
M]
TPMx_CONF[T
RGSEL] (4 bit
field) TPMx_CONF[T
RGSEL] (4 bit
field)
—
—
—
—
—
—
—
—
—
—
—
—
Table continues on the next page...
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Chapter 3 Chip Configuration
Table 3-1. Module to Module Interconnects (continued)
Peripheral Signal — to Peripheral Use Case Control Comment
TPM1 Timebase to TPMx TPM Global
timebase input
PIT CHx TIF0, TIF1 to TPMx TPM Trigger
input
RTC ALARM or
SECONDS
EXTRG_IN EXTRG_IN to TPMx TPM Trigger
CMP0 CMP0_OUT to TPMx TPM Trigger
UART0 UART0_TX to Modulated by
PIT TIF0 to DAC Advance DAC
PIT TIF0 to DMA CH0 DMA HW
PIT TIF1 to DMA CH1 DMA HW
to TPMx TPM Trigger
input
input
input
UART
TPM1 CH0
modulation
FIFO
Trigger
Trigger
TPMx_CONF[G
TBEEN]
TPMx_CONF[T
RGSEL] (4 bit
field)
TPMx_CONF[T
RGSEL] (4 bit
field) TPMx_CONF[T
RGSEL] (4 bit
field) TPMx_CONF[T
RGSEL] (4 bit
field)
SOPT5_UART0
TXSRC
DAC HWTRG
Select
DMA MUX
register option
DMA MUX
register option
—
If PIT is
triggering the
TPM, the TPM
clock must be
faster than Bus
clock.
—
—
—
—
—
—
—

3.2.2 Analog reference options

Several analog blocks have selectable reference voltages as shown in the below table. These options allow analog peripherals to share or have separate analog references. Care should be taken when selecting analog references to avoid cross talk noise.
Table 3-2. Analog reference options
Module Reference option Comment/ Reference selection
12-bit SAR ADC 1 - VREFH
2 - VDDA
3 - Reserved
CMP with 6-bit DAC Vin1 - VREFH
Vin2 - VDD
1. Use this option for the best ADC operation.
1
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Selected by ADCx_SC2[REFSEL] bits
Selected by CMPx_DACCR[VRSEL] bit
Page 44
ARM Cortex-M0+
Core
Debug Interrupts
Crossbar
switch

Core Modules

3.3
Core Modules

3.3.1 ARM Cortex-M0+ Core Configuration

This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at www.arm.com.
Figure 3-1. Core configuration
Table 3-3. Reference links to related information
Topic Related module Reference
Full description ARM Cortex-M0+ core,
r0p0
System memory map System memory map
Clocking Clock distribution
Power management Power management
System/instruction/data
bus module
Debug Serial Wire Debug
Interrupts Nested Vectored
Crossbar switch Crossbar switch
(SWD)
Interrupt Controller
(NVIC)
Miscellaneous Control
Module (MCM)
ARM Cortex-M0+ Technical Reference Manual, r0p0
Debug
NVIC
MCM
3.3.1.1 ARM Cortex M0+ Core
The ARM Cortex M0+ parameter settings are as follows:
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Chapter 3 Chip Configuration
Table 3-4. ARM Cortex-M0+ parameter settings
Parameter Verilog Name Value Description
Arch Clock Gating ACG 1 = Present Implements architectural clock gating
DAP Slave Port Support AHBSLV 1 Support any AHB debug access port (like the
CM4 DAP)
DAP ROM Table Base BASEADDR 0xF000_2003 Base address for DAP ROM table
Endianess BE 0 Little endian control for data transfers
Breakpoints BKPT 2 Implements 2 breakpoints
Debug Support DBG 1 = Present
Halt Event Support HALTEV 1 = Present
I/O Port IOP 1 = Present Implements single-cycle ld/st accesses to
special address space
IRQ Mask Enable IRQDIS 0x00000000 Assume (for now) all 32 IRQs are used (set if
IRQ is disabled)
Debug Port Protocol JTAGnSW 0 = SWD SWD protocol, not JTAG
Core Memory Protection MPU 0 = Absent No MPU
Number of IRQs NUMIRQ 32 Assume full NVIC request vector
Reset all regs RAR 0 = Standard Do not force all registers to be async reset
Multiplier SMUL 0 = Fast Mul Implements single-cycle multiplier
Multi-drop Support SWMD 0 = Absent Do not include serial wire support for multi-
drop
System Tick Timer SYST 1 = Present Implements system tick timer (for CM4
compatibility) DAP Target ID TARGETID 0 User/Privileged USER 1 = Present Implements processor operating modes
Vector Table Offset Register VTOR 1 = Present Implements relocation of exception vector
table
WIC Support WIC 1 = Present Implements WIC interface
WIC Requests WICLINES 34 Exact number of wakeup IRQs is 34
Watchpoints WPT 2 Implements 2 watchpoints
For details on the ARM Cortex-M0+ processor core, see the ARM website: www.arm.com.
3.3.1.2 Buses, Interconnects, and Interfaces
The ARM Cortex-M0+ core has two bus interfaces:
• single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all system memory, which includes flash and RAM.
• single 32-bit I/O port bus interfacing to the GPIO with 1-cycle loads and stores.
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Nested Vectored
Interrupt Controller
(NVIC)
ARM Cortex-M0+
core
Interrupts
Module
Module
Module
PPB
Core Modules
3.3.1.3 System Tick Timer
The CLKSOURCE bit in SysTick Control and Status register selects either the core clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock (when CLKSOURCE = 0). Because the timing reference is a variable frequency, the TENMS bit in the SysTick Calibration Value Register is always zero.
3.3.1.4 Debug Facilities
This device supports standard ARM 2-pin SWD debug port.
3.3.1.5 Core Privilege Levels
The Core on this device is implemented with both Privileged and Unprivileged levels. The ARM documentation uses different terms than this document to distinguish between privilege levels.
If you see this term... it also means this term...
Privileged Supervisor Unprivileged or user User

3.3.2 Nested Vectored Interrupt Controller (NVIC) Configuration

This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at www.arm.com.
Figure 3-2. NVIC configuration
Table 3-5. Reference links to related information
Topic Related module Reference
Full description Nested Vectored
Interrupt Controller
(NVIC)
System memory map System memory map
Clocking Clock distribution
ARM Cortex-M0+ Technical Reference Manual
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Chapter 3 Chip Configuration
Table 3-5. Reference links to related information (continued)
Topic Related module Reference
Power management Power management
Private Peripheral Bus
(PPB)
ARM Cortex-M0+ core ARM Cortex-M0+ core
3.3.2.1 Interrupt priority levels
This device supports 4 priority levels for interrupts. Therefore, in the NVIC each source in the IPR registers contains 2 bits. For example, IPR0 is shown below:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R W
IRQ3
0 0 0 0 0 0
IRQ2
0 0 0 0 0 0
IRQ1
0 0 0 0 0 0
IRQ0
0 0 0 0 0 0
3.3.2.2 Non-maskable interrupt
The non-maskable interrupt request to the NVIC is controlled by the external NMI signal. The pin the NMI signal is multiplexed on, must be configured for the NMI function to generate the non-maskable interrupt request.
3.3.2.3 Interrupt channel assignments
The interrupt vector assignments are defined in the following table.
• Vector number — the value stored on the stack when an interrupt is serviced.
• IRQ number — non-core interrupt source count, which is the vector number minus
16.
The IRQ number is used within ARM's NVIC documentation.
Table 3-7. Interrupt vector assignments
Address Vector IRQ
ARM Core System Handler Vectors
0x0000_0000 0 — — ARM core Initial Stack Pointer 0x0000_0004 1 — — ARM core Initial Program Counter
1
NVIC
IPR
register
number
Source module Source description
2
Table continues on the next page...
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Core Modules
Table 3-7. Interrupt vector assignments (continued)
Address Vector IRQ
0x0000_0008 2 — — ARM core Non-maskable Interrupt (NMI) 0x0000_000C 3 — — ARM core Hard Fault 0x0000_0010 4 — — — — 0x0000_0014 5 — — — — 0x0000_0018 6 — — — — 0x0000_001C 7 — — — — 0x0000_0020 8 — — — — 0x0000_0024 9 — — — — 0x0000_0028 10 — — — — 0x0000_002C 11 — — ARM core Supervisor call (SVCall) 0x0000_0030 12 — — — — 0x0000_0034 13 — — — — 0x0000_0038 14 — — ARM core Pendable request for system service
0x0000_003C 15 — — ARM core System tick timer (SysTick)
Non-Core Vectors
0x0000_0040 16 0 0 DMA DMA channel 0 transfer complete and error 0x0000_0044 17 1 0 DMA DMA channel 1 transfer complete and error 0x0000_0048 18 2 0 DMA DMA channel 2 transfer complete and error 0x0000_004C 19 3 0 DMA DMA channel 3 transfer complete and error 0x0000_0050 20 4 1 — — 0x0000_0054 21 5 1 FTFA Command complete and read collision 0x0000_0058 22 6 1 PMC Low-voltage detect, low-voltage warning 0x0000_005C 23 7 1 LLWU Low Leakage Wakeup 0x0000_0060 24 8 2 I2C0 0x0000_0064 25 9 2 — 0x0000_0068 26 10 2 SPI0 Single interrupt vector for all sources 0x0000_006C 27 11 2 — 0x0000_0070 28 12 3 UART0 Status and error 0x0000_0074 29 13 3 — 0x0000_0078 30 14 3 — 0x0000_007C 31 15 3 ADC0 0x0000_0080 32 16 4 CMP0 0x0000_0084 33 17 4 TPM0 0x0000_0088 34 18 4 TPM1 0x0000_008C 35 19 4 — 0x0000_0090 36 20 5 RTC Alarm interrupt 0x0000_0094 37 21 5 RTC Seconds interrupt
1
NVIC
IPR
register
number
Source module Source description
2
(PendableSrvReq)
Table continues on the next page...
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Chapter 3 Chip Configuration
Table 3-7. Interrupt vector assignments (continued)
Address Vector IRQ
0x0000_0098 38 22 5 PIT Single interrupt vector for all channels 0x0000_009C 39 23 5 — — 0x0000_00A0 40 24 6 — 0x0000_00A4 41 25 6 — 0x0000_00A8 42 26 6 — 0x0000_00AC 43 27 6 MCG 0x0000_00B0 44 28 7 LPTMR0 0x0000_00B4 45 29 7 — 0x0000_00B8 46 30 7 Port control module Pin detect (Port A) 0x0000_00BC 47 31 7 Port control module Pin detect (Port B )
1. Indicates the NVIC's interrupt source number.
2. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4
1
NVIC
IPR
register
number
Source module Source description
2
3.3.2.3.1 Determining the bitfield and register location for configuring a particular interrupt
Suppose you need to configure the SPI0 interrupt. The following table is an excerpt of the SPI0 row from Interrupt priority levels.
Table 3-8. Interrupt vector assignments
Address Vector IRQ
0x0000_0068 26 10 2 SPI0 Single interrupt vector for all sources
1. Indicates the NVIC's interrupt source number.
2. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4.
1
NVIC IPR
register
number
Source module Source description
2
• The NVIC registers you would use to configure the interrupt are:
• NVICIPR2
• To determine the particular IRQ's bitfield location within these particular registers:
• NVICIPR2 bitfield starting location = 8 * (IRQ mod 4) + 6 = 22
Since the NVICIPR bitfields are 2-bit wide (4 priority levels), the NVICIPR2 bitfield range is 22-23
Therefore, the following bitfield locations are used to configure the SPI0 interrupts:
• NVICIPR2[23:22]
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Page 50
Asynchronous
Wake-up Interrupt
Controller (AWIC)
Nested vectored
interrupt controller
(NVIC)
Wake-up
requests
Module
Module
Clock logic
Core Modules
3.3.3 Asynchronous wake-up interrupt controller (AWIC)
configuration
This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at www.arm.com.
Figure 3-3. Asynchronous wake-up interrupt controller configuration
Table 3-9. Reference links to related information
Topic Related module Reference
System memory map System memory map
Clocking Clock distribution
Power management Power management
Nested vectored
interrupt controller
(NVIC)
Wake-up requests AWIC wake-up sources
NVIC
3.3.3.1 Wake-up sources
The device uses the following internal and external inputs to the AWIC module.
Table 3-10. AWIC stop wake-up sources
Wake-up source Description
Available system resets RESET pin when LPO is its clock source Low-voltage detect Power management controller - functional in Stop mode Low-voltage warning Power management controller - functional in Stop mode Pin interrupts Port control module - any enabled pin interrupt is capable of waking the system ADC The ADC is functional when using internal clock source CMP0 Interrupt in normal or trigger mode
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Page 51
Table 3-10. AWIC stop wake-up sources (continued)
Register access
Peripheral
bridge
System integration
module (SIM)
Wake-up source Description
I2Cx Address match wakeup UART0 Any interrupt provided clock remains enabled RTC Alarm or seconds interrupt NMI NMI pin TPMx Any interrupt provided clock remains enabled LPTMR Any interrupt provided clock remains enabled SPI Slave mode interrupt
Chapter 3 Chip Configuration
3.4

System Modules

3.4.1 SIM Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-4. SIM configuration
Table 3-11. Reference links to related information
Topic Related module Reference
Full description SIM SIM
System memory map System memory map
Clocking Clock distribution
Power management Power management
Freescale Semiconductor, Inc. 51
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Power Management
Controller (PMC)
Register access
Peripheral
bridge
System Mode
Controller (SMC)
Resets
System Modules

3.4.2 System Mode Controller (SMC) Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-5. System Mode Controller configuration
Table 3-12. Reference links to related information
Topic Related module Reference
Full description System Mode
Controller (SMC)
System memory map System memory map
Power management Power management
Power management
controller (PMC)
Low-Leakage Wakeup
Unit (LLWU)
Reset Control Module
(RCM)
SMC
PMC
LLWU
Reset
3.4.2.1 VLLS2 not supported
VLLS2 power mode is not supported on this device.

3.4.3 PMC Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Register access
Power Management
Controller (PMC)
Module signals
Peripheral
bridge
Module signals
System Mode
Controller (SMC)
Low-Leakage
Wakeup Unit
Chapter 3 Chip Configuration
Figure 3-6. PMC configuration
Table 3-13. Reference links to related information
Topic Related module Reference
Full description PMC PMC
System memory map System memory map
Power management Power management
Full description System Mode
Controller (SMC)
Low-Leakage Wakeup
Unit (LLWU)
Reset Control Module
(RCM)
System Mode Controller
LLWU
Reset

3.4.4 Low-Leakage Wake-up Unit (LLWU) Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Low-Leakage Wake-up
Unit (LLWU)
Power Management
Controller (PMC)
Peripheral
bridge 0
Register access
Wake-up
requests
Module
Module
System Modules
Figure 3-7. Low-Leakage Wake-up Unit configuration
Table 3-14. Reference links to related information
Topic Related module Reference
Full description LLWU LLWU
System memory map System memory map
Clocking Clock distribution
Power management Power management chapter
Power Management
Controller (PMC)
System Mode
Controller (SMC)
Wake-up requests LLWU wake-up sources
Power Management Controller (PMC)
System Mode Controller
3.4.4.1 LLWU interrupt
3.4.4.2 Wake-up Sources
The device uses the following internal peripheral and external pin inputs as wakeup sources to the LLWU module. LLWU_Px are external pin inputs, and LLWU_M0IF­M7IF are connections to the internal peripheral interrupt flags.
54 Freescale Semiconductor, Inc.
Do not mask the LLWU interrupt when in LLS mode. Masking the interrupt prevents the device from exiting stop mode when a wakeup is detected.
In addition to the LLWU wakeup sources, the device also wakes from low power modes when NMI or RESET pins are enabled and the respective pin is asserted.
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NOTE
NOTE
Page 55
Miscellaneous
Control Module
(MCM)
Transfers
ARM Cortex-M0+
core
Flash Memory
Controller
Transfers
Chapter 3 Chip Configuration
Table 3-15. LLWU Wakeup Sources
IRQ Module source or pin name
LLWU_P0 PTA4 LLWU_P1 PTA5 LLWU_P2 PTA6 LLWU_P3 PTA7 LLWU_P4 PTB0 LLWU_P5 PTB2 LLWU_P6 PTB4
LLWU_P7 PTA0 LLWU_M0IF LPTMR0 LLWU_M1IF CMP0 LLWU_M2IF Reserved LLWU_M3IF Reserved LLWU_M4IF TSI0 LLWU_M5IF RTC Alarm LLWU_M6IF Reserved LLWU_M7IF RTC Seconds

3.4.5 MCM Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-8. MCM configuration
Table 3-16. Reference links to related information
Topic Related module Reference
Full description Miscellaneous control
module (MCM)
System memory map System memory map
Clocking Clock distribution
Power management Power management
Private Peripheral Bus
(PPB)
ARM Cortex-M0+ core ARM Cortex-M0+ core
MCM
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Crossbar Switch
Slave Modules
Master Modules
M2
M0
S0
S2
ARM core
unified bus
DMA
Flash
controller
S1
SRAML
BME
Peripheral
bridge 0
GPIO
controller
SRAMU
Peripherals
System Modules
Table 3-16. Reference links to related information (continued)
Topic Related module Reference
Transfer Flash memory
Flash memory controller
controller

3.4.6 Crossbar-Light Switch Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
56 Freescale Semiconductor, Inc.
Figure 3-9. Crossbar-Light switch integration
Table 3-17. Reference links to related information
Topic Related module Reference
Full description Crossbar switch Crossbar Switch
System memory map System memory map
Clocking Clock Distribution Crossbar switch master ARM Cortex-M0+ core ARM Cortex-M0+ core Crossbar switch master DMA controller DMA controller
Crossbar switch slave Flash memory
controller Crossbar switch slave SRAM controller SRAM configuration Crossbar switch slave Peripheral bridge Peripheral bridge
2-ported peripheral GPIO controller GPIO controleer
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Flash memory controller
Page 57
Peripherals
Transfers
AIPS-Lite
peripheral bridge
Transfers
Crossbar switch
Chapter 3 Chip Configuration
3.4.6.1 Crossbar-Light Switch Master Assignments
The masters connected to the crossbar switch are assigned as follows:
Master module Master port number
ARM core unified bus 0 DMA 2
3.4.6.2 Crossbar Switch Slave Assignments
This device contains 3 slaves connected to the crossbar switch. The slave assignment is as follows:
Slave module Slave port number
Flash memory controller 0 SRAM controller 1 Peripheral bridge 0 2

3.4.7 Peripheral Bridge Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-10. Peripheral bridge configuration
Table 3-18. Reference links to related information
Topic Related module Reference
Full description Peripheral bridge
(AIPS-Lite)
System memory map System memory map
Clocking Clock Distribution
Crossbar switch Crossbar switch Crossbar switch
Peripheral bridge (AIPS-Lite)
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DMA Request
Multiplexer
DMA controller
Requests
Module
Module
Module
Peripheral
bridge 0
Register access
Channel
request
System Modules
3.4.7.1 Number of peripheral bridges
This device contains one peripheral bridge.
3.4.7.2 Memory maps
The peripheral bridges are used to access the registers of most of the modules on this device. See AIPS0 Memory Map for the memory slot assignment for each module.

3.4.8 DMA request multiplexer configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-11. DMA request multiplexer configuration
Table 3-19. Reference links to related information
Topic Related module Reference
Full description DMA request
multiplexer
System memory map System memory map
Clocking Clock distribution
Power management Power management
Channel request DMA controller DMA Controller
Requests DMA request sources
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DMA Mux
Page 59
Chapter 3 Chip Configuration
3.4.8.1 DMA MUX Request Sources
This device includes a DMA request mux that allows up to 63 DMA request signals to be mapped to any of the 4 DMA channels. Because of the mux there is no hard correlation between any of the DMA request sources and a specific DMA channel. Some of the modules support Asynchronous DMA operation as indicated by the last column in the following DMA source assignment table.
Table 3-20. DMA request sources - MUX 0
Source
number
0 — Channel disabled 1 Reserved Not used 2 UART0 Receive Yes 3 UART0 Transmit Yes 4 Reserved — 5 Reserved — 6 Reserved — 7 Reserved — 8 Reserved —
9 Reserved — 10 Reserved — 11 Reserved — 12 Reserved — 13 Reserved — 14 Reserved — 15 Reserved — 16 SPI0 Receive 17 SPI0 Transmit 18 Reserved — 19 Reserved — 20 Reserved — 21 Reserved — 22 I2C0 — 23 Reserved — 24 TPM0 Channel 0 Yes 25 TPM0 Channel 1 Yes 26 TPM0 Channel 2 Yes 27 TPM0 Channel 3 Yes 28 TPM0 Channel 4 Yes 29 TPM0 Channel 5 Yes 30 Reserved —
Source module Source description Async DMA
1
capable
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System Modules
Table 3-20. DMA request sources - MUX 0 (continued)
Source
number
31 Reserved — 32 TPM1 Channel 0 Yes 33 TPM1 Channel 1 Yes 34 Reserved — 35 Reserved — 36 Reserved — 37 Reserved — 38 Reserved — 39 Reserved — 40 ADC0 — Yes 41 Reserved — 42 CMP0 — Yes 43 Reserved — 44 Reserved — 45 Reserved — 46 Reserved — 47 Reserved — 48 Reserved — 49 Port control module Port A Yes 50 Port control module Port B Yes 51 Reserved — 52 Reserved — 53 Reserved — 54 TPM0 Overflow Yes 55 TPM1 Overflow Yes 56 Reserved — 57 Reserved — 58 Reserved — 59 Reserved — 60 DMA MUX Always enabled 61 DMA MUX Always enabled 62 DMA MUX Always enabled 63 DMA MUX Always enabled
Source module Source description Async DMA
capable
1. Configuring a DMA channel to select source 0 or any of the reserved sources disables that DMA channel.
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DMA Controller
Crossbar switch
Requests
Peripheral
bridge 0
Register access
Transfers
DMA Multiplexer
Chapter 3 Chip Configuration
3.4.8.2 DMA transfers via PIT trigger
The PIT module can trigger a DMA transfer on the first two DMA channels. The assignments are detailed at PIT/DMA Periodic Trigger Assignments .

3.4.9 DMA Controller Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-12. DMA Controller configuration
Table 3-21. Reference links to related information
Topic Related module Reference
Full description DMA controller DMA controller
System memory map System memory map
Clocking Clock distribution
Power management Power management
Crossbar switch Crossbar switch Crossbar switch
Requests DMA request sources

3.4.10 Computer Operating Properly (COP) Watchdog Configuration

This section summarizes how the module has been configured in the chip.
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WDOG
Mode Controller
Peripheral
bridge 0
Register access
System Modules
Figure 3-13. COP watchdog configuration
Table 3-22. Reference links to related information
Topic Related module Reference
Clocking Clock distribution Power management Power management Programming model System Integration
Module (SIM)
SIM
3.4.10.1 COP clocks
The two clock inputs for the COP are the 1 kHz clock and the bus clock.
3.4.10.2 COP watchdog operation
The COP watchdog is intended to force a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter before it times out, a system reset is generated to force the system back to a known starting point.
After any reset, the COP watchdog is enabled. If the COP watchdog is not used in an application, it can be disabled by clearing COPCTRL[COPT] in the SIM.
The COP counter is reset by writing 0x55 and 0xAA (in that order) to the address of the SIM's Service COP (SRVCOP) register during the selected timeout period. Writes do not affect the data in the SRVCOP register. As soon as the write sequence is complete, the COP timeout period is restarted. If the program fails to perform this restart during the timeout period, the microcontroller resets. Also, if any value other than 0x55 or 0xAA is written to the SRVCOP register, the microcontroller immediately resets.
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Chapter 3 Chip Configuration
The SIM's COPCTRL[COPCLKS] field selects the clock source used for the COP timer. The clock source options are either the bus clock or an internal 1 kHz clock source. With each clock source, there are three associated timeouts controlled by COPCTRL[COPT]. The following table summarizes the control functions of the COPCLKS and COPT bits. The COP watchdog defaults to operation from the 1 kHz clock source and the longest timeout for that clock source (210 cycles).
Table 3-23. COP configuration options
Control Bits Clock Source COP Window Opens
COPCTRL[COPCLKS] COPCTRL[COPT]
N/A 00 N/A N/A COP is disabled
0 01 1 kHz N/A 25 cycles (32 ms) 0 10 1 kHz N/A 28 cycles (256 ms) 0 11 1 kHz N/A 210 cycles (1024 ms) 1 01 Bus 6,144 cycles 213 cycles 1 10 Bus 49,152 cycles 216 cycles 1 11 Bus 196,608 cycles 218 cycles
(COPCTRL[COPW]=1)
COP Overflow Count
After the bus clock source is selected, windowed COP operation is available by setting COPCTRL[COPW] in the SIM. In this mode, writes to the SRVCOP register to clear the COP timer must occur in the last 25% of the selected timeout period. A premature write immediately resets the chip. When the 1 kHz clock source is selected, windowed COP operation is not available.
The COP counter is initialized by the first writes to the SIM's COPCTRL register and after any system reset. Subsequent writes to the SIM's COPCTRL register have no effect on COP operation. Even if an application uses the reset default settings of the COPT, COPCLKS, and COPW bits, the user should write to the write-once COPCTRL register during reset initialization to lock in the settings. This approach prevents accidental changes if the application program becomes lost.
The write to the SRVCOP register that services (clears) the COP counter should not be placed in an interrupt service routine (ISR) because the ISR could continue to be executed periodically even if the main application program fails.
If the bus clock source is selected, the COP counter does not increment while the microcontroller is in debug mode or while the system is in stop (including VLPS or LLS) mode. The COP counter resumes when the microcontroller exits debug mode or stop mode.
If the 1 kHz clock source is selected, the COP counter is re-initialized to zero upon entry to either debug mode or stop (including VLPS or LLS) mode. The counter begins from zero upon exit from debug mode or stop mode.
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Register access
Peripheral
bridge
Multipurpose Clock
Generator (MCG)
System
oscillator
System integration
module (SIM)

Clock Modules

Regardless of the clock selected, the COP is disabled when the chip enters a VLLSx mode. Upon a reset that wakes the chip from the VLLSx mode, the COP is re-initialized and enabled as for any reset.
3.4.10.3 Clock Gating
This family of devices includes clock gating control for each peripheral, that is, the clock to each peripheral can explicitly be gated on or off, using clock-gate control bits in the SIM module.
3.5
Clock Modules

3.5.1 MCG Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-14. MCG configuration
Table 3-24. Reference links to related information
Topic Related module Reference
Full description MCG MCG
System memory map System memory map
Clocking Clock distribution Power management Power management
Signal multiplexing Port control Signal multiplexing
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Signal multiplexing
Register access
Peripheral
bridge
System oscillator
MCG
Module signals
RTC
Chapter 3 Chip Configuration
3.5.1.1 MCG FLL modes
On L-series devices the MCGFLLCLK frequency is limited to 48 MHz max. The DCO is limited to the two lowest range settings (MCG_C4[DRST_DRS] must be set to either 0b00 or 0b01).

3.5.2 OSC Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-15. OSC configuration
Table 3-25. Reference links to related information
Topic Related module Reference
Full description OSC OSC
System memory map System memory map
Clocking Clock distribution Power management Power management
Signal multiplexing Port control Signal multiplexing
Full description MCG MCG
3.5.2.1 OSC modes of operation with MCG and RTC
The most common method of controlling the OSC block is through MCG clock source selection MCG_C1[CLKS] and the MCG_C2 register bits to configure the oscillator frequency range, gain-mode, and for crystal or external clock operation. The OSC_CR also provides control for enabling the OSC and configuring internal load capacitors for the EXTAL and XTAL pins. See the OSC and MCG chapters for more details.
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Register access
Flash memory
Transfers
Flash memory
controller
Peripheral bus
controller 0

Memories and Memory Interfaces

The RTC_CR[OSCE] bit has overriding control over the MCG and OSC_CR enable functions. When RTC_CR[OSCE] is set, the OSC is configured for low frequency, low power and the RTC_CR[SCxP] bits override the OSC_CR[SCxP] bits to control the internal capacitance configuration. See the RTC chapter for more details.
3.6
Memories and Memory Interfaces

3.6.1 Flash Memory Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-16. Flash memory configuration
Table 3-26. Reference links to related information
Topic Related module Reference
Full description Flash memory Flash memory
System memory map System memory map
Clocking Clock Distribution
Transfers Flash memory
controller
Register access Peripheral bridge Peripheral bridge
Flash memory controller
3.6.1.1 Flash Memory Sizes
The devices covered in this document contain 1 program flash block consisting of 1 KB sectors.
The amounts of flash memory for the devices covered in this document are:
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Program flash
Flash configuration field
Program flash base address
Flash memory base address
Registers
Chapter 3 Chip Configuration
Table 3-27. KL04 flash memory size
Device Program flash (KB) Block 0 (P-Flash) address range
MKL04Z8VFK4 8 0x0000_0000 – 0x0000_1FFF MKL04Z16VFK4 16 0x0000_0000 – 0x0000_3FFF MKL04Z32VFK4 32 0x0000_0000 – 0x0000_7FFF
MKL04Z8VLC4 8 0x0000_0000 – 0x0000_1FFF MKL04Z16VLC4 16 0x0000_0000 – 0x0000_3FFF MKL04Z32VLC4 32 0x0000_0000 – 0x0000_7FFF
MKL04Z8VFM4 8 0x0000_0000 – 0x0000_1FFF MKL04Z16VFM4 16 0x0000_0000 – 0x0000_3FFF MKL04Z32VFM4 32 0x0000_0000 – 0x0000_7FFF
MKL04Z16VLF4 16 0x0000_0000 – 0x0000_3FFF MKL04Z32VLF4 32 0x0000_0000 – 0x0000_7FFF
3.6.1.2 Flash Memory Map
The flash memory and the flash registers are located at different base addresses as shown in the following figure. The base address for each is specified in System memory map.
Figure 3-17. Flash memory map
The on-chip Flash is implemented in a portion of the allocated Flash range to form a contiguous block in the memory map beginning at address 0x0000_0000. See Flash
Memory Sizes for details of supported ranges.
Accesses to the flash memory ranges outside the amount of Flash on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master. Read collision events in which flash memory is accessed while a flash memory resource is being manipulated by a flash command also generates a bus error response.
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Memories and Memory Interfaces
3.6.1.3 Flash Security
How flash security is implemented on this device is described in Chip Security.
3.6.1.4 Flash Modes
The flash memory chapter defines two modes of operation - NVM normal and NVM special modes. On this device, The flash memory only operates in NVM normal mode. All references to NVM special mode should be ignored.
3.6.1.5 Erase All Flash Contents
In addition to software, the entire flash memory may be erased external to the flash memory via the SW-DP debug port by setting MDM-AP CONTROL[0]. MDM-AP STATUS[0] is set to indicate the mass erase command has been accepted. MDM-AP STATUS[0] is cleared when the mass erase completes.
3.6.1.6 FTFA_FOPT Register
The flash memory's FTFA_FOPT register allows the user to customize the operation of the MCU at boot time. See FOPT boot options for details of its definition.

3.6.2 Flash Memory Controller Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
See MCM_PLACR register description for details on the reset configuration of the FMC.
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Flash memory
controller
Transfers
Transfers
Flash memory
Crossbar switch
MCM
SRAM upper
Transfers
Cortex-M0+
core
switch
SRAM lower
crossbar
SRAM
controller
Chapter 3 Chip Configuration
Figure 3-18. Flash memory controller configuration
Table 3-28. Reference links to related information
Topic Related module Reference
Full description Flash memory
controller
System memory map System memory map
Clocking Clock Distribution Transfers Flash memory Flash memory Transfers Crossbar switch Crossbar Switch
Register access MCM MCM
Flash memory controller

3.6.3 SRAM Configuration

This section summarizes how the module has been configured in the chip.
Figure 3-19. SRAM configuration
Table 3-29. Reference links to related information
Topic Related module Reference
Full description SRAM SRAM
System memory map System memory map
Clocking Clock Distribution
ARM Cortex-M0+ core ARM Cortex-M0+ core
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Memories and Memory Interfaces
3.6.3.1 SRAM Sizes
This device contains SRAM which could be accessed by bus masters through the cross­bar switch. The amount of SRAM for the devices covered in this document is shown in the following table.
Table 3-30. KL04 SRAM memory size
Device SRAM (KB)
MKL04Z8VFK4 1 MKL04Z16VFK4 2 MKL04Z32VFK4 4
MKL04Z8VLC4 1 MKL04Z16VLC4 2 MKL04Z32VLC4 4
MKL04Z8VFM4 1 MKL04Z16VFM4 2 MKL04Z32VFM4 4
MKL04Z16VLF4 2 MKL04Z32VLF4 4
3.6.3.2 SRAM Ranges
The on-chip SRAM is split into two ranges, 1/4 is allocated SRAM_L and 3/4 is allocated to SRAM_U.
The on-chip RAM is implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in the memory map. As such:
• SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending address.
• SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning address.
Valid address ranges for SRAM_L and SRAM_U are then defined as:
• SRAM_L = [0x2000_0000–(SRAM_size/4)] to 0x1FFF_FFFF
• SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size*(3/4))-1]
This is illustrated in the following figure.
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SRAM_U
0x2000_0000
SRAM size *(1/4)
SRAM_L
0x1FFF_FFFF
SRAM size * (3/4)
0x2000_0000 – SRAM_size/4
0x2000_0000 + SRAM_size(3/4) - 1
Chapter 3 Chip Configuration
For example, for a device containing 16 KB of SRAM the ranges are:
• SRAM_L: 0x1FFF_F000 – 0x1FFF_FFFF
• SRAM_U: 0x2000_0000 – 0x2000_2FFF
3.6.3.3 SRAM retention in low power modes
The SRAM is retained down to VLLS3 mode. In VLLS1 and VLLS0 no SRAM is retained.
3.7

Analog

3.7.1 12-bit SAR ADC Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-20. SRAM blocks memory map
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Signal multiplexing
Module signals
Register access
12-bit SAR ADC
Peripheral bus
controller 0
Other peripherals
Analog
Figure 3-21. 12-bit SAR ADC configuration
Table 3-31. Reference links to related information
Topic Related module Reference
Full description 12-bit SAR ADC 12-bit SAR ADC
System memory map System memory map
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.7.1.1 ADC Instantiation Information
This device contains one 12-bit successive approximation ADC with up to 14-channels. The ADC supports both software and hardware triggers. The hardware trigger sources are
listed in the Module-to-Module section. The number of ADC channels present on the device is determined by the pinout of the
specific device package and is shown in the following table.
Table 3-32. Number of KL04 ADC channels
Device Number of ADC channels
MKL04Z8VFK4 12 MKL04Z16VFK4 12 MKL04Z32VFK4 12
MKL04Z8VLC4 14 MKL04Z16VLC4 14 MKL04Z32VLC4 14
MKL04Z8VFM4 14 MKL04Z16VFM4 14 MKL04Z32VFM4 14
MKL04Z16VLF4 14
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Chapter 3 Chip Configuration
Table 3-32. Number of KL04 ADC channels (continued)
Device Number of ADC channels
MKL04Z32VLF4 14
3.7.1.2 DMA Support on ADC
Applications may require continuous sampling of the ADC that may have considerable load on the CPU. The ADC supports DMA request functionality for higher performance when the ADC is sampled at a very high rate. The ADC can trigger the DMA (via DMA req) on conversion completion.
3.7.1.3 ADC0 Connections/Channel Assignment
3.7.1.3.1 ADC0 Channel Assignment
ADC Channel
(SC1n[ADCH])
00000 AD0 Reserved ADC0_SE0 00001 AD1 Reserved ADC0_SE1 00010 AD2 Reserved ADC0_SE2 00011 AD3 Reserved ADC0_SE3 00100 AD4 Reserved ADC0_SE4 00101 AD5 Reserved ADC0_SE5 00110 AD6 Reserved ADC0_SE6 00111 AD7 Reserved ADC0_SE7 01000 AD8 Reserved ADC0_SE8 01001 AD9 Reserved ADC0_SE9 01010 AD10 Reserved ADC0_SE10 01011 AD11 Reserved ADC0_SE11 01100 AD12 Reserved ADC0_SE12 01101 AD13 Reserved ADC0_SE13 01110 AD14 Reserved Reserved 01111 AD15 Reserved Reserved 10000 AD16 Reserved Reserved 10001 AD17 Reserved Reserved 10010 AD18 Reserved Reserved 10011 AD19 Reserved Reserved 10100 AD20 Reserved Reserved
Channel Input signal
(SC1n[DIFF]= 1)
Input signal
(SC1n[DIFF]= 0)
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Analog
ADC Channel
(SC1n[ADCH])
10101 AD21 Reserved Reserved 10110 AD22 Reserved Reserved 10111 AD23 Reserved Reserved 11000 AD24 Reserved Reserved 11001 AD25 Reserved Reserved 11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E) 11011 AD27 Bandgap (Diff) 11100 AD28 Reserved Reserved 11101 AD29 -VREFH (Diff) VREFH (S.E) 11110 AD30 Reserved VREFL 11111 AD31 Module Disabled Module Disabled
1. This is the PMC bandgap 1V reference voltage. Prior to reading from this ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (VBG) specification.
Channel Input signal
(SC1n[DIFF]= 1)
1
Input signal
(SC1n[DIFF]= 0)
Bandgap (S.E)
1
3.7.1.4 ADC Analog Supply and Reference Connections
This device internally connects VDDA to VDD and VSSA to VSS. This device contains separate VREFH and VREFL pins on 32-pin and higher devices.
These pins are internally connected to VDD and VSS respectively, on packages less than 32-pin.
3.7.1.5 ADC Reference Options
The ADC supports the following references:
• VREFH/VREFL - connected as the primary reference option
• VDDA - connected as the V
reference option
ALT
3.7.1.6 Alternate clock
For this device, the alternate clock is connected to OSCERCLK.
NOTE
This clock option is only usable when OSCERCLK is in the MHz range. A system with OSCERCLK in the kHz range has the optional clock source below minimum ADC clock operating frequency.
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Signal multiplexing
Module signals
Register access
CMP
Peripheral
bridge 0
Other peripherals
Chapter 3 Chip Configuration

3.7.2 CMP Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-22. CMP configuration
Table 3-33. Reference links to related information
Topic Related module Reference
Full description Comparator (CMP) Comparator
System memory map System memory map
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.7.2.1 CMP Instantiation Information
The device includes one high speed comparator and two 8-input multiplexors for both the inverting and non-inverting inputs of the comparator. Each CMP input channel connects to both muxes. Two of the channels are connected to internal sources, leaving resources to support up to 6 input pins. See the channel assignment table for a summary of CMP input connections for this device.
The CMP also includes one 6-bit DAC with a 64-tap resistor ladder network, which provides a selectable voltage reference for applications where voltage reference is needed for internal connection to the CMP.
The CMP can be optionally on in all modes except VLLS0. The CMP has several module to module interconnects in order to facilitate ADC
triggering, TPM triggering and UART IR interfaces. For complete details on the CMP module interconnects please refer to the Module-to-Module section.
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Analog
The CMP does not support window compare function and CMP_CR1[WE] must always be written to 0. The sample function has limited functionality since the SAMPLE input to the block is not connected to a valid input. Usage of sample operation is limited to a divided version of the bus clock (CMP_CR1[SE] = 0).
Due to the pin number limitation, the CMP pass through mode is not supported by this device, so the CMPx_MUXCR[PSTM] must be left as 0.
3.7.2.2 CMP input connections
The following table shows the fixed internal connections to the CMP.
Table 3-34. CMP input connections
CMP Inputs CMP0
IN0 CMP0_IN0 IN1 CMP0_IN1 IN2 CMP0_IN2 IN3 CMP0_IN3 IN4 — IN5 — IN6 Bandgap IN7 6-bit DAC0 reference
1
1. This is the PMC bandgap 1V reference voltage. Prior to using as CMP input, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data sheet for the bandgap voltage (VBG) specification.
3.7.2.3 CMP external references
The 6-bit DAC sub-block supports selection of two references. For this device, the references are connected as follows:
• VREFH - V
input. When using VREFH, any ADC conversion using this same
in1
reference at the same time is negatively impacted.
• VDD - V
in2
input
3.7.2.4 CMP trigger mode
The CMP and 6-bit DAC sub-block supports trigger mode operation when the CMP_CR1[TRIGM] is set. When trigger mode is enabled, the trigger event will initiate a compare sequence that must first enable the CMP and DAC prior to performing a CMP operation and capturing the output. In this device, control for this two staged sequencing
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is provided from the LPTMR. The LPTMR triggering output is always enabled when the LPTMR is enabled. The first signal is supplied to enable the CMP and DAC and is asserted at the same time as the TCF flag is set. The delay to the second signal that triggers the CMP to capture the result of the compare operation is dependent on the LPTMR configuration. In Time Counter mode with prescaler enabled, the delay is 1/2 Prescaler output period. In Time Counter mode with prescaler bypassed, the delay is 1/2 Prescaler clock period.
The delay between the first signal from LPTMR and the second signal from LPTMR must be greater than the Analog comparator initialization delay as defined in the device datasheet.
3.8

Timers

3.8.1 Timer/PWM Module Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-23. TPM configuration
Table 3-35. Reference links to related information
Topic Related module Reference
Full description Timer/PWM Module Timer/PWM Module
System memory map System memory map
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
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Timers
3.8.1.1 TPM Instantiation Information
This device contains two Low Power TPM modules (TPM). All TPM modules in the device only are configured as basic TPM function, and no quadrature decoder function and all can be functional in Stop/VLPS mode. The clock source is either external or internal in Stop/VLPS mode.
The following table shows how these modules are configured.
Table 3-36. TPM configuration
TPM instance Number of channels Features/usage
TPM0 6 Basic TPM,functional in Stop/VLPS mode TPM1 2 Basic TPM,functional in Stop/VLPS mode
There are several connections to and from the TPMs in order to facilitate customer use cases. For complete details on the TPM module interconnects please refer to the Module-
to-Module section.
3.8.1.2 Clock Options
The TPM blocks are clocked from a single TPM clock that can be selected from OSCERCLK, MCGIRCLK, or MCGFLLCLK. The selected source is controlled by SIM_SOPT2[TPMSRC] control registers.
Each TPM also supports an external clock mode (TPM_SC[CMOD]=1x) in which the counter increments after a synchronized (to the selected TPM clock source) rising edge detect of an external clock input. The available external clock (either TPM_CLKIN0 or TPM_CLKIN1) is selected by SIM_SOPT4[TPMxCLKSEL] control register. To guarantee valid operation the selected external clock must be less than half the frequency of the selected TPM clock source.
3.8.1.3 Trigger Options
Each TPM has a selectable trigger input source controlled by the TPMx_CONF[TRGSEL] field to use for starting the counter and/or reloading the counter. The options available are shown in the following table.
Table 3-37. TPM trigger options
TPMx_CONF[TRGSEL] Selected source
0000 External trigger pin input (EXTRG_IN)
Table continues on the next page...
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Chapter 3 Chip Configuration
Table 3-37. TPM trigger options (continued)
TPMx_CONF[TRGSEL] Selected source
0001 CMP0 output 0010 Reserved 0011 Reserved 0100 PIT trigger 0 0101 PIT trigger 1 0110 Reserved 0111 Reserved 1000 TPM0 overflow 1001 TPM1 overflow 1010 Reserved 1011 Reserved 1100 RTC alarm 1101 RTC seconds 1110 LPTMR trigger 1111 Reserved
3.8.1.4 Global Timebase
Each TPM has a global timebase feature controlled by the TPMx_CONF[GTBEEN] bit. TPM1 is configured as the global time when this option is enabled.
3.8.1.5 TPM Interrupts
The TPM has multiple sources of interrupt. However, these sources are OR'd together to generate a single interrupt request to the interrupt controller. When an TPM interrupt occurs, read the TPM status registers to determine the exact interrupt source.

3.8.2 PIT Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Register access
Peripheral
bridge
Periodic interrupt
timer
Timers
Figure 3-24. PIT configuration
Table 3-38. Reference links to related information
Topic Related module Reference
Full description PIT PIT
System memory map System memory map
Clocking Clock Distribution
Power management Power management
3.8.2.1 PIT/DMA Periodic Trigger Assignments
The PIT generates periodic trigger events to the DMA channel mux as shown in the table below.
Table 3-39. PIT channel assignments for periodic DMA triggering
PIT Channel DMA Channel Number
PIT Channel 0 DMA Channel 0 PIT Channel 1 DMA Channel 1
3.8.2.2 PIT/ADC Triggers
PIT triggers are selected as ADCx trigger sources using the SOPT7[ADCxTRGSEL] bits in the SIM module. For more details, refer to SIM chapter.
3.8.2.3 PIT/TPM Triggers
PIT triggers are selected as TPMx trigger sources using the TPMx_CONF[TRGSEL] bits in the TPM module. For more details, refer to TPM chapter.
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Chapter 3 Chip Configuration
3.8.2.4 PIT/DAC Triggers
PIT Channel 0 is configured as the DAC hardware trigger source. For more details, refer to DAC chapter.

3.8.3 Low-power timer configuration

Figure 3-25. LPT configuration
Table 3-40. Reference links to related information
Topic Related module Reference
Full description Low-power timer Low-power timer
System memory map System memory map
Clocking Clock Distribution
Power management Power management
Signal Multiplexing Port control Signal Multiplexing
3.8.3.1 LPTMR Instantiation Information
The low-power timer (LPTMR) allows operation during all power modes. The LPTMR can operate as a real-time interrupt or pulse accumulator. It includes a 15-bit prescaler (real-time interrupt mode) or glitch filter (pulse accumulator mode).
The LPTMR can be clocked from the internal reference clock, the internal 1 kHz LPO, OSCERCLK, or an external 32.768 kHz crystal. In VLLS0 mode, the clocking option is limited to an external pin with the OSC configured for bypass (external clock) operation.
An interrupt is generated (and the counter may reset) when the counter equals the value in the 16-bit compare register.
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Timers
3.8.3.2 LPTMR pulse counter input options
The LPTMR_CSR[TPS] bitfield configures the input source used in pulse counter mode. The following table shows the chip-specific input assignments for this bitfield.
LPTMR_CSR[TPS] Pulse counter input number Chip input
00 0 CMP0 output 01 1 LPTMR_ALT1 pin 10 2 LPTMR_ALT2 pin 11 3 LPTMR_ALT3 pin
3.8.3.3 LPTMR prescaler/glitch filter clocking options
The prescaler and glitch filter of the LPTMR module can be clocked from one of four sources determined by the LPTMR0_PSR[PCS] bitfield. The following table shows the chip-specific clock assignments for this bitfield.
NOTE
The chosen clock must remain enabled if the LPTMR is to continue operating in all required low-power modes.
LPTMR0_PSR[PCS] Prescaler/glitch filter clock
number
00 0 MCGIRCLK — internal reference clock
01 1 LPO — 1 kHz clock (not available in
10 2 ERCLK32K (not available in VLLS0
11 3 OSCERCLK — external reference clock
Chip clock
(not available in LLS and VLLS modes)
VLLS0 mode)
mode when using 32 kHz oscillator)
(not available in VLLS0 mode)
See Clock Distribution for more details on these clocks.

3.8.4 RTC configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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Register access
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Module signals
Real-time clock
Chapter 3 Chip Configuration
Figure 3-26. RTC configuration
Table 3-41. Reference links to related information
Topic Related module Reference
Full description RTC RTC
System memory map System memory map
Clocking Clock Distribution
Power management Power management
3.8.4.1 RTC Instantiation Information
RTC prescaler is clocked by ERCLK32K. RTC is reset on POR Only. RTC_CR[OSCE] can override the configuration of the System OSC, configuring the
OSC for 32 kHz crystal operation in all power modes except VLLS0, and through any System Reset. When OSCE is enabled, the RTC also overrides the capacitor configurations.
3.8.4.2 RTC_CLKOUT options
RTC_CLKOUT pin can be driven either with the RTC 1 Hz output or with the OSCERCLK on-chip clock source. Control for this option is through SIM_SOPT2[RTCCLKOUTSEL] bit.
When RTCCLKOUTSEL = 0, the RTC 1 Hz clock is output is selected on the RTC_CLKOUT pin. When RTCCLKOUTSEL = 1, OSCERCLK clock is output on the RTC_CLKOUT pin.
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SPI
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bridge
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Communication interfaces

3.9
Communication interfaces

3.9.1 SPI configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-27. SPI configuration
Table 3-42. Reference links to related information
Topic Related module Reference
Full description SPI SPI
System memory map System memory map
Clocking Clock Distribution
Signal Multiplexing Port control Signal Multiplexing
3.9.1.1 SPI Instantiation Information
This device contains one SPI module that supports 8-bit data length. SPI0 is clocked on the bus clock. The SPI supports DMA request and can operate in VLPS mode. When the SPI is
operating in VLPS mode, it will operate as a slave. SPI can wakeup MCU from VLPS mode upon reception of SPI data in slave mode.
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2
I C
Chapter 3 Chip Configuration

3.9.2 I2C Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Figure 3-28. I2C configuration
Table 3-43. Reference links to related information
Topic Related module Reference
Full description I2C I2C
System memory map System memory map
Clocking Clock Distribution
Power management Power management
Signal Multiplexing Port control Signal Multiplexing
3.9.2.1 IIC Instantiation Information
This device has one IIC module. When the package pins associated with IIC have their mux select configured for IIC
operation, the pins (SCL and SDA) are driven in a pseudo open drain configuration. The digital glitch filter implemented in the IIC0 module, controlled by the
I2C0_FLT[FLT] registers, is clocked from the bus clock and thus has filter granularity in bus clock cycle counts.

3.9.3 UART Configuration

This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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UART
Communication interfaces
Figure 3-29. UART configuration
Table 3-44. Reference links to related information
Topic Related module Reference
Full description UART0 UART
System memory map System memory map
Clocking Clock Distribution
Power management Power management
Signal Multiplexing Port control Signal Multiplexing
3.9.3.1 UART0 overview
The UART0 module supports basic UART with DMA interface function, x4 to x32 oversampling of baud-rate.
This module supports LIN slave operation. The module can remain functional in VLPS mode provided the clock it is using remains
enabled. ISO7816 protocol is intended to be handled in software for this product. To support smart
card reading, TxD pin can be configured as pseudo open drain for 1-wire half-duplex like ISO7816 communication via the SIM_SOPT5[UART0ODE] bit.
3.9.3.2 UART1 and UART2 Overview
This device contains two basic universal asynchronous receiver/transmitter (UART) modules with DMA function support. Generally, these modules are used in RS-232, RS-485, and other communications. This module supports LIN Slave operation.
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Register access
Peripheral
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Module signals
GPIO controller
ARM Cortex -M0+
Core
Register access
Chapter 3 Chip Configuration
3.10

Human-machine interfaces (HMI)

3.10.1 GPIO Configuration

Figure 3-30. GPIO configuration
Table 3-45. Reference links to related information
Topic Related module Reference
Full description GPIO GPIO
System memory map System memory map
Clocking Clock Distribution
Power management Power management
Crossbar switch Crossbar switch Crossbar switch
Signal Multiplexing Port control Signal Multiplexing
3.10.1.1 GPIO Instantiation Information
The device includes four pins, PTB0, PTB1, PTA12, and PTA13, with high current drive capability. These pins can be used to drive LED or power MOSFET directly. The high drive capability applies to all functions which are multiplexed on these pins (UART, TPM, SPI...etc)
3.10.1.1.1 Pull Devices and Directions
The pull devices are enabled out of POR only on RESET_B, NMI_b and respective SWD signals. Other pins can be enabled by writing to PORTx_PCRn[PE] field.
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Human-machine interfaces (HMI)
All the pins are hard wired to be pullup except for SWD_CLK. The state will be reflected in the PORTx_PCRn[PS] field.
3.10.1.2 Port Control and Interrupt Summary
The following table provides more information regarding the Port Control and Interrupt configurations .
Table 3-46. Ports Summary
Feature Port A Port B
Pull Select control No No Pull Select at reset PTA0=Pull down, Others=Pull up Pull up Pull Enable control Yes Yes
Pull Enable at reset PTA0/PTA2/RESET_b=Enabled;
Others=Disabled
Slew Rate Enable control No No
Slew Rate Enable at reset PTA2/PTA6/PTA7/PTA15=Disabled;
Others=Enabled
Passive Filter Enable control RESET_b only PTB5 only
Passive Filter Enable at reset RESET_b=Enabled; Others=Disabled Disabled
Open Drain Enable control Open Drain Enable at reset Disabled Disabled
Drive Strength Enable control PTA12/PTA13 only PTB0/PTB1 only
Drive Strength Enable at reset Disabled Disabled
Pin Mux control Yes Yes
Pin Mux at reset PTA0/PTA2=ALT3; Others=ALT0 PTB5=ALT3; Others=ALT0
Lock Bit No No
Interrupt and DMA Request PTA0/PTA1/PTA7/PTA10/PTA11/
Digital Glitch Filter No No
1
No No
PTA12/PTA16/PTA17/PTA18 only
PTB5=Enabled; Others=Disabled
PTB0/PTB15/PTB16/PTB17= Disabled; Others=Enabled
PTB0/PTB1/PTB2/PTB3/PTB4/PTB5/ PTB6/PTB7/PTB14 only
1. UART signals can be configured for open-drain using SIM_SOPT5 register. IIC signals are automatically enabled for open drain when selected.
3.10.1.3 GPIO accessibility in the memory map
The GPIO is multi-ported and can be accessed directly by the core with zero wait states at base address 0xF800_0000. It can also be accessed by the core and DMA masters through the cross bar/AIPS interface at 0x400F_F000 and at an aliased slot (15) at
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Chapter 3 Chip Configuration
address 0x4000_F000. All BME operations to the GPIO space can be accomplished referencing the aliased slot (15) at address 0x4000_F000. Only some of the BME operations can be accomplished referencing GPIO at address 0x400F_F000.
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Chapter 4 Memory Map

4.1 Introduction

This device contains various memories and memory-mapped peripherals which are located in a 4 GB memory space. This chapter describes the memory and peripheral locations within that memory space.

4.2 System memory map

The following table shows the high-level device memory map.
Table 4-1. System memory map
System 32-bit Address Range Destination Slave Access
0x0000_0000–0x07FF_FFFF
0x0800_0000–0x1FFF_FBFF Reserved — 0x1FFF_FC00-0x1FFF_FFFF 0x2000_0000-0x2000_0BFF 0x2000_0C00–0x3FFF_FFFF Reserved – 0x4000_0000–0x4007_FFFF AIPS Peripherals Cortex-M0+ core &
0x4008_0000–0x400F_EFFF Reserved – 0x400F_F000–0x400F_FFFF General purpose input/output (GPIO) Cortex-M0+ core &
0x4010_0000–0x43FF_FFFF Reserved – 0x4400_0000–0x5FFF_FFFF Bit Manipulation Engine (BME) access to AIPS Peripherals for
0x6000_0000–0xDFFF_FFFF Reserved – 0xE000_0000–0xE00F_FFFF Private Peripherals Cortex-M0+ core 0xE010_0000–0xEFFF_FFFF Reserved – 0xF000_0000–0xF000_0FFF Micro Trace Buffer (MTB) registers Cortex-M0+ core
1
2
2
Program flash and read-only data (Includes exception vectors in first 196 bytes)
SRAM_L: Lower SRAM All masters SRAM_U: Upper SRAM All masters
slots 0-127
3
All masters
DMA
DMA
Cortex-M0+ core
Table continues on the next page...
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Program flash
Flash configuration field
Program flash base address
Flash memory base address
Registers

Flash Memory Map

Table 4-1. System memory map (continued)
System 32-bit Address Range Destination Slave Access
0xF000_1000–0xF000_1FFF MTB Data Watchpoint and Trace (MTBDWT) registers Cortex-M0+ core 0xF000_2000–0xF000_2FFF ROM table Cortex-M0+ core 0xF000_3000–0xF000_3FFF Miscellaneous Control Module (MCM) Cortex-M0+ core 0xF000_4000–0xF7FF_FFFF Reserved – 0xF800_0000–0xFFFF_FFFF IOPORT: GPIO (single cycle) Cortex-M0+ core
1. The program flash always begins at 0x0000_0000 but the end of implemented flash varies depending on the amount of flash implemented for a particular device. See Flash Memory Sizes for details.
2. This range varies depending on SRAM sizes. See SRAM Ranges for details.
3. Includes BME operations to GPIO at slot 15 (based at 0x4000_F000).
4.3 Flash Memory Map
The flash memory and the flash registers are located at different base addresses as shown in the following figure. The base address for each is specified in System memory map.
The on-chip Flash is implemented in a portion of the allocated Flash range to form a contiguous block in the memory map beginning at address 0x0000_0000. See Flash
Memory Sizes for details of supported ranges.
Accesses to the flash memory ranges outside the amount of Flash on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master. Read collision events in which flash memory is accessed while a flash memory resource is being manipulated by a flash command also generates a bus error response.
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Figure 4-1. Flash memory map
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4.3.1 Alternate Non-Volatile IRC User Trim Description
The following non-volatile locations (4 bytes) are reserved for custom IRC user trim supported by some development tools. An alternate IRC trim to the factory loaded trim can be stored at this location. To override the factory trim, user software must load new values into the MCG trim registers.
Non-Volatile Byte Address Alternate IRC Trim Value
0x0000_03FC Reserved 0x0000_03FD Reserved 0x0000_03FE (bit 0) SCFTRIM 0x0000_03FE (bit 4:1) FCTRIM 0x0000_03FF SCTRIM

4.4 SRAM memory map

The on-chip RAM is split between SRAM_L and SRAM_U. The RAM is also implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in the memory map. See SRAM Ranges for details.
Accesses to the SRAM_L and SRAM_U memory ranges outside the amount of RAM on the device causes the bus cycle to be terminated with an error followed by the appropriate response in the requesting bus master.

4.5 Bit Manipulation Engine

The Bit Manipulation Engine (BME) provides hardware support for atomic read-modify­write memory operations to the peripheral address space. By combining the basic load and store instruction support in the Cortex-M instruction set architecture with the concept of decorated storage provided by the BME, the resulting implementation provides a robust and efficient read-modify-write capability to this class of ultra low-end microcontrollers. See the Bit Manipulation Engine Block Guide (BME) for a detailed description of BME functionality.
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Peripheral bridge (AIPS-Lite) memory map

4.6 Peripheral bridge (AIPS-Lite) memory map
The peripheral memory map is accessible via one slave port on the crossbar in the 0x4000_0000–0x400F_FFFF region. The device implements one peripheral bridge that defines a 1024 KB address space.
The three regions associated with this space are:
• A 128 KB region, partitioned as 32 spaces, each 4 KB in size and reserved for on­platform peripheral devices. The AIPS controller generates unique module enables for all 32 spaces.
• A 384 KB region, partitioned as 96 spaces, each 4 KB in size and reserved for off­platform modules. The AIPS controller generates unique module enables for all 96 spaces.
• The last slot is a 4 KB region beginning at 0x400F_F000 for accessing the GPIO module. The GPIO slot (slot 128) is an alias of slot 15. This block is also directly interfaced to the core and provides direct access without incurring wait states associated with accesses via the AIPS controller.
Modules that are disabled via their clock gate control bits in the SIM registers disable the associated AIPS slots. Access to any address within an unimplemented or disabled peripheral bridge slot results in a transfer error termination.
For programming model accesses via the peripheral bridges, there is generally only a small range within the 4 KB slots that is implemented. Accessing an address that is not implemented in the peripheral results in a transfer error termination.

4.6.1 Read-after-write sequence and required serialization of memory operations

In some situations, a write to a peripheral must be completed fully before a subsequent action can occur. Examples of such situations include:
• Exiting an interrupt service routine (ISR)
• Changing a mode
• Configuring a function
In these situations, application software must perform a read-after-write sequence to guarantee the required serialization of the memory operations:
1. Write the peripheral register.
2. Read the written peripheral register to verify the write.
3. Continue with subsequent operations.
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4.6.2 Peripheral Bridge (AIPS-Lite) Memory Map

Table 4-2. Peripheral bridge 0 slot assignments
Chapter 4 Memory Map
System 32-bit base address Slot
number
0x4000_0000 0 — 0x4000_1000 1 — 0x4000_2000 2 — 0x4000_3000 3 — 0x4000_4000 4 — 0x4000_5000 5 — 0x4000_6000 6 — 0x4000_7000 7 — 0x4000_8000 8 DMA controller 0x4000_9000 9 — 0x4000_A000 10 — 0x4000_B000 11 — 0x4000_C000 12 — 0x4000_D000 13 — 0x4000_E000 14 — 0x4000_F000 15 GPIO controller (aliased to 0x400F_F000) 0x4001_0000 16 — 0x4001_1000 17 — 0x4001_2000 18 — 0x4001_3000 19 — 0x4001_4000 20 — 0x4001_5000 21 — 0x4001_6000 22 — 0x4001_7000 23 — 0x4001_8000 24 — 0x4001_9000 25 — 0x4001_A000 26 — 0x4001_B000 27 — 0x4001_C000 28 — 0x4001_D000 29 — 0x4001_E000 30 — 0x4001_F000 31 — 0x4002_0000 32 Flash memory 0x4002_1000 33 DMA channel mutiplexer 0 0x4002_2000 34 —
Module
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Peripheral bridge (AIPS-Lite) memory map
Table 4-2. Peripheral bridge 0 slot assignments (continued)
System 32-bit base address Slot
number
0x4002_3000 35 — 0x4002_4000 36 — 0x4002_5000 37 — 0x4002_6000 38 — 0x4002_7000 39 — 0x4002_8000 40 — 0x4002_9000 41 — 0x4002_A000 42 — 0x4002_B000 43 — 0x4002_C000 44 — 0x4002_D000 45 — 0x4002_E000 46 — 0x4002_F000 47 — 0x4003_0000 48 — 0x4003_1000 49 — 0x4003_2000 50 — 0x4003_3000 51 — 0x4003_4000 52 — 0x4003_5000 53 — 0x4003_6000 54 — 0x4003_7000 55 Periodic interrupt timers (PIT) 0x4003_8000 56 Timer'/PWM (TPM) 0 0x4003_9000 57 Timer'/PWM (TPM) 1 0x4003_A000 58 — 0x4003_B000 59 Analog-to-digital converter (ADC) 0 0x4003_C000 60 — 0x4003_D000 61 Real-time clock (RTC) 0x4003_E000 62 — 0x4003_F000 63 — 0x4004_0000 64 Low-power timer (LPTMR) 0x4004_1000 65 — 0x4004_2000 66 — 0x4004_3000 67 — 0x4004_4000 68 — 0x4004_5000 69 — 0x4004_6000 70 — 0x4004_7000 71 SIM low-power logic 0x4004_8000 72 System integration module (SIM) 0x4004_9000 73 Port A multiplexing control
Module
Table continues on the next page...
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Table 4-2. Peripheral bridge 0 slot assignments (continued)
System 32-bit base address Slot
number
0x4004_A000 74 Port B multiplexing control 0x4004_B000 75 — 0x4004_C000 76 — 0x4004_D000 77 — 0x4004_E000 78 — 0x4004_F000 79 — 0x4005_0000 80 — 0x4005_1000 81 — 0x4005_2000 82 — 0x4005_3000 83 — 0x4005_4000 84 — 0x4005_5000 85 — 0x4005_6000 86 — 0x4005_7000 87 — 0x4005_8000 88 — 0x4005_9000 89 — 0x4005_A000 90 — 0x4005_B000 91 — 0x4005_C000 92 — 0x4005_D000 93 — 0x4005_E000 94 — 0x4005_F000 95 — 0x4006_0000 96 — 0x4006_1000 97 — 0x4006_2000 98 — 0x4006_3000 99 — 0x4006_4000 100 Multi-purpose Clock Generator (MCG) 0x4006_5000 101 System oscillator (OSC) 0x4006_6000 102 I2C 0 0x4006_7000 103 — 0x4006_8000 104 — 0x4006_9000 105 — 0x4006_A000 106 UART 0 0x4006_B000 107 — 0x4006_C000 108 — 0x4006_D000 109 — 0x4006_E000 110 — 0x4006_F000 111 — 0x4007_0000 112 —
Module
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Private Peripheral Bus (PPB) memory map

Table 4-2. Peripheral bridge 0 slot assignments (continued)
System 32-bit base address Slot
number
0x4007_1000 113 — 0x4007_2000 114 — 0x4007_3000 115 Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) 0x4007_4000 116 — 0x4007_5000 117 — 0x4007_6000 118 SPI 0 0x4007_7000 119 — 0x4007_8000 120 — 0x4007_9000 121 — 0x4007_A000 122 — 0x4007_B000 123 — 0x4007_C000 124 Low-leakage wakeup unit (LLWU) 0x4007_D000 125 Power management controller (PMC) 0x4007_E000 126 System Mode controller (SMC) 0x4007_F000 127 Reset Control Module (RCM) 0x400F_F000 128 GPIO controller
Module

4.6.3 Modules Restricted Access in User Mode

In user mode, for MCG, RCM, SIM (slot 71 and 72), SMC, LLWU, and PMC, reads are allowed, but writes are blocked and generate bus error.
4.7 Private Peripheral Bus (PPB) memory map
The PPB is part of the defined ARM bus architecture and provides access to select processor-local modules. These resources are only accessible from the core; other system masters do not have access to them.
Table 4-3. PPB memory map
System 32-bit Address Range Resource Additional Range Detail Resource
0xE000_0000–0xE000_DFFF Reserved
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Chapter 4 Memory Map
Table 4-3. PPB memory map (continued)
System 32-bit Address Range Resource Additional Range Detail Resource
0xE000_E000–0xE000_EFFF System Control Space
(SCS)
0xE000_F000–0xE00F_EFFF Reserved 0xE00F_F000–0xE00F_FFFF Core ROM Space (CRS)
0xE000_E000–0xE000_E00F Reserved 0xE000_E010–0xE000_E0FF SysTick 0xE000_E100–0xE000_ECFF NVIC 0xE000_ED00–0xE000_ED8F System Control Block 0xE000_ED90–0xE000_EDEF Reserved 0xE000_EDF0–0xE000_EEFF Debug 0xE000_EF00–0xE000_EFFF Reserved
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Private Peripheral Bus (PPB) memory map
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