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NXP Semiconductors
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MKL04Z32VFK4
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NXP Semiconductors MKL04Z16VFM4, MKL04Z32VLC4, MKL04Z32VFM4, MKL04Z16VLF4, MKL04Z32VLF4 Reference Manual

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KL04 Sub-Family Reference Manual
Supports: MKL04Z8VFK4, MKL04Z16VFK4, MKL04Z32VFK4,
MKL04Z8VLC4, MKL04Z16VLC4, MKL04Z32VLC4, MKL04Z8VFM4,
MKL04Z16VFM4, MKL04Z32VFM4, MKL04Z16VLF4, and
MKL04Z32VLF4
Document Number: KL04P48M48SF1RM
Rev. 3.1, November 2012
KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012
Contents
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................29
1.1.1 Purpose.........................................................................................................................................................29
1.1.2 Audience......................................................................................................................................................29
1.2 Conventions..................................................................................................................................................................29
1.2.1 Numbering systems......................................................................................................................................29
1.2.2 Typographic notation...................................................................................................................................30
1.2.3 Special terms................................................................................................................................................30
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................31
2.2 Kinetis L Series.............................................................................................................................................................31
2.3 KL04 Sub-Family Introduction.....................................................................................................................................34
2.4 Module functional categories........................................................................................................................................35
2.4.1 ARM® Cortex™-M0+ Core Modules.........................................................................................................35
2.4.2 System Modules...........................................................................................................................................36
2.4.3 Memories and Memory Interfaces...............................................................................................................37
2.4.4 Clocks...........................................................................................................................................................37
2.4.5 Security and Integrity modules....................................................................................................................37
2.4.6 Analog modules...........................................................................................................................................38
2.4.7 Timer modules.............................................................................................................................................38
2.4.8 Communication interfaces...........................................................................................................................39
2.4.9 Human-machine interfaces..........................................................................................................................39
2.5 Orderable part numbers.................................................................................................................................................39
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................41
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3.2 Module to Module Interconnects..................................................................................................................................41
3.2.1 Module to Module Interconnects.................................................................................................................41
3.2.2 Analog reference options.............................................................................................................................43
3.3 Core Modules................................................................................................................................................................44
3.3.1 ARM Cortex-M0+ Core Configuration.......................................................................................................44
3.3.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................46
3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration............................................................50
3.4 System Modules............................................................................................................................................................51
3.4.1 SIM Configuration.......................................................................................................................................51
3.4.2 System Mode Controller (SMC) Configuration...........................................................................................52
3.4.3 PMC Configuration......................................................................................................................................52
3.4.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................53
3.4.5 MCM Configuration....................................................................................................................................55
3.4.6 Crossbar-Light Switch Configuration..........................................................................................................56
3.4.7 Peripheral Bridge Configuration..................................................................................................................57
3.4.8 DMA request multiplexer configuration......................................................................................................58
3.4.9 DMA Controller Configuration...................................................................................................................61
3.4.10 Computer Operating Properly (COP) Watchdog Configuration..................................................................61
3.5 Clock Modules..............................................................................................................................................................64
3.5.1 MCG Configuration.....................................................................................................................................64
3.5.2 OSC Configuration......................................................................................................................................65
3.6 Memories and Memory Interfaces................................................................................................................................66
3.6.1 Flash Memory Configuration.......................................................................................................................66
3.6.2 Flash Memory Controller Configuration.....................................................................................................68
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3.6.3 SRAM Configuration...................................................................................................................................69
3.7 Analog...........................................................................................................................................................................71
3.7.1 12-bit SAR ADC Configuration..................................................................................................................71
3.7.2 CMP Configuration......................................................................................................................................75
3.8 Timers...........................................................................................................................................................................77
3.8.1 Timer/PWM Module Configuration............................................................................................................77
3.8.2 PIT Configuration........................................................................................................................................79
3.8.3 Low-power timer configuration...................................................................................................................81
3.8.4 RTC configuration.......................................................................................................................................82
3.9 Communication interfaces............................................................................................................................................84
3.9.1 SPI configuration.........................................................................................................................................84
3.9.2 I2C Configuration........................................................................................................................................85
3.9.3 UART Configuration...................................................................................................................................85
3.10 Human-machine interfaces (HMI)................................................................................................................................87
3.10.1 GPIO Configuration.....................................................................................................................................87
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................91
4.2 System memory map.....................................................................................................................................................91
4.3 Flash Memory Map.......................................................................................................................................................92
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................92
4.4 SRAM memory map.....................................................................................................................................................93
4.5 Bit Manipulation Engine...............................................................................................................................................93
4.6 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................94
4.6.1 Read-after-write sequence and required serialization of memory operations..............................................94
4.6.2 Peripheral Bridge (AIPS-Lite) Memory Map..............................................................................................95
4.6.3 Modules Restricted Access in User Mode...................................................................................................98
4.7 Private Peripheral Bus (PPB) memory map..................................................................................................................98
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Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................101
5.2 Programming model......................................................................................................................................................101
5.3 High-Level device clocking diagram............................................................................................................................101
5.4 Clock definitions...........................................................................................................................................................102
5.4.1 Device clock summary.................................................................................................................................103
5.5 Internal clocking requirements.....................................................................................................................................105
5.5.1 Clock divider values after reset....................................................................................................................105
5.5.2 VLPR mode clocking...................................................................................................................................106
5.6 Clock Gating.................................................................................................................................................................106
5.7 Module clocks...............................................................................................................................................................106
5.7.1 PMC 1-kHz LPO clock................................................................................................................................107
5.7.2 COP clocking...............................................................................................................................................108
5.7.3 RTC clocking...............................................................................................................................................108
5.7.4 LPTMR clocking..........................................................................................................................................109
5.7.5 TPM clocking...............................................................................................................................................109
5.7.6 UART clocking............................................................................................................................................110
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................111
6.2 Reset..............................................................................................................................................................................111
6.2.1 Power-on reset (POR)..................................................................................................................................112
6.2.2 System reset sources....................................................................................................................................112
6.2.3 MCU Resets.................................................................................................................................................115
6.2.4 Reset Pin .....................................................................................................................................................116
6.2.5 Debug resets.................................................................................................................................................117
6.3 Boot...............................................................................................................................................................................118
6.3.1 Boot sources.................................................................................................................................................118
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6.3.2 FOPT boot options.......................................................................................................................................118
6.3.3 Boot sequence..............................................................................................................................................119
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................121
7.2 Clocking Modes............................................................................................................................................................121
7.2.1 Partial Stop...................................................................................................................................................121
7.2.2 DMA Wakeup..............................................................................................................................................122
7.2.3 Compute Operation......................................................................................................................................123
7.2.4 Peripheral Doze............................................................................................................................................124
7.2.5 Clock Gating................................................................................................................................................125
7.3 Power modes.................................................................................................................................................................125
7.4 Entering and exiting power modes...............................................................................................................................127
7.5 Module Operation in Low Power Modes......................................................................................................................127
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................131
8.2 Flash Security...............................................................................................................................................................131
8.3 Security Interactions with other Modules.....................................................................................................................131
8.3.1 Security Interactions with Debug.................................................................................................................132
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................133
9.2 Debug Port Pin Descriptions.........................................................................................................................................133
9.3 SWD status and control registers..................................................................................................................................134
9.3.1 MDM-AP Control Register..........................................................................................................................135
9.3.2 MDM-AP Status Register............................................................................................................................136
9.4 Debug Resets................................................................................................................................................................138
9.5 Micro Trace Buffer (MTB)...........................................................................................................................................139
9.6 Debug in Low Power Modes........................................................................................................................................139
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9.7 Debug & Security.........................................................................................................................................................139
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................141
10.2 Signal Multiplexing Integration....................................................................................................................................141
10.2.1 Port control and interrupt module features..................................................................................................142
10.2.2 Clock gating.................................................................................................................................................143
10.2.3 Signal multiplexing constraints....................................................................................................................143
10.3 Pinout............................................................................................................................................................................143
10.3.1 KL04 signal multiplexing and pin assignments...........................................................................................143
10.3.2 KL04 Pinouts...............................................................................................................................................145
10.4 Module Signal Description Tables................................................................................................................................149
10.4.1 Core Modules...............................................................................................................................................149
10.4.2 System Modules...........................................................................................................................................150
10.4.3 Clock Modules.............................................................................................................................................150
10.4.4 Memories and Memory Interfaces...............................................................................................................150
10.4.5 Analog..........................................................................................................................................................150
10.4.6 Timer Modules.............................................................................................................................................151
10.4.7 Communication Interfaces...........................................................................................................................152
10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................152
Chapter 11
Port control and interrupts (PORT)
11.1 Introduction...................................................................................................................................................................153
11.2 Overview.......................................................................................................................................................................153
11.2.1 Features........................................................................................................................................................153
11.2.2 Modes of operation......................................................................................................................................154
11.3 External signal description............................................................................................................................................154
11.4 Detailed signal description............................................................................................................................................155
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11.5 Memory map and register definition.............................................................................................................................155
11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................158
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................160
11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................161
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................161
11.6 Functional description...................................................................................................................................................162
11.6.1 Pin control....................................................................................................................................................162
11.6.2 Global pin control........................................................................................................................................163
11.6.3 External interrupts........................................................................................................................................163
Chapter 12
System integration module (SIM)
12.1 Introduction...................................................................................................................................................................165
12.1.1 Features........................................................................................................................................................165
12.2 Memory map and register definition.............................................................................................................................165
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................167
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................167
12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................168
12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................170
12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................171
12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................172
12.2.7 System Device Identification Register (SIM_SDID)...................................................................................174
12.2.8 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................176
12.2.9 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................177
12.2.10 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................179
12.2.11 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................180
12.2.12 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................181
12.2.13 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................183
12.2.14 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................184
12.2.15 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................185
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12.2.16 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................185
12.2.17 Unique Identification Register Low (SIM_UIDL)......................................................................................186
12.2.18 COP Control Register (SIM_COPC)...........................................................................................................186
12.2.19 Service COP Register (SIM_SRVCOP)......................................................................................................187
12.3 Functional description...................................................................................................................................................188
Chapter 13
System Mode Controller (SMC)
13.1 Introduction...................................................................................................................................................................189
13.2 Modes of operation.......................................................................................................................................................189
13.3 Memory map and register descriptions.........................................................................................................................191
13.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................191
13.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................193
13.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................194
13.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................195
13.4 Functional description...................................................................................................................................................196
13.4.1 Power mode transitions................................................................................................................................196
13.4.2 Power mode entry/exit sequencing..............................................................................................................199
13.4.3 Run modes....................................................................................................................................................201
13.4.4 Wait modes..................................................................................................................................................203
13.4.5 Stop modes...................................................................................................................................................204
13.4.6 Debug in low power modes.........................................................................................................................207
Chapter 14
Power Management Controller (PMC)
14.1 Introduction...................................................................................................................................................................209
14.2 Features.........................................................................................................................................................................209
14.3 Low-voltage detect (LVD) system................................................................................................................................209
14.3.1 LVD reset operation.....................................................................................................................................210
14.3.2 LVD interrupt operation...............................................................................................................................210
14.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................210
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14.4 I/O retention..................................................................................................................................................................211
14.5 Memory map and register descriptions.........................................................................................................................211
14.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................212
14.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................213
14.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................214
Chapter 15
Low-Leakage Wakeup Unit (LLWU)
15.1 Introduction...................................................................................................................................................................217
15.1.1 Features........................................................................................................................................................217
15.1.2 Modes of operation......................................................................................................................................218
15.1.3 Block diagram..............................................................................................................................................219
15.2 LLWU signal descriptions............................................................................................................................................220
15.3 Memory map/register definition...................................................................................................................................220
15.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................221
15.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................222
15.3.3 LLWU Module Enable register (LLWU_ME)............................................................................................223
15.3.4 LLWU Flag 1 register (LLWU_F1).............................................................................................................225
15.3.5 LLWU Flag 3 register (LLWU_F3).............................................................................................................226
15.3.6 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................228
15.3.7 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................229
15.4 Functional description...................................................................................................................................................230
15.4.1 LLS mode.....................................................................................................................................................231
15.4.2 VLLS modes................................................................................................................................................231
15.4.3 Initialization.................................................................................................................................................231
Chapter 16
Reset Control Module (RCM)
16.1 Introduction...................................................................................................................................................................233
16.2 Reset memory map and register descriptions...............................................................................................................233
16.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................233
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16.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................235
16.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................236
16.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................237
Chapter 17
Bit Manipulation Engine (BME)
17.1 Introduction...................................................................................................................................................................239
17.1.1 Overview......................................................................................................................................................240
17.1.2 Features........................................................................................................................................................240
17.1.3 Modes of Operation.....................................................................................................................................241
17.2 External Signal Description..........................................................................................................................................241
17.3 Memory Map and Register Definition..........................................................................................................................242
17.4 Functional Description..................................................................................................................................................242
17.4.1 BME Decorated Stores.................................................................................................................................242
17.4.2 BME Decorated Loads.................................................................................................................................248
17.4.3 Additional Details on Decorated Addresses and GPIO Accesses................................................................255
17.5 Application Information................................................................................................................................................256
Chapter 18
Miscellaneous Control Module (MCM)
18.1 Introduction...................................................................................................................................................................259
18.1.1 Features........................................................................................................................................................259
18.2 Memory map/register descriptions...............................................................................................................................259
18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................260
18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................261
18.2.3 Platform Control Register (MCM_PLACR)................................................................................................261
18.2.4 Compute Operation Control Register (MCM_CPO)...................................................................................264
Chapter 19
Micro Trace Buffer (MTB)
19.1 Introduction...................................................................................................................................................................267
19.1.1 Overview......................................................................................................................................................267
19.1.2 Features........................................................................................................................................................270
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19.1.3 Modes of Operation.....................................................................................................................................271
19.2 External Signal Description..........................................................................................................................................271
19.3 Memory Map and Register Definition..........................................................................................................................272
19.3.1 MTB_RAM Memory Map...........................................................................................................................272
19.3.2 MTB_DWT Memory Map...........................................................................................................................285
19.3.3 System ROM Memory Map.........................................................................................................................295
Chapter 20
Crossbar Switch Lite (AXBS-Lite)
20.1 Introduction...................................................................................................................................................................301
20.1.1 Features........................................................................................................................................................301
20.2 Memory Map / Register Definition...............................................................................................................................301
20.3 Functional Description..................................................................................................................................................302
20.3.1 General operation.........................................................................................................................................302
20.3.2 Arbitration....................................................................................................................................................303
20.4 Initialization/application information...........................................................................................................................304
Chapter 21
Peripheral Bridge (AIPS-Lite)
21.1 Introduction...................................................................................................................................................................305
21.1.1 Features........................................................................................................................................................305
21.1.2 General operation.........................................................................................................................................305
21.2 Functional description...................................................................................................................................................306
21.2.1 Access support.............................................................................................................................................306
Chapter 22
Direct Memory Access Multiplexer (DMAMUX)
22.1 Introduction...................................................................................................................................................................307
22.1.1 Overview......................................................................................................................................................307
22.1.2 Features........................................................................................................................................................308
22.1.3 Modes of operation......................................................................................................................................308
22.2 External signal description............................................................................................................................................309
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22.3 Memory map/register definition...................................................................................................................................309
22.3.1 Channel Configuration register (DMAMUXx_CHCFGn)..........................................................................309
22.4 Functional description...................................................................................................................................................310
22.4.1 DMA channels with periodic triggering capability......................................................................................311
22.4.2 DMA channels with no triggering capability...............................................................................................313
22.4.3 Always-enabled DMA sources....................................................................................................................313
22.5 Initialization/application information...........................................................................................................................314
22.5.1 Reset.............................................................................................................................................................314
22.5.2 Enabling and configuring sources................................................................................................................314
Chapter 23
DMA Controller Module
23.1 Introduction...................................................................................................................................................................319
23.1.1 Overview......................................................................................................................................................319
23.1.2 Features........................................................................................................................................................320
23.2 DMA Transfer Overview..............................................................................................................................................321
23.3 Memory Map and Registers..........................................................................................................................................322
23.3.1 Source Address Register (DMA_SARn).....................................................................................................323
23.3.2 Destination Address Register (DMA_DARn).............................................................................................324
23.3.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn).............................................................325
23.3.4 DMA Control Register (DMA_DCRn)........................................................................................................327
23.4 Functional Description..................................................................................................................................................331
23.4.1 Transfer Requests (Cycle-Steal and Continuous Modes)............................................................................331
23.4.2 Channel Initialization and Startup................................................................................................................331
23.4.3 Dual-Address Data Transfer Mode..............................................................................................................333
23.4.4 Advanced Data Transfer Controls: Auto-Alignment...................................................................................334
23.4.5 Termination..................................................................................................................................................335
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Chapter 24
Multipurpose Clock Generator (MCG)
24.1 Introduction...................................................................................................................................................................337
24.1.1 Features........................................................................................................................................................337
24.1.2 Modes of Operation.....................................................................................................................................339
24.2 External Signal Description..........................................................................................................................................340
24.3 Memory Map/Register Definition.................................................................................................................................340
24.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................340
24.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................342
24.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................343
24.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................343
24.3.5 MCG Control 6 Register (MCG_C6)...........................................................................................................345
24.3.6 MCG Status Register (MCG_S)..................................................................................................................345
24.3.7 MCG Status and Control Register (MCG_SC)............................................................................................346
24.3.8 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................348
24.3.9 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................348
24.4 Functional Description..................................................................................................................................................348
24.4.1 MCG mode state diagram............................................................................................................................348
24.4.2 Low Power Bit Usage..................................................................................................................................352
24.4.3 MCG Internal Reference Clocks..................................................................................................................352
24.4.4 External Reference Clock............................................................................................................................353
24.4.5 MCG Fixed frequency clock .......................................................................................................................353
24.4.6 MCG Auto TRIM (ATM)............................................................................................................................353
24.5 Initialization / Application information........................................................................................................................355
24.5.1 MCG module initialization sequence...........................................................................................................355
24.5.2 Using a 32.768 kHz reference......................................................................................................................357
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24.5.3 MCG mode switching..................................................................................................................................358
Chapter 25
Oscillator (OSC)
25.1 Introduction...................................................................................................................................................................365
25.2 Features and Modes......................................................................................................................................................365
25.3 Block Diagram..............................................................................................................................................................366
25.4 OSC Signal Descriptions..............................................................................................................................................366
25.5 External Crystal / Resonator Connections....................................................................................................................367
25.6 External Clock Connections.........................................................................................................................................368
25.7 Memory Map/Register Definitions...............................................................................................................................369
25.7.1 OSC Memory Map/Register Definition.......................................................................................................369
25.8 Functional Description..................................................................................................................................................370
25.8.1 OSC Module States......................................................................................................................................370
25.8.2 OSC Module Modes.....................................................................................................................................372
25.8.3 Counter.........................................................................................................................................................373
25.8.4 Reference Clock Pin Requirements.............................................................................................................373
25.9 Reset..............................................................................................................................................................................374
25.10 Low Power Modes Operation.......................................................................................................................................374
25.11 Interrupts.......................................................................................................................................................................374
Chapter 26
Flash Memory Controller (FMC)
26.1 Introduction...................................................................................................................................................................375
26.1.1 Overview......................................................................................................................................................375
26.1.2 Features........................................................................................................................................................375
26.2 Modes of operation.......................................................................................................................................................376
26.3 External signal description............................................................................................................................................376
26.4 Memory map and register descriptions.........................................................................................................................376
26.5 Functional description...................................................................................................................................................376
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Chapter 27
Flash Memory Module (FTFA)
27.1 Introduction...................................................................................................................................................................379
27.1.1 Features........................................................................................................................................................380
27.1.2 Block Diagram.............................................................................................................................................380
27.1.3 Glossary.......................................................................................................................................................381
27.2 External Signal Description..........................................................................................................................................382
27.3 Memory Map and Registers..........................................................................................................................................382
27.3.1 Flash Configuration Field Description.........................................................................................................382
27.3.2 Program Flash IFR Map...............................................................................................................................383
27.3.3 Register Descriptions...................................................................................................................................384
27.4 Functional Description..................................................................................................................................................392
27.4.1 Flash Protection............................................................................................................................................393
27.4.2 Interrupts......................................................................................................................................................393
27.4.3 Flash Operation in Low-Power Modes........................................................................................................394
27.4.4 Functional Modes of Operation...................................................................................................................394
27.4.5 Flash Reads and Ignored Writes..................................................................................................................394
27.4.6 Read While Write (RWW)...........................................................................................................................395
27.4.7 Flash Program and Erase..............................................................................................................................395
27.4.8 Flash Command Operations.........................................................................................................................395
27.4.9 Margin Read Commands.............................................................................................................................400
27.4.10 Flash Command Description........................................................................................................................401
27.4.11 Security........................................................................................................................................................414
27.4.12 Reset Sequence............................................................................................................................................416
Chapter 28
Analog-to-Digital Converter (ADC)
28.1 Introduction...................................................................................................................................................................417
28.1.1 Features........................................................................................................................................................417
28.1.2 Block diagram..............................................................................................................................................418
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28.2 ADC Signal Descriptions..............................................................................................................................................419
28.2.1 Analog Power (VDDA)...............................................................................................................................420
28.2.2 Analog Ground (VSSA)...............................................................................................................................420
28.2.3 Voltage Reference Select.............................................................................................................................420
28.2.4 Analog Channel Inputs (ADx).....................................................................................................................421
28.3 Register definition.........................................................................................................................................................421
28.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)...................................................................................422
28.3.2 ADC Configuration Register 1 (ADCx_CFG1)...........................................................................................425
28.3.3 ADC Configuration Register 2 (ADCx_CFG2)...........................................................................................427
28.3.4 ADC Data Result Register (ADCx_Rn).......................................................................................................428
28.3.5 Compare Value Registers (ADCx_CVn).....................................................................................................429
28.3.6 Status and Control Register 2 (ADCx_SC2)................................................................................................430
28.3.7 Status and Control Register 3 (ADCx_SC3)................................................................................................432
28.3.8 ADC Offset Correction Register (ADCx_OFS)...........................................................................................433
28.3.9 ADC Plus-Side Gain Register (ADCx_PG).................................................................................................434
28.3.10 ADC Plus-Side General Calibration Value Register (ADCx_CLPD).........................................................434
28.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)..........................................................435
28.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)..........................................................435
28.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)..........................................................436
28.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP2)..........................................................436
28.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP1)..........................................................437
28.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP0)..........................................................437
28.4 Functional description...................................................................................................................................................438
28.4.1 Clock select and divide control....................................................................................................................438
28.4.2 Voltage reference selection..........................................................................................................................439
28.4.3 Hardware trigger and channel selects..........................................................................................................439
28.4.4 Conversion control.......................................................................................................................................440
28.4.5 Automatic compare function........................................................................................................................447
28.4.6 Calibration function.....................................................................................................................................449
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28.4.7 User-defined offset function........................................................................................................................450
28.4.8 Temperature sensor......................................................................................................................................451
28.4.9 MCU wait mode operation...........................................................................................................................452
28.4.10 MCU Normal Stop mode operation.............................................................................................................452
28.4.11 MCU Low-Power Stop mode operation......................................................................................................453
28.5 Initialization information..............................................................................................................................................454
28.5.1 ADC module initialization example............................................................................................................454
28.6 Application information................................................................................................................................................456
28.6.1 External pins and routing.............................................................................................................................456
28.6.2 Sources of error............................................................................................................................................458
Chapter 29
Comparator (CMP)
29.1 Introduction...................................................................................................................................................................463
29.2 CMP features................................................................................................................................................................463
29.3 6-bit DAC key features.................................................................................................................................................464
29.4 ANMUX key features...................................................................................................................................................465
29.5 CMP, DAC and ANMUX diagram...............................................................................................................................465
29.6 CMP block diagram......................................................................................................................................................466
29.7 Memory map/register definitions..................................................................................................................................468
29.7.1 CMP Control Register 0 (CMPx_CR0).......................................................................................................468
29.7.2 CMP Control Register 1 (CMPx_CR1).......................................................................................................469
29.7.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................471
29.7.4 CMP Status and Control Register (CMPx_SCR).........................................................................................471
29.7.5 DAC Control Register (CMPx_DACCR)....................................................................................................472
29.7.6 MUX Control Register (CMPx_MUXCR)..................................................................................................473
29.8 Functional description...................................................................................................................................................474
29.8.1 CMP functional modes.................................................................................................................................474
29.8.2 Power modes................................................................................................................................................483
29.8.3 Startup and operation...................................................................................................................................484
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29.8.4 Low-pass filter.............................................................................................................................................484
29.9 CMP interrupts..............................................................................................................................................................487
29.10 DMA support................................................................................................................................................................487
29.11 CMP Asyncrhonous DMA support...............................................................................................................................487
29.12 Digital-to-analog converter...........................................................................................................................................488
29.13 DAC functional description..........................................................................................................................................488
29.13.1 Voltage reference source select....................................................................................................................488
29.14 DAC resets....................................................................................................................................................................489
29.15 DAC clocks...................................................................................................................................................................489
29.16 DAC interrupts..............................................................................................................................................................489
29.17 CMP Trigger Mode.......................................................................................................................................................489
Chapter 30
Timer/PWM Module (TPM)
30.1 Introduction...................................................................................................................................................................491
30.1.1 TPM Philosophy..........................................................................................................................................491
30.1.2 Features........................................................................................................................................................491
30.1.3 Modes of Operation.....................................................................................................................................492
30.1.4 Block Diagram.............................................................................................................................................492
30.2 TPM Signal Descriptions..............................................................................................................................................493
30.2.1 TPM_EXTCLK — TPM External Clock....................................................................................................493
30.2.2 TPM_CHn — TPM Channel (n) I/O Pin.....................................................................................................494
30.3 Memory Map and Register Definition..........................................................................................................................494
30.3.1 Status and Control (TPMx_SC)...................................................................................................................496
30.3.2 Counter (TPMx_CNT).................................................................................................................................497
30.3.3 Modulo (TPMx_MOD)................................................................................................................................498
30.3.4 Channel (n) Status and Control (TPMx_CnSC)...........................................................................................499
30.3.5 Channel (n) Value (TPMx_CnV).................................................................................................................501
30.3.6 Capture and Compare Status (TPMx_STATUS).........................................................................................501
30.3.7 Configuration (TPMx_CONF).....................................................................................................................503
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30.4 Functional Description..................................................................................................................................................505
30.4.1 Clock Domains.............................................................................................................................................505
30.4.2 Prescaler.......................................................................................................................................................506
30.4.3 Counter.........................................................................................................................................................506
30.4.4 Input Capture Mode.....................................................................................................................................508
30.4.5 Output Compare Mode.................................................................................................................................509
30.4.6 Edge-Aligned PWM (EPWM) Mode...........................................................................................................510
30.4.7 Center-Aligned PWM (CPWM) Mode........................................................................................................512
30.4.8 Registers Updated from Write Buffers........................................................................................................514
30.4.9 DMA............................................................................................................................................................514
30.4.10 Reset Overview............................................................................................................................................515
30.4.11 TPM Interrupts.............................................................................................................................................515
Chapter 31
Periodic Interrupt Timer (PIT-RTI)
31.1 Introduction...................................................................................................................................................................517
31.1.1 Block diagram..............................................................................................................................................517
31.1.2 Features........................................................................................................................................................518
31.2 Signal description..........................................................................................................................................................518
31.3 Memory map/register description.................................................................................................................................519
31.3.1 PIT Module Control Register (PIT_MCR)..................................................................................................519
31.3.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H)...............................................................................521
31.3.3 PIT Lower Lifetime Timer Register (PIT_LTMR64L)...............................................................................521
31.3.4 Timer Load Value Register (PIT_LDVALn)...............................................................................................522
31.3.5 Current Timer Value Register (PIT_CVALn).............................................................................................522
31.3.6 Timer Control Register (PIT_TCTRLn)......................................................................................................523
31.3.7 Timer Flag Register (PIT_TFLGn)..............................................................................................................524
31.4 Functional description...................................................................................................................................................524
31.4.1 General operation.........................................................................................................................................524
31.4.2 Interrupts......................................................................................................................................................526
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31.4.3 Chained timers.............................................................................................................................................526
31.5 Initialization and application information.....................................................................................................................526
31.6 Example configuration for chained timers....................................................................................................................527
31.7 Example configuration for the lifetime timer...............................................................................................................528
Chapter 32
Low-Power Timer (LPTMR)
32.1 Introduction...................................................................................................................................................................531
32.1.1 Features........................................................................................................................................................531
32.1.2 Modes of operation......................................................................................................................................531
32.2 LPTMR signal descriptions..........................................................................................................................................532
32.2.1 Detailed signal descriptions.........................................................................................................................532
32.3 Memory map and register definition.............................................................................................................................532
32.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)......................................................................533
32.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)................................................................................534
32.3.3 Low Power Timer Compare Register (LPTMRx_CMR).............................................................................536
32.3.4 Low Power Timer Counter Register (LPTMRx_CNR)...............................................................................536
32.4 Functional description...................................................................................................................................................537
32.4.1 LPTMR power and reset..............................................................................................................................537
32.4.2 LPTMR clocking..........................................................................................................................................537
32.4.3 LPTMR prescaler/glitch filter......................................................................................................................537
32.4.4 LPTMR compare..........................................................................................................................................539
32.4.5 LPTMR counter...........................................................................................................................................539
32.4.6 LPTMR hardware trigger.............................................................................................................................540
32.4.7 LPTMR interrupt..........................................................................................................................................540
Chapter 33
Real Time Clock (RTC)
33.1 Introduction...................................................................................................................................................................541
33.1.1 Features........................................................................................................................................................541
33.1.2 Modes of operation......................................................................................................................................541
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33.1.3 RTC Signal Descriptions.............................................................................................................................541
33.2 Register definition.........................................................................................................................................................542
33.2.1 RTC Time Seconds Register (RTC_TSR)...................................................................................................543
33.2.2 RTC Time Prescaler Register (RTC_TPR)..................................................................................................543
33.2.3 RTC Time Alarm Register (RTC_TAR).....................................................................................................544
33.2.4 RTC Time Compensation Register (RTC_TCR).........................................................................................544
33.2.5 RTC Control Register (RTC_CR)................................................................................................................545
33.2.6 RTC Status Register (RTC_SR)..................................................................................................................547
33.2.7 RTC Lock Register (RTC_LR)....................................................................................................................548
33.2.8 RTC Interrupt Enable Register (RTC_IER).................................................................................................549
33.3 Functional description...................................................................................................................................................550
33.3.1 Power, clocking, and reset...........................................................................................................................550
33.3.2 Time counter................................................................................................................................................551
33.3.3 Compensation...............................................................................................................................................551
33.3.4 Time alarm...................................................................................................................................................552
33.3.5 Update mode................................................................................................................................................552
33.3.6 Register lock................................................................................................................................................553
33.3.7 Interrupt........................................................................................................................................................553
Chapter 34
Serial Peripheral Interface (SPI)
34.1 Introduction...................................................................................................................................................................555
34.1.1 Features........................................................................................................................................................555
34.1.2 Modes of Operation.....................................................................................................................................556
34.1.3 Block Diagrams............................................................................................................................................557
34.2 External Signal Description..........................................................................................................................................559
34.2.1 SPSCK — SPI Serial Clock.........................................................................................................................559
34.2.2 MOSI — Master Data Out, Slave Data In...................................................................................................560
34.2.3 MISO — Master Data In, Slave Data Out...................................................................................................560
34.2.4 SS — Slave Select........................................................................................................................................560
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34.3 Memory Map and Register Descriptions......................................................................................................................561
34.3.1 SPI control register 1 (SPIx_C1)..................................................................................................................561
34.3.2 SPI control register 2 (SPIx_C2)..................................................................................................................563
34.3.3 SPI baud rate register (SPIx_BR).................................................................................................................564
34.3.4 SPI status register (SPIx_S).........................................................................................................................565
34.3.5 SPI data register (SPIx_D)...........................................................................................................................566
34.3.6 SPI match register (SPIx_M).......................................................................................................................567
34.4 Functional Description..................................................................................................................................................568
34.4.1 General.........................................................................................................................................................568
34.4.2 Master Mode................................................................................................................................................568
34.4.3 Slave Mode..................................................................................................................................................570
34.4.4 SPI Transmission by DMA..........................................................................................................................571
34.4.5 SPI Clock Formats.......................................................................................................................................573
34.4.6 SPI Baud Rate Generation...........................................................................................................................576
34.4.7 Special Features...........................................................................................................................................576
34.4.8 Error Conditions...........................................................................................................................................578
34.4.9 Low Power Mode Options...........................................................................................................................579
34.4.10 Reset.............................................................................................................................................................580
34.4.11 Interrupts......................................................................................................................................................581
34.5 Initialization/Application Information..........................................................................................................................582
34.5.1 Initialization Sequence.................................................................................................................................582
34.5.2 Pseudo-Code Example.................................................................................................................................583
Chapter 35
Inter-Integrated Circuit (I2C)
35.1 Introduction...................................................................................................................................................................587
35.1.1 Features........................................................................................................................................................587
35.1.2 Modes of operation......................................................................................................................................588
35.1.3 Block diagram..............................................................................................................................................588
35.2 I2C signal descriptions..................................................................................................................................................589
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35.3 Memory map and register descriptions.........................................................................................................................589
35.3.1 I2C Address Register 1 (I2Cx_A1)..............................................................................................................590
35.3.2 I2C Frequency Divider register (I2Cx_F)....................................................................................................591
35.3.3 I2C Control Register 1 (I2Cx_C1)...............................................................................................................592
35.3.4 I2C Status register (I2Cx_S)........................................................................................................................593
35.3.5 I2C Data I/O register (I2Cx_D)...................................................................................................................595
35.3.6 I2C Control Register 2 (I2Cx_C2)...............................................................................................................596
35.3.7 I2C Programmable Input Glitch Filter register (I2Cx_FLT).......................................................................597
35.3.8 I2C Range Address register (I2Cx_RA)......................................................................................................598
35.3.9 I2C SMBus Control and Status register (I2Cx_SMB).................................................................................599
35.3.10 I2C Address Register 2 (I2Cx_A2)..............................................................................................................600
35.3.11 I2C SCL Low Timeout Register High (I2Cx_SLTH)..................................................................................601
35.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL)...................................................................................601
35.4 Functional description...................................................................................................................................................601
35.4.1 I2C protocol.................................................................................................................................................601
35.4.2 10-bit address...............................................................................................................................................607
35.4.3 Address matching.........................................................................................................................................608
35.4.4 System management bus specification........................................................................................................609
35.4.5 Resets...........................................................................................................................................................612
35.4.6 Interrupts......................................................................................................................................................612
35.4.7 Programmable input glitch filter..................................................................................................................614
35.4.8 Address matching wakeup...........................................................................................................................615
35.4.9 DMA support...............................................................................................................................................615
35.5 Initialization/application information...........................................................................................................................616
Chapter 36
Universal Asynchronous Receiver/Transmitter (UART0)
36.1 Introduction...................................................................................................................................................................619
36.1.1 Features........................................................................................................................................................619
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36.1.2 Modes of operation......................................................................................................................................620
36.1.3 Block diagram..............................................................................................................................................620
36.2 Register definition.........................................................................................................................................................622
36.2.1 UART Baud Rate Register High (UARTx_BDH).......................................................................................623
36.2.2 UART Baud Rate Register Low (UARTx_BDL)........................................................................................624
36.2.3 UART Control Register 1 (UARTx_C1).....................................................................................................624
36.2.4 UART Control Register 2 (UARTx_C2).....................................................................................................626
36.2.5 UART Status Register 1 (UARTx_S1)........................................................................................................627
36.2.6 UART Status Register 2 (UARTx_S2)........................................................................................................629
36.2.7 UART Control Register 3 (UARTx_C3).....................................................................................................631
36.2.8 UART Data Register (UARTx_D)...............................................................................................................632
36.2.9 UART Match Address Registers 1 (UARTx_MA1)....................................................................................633
36.2.10 UART Match Address Registers 2 (UARTx_MA2)....................................................................................634
36.2.11 UART Control Register 4 (UARTx_C4).....................................................................................................634
36.2.12 UART Control Register 5 (UARTx_C5).....................................................................................................635
36.3 Functional description...................................................................................................................................................636
36.3.1 Baud rate generation....................................................................................................................................636
36.3.2 Transmitter functional description...............................................................................................................636
36.3.3 Receiver functional description...................................................................................................................638
36.3.4 Additional UART functions.........................................................................................................................641
36.3.5 Interrupts and status flags............................................................................................................................643
Chapter 37
General-Purpose Input/Output (GPIO)
37.1 Introduction...................................................................................................................................................................645
37.1.1 Features........................................................................................................................................................645
37.1.2 Modes of operation......................................................................................................................................645
37.1.3 GPIO signal descriptions.............................................................................................................................646
37.2 Memory map and register definition.............................................................................................................................647
37.2.1 Port Data Output Register (GPIOx_PDOR).................................................................................................648
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37.2.2 Port Set Output Register (GPIOx_PSOR)....................................................................................................649
37.2.3 Port Clear Output Register (GPIOx_PCOR)................................................................................................649
37.2.4 Port Toggle Output Register (GPIOx_PTOR).............................................................................................650
37.2.5 Port Data Input Register (GPIOx_PDIR).....................................................................................................650
37.2.6 Port Data Direction Register (GPIOx_PDDR).............................................................................................651
37.3 FGPIO memory map and register definition................................................................................................................651
37.3.1 Port Data Output Register (FGPIOx_PDOR)..............................................................................................652
37.3.2 Port Set Output Register (FGPIOx_PSOR).................................................................................................652
37.3.3 Port Clear Output Register (FGPIOx_PCOR).............................................................................................653
37.3.4 Port Toggle Output Register (FGPIOx_PTOR)...........................................................................................653
37.3.5 Port Data Input Register (FGPIOx_PDIR)...................................................................................................654
37.3.6 Port Data Direction Register (FGPIOx_PDDR)..........................................................................................654
37.4 Functional description...................................................................................................................................................655
37.4.1 General-purpose input..................................................................................................................................655
37.4.2 General-purpose output................................................................................................................................655
37.4.3 IOPORT.......................................................................................................................................................655
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Chapter 1 About This Document
1.1

Overview

1.1.1 Purpose

This document describes the features, architecture, and programming model of the Freescale KL04 microcontroller.

1.1.2 Audience

This document is primarily for system architects and software application developers who are using or considering using the KL04KL02 microcontroller in a system.
1.2

Conventions

1.2.1 Numbering systems

The following suffixes identify different numbering systems:
This suffix Identifies a
b Binary number. For example, the binary equivalent of the
number 5 is written 101b. In some cases, binary numbers are shown with the prefix 0b.
d Decimal number. Decimal numbers are followed by this suffix
only when the possibility of confusion exists. In general, decimal numbers are shown without a suffix.
h Hexadecimal number. For example, the hexadecimal
equivalent of the number 60 is written 3Ch. In some cases, hexadecimal numbers are shown with the prefix 0x.
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Conventions

1.2.2 Typographic notation

The following typographic notation is used throughout this document:
Example Description
placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for
the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers.
code
SR[SCM] A mnemonic in brackets represents a named field in a register. This example refers to the
REVNO[6:4], XAD[7:0] Numbers in brackets and separated by a colon represent either:
Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type is also used for example code. Instruction mnemonics and directives in text and tables are shown in all caps; for example, BSR.
Scaling Mode (SCM) field in the Status Register (SR).
• A subset of a register's named field For example, REVNO[6:4] refers to bits 6–4 that are part of the COREREV field that
occupies bits 6–0 of the REVNO register.
• A continuous range of individual signals of a bus For example, XAD[7:0] refers to signals 7–0 of the XAD bus.

1.2.3 Special terms

The following terms have special meanings:
Term Meaning
asserted Refers to the state of a signal as follows:
• An active-high signal is asserted when high (1).
• An active-low signal is asserted when low (0).
deasserted Refers to the state of a signal as follows:
• An active-high signal is deasserted when low (0).
• An active-low signal is deasserted when high (1).
In some cases, deasserted signals are described as negated.
reserved Refers to a memory space, register, or field that is either
reserved for future use or for which, when written to, the module or chip behavior is unpredictable.
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