NXP Semiconductors MCF5235 Reference Manual

Freescale Semiconductor

Reference Manual Addendum

MCF5235RMAD

Rev. 2.2, 05/2007

MCF5235 Ref erence Man ual Err ata

by: Microcontroller Division

This errata document describes corrections to the
MCF5235 Reference Manual, order number
MCF5235RM. For convenience, the addenda items are
grouped by revision. Please check our website at

http://www.freescale.com/coldfire for the latest updates.

The current version available of the MCF5235 Reference
Manual is Revision 2.

Table of Contents

1 Errata for Revision 2............................................2

2 Errata for Revision 1.1.........................................5

3 Revision History ............... ... ... .............................8

© Freescale Semiconductor, Inc., 2007. All rights reserved.

Errata for Revision 2

1 Errata for Revision 2

Table 1. MCF5235RM Rev 2 Errata

Location Description

Figure 1-1/Page 1-3 Change instance of CIM to “CCM and Reset Controller”.

Section 1.3.1/Page 1-8 Change “Chip Integration Module (CIM)” to “Chip Configuration Module (CCM)”.

Move Reset sub-bullet (and its sub-bullets) up one level.
Table 2-1/Page 2-5 Change SD_CKE pin location from 139 to “—” for the 160QFP device.
Table 2-1/Page 2-6 Change QSPI_CS1 pin location from “—” to 139 for the 160QFP device.
Table 3-1/Page 3-4 Remove last sentence in C bit field description.
Table 3-5/Page 3-8 Change PC’s Written with MOVEC entry to “No”.

Section 3.4/Page 3-9 Change last bullet to “Use of separate system stack pointers for user and supervisor

modes”

Section 3.5/Page 3-10 Change last sentence in fourth paragraph (step 2) to “The IACK cycle is mapped to special

locations within the interrupt controller's address space with the interrupt level encoded in

the address."

Figure 4-9/Page 4-14 Add minus sign to the exponent so that it is “–(i + 1 – N)”.

Table 5-3/Page 5-7 Change reset value of ACR0, ACR1 to “See Section” since some of the bits are undefined

after reset.

Figure 5-2/Page 5-7 Change CACR fields to R/W, since they may be read via the debug module.
Table 5-5/Page 5-10 For split instruction/data cache entry, swap text in parantheses in the description field.

Instruction cache uses the upper half of the arrays, while data cache uses the lower half.

Figure 5-3/Page 5-11 Change reset value of ACR: Bits 31-16, 14-13, 6-5, and 2 are undefined, and other bits are

cleared.

Change ACR fields to R/W, since they may be read via the debug module.

Section 5.2.1.2/Page 5-11 Change note to:

NOTE

Peripheral (IPSBAR) space should not be cached. The
combination of the CACR defaults and the two ACRn
registers must define the non-cacheable attribute for
this address space.

Figure 6-1/Page 6-2 Change RAMBAR fields to R/W, since they may be read via the debug module.

Section 11.2.1.1/Page 11-3 After the first paragraph add the following note:

NOTE

Accessing reserved IPSBAR memory space could
result in an unterminated bus cycle that causes the
core to hang. Only a hard reset will allow the core to
recover from this state. Therefore, all bus accesses to
IPSBAR space should fall within a module's memory

map space.
Table 12-1/Page 12-5 Change SD_CKE pin location from 139 to “—” for the 160QFP device.
Table 12-1/Page 12-7 Change QSPI_CS1 pin location from “—” to 139 for the 160QFP device.

Table 12-9/Page 12-21 Change footnote from “...of the RCSC field in the CIM reset configuration register.” to “... of

the RCR[RCSC] field in the reset controller.”

MCF5235 Reference Manual Errata, Rev. 2.2

Freescale Semiconductor2

Errata for Revision 2

Interrupt

Level

ICR[IL]

Priority
ICR[IP]

Supported Interrupt

Sources

7

7

#8–63

6
5
4

— (Mid-point) #7 (IRQ7)

3

#8–63

2
1
0

6

7–4 #8–63

— (Mid-point) #6 (IRQ6)

3–0 #8–63

5

7–4 #8–63

— (Mid-point) #5 (IRQ5)

3–0 #8–63

4

7–4 #8–63

— (Mid-point) #4 (IRQ4)

3–0 #8–63

3

7–4 #8–63

— (Mid-point) #3 (IRQ3)

3–0 #8–63

2

7–4 #8–63

— (Mid-point) #2 (IRQ2)

3–0 #8–63

1

7–4 #8–63

— (Mid-point) #1 (IRQ1)

3–0 #8–63

Table 1. MCF5235RM Rev 2 Errata (continued)

Location Description

Table 12-10/Page 12-22 In PAR_TSIZ1 field change CIM to CCM.

In PAR_TSIZ0 field change CIM to CCM.

Table 13-1/Page 13-3 Replace table with the one below to better illustrate the interrupt priority and level

assignments.

Table 13-2/Page 13-5 In footnote, remove mention of the SWIACK register, as it is not supported in the global

Table 13-3/Page 13-6 Added global IACK addresses for the L1IACK–L7IA CK registers in the IPSBAR offset

Section 13.2.1.7/Page 13-18 Change last paragraph to: “In addition to the IACK registers within each interrupt controller,

Section 14.4/Page 14-13 Remove last sentence in this section starting with “BCRn decrements...” since SAA bit is

Section 14.4.4.1/Page 14-16 Change DREQ

Freescale Semiconductor 3

IACK space.

column, 0xFE4–0xFFC.

there are global LnIACK registers. A read from one of the global LnIACK registers returns
the vector for the highest priority unmasked interrupt within a level for all interrupt
controllers. There is no global SWIACK register. However, reading the SWIACK register
from each interrupt controller return s the vector number of the highest priority unmasked
request within that controller.”

not supported.

[32:0] to DREQ[3:0].

MCF5235 Reference Manual Errata, Rev. 2.2