NXP Semiconductors MC9S12ZVH64, MC9S12ZVH128 Reference Manual

S12 MagniV
Microcontrollers

freescale.com

MC9S12ZVH-Family
Reference Manual

MC9S12ZVHRMV1
Rev. 1.05
03/2015

To provide the most up-to-date information, the online revision of our documents is the most current. Your
printed copy may be an earlier revision. To verify you have the latest information available, refer to:

freescale.com

The following revision history table summarizes changes. This document contains information for all
constituent modules, with the exception of the S12Z CPU. For S12ZCPU information please refer to the
CPU S12Z Reference Manual. A full list of family members and options is included in the appendices.

Revision History

Date

Sep, 2013 1.00

Sep, 2013 1.01

Mar, 2014 1.02

Revision

Level

Description

First external release version

- replace the ZVH64 100pin with ZVH128 100pin

- CANPHY update to pass conformance test for 2N65E

- Update OSC etc electrical spec

Corrected footers in TOC, S12ZBDC and Appendix N
Removed list of chapters
Corrected TOC format of appendix listing
Corrected SCIBDL reset value
SPI added MISO pin name to block diagram

Changed V
Changed VDDC load current in RPM to 2.5mA

Changed STOP IDD max. to 700uA at 150C
Changed STOP IDD max. to 65uA at -40C
Changed WAIT IDD max to 21mA at 105C
Changed RUN IDD max to 32mA at 105C
Removed incorrect reference to over-temperature protection
Corrected vector mapping of ADC CONIF_OIE interrupt
Changed STOP mode BDC enabled dependency description (section 1.10.3)
Added frequency spec. for WSTAT disable to Operating Conditions table
Updated ADC section (formatting and wording improvements).
Updated BDC section (improved description of NORESP bit)
Updated CPMU section (improved description of CSAD bit)
Updated FTMRZ section (description of protection in SSC Mode)
Removed electrical parameter classification
Removed references to production test (Tables B-3 and L-2)
Added NVM shipping information to appendix G.3

minimum to 2.95V

LVRXA

Jun, 2014 1.03 Corrected ordering information controller family encoding in Appendix N

Updated BKGD pin I/O specification

Sep, 2014 1.04

Mar, 2015 1.05

Specified ADC accuracy for a range of VDDA and VREF
Updated CANPHY over current detection specification.

CPMU chapter updated. See chapter revision history
Minor BDC chapter correction. See chapter revision history
Corrected 100LQFP diagram pins 76-79 and Table 1-7 Pin 103 mapping
Removed reference to PortP wake-up capability. It has no wake-up capability
Added Startup from reset parameters based on simulation to Table I-1
Corrected ADC result reference alignment.
Extended BKGD V

Updated BATS electrical parameters

condition from 3.15V to 3.13V

IL

Chapter 1

Device Overview MC9S12ZVH-Family

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.2.1 MC9S12ZVH-Family Member Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.3 Maskset 0N65E and 1N65E device compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.4 Maskset 2N65E and 1N65E/0N65E device compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.5 Chip-Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.6 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.6.1 S12Z Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

1.6.2 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

1.6.3 Clocks, Reset & Power Management Unit (CPMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.6.4 Main External Oscillator (XOSCLCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.6.5 32K External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

1.6.6 System Integrity Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

1.6.7 Real Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

1.6.8 Timer (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

1.6.9 Pulse Width Modulation Module (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.6.10 Simple Sound Generator (SSG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.6.11 Liquid Crystal Display driver (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.6.12 Stepper Motor Controller (MC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.6.13 Stepper Stall Detect (SSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.6.14 CAN Physical Layer (CANPHY) transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.6.15 Multi-Scalable Controller Area Network (MSCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.6.16 Inter-IC Bus Module (IIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.6.17 Serial Communication Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1.6.18 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1.6.19 Analog-to-Digital Converter Module (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1.6.20 Supply Voltage Sensor (BATS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1.6.21 On-Chip Voltage Regulator system (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1.7 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

1.7.1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

1.7.2 Part ID registers Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

1.8 Signal Description and Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

1.8.1 Pin Assignment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

1.8.2 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1.8.3 VSENSE - Voltage Sensor Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

1.8.4 BCTLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

1.8.5 VDDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

1.8.6 BCTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

1.8.7 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

1.9 Package and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

1.10 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

1.10.1 Chip Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

1.10.2 Debugging Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

S12ZVH Family Reference Manual , Rev. 1.05

Freescale Semiconductor 3

1.10.3 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

1.11 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

1.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

1.11.2 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

1.11.3 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

1.11.4 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

1.11.5 Reprogramming the Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

1.11.6 Complete Memory Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

1.12 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

1.12.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

1.12.2 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

1.12.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

1.13 COP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

1.14 ADC0 Internal Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

1.15 The ADC0 VRH/VRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

1.16 The ADC0 Conversion Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

1.17 ADC Result Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

1.18 BDC Clock Source Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

1.19 FTMRZ Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

1.20 RTC Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

1.21 LCD Clock Source Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

1.22 32K OSC enable control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Chapter 2

Port Integration Module (S12ZVHPIMV0)

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

2.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

2.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

2.3.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

2.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

2.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

2.4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

2.4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

2.4.4 Pin interrupts and Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

2.5 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

2.5.1 Port Data and Data Direction Register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

2.5.2 SCI0,1 Baud Rate Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

2.5.3 RTC on chip calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

2.5.4 RTC off chip calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

S12ZVH Family Reference Manual, Rev. 1.05

4 Freescale Semiconductor

Chapter 3

Memory Mapping Control (S12ZMMCV1)

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

3.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

3.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

3.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

3.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2

3.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

3.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

3.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3

3.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

3.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

3.4.1 Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

3.4.2 Illegal Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

3.4.3 Uncorrectable ECC Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Chapter 4

Interrupt (S12ZINTV0)

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

4.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

4.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

4.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

4.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

4.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

4.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

4.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

4.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

4.4.1 S12Z Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

4.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

4.4.3 Priority Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

4.4.4 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

4.4.5 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

4.4.6 Interrupt Vector Table Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

4.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

4.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

4.5.2 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

4.5.3 Wake Up from Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Chapter 5

Background Debug Controller (S12ZBDCV2)

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

5.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

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5.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

5.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

5.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

5.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

5.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

5.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

5.4.2 Enabling BDC And Entering Active BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

5.4.3 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

5.4.4 BDC Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

5.4.5 BDC Access Of Internal Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

5.4.6 BDC Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

5.4.7 Serial Interface Hardware Handshake (ACK Pulse) Protocol . . . . . . . . . . . . . . . . . . . . 169

5.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

5.4.9 Hardware Handshake Disabled (ACK Pulse Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . 172

5.4.10 Single Stepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

5.4.11 Serial Communication Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

5.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

5.5.1 Clock Frequency Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Chapter 6

S12Z Debug (S12ZDBGV2) Module

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

6.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

6.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

6.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

6.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

6.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

6.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

6.2.1 External Event Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

6.2.2 Profiling Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

6.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

6.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

6.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

6.4.1 DBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

6.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

6.4.3 Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

6.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

6.4.5 Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

6.4.6 Code Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

6.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

6.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

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6.5.1 Avoiding Unintended Breakpoint Re-triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

6.5.2 Debugging Through Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

6.5.3 Breakpoints from other S12Z sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

6.5.4 Code Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

Chapter 7

S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6)

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

7.1.3 S12CPMU_UHV_V6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

7.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

7.2.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

7.2.2 EXTAL and XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

7.2.3 VSUP — Regulator Power Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

7.2.4 VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 233

7.2.5 VDDX, VSSX— Pad Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

7.2.6 BCTL— Base Control Pin for external PNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

7.2.7 BCTLC — Base Control Pin for external PNP for VDDC power domain . . . . . . . . . . 234

7.2.8 VSS1,2 — Core Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

7.2.9 VDD— Core Logic Supply Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

7.2.10 VDDF— NVM Logic Supply Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

7.2.11 API_EXTCLK — API external clock output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

7.2.12 TEMPSENSE — Internal Temperature Sensor Output Voltage . . . . . . . . . . . . . . . . . . 235

7.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

7.4.1 Phase Locked Loop with Internal Filter (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

7.4.2 Startup from Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

7.4.3 Stop Mode using PLLCLK as source of the Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . 279

7.4.4 Full Stop Mode using Oscillator Clock as source of the Bus Clock . . . . . . . . . . . . . . . 279

7.4.5 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

7.4.6 System Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

7.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

7.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

7.5.2 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

7.5.3 Oscillator Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

7.5.4 PLL Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

7.5.5 Computer Operating Properly Watchdog (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 285

7.5.6 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

7.5.7 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

7.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

7.6.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

7.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

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7.7.1 General Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

7.7.2 Application information for COP and API usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

7.7.3 Application Information for PLL and Oscillator Startup . . . . . . . . . . . . . . . . . . . . . . . . 289

Chapter 8

Timer Module (TIM16B8CV3) Block Description

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

8.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

8.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

8.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

8.2.1 IOC7 — Input Capture and Output Compare Channel 7 . . . . . . . . . . . . . . . . . . . . . . . . 295

8.2.2 IOC6 - IOC0 — Input Capture and Output Compare Channel 6-0 . . . . . . . . . . . . . . . . 295

8.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

8.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

8.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

8.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

8.4.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

8.4.5 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

8.4.6 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

8.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

8.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

8.6.1 Channel [7:0] Interrupt (C[7:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

8.6.2 Pulse Accumulator Input Interrupt (PAOVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

8.6.3 Pulse Accumulator Overflow Interrupt (PAOVF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

8.6.4 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

Chapter 9

Pulse-Width Modulator (S12PWM8B8CV2)

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

9.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

9.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

9.2.1 PWM7 - PWM0 — PWM Channel 7 - 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

9.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

9.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

9.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

9.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

9.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

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9.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

9.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

Chapter 10

Analog-to-Digital Converter (ADC12B_LBA_V1)

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

10.2 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

10.2.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

10.2.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

10.3 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

10.3.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

10.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

10.4.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

10.4.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

10.5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

10.5.2 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

10.5.3 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

10.6 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

10.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

10.7.1 ADC Conversion Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

10.7.2 ADC Sequence Abort Done Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

10.7.3 ADC Error and Conversion Flow Control Issue Interrupt . . . . . . . . . . . . . . . . . . . . . . . 407

10.8 Use Cases and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

10.8.1 List Usage — CSL single buffer mode and RVL single buffer mode . . . . . . . . . . . . . . 408

10.8.2 List Usage — CSL single buffer mode and RVL double buffer mode . . . . . . . . . . . . . 408

10.8.3 List Usage — CSL double buffer mode and RVL double buffer mode . . . . . . . . . . . . . 409

10.8.4 List Usage — CSL double buffer mode and RVL single buffer mode . . . . . . . . . . . . . 409

10.8.5 List Usage — CSL double buffer mode and RVL double buffer mode . . . . . . . . . . . . . 410

10.8.6 RVL swapping in RVL double buffer mode and related registers ADCIMDRI and
ADCEOLRI 410

10.8.7 Conversion flow control application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412

10.8.8 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

10.8.9 Triggered Conversion — Single CSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

10.8.10Fully Timing Controlled Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

Chapter 11

Freescale’s Scalable Controller Area Network (S12MSCANV3)

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

11.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

11.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

11.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

11.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

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11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

11.2.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

11.2.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

11.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

11.3.3 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442

11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

11.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

11.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

11.4.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

11.4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

11.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464

11.4.6 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

11.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

11.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470

11.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470

11.5.2 Bus-Off Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470

Chapter 12

Serial Peripheral Interface (S12SPIV5)

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

12.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

12.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

12.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471

12.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

12.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

12.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

12.2.3 SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

12.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

12.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

12.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

12.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

12.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

12.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

12.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

12.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

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Chapter 13

Inter-Integrated Circuit (IICV3) Block Description

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

13.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

13.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

13.2.1 IIC_SCL — Serial Clock Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

13.2.2 IIC_SDA — Serial Data Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

13.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

13.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

13.4.1 I-Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

13.4.2 Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

13.4.3 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

13.4.4 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

13.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

13.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

13.7 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

13.7.1 IIC Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

Chapter 14

Liquid Crystal Display (LCD40F4BV3) Block Description

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525

14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526

14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526

14.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526

14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

14.2.1 BP[3:0] — Analog Backplane Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

14.2.2 FP[39:0] — Analog Frontplane Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

14.2.3 VLCD — LCD Supply Voltage Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

14.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530

14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

14.4.1 LCD Driver Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

14.4.2 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

14.4.3 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

14.4.4 LCD Waveform Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

14.4.5 LCD Clock Inputs & Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546

14.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547

14.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547

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Chapter 15

Serial Communication Interface (S12SCIV6)

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

15.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

15.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550

15.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

15.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

15.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

15.2.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

15.2.2 RXD — Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

15.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

15.3.1 Module Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553

15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

15.4.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567

15.4.2 LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567

15.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568

15.4.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569

15.4.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570

15.4.6 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

15.4.7 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583

15.4.8 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584

15.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584

15.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584

15.5.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

15.5.3 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

15.5.4 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

15.5.5 Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

Chapter 16

Motor Controller (MC10B8CV1)

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589

16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589

16.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589

16.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592

16.2.1 M0C0M/M0C0P/M0C1M/M0C1P — PWM Output Pins for Motor 0 . . . . . . . . . . . . 592

16.2.2 M1C0M/M1C0P/M1C1M/M1C1P — PWM Output Pins for Motor 1 . . . . . . . . . . . . 592

16.2.3 M2C0M/M2C0P/M2C1M/M2C1P — PWM Output Pins for Motor 2 . . . . . . . . . . . . 592

16.2.4 M3C0M/M3C0P/M3C1M/M3C1P — PWM Output Pins for Motor 3 . . . . . . . . . . . . 593

16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601

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16.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601

16.4.2 PWM Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

16.4.3 Motor Controller Counter Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

16.4.4 Output Switching Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614

16.4.5 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

16.4.6 Operation in Stop and Pseudo-Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

16.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

16.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

16.6.1 Timer Counter Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

16.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616

16.7.1 Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616

Chapter 17

Stepper Stall Detector (SSDV2) Block Description

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621

17.1.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621

17.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621

17.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622

17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623

17.2.1 COSM/COSP — Cosine Coil Pins for Motor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623

17.2.2 SINM/SINP — Sine Coil Pins for Motor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623

17.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624

17.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624

17.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624

17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631

17.4.1 Return to Zero Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632

17.4.2 Full Step States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632

17.4.3 Operation in Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636

17.4.4 Stall Detection Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636

Chapter 18

Real-Time Counter With Calendar (RTCV2)

18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639

18.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639

18.2.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639

18.2.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640

18.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641

18.3.1 OSCCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641

18.3.2 OSCCLK_32K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

18.3.3 IRCCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

18.3.4 RTCCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

18.3.5 CALCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

18.4 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642

18.4.1 RTC Control Register 1(RTCCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643

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18.4.2 RTC Control Register 2 (RTCCTL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644

18.4.3 RTC Control Register 3 (RTCCTL3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644

18.4.4 RTC Control Register 4 (RTCCTL4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

18.4.5 RTC Status Register 1 (RTCS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646

18.4.6 RTC Compensation Configure Register (RTCCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

18.4.7 RTC Counter Register (RTCCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648

18.4.8 RTC Modulo Register (RTCMOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649

18.4.9 RTC Second Register (RTCSECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649

18.4.10RTC Minute Register (RTCMINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

18.4.11RTC Hour Register (RTCHRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

18.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

18.5.1 RTC clock and reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

18.5.2 Calendar Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

18.5.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

18.5.4 RTC Clock Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652

18.5.5 Calendar Register and Bit Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653

18.5.6 Load buffer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

18.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

18.6.1 RTC Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

18.6.2 RTC compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

Chapter 19

Simple Sound Generator (SSGV1)

19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

19.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

19.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657

19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658

19.2.1 SGT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658

19.2.2 SGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

19.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

19.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

19.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670

19.4.1 SSG Amplitude Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670

19.4.2 SSG Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

19.4.3 SSG Attack and Decay function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

19.4.4 SSG Start and Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674

19.4.5 Register Reload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675

19.4.6 SSG Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676

19.5 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676

Chapter 20

ECC Generation module (SRAM_ECCV1)

20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677

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20.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677

20.2 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677

20.2.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677

20.2.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679

20.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683

20.3.1 Aligned 2 and 4 Byte Memory write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684

20.3.2 Other Memory write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684

20.3.3 Memory read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685

20.3.4 Memory initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685

20.3.5 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685

20.3.6 ECC Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

20.3.7 ECC Debug Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

Chapter 21

128 KB Flash Module (S12ZFTMRZ128K4KV2)

21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690

21.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690

21.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

21.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

21.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692

21.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

21.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

21.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697

21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717

21.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717

21.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717

21.4.3 Flash Block Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717

21.4.4 Internal NVM resource . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718

21.4.5 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718

21.4.6 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . 723

21.4.7 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724

21.4.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740

21.4.9 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740

21.4.10Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741

21.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741

21.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741

21.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 742

21.5.3 .Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . 742

21.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742

Chapter 22

CAN Physical Layer (S12CANPHYV2)

22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743

22.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743

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22.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744

22.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744

22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745

22.2.1 CANH — CAN Bus High Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746

22.2.2 CANL — CAN Bus Low Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746

22.2.3 SPLIT — CAN Bus Termination Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746

22.2.4 VDDC — Supply Pin for CAN Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746

22.2.5 VSSC — Ground Pin for CAN Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746

22.3 Internal Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746

22.3.1 CPTXD — TXD Input to CAN Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746

22.3.2 CPRXD — RXD Output of CAN Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746

22.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747

22.4.1 This section provides a detailed description of all registers accessible in the CAN Physical
Layer.Module Memory Map 747

22.4.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748

22.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755

22.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755

22.5.2 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755

22.5.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757

22.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758

22.6.1 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758

22.6.2 Wake-up Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759

22.6.3 Bus Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759

22.6.4 CPTXD-Dominant Timeout Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759

Chapter 23

Supply Voltage Sensor - (BATSV2)

23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761

23.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761

23.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761

23.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762

23.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762

23.2.1 VSENSE — Supply (Battery) Voltage Sense Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762

23.2.2 VSUP — Voltage Supply Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763

23.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763

23.3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763

23.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764

23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769

23.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769

23.4.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770

Appendix A

MCU Electrical Specifications

A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773

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A.1.1 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774

A.1.2 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775

A.1.3 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776

A.1.4 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777

A.1.5 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778

A.1.6 Power Dissipation and Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779

A.1.7 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782

A.1.8 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784

A.1.9 ADC Conversion Result Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786

Appendix B

ADC Electricals

B.1 ADC Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787

B.1.1 Factors Influencing Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787

B.1.2 ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789

Appendix C

PLL Electrical Specifications

C.1 Reset, Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793

C.1.1 Phase Locked Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793

Appendix D

IRC Electrical Specifications

Appendix E

LCD Electrical Specifications

E.1 LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797

Appendix F

MSCAN Electrical Specifications

F.1 MSCAN Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799

Appendix G

NVM Electrical Parameters

G.1 NVM Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801

G.2 NVM Reliability Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802

G.3 NVM Factory Shipping Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803

Appendix H

BATS Electrical Specifications

H.1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805

H.2 Static Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806

H.3 Dynamic Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807

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Appendix I

VREG Electrical Specifications

Appendix J

S12CANPHY Electrical Specifications

J.1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811

J.2 Static Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811

J.3 Dynamic Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814

Appendix K

Electrical Characteristics for the Oscillator (OSCLCPcr)

K.1 OSCLCP Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817

Appendix L

OSC32K Electrical Specifications

L.1 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819

L.2 Frequency Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819

Appendix M

SPI Electrical Specifications

M.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821

M.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823

Appendix N

Ordering Information

Appendix O

Package Information

O.1 144 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830

O.2 100 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833

Appendix P

Detailed Register Address Map

P.1 Detailed Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837

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Chapter 1 Device Overview MC9S12ZVH-Family

T able 1-1. Revision History

Version

Number

0.0 May 2011 • initial Draft

0.1 Nov 2011 • add the 100LQFP VSSC

0.2 Dec 2011 • update base on review feedback

0.3 Feb 2012 • update VRH/VRL, update base on review feedback

0.4 Apri 2012 • update Section 1.18, “BDC Clock Source Connectivity“

0.5 Sep 2012 • Update the ADC conversion reference IFR location

0.6 Oct 2012 • Add Section 1.3, “Maskset 0N65E and 1N65E device compare“ and update description

0.7 Nov 2012 • Update BDC related change on 1N65E

0.8 Nov 2012 • Update CANPHY related change on 1N65E

0.9 July 2013 • Replace the 64K 100pin with 128K 100pin

Revision

Date

Description of Changes

• update the pin names for ADC/CAN/IIC/CANPHY/SPI/SSG with index number

• Add note on VDDC handle for 100pin

• Fix base on review feedback

• Add FTMRZ related connection

for 1N65E device

• Add 2N65E related update

1.1 Introduction

The MC9S12ZVH-Family is an optimized automotive 16-bit microcontroller product line focused on low­cost, high-performance and application component count reduction. This family integrates the components
of an S12HY or S12XHY-family micr ocontroller with a CAN Physical interface, a 5V regulator system to
supply the microcontroller and other components. The MC9S12ZVH-Family is targeted at automotive &
motorcycle instrument cluster applications requiring CAN connectivity, stepper motor gauges, and
segment LCD displays.

The MC9S12ZVH-Family features a 4x40 liquid crystal display (LCD) controller/driver and a pulse
width modulated motor controller (MC) consisting of up to 16 high current outputs. The device is capable
of stepper motor stall detection (SSD) via hardware or software, please contact Freescale sales office for
detailed information on software SSD.

The MC9S12ZVH-Family delivers an optimized solution with the integration of several key system
components into a single device, optimizing system architecture and achieving significant PCB space
savings. The MC9S12ZVH-Family delivers all the advantages and efficiencies of a 16-bit MCU while
retaining the low cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed
by users of Freescale’s existing 8-bit and 16-bit MCU families. The MC9S12ZVH-Family also features

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Chapter 1 Device Overview MC9S12ZVH-Family

the revolutionary S12Z CPU with code size & execution efficiencies even higher than our class leading
S12X CPU. This also provides a linear memory map for flash memory for all members of the family,
eliminating the awkwardness and performance impact of page swapping. In addition to the I/O ports
available in each module, further I/O ports are available with interrupt capability allowing wake-up from
stop or wait modes.

1.2 Features

This section describes the key features of the MC9S12ZVH-Family.

1.2.1 MC9S12ZVH-Family Member Comparison

Table 1-2 provides a summary of feature set differences within the MC9S12ZVH-Family. All other

features are common to all MC9S12ZVH-Family members.

Table 1-2. MC9S12ZVH-Family features

Feature MC9S12ZVH128 MC9S12ZVH64
CPU HCS12Z HCS12Z
Flash memory (ECC) 128 KB 64 KB
EEPROM (ECC) 4 KB 4 KB
RAM (ECC) 8 KB 4 KB
Stepper Motor Drive (with HW SSD) 2 4 4
Segment LCD 4 x 32 4 x 40 4 x 40
Simple Sound Generator (SSG) Yes Yes Yes
SCI 2 2
SPI 1 1
IIC 1 1
CAN (digital communication

module)
High Speed CAN Physical layer - 1 1

(1)

Timer

PWM 8 ch (8-bit) / 4ch (16-bit) 8 ch (8-bit) / 4ch (16-bit)
RTC Yes Yes

one 4ch x 16-bit, one

7ch x16-bit

11

two 8ch x 16-bit two 8ch x 16-bit

ADC Resolution 10-bit resolution 10-bit resolution
ADC Inputs 4 pins + internal signals 8 pins + internal signals 8 pins + internal sign als
Key Wakeup Pins 19 24 24

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Chapter 1 Device Overview MC9S12ZVH-Family

Feature MC9S12ZVH128 MC9S12ZVH64
Frequency modulated PLL Yes Yes
Internal 1 MHz RC oscillator Yes Yes

Autonomous window watchdog 1 (with independent clock sourc e )

Direct Battery Voltage sense pin Yes Yes
Vsup sense Yes Yes
Chip temperature sensor 1 General sensor 1 General sensor

VSUP Supply voltage

VDDX Output current

Maximum Bus Frequency 32 MHz 32 MHz
Package 100 pins (LQFP) 144 pins (LQFP) 144 pins (LQFP)

5.5 V – 18 V (normal operation)

up to 40V (protected operation)

Determined by power dissipation of external

ballast

1 (with independent

clock source)

5.5 V – 18 V (normal
operation)

up to 40V (protected

operation)

Determined by power

dissipation of external

ballast

1. The channles show here just reflect the avaiable IOC pins, the timer are still 2 x 8 channles

1.3 Maskset 0N65E and 1N65E device compare

0N65E and 1N65E devices have difference on some module versions. Table 1-3 shows the difference.

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Chapter 1 Device Overview MC9S12ZVH-Family

NOTE User should take care when switch from 0N65E to 1N65E device

Table 1-3. Device Difference for 0N65E and 1N65E

0N65E 1N65E

RTC V1 V2

CPMU V4 V6

DBG V1 V2

SCI V5 V6

FTMRZ V1 V2

BDC V1 V2

CANPHY V1 V2

MCU BDC fast clock source to CORE clock BDC fast clock source to Bus clock

ADC reference voltage to IFR

1.4 Maskset 2N65E and 1N65E/0N65E device compare

on 2N65E, the CANPHY is update in order to pass conformance test. It changes the bus error behavior to
keep CANH bus driver operational if CANH and/or CANL sensed below ground. See CANPHY block
guide for the detailed information.

1.5 Chip-Level Features

On-chip modules available within the family include the following features:

• S12Z CPU core

• 128 or 64 KB on-chip flash with ECC

• 4 KB EEPROM with ECC

• 8 or 4 KB on-chip SRAM with ECC

• Phase locked loop (IPLL) frequency multiplier with internal filter

• 1 MHz internal RC oscillator with +/-1.3% accuracy over rated temperature range

• 4-20 MHz amplitude controlled pierce oscillator

• 32 KHz oscillator for RTC and LCD

• Internal COP (watchdog) module

• LCD driver for segment LCD with 40 frontplanes x 4 backplanes

• Stepper Motor Controller with drivers for up to 4 motors

• Up to 4 Stepper Stall Detector (SSD) modules (one for each motor)

• Real Time Clock (RTC) support the Hour/Minute/Second function and frequency compensation

• One Analog-to-Digital Converters (ADC) with 10-bit resolution and up to 8 channels available on
external pins

• Two Timer module (TIM) supporting input/output channels that provide a range of 16-bit input
capture & output compare (8 channels)

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Chapter 1 Device Overview MC9S12ZVH-Family

• One Pulse Width Modulation (PWM) modules with up to 8 x 8-bit channels

• Simple Sound Generation (SSG) for monotonic tone generation

• One Inter-Integrated Circuit (IIC) module

• One Serial Peripheral Interface (SPI) module

• Two Serial Communication Interface (SCI) module supporting LIN 1.3, 2.0, 2.1 and SAE J2602
communications

• Up to one on-chip high-speed CAN physical layer transceiver

• One MSCAN (up to 1 Mbp/s, CAN 2.0 A, B compliant) module

• On-chip Voltage Regulator (VREG) for regulation of input supply and all internal voltages
— Optional VREG ballast control output to supply an external or internal CAN physical layer

• Autonomous Periodic Interrupt (API) (combination with cyclic, watchdog)

• Supply voltage sense with low battery warning.

• Chip temperature sensor

1.6 Module Features

The following sections provide more details of the integrated modules.

1.6.1 S12Z Central Processor Unit (CPU)

The S12Z CPU is a revolutionary high-speed core, with code size and execution efficiencies over the S12X
CPU. The S12Z CPU also provides a linear memory map eliminating the inconvenience & performance
impact of page swapping.

• Harvard Architecture - parallel data and code access

• 3 stage pipeline

• 32-Bit wide instruction and databus

• 32-Bit ALU

• 24-bit addressing, i.e. 16 MB linear address space

• Instructions and Addressing modes optimized for C-Programming & Compiler
— MAC unit 32bit += 32bit*32bit
— Hardware divider
— Single cycle multi-bit shifts (Barrel shifter)
— Special instructions for fixed point match

• Unimplemented opcode traps

• Unprogrammed byte value (0xFF) defaults to SWI instruction

1.6.1.1 Background Debug Controller (BDC)

• Background Debug Controller (BDC) with single-wire interface
— Non-intrusive memory access commands

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Chapter 1 Device Overview MC9S12ZVH-Family

— Supports in-circuit programming of on-chip nonvolatile memory

1.6.1.2 Debugger (DBG)

• Enhanced DBG module including:
— Four comparators (A, B, C and D) each configurable to monitor PC addresses or addresses of

data accesses
— A and C compare full address bus and full 32-bit data bus with data bus mask register
— B and D compare full address bus only
— Three modes: simple address/data match, inside address range, or outside address range
— Tag-type or force-type hardware breakpoint requests

• State sequencer control

• 64 x 64-bit circular trace buffer to capture change-of-flow addresses or address and data of every
access

— Begin, End and Mid alignment of tracing to trigger

• Profiling mode

1.6.2 Embedded Memory

1.6.2.1 Flash

On-chip flash memory :

• Up to 128 KB of program flash memory
— 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit fault correction

and double fault detection
— Erase sector size 512 bytes
— Automated program and erase algorithm
— User margin level setting for reads
— Protection scheme to prevent accidental program or erase

1.6.2.2 EEPROM

• Up to 4 KB EEPROM
— 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction

and double fault detection
— Erase sector size 4 bytes
— Automated program and erase algorithm
— User margin level setting for reads

1.6.2.3 SRAM

• Up to 8 KB of general-purpose RAM with ECC

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— Single bit error correction and double bit error detection

1.6.3 Clocks, Reset & Power Management Unit (CPMU)

• Real Time Interrupt (RTI)

• Clock Monitor, supervising the correct function of the oscillator (CM)

• System reset generation

• Autonomous periodic interrupt (API) (combination with cyclic, watchdog)

• Low Power Operation
— RUN mode is the main full performance operating mode with the entire device clocked.
— WAIT mode when the internal CPU clock is switched off, so the CPU does not execute

instructions.

— Pseudo STOP - system clocks are stopped but the RTI, COP, API, RTC and LCD modules can

be enabled with clock source from the osc.

— STOP - the oscillator is stopped in this mode, all clocks are switched off and all counters and

dividers remain frozen. The 32 KHz oscillator can be enabled, RTC and LCD can be still
function if enabled. The API and COP can still function if their clock source are from API
clock(ACLK).

1.6.3.1 Internal Phase-Locked Loop (IPLL)

• Phase-locked-loop clock frequency multiplier
— No external components required
— Reference divider and multiplier allow large variety of clock rates
— Automatic bandwidth control mode for low-jitter operation
— Automatic frequency lock detector
— Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)
— Reference clock sources:

– Internal 1 MHz RC oscillator (IRC)
– External 4-20 MHz crystal oscillator/resonator

1.6.3.2 Internal RC Oscillator (IRC)

• Trimmable internal reference clock.
— Frequency: 1 MHz; Trimmed accuracy over -40C to 150C junction temperature range:

1.3%

1.6.4 Main External Oscillator (XOSCLCP)

• Loop control Pierce oscillator using 4 MHz to 20 MHz crystal
— Current gain control on amplitude output
— Signal with low harmonic distortion

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Chapter 1 Device Overview MC9S12ZVH-Family

— Low power
— Good noise immunity
— Eliminates need for external current limiting resistor
— Transconductance sized for optimum start-up margin for typical crystals
— Oscillator pins shared with GPIO functionality

1.6.5 32K External Oscillator

• Low speed oscillator using 32 KHz to 40 KHz crystal
— Low power
— Good noise immunity
— Oscillator pins shared with GPIO functionality

1.6.6 System Integrity Support

• Power-On Reset (POR)

• Illegal address detection

• Low-voltage detection and low voltage reset generation

• Clock monitor

• High temperature Interrupt

• Computer Operating Properly (COP) watchdog
— Configurable as window COP for enhanced failure detection
— Can be initialized out of reset using option bits located in flash memory

• Unimplemented opcode traps

• Unprogrammed byte value (0xFF) defaults to SWI instruction

• ECC support on embedded NVM

1.6.7 Real Time Clock (RTC)

• Basic Clock functions with separate counters for Hour, Minutes and Seconds.Hardware
Compensation to reduce the effects of frequency variation on the 1 Hz clock (to the counters)
caused by temperature changes of crystal characteristics. Correction factor calculated by firmware.
(Programmable correction factor).

• 16-bit CPU register programming interface with protection against run-away code.

• Option to output the buffered 32.768 kHz clock or the compensated 1 Hz clock for calibration.

1.6.8 Timer (TIM)

• Up to two timer modules for input capture or output compare
— 8 x 16-bit channels per module

• 16-bit free-running counter with 8-bit precision prescaler

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• 16-bit pulse accumulator

1.6.9 Pulse Width Modulation Module (PWM)

• 8 channels x 8-bit (4 channels x 16-bit)

• Programmable period and duty cycle per channel

• Center-aligned or edge-aligned outputs

• Programmable clock select logic with a wide range of frequencies

1.6.10 Simple Sound Generator (SSG)

• Programmable amplitude level with maximum 11 bit resolution from zero amplitude to max
amplitude

• Sound STOP function to stop sound generation immediately

• Registers double-buffered synchronously reload at edge of tone to avoid distortion of output tone.

• Interrupt generated when SSG configure registers reload occurs

• Input clock prescaler with 11 bit resolution

• Module disable for power saving when SSG is not in use

• Separate or mixed frequency and amplitude outputs for flexibility in external hardware variation.

• Decay/attack function which can decrease/increase sound amplitude automatically without cpu
interaction. The function includs linear, gong and exponential decay/attack profiles

1.6.11 Liquid Crystal Display driver (LCD)

• Up to 40 frontplanes and 4 backplanes or general-purpose input or output

• 5 modes of operation allow for different display sizes to meet application requirements

• Unused frontplane and backplane pins can be used as general-purpose I/O

1.6.12 Stepper Motor Controller (MC)

• PWM motor controller (MC) with up to 16 high current outputs

• Each PWM channel switchable between two drivers in an H-bridge configuration

• Left, right and center aligned outputs

• Support for sine and cosine drive

• Dithering

• Output slew rate control

1.6.13 Stepper Stall Detect (SSD)

• Up to four SSD

• Programmable Full Step State

• Programmable Integration polarity

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Chapter 1 Device Overview MC9S12ZVH-Family

• Blanking (recirculation) state

• 16-bit Integration Accumulator register

• 16-Bit Modulus Down Counter with interrupt

1.6.14 CAN Physical Layer (CANPHY) transceiver

• High speed CAN interface for baud rates of up to 1 Mbit/s

• ISO 11898-2 and ISO 11898-5 compliant for 12 V battery systems

• SPLIT pin driver for bus recessive level stabilization

• Low power mode with remote CAN wake-up handled by MSCAN module

• Over-current shutdown for CANH and CANL

• Voltage monitoring on CANH and CANL

• CPTXD-dominant timeout feature monitoring the CPTXD signal on 1N65E/2N65E

1.6.15 Multi-Scalable Controller Area Network (MSCAN)

• Implementation of the CAN protocol — Version 2.0A/B

• Five receive buffers with FIFO storage scheme

• Three transmit buffers with internal prioritization using a “local priority” concept

• Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, or four
16-bit filters, or either 8-bit filters

• Programmable wake-up functionality with integrated low-pass filter

1.6.16 Inter-IC Bus Module (IIC)

• Compatible with I2C bus standard

• Multi-master operation

• Software programmable for one of 256 different serial clock frequencies

• Software selectable acknowledge bit

• Interrupt driven byte-by-byte data transfer

• Arbitration lost interrupt with automatic mode switching from master to slave

• Calling address identification interrupt

• Start and stop signal generation/detection

• Repeated start signal generation

• Acknowledge bit generation/detection

• Bus busy detection

• General Call Address detection

• Compliant to ten-bit address

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1.6.17 Serial Communication Interface Module (SCI)

• Full-duplex or single-wire operation

• Standard mark/space non-return-to-zero (NRZ) format

• 13-bit baud rate selection for 0N65E device

• 16-bit baud rate selection for 1N65E device

• Programmable character length

• Programmable polarity for transmitter and receiver

• Active edge receive wakeup

• Break detection/generation supporting LIN communications

1.6.18 Serial Peripheral Interface Module (SPI)

• Configurable 8- or 16-bit data size

• Full-duplex or single-wire bidirectional

• Double-buffered transmit and receive

• Master or slave mode

• MSB-first or LSB-first shifting

• Serial clock phase and polarity options

1.6.19 Analog-to-Digital Converter Module (ADC)

• One ADC
— 10-bit resolution
— Up to 8 external channels & 8 internal channels
— Left or right aligned result data
— Continuous conversion mode

• ADC directly writes results to RAM, preventing stall of further conversions

• Internal signals monitored with the ADC module
— Vrh, Vrl, Vrl+Vrh/2, Vsup or Vsense monitor, Vbg, TempSense.

• External pins can also be used as digital I/O

1.6.20 Supply Voltage Sensor (BATS)

• VSENSE & VSUP pin low or a high voltage interrupt

• VSENSE & VSUP pin can be routed via an internal divider to the internal ADC channel

• Generation of low or high voltage interrupts

1.6.21 On-Chip Voltage Regulator system (VREG)

• Voltage regulator

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Chapter 1 Device Overview MC9S12ZVH-Family

— Linear voltage regulator directly supplied by V
— Low-voltage detect with low-voltage interrupt V

(protected V

SUP

SUP

BAT

)

— Power-On Reset (POR)
— Low-Voltage Reset (LVR)
— External ballast device support to reduce internal power dissipation
— Capable of supplying both the MCU internally plus external components
— Over-temperature interrupt

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30 Freescale Semiconductor

1.7 Block Diagram

ADC0

SCI1

AN0_[7:0]

10-bit 8-channel
Analog-Digital Converter

TIM1

Asynchronous Serial IF

ECLK

RXD1

VDDA/VRH

VSSA/VRL

VDDX3,2,1/VSSX3,2,1

VDDM2/VSSM2

5V IO Supply

VDDM1/VSSM1

PTU

Motor Driver0

IIC0

SDA0

SCL0

VLCD

VDDA/VSSA

CAN0

RXCAN0

TXCAN0

msCAN 2.0B

PA[ 7:0]

PTA

SSD 0

PB[3:0]

PTB

PH[7:0]

PTH

PD[7:0]

PTD

PF[7:0]

PTF

PG[7:0]

PTG

PC[7:0]

PTC

PP[7:0]

PTP

PT[7:0]

PTT(KWT)

PS[7:0]

PTS(KWS)

IOC1_[7:0]

XIRQ/IRQ function

PWM0

PWM[7:0]

SCI0
Asynchronous Serial IF

SS0

SCK0

MOSI0

MISO0

SPI0

Synchronous Serial IF

40 X 4 LCD display

PU[7:0]

PTAD(KWAD)

SSG0

SGA0

SGT0

4 KB, 8KB RAM with ECC

4 KB EEPROM with ECC

VSUP

64 KB, 128 KB Flash with ECC

S12ZCPU

VDDA

VSS1

Voltage Regulator

(Nominal 12 V)

BATS

Voltage Supply Monitor

BCTL

VDDX1

VDD

VDDF

VSS2

BCTLC

VDDC

RESET

EXTAL

XTAL

BKGD

Real Time Interrupt

Clock Monitor

Background

TEST

Debug Controller

Interrupt Module

COP Watchdog

PLL with Frequency

Modulation option

Debug Module
4 Comparators
64 Byte Trace Buffer

Reset Generation

and Test Entry

Auto. Periodic Int.

Low Power Pierce

Oscillator

PE0

PTE[1:0]

PE1

BDC

DBG

CANPHY

CANH0

CANL0

VDDC

SPLIT0

VSSC

32K_EXTAL

32K_XTAL

PE2

PTE[3:2]

PE3

32.768K OSC

Motor Driver1

SSD 1

PTV

Motor Driver2

SSD 2

PV[7:0]

Motor Driver3

SSD 3

VSENSE

TIM0

IOC0_[7:0]

PS7

PS6

RTC

Internal 1 MHz

Oscillator

TXD1

RXD0

TXD0

PAD[7:0]

Figure 1-1. MC9S12ZVH-Family Block Diagram

Chapter 1 Device Overview MC9S12ZVH-Family

Freescale Semiconductor 31

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Chapter 1 Device Overview MC9S12ZVH-Family

1.7.1 Device Memory Map

Table 1-4 shows the device register memory map.

Table 1-4. Module Register Address Ranges

Address Module

0x0000-0x0003 ID Registers 4

0x0004-0x000F

0x0010-0x001F INT 16

0x0020-0x006F

0x0070-0x00FF MMC 14 4

0x0100-0x017F DBG 12 8

0x0180-0x01FF

0x0200-0x037F PIM 38 4

0x0380-0x039F FTMRZ 32

0x03A0-0x03BF

0x03C0-0x03CF RAM ECC 16

0x03D0-0x03FF

0x0400-0x042F TIM1 48

0x0430-0x047F

0x0480-0x04AF PWM 48

Reserved 12

Reserved 80

Reserved 128

Reserved 32

Reserved 48

Reserved 80

Size

(Bytes)

0x04B0-0x05BF

0x05C0-0x05EF TIM0 48

0x05F0-0x05FF

0x0600-0x063F ADC0 64

0x0640-0x06BF

0x06C0-0x06DF CPMU 32

0x06E0-0x06EF

0x06F0-0x06F7 BATS 8

0x06F8-0x06FF

0x0700-0x0707 SCI0 8

0x0708-0x070F

0x0710-0x0717 SCI1 8

0x0718-0x077F

0x0780-0x0787 SPI0 8

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Reserved 272

Reserved 16

Reserved 128

Reserved 16

Reserved 8

Reserved 8

Reserved 104

32 Freescale Semiconductor

Chapter 1 Device Overview MC9S12ZVH-Family

Table 1-4. Module Register Address Ranges

Address Module

0x0788-0x07BF Reserved 56

0x07C0-0x07C7 IIC0 8

0x07C8-0x07FF

0x0800-0x083F CAN0 64

0x0840-0x098F

0x0990-0x0997 CANPHY0 8

0x0998-0x09FF

0x0A00-0x0A1F LCD 32

0x0A20-0x0A3F

0x0A40-0x0A7F MC 64

0x0A80-0x0A87 SSD0 8

0x0A88-0x0A8F

0x0A90-0x0A97 SSD1 8

0x0A98-0x0A9F

0x0AA0-0x0AA7 SSD2 8

Reserved 56

Reserved 336

Reserved 104

Reserved 32

Reserved 8

Reserved 8

Size

(Bytes)

0x0AA8-0x0AAF

0x0AB0-0x0AB7 SSD3 8

0x0AB8-0x0ADF

0x0AE0-0x0AEF RTC 16

0x0AF0-0x0AFF

0x0B00-0x0B17 SSG0 24

0x0B18-0x0FFF

Reserved 8

Reserved 40

Reserved 16

Reserved 1256

NOTE

Reserved register space shown in the table is not allocated to any module.
This register space is reserved for future use. W riting to these locations ha s
no effect. Read access to these locations returns zero.

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Chapter 1 Device Overview MC9S12ZVH-Family

0x00_1000

0x00_0000

0x10_0000

0x1F_4000

0x80_0000

0xFF_FFFF

RAM

EEPROM

Unimplemented

Program NVM

Register Space

4 KByte

max. 1 MB - 4 KB

max. 1 MB - 48 KB

max. 8 MB

6 MB

High address aligned

Low address aligned

0x1F_8000

Unimplemented

address range

0x1F_C000

Reserved (read only)

6 KB

NVM IFR

256 Byte

Reserved

512 Byte

0x20_0000

34 Freescale Semiconductor

Figure 1-2. MC9S12ZVH-Family Global Memory Map.

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1.7.2 Part ID registers Assignments

The Part ID registers is located in four 8-bit registers at addresses 0x0000-0x0003. The read-only value is
a unique ID for each revision of the chip. Table 1-5 shows the assigned Part ID register value.

Table 1-5. Assigned IDs Numbers

Device Mask Set number Part ID

MC9S12ZVH128 0N65E 32’h01170000

MC9S12ZVH64 0N65E 32’h01170000

MC9S12ZVH128 1N65E 32’h01171000

MC9S12ZVH64 1N65E 32’h01171000

MC9S12ZVH128 2N65E 32’h01171100

MC9S12ZVH64 2N65E 32’h01171100

1.8 Signal Description and Device Pinouts

This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals. It is built from the signal description sections of the
individual IP blocks on the device.

1.8.1 Pin Assignment Overview

Table 1-6 provides a summary of which ports are available for 100-pin and 144-pin package option.

Table 1-6. Port Availability by Package Option

Port 144 LQFP 100 LQFP

Port AD PAD[7:0] PAD[3:0]

Port A PA[7:0] PA[7:2]

Port B PB[3:0] PB[3:0]

Port C PC[7:0] PC[5:4]

Port D PD[7:0] PD[7:3]

Port E PE[3:0] PE[3:0]

Port F PF[7:0] PF[7:0]

Port G PG[7:0] PG[7:0]

Port H PH[7:0] PH[3:0]

Port P PP[7:0] PP[1,3,5,7]

Port S PS[7:0] PS[7:0]

Port T PT[7:0] PT[7:6], PT[4:0]

Port U PU[7:0] PU[7:0]

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Table 1-6. Port Availability by Package Option

Port 144 LQFP 100 LQFP

Port V PV[7:0] —

sum of ports 104 72

NOTE

T o avoid current drawn from floating inputs, all non-bonded pins should be
configured as output or configured as input with a pull up or pull down
device enabled

1.8.2 Detailed Signal Descriptions

1.8.2.1 RESET — External Reset Signal

The RESET signal is an active low bidirectional control signal. It acts as an input to initialize the MCU to
a known start-up state, and an output when an internal MCU function causes a reset. The RESET pin has
an internal pull-up device.

1.8.2.2 TEST — Test Pin

This input only pin is reserved for factory test. This pin has an internal pull-down device.

NOTE

The TEST pin must be tied to ground in all applications.

1.8.2.3 MODC — Mode C Signal

The MODC signal is used as a MCU operating mode select during reset. The state of this signal is latched
to the MODC bit at the rising edge of RESET. The signal has an internal pull-up device.

1.8.2.4 PAD[7:0] / KWAD[7:0] — Port AD, Input Pins of ADC

P AD[7:0] are general-purpose input or output signals. The signals can be configured on per signal basis as
interrupt inputs with wake-up capability (KWAD[7:0]). These signals can have a pull-up or pull-down
device selected and enabled on per signal basis. Out of reset the pull devices are disabled.

1.8.2.5 PA[7:0] — Port A I/O Signals

P A[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected
and enabled on per signal basis. Out of reset the pull-down devices are enabled.

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1.8.2.6 PB[3:0] — Port B I/O Signals

PB[3:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected
and enabled on per signal basis. Out of reset the pull-down devices are enabled.

1.8.2.7 PC[7:0] — Port C I/O Signals

PC[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected
and enabled on per signal basis. Out of reset the pull devices are disabled.

1.8.2.8 PD[7:0] — Port D I/O Signals

PD[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected
and enabled on per signal basis. Out of reset the pull-down devices are enabled.

1.8.2.9 PE[3:0] — Port E I/O Signals

PE[3:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected
and enabled on per signal basis. Out of reset the pull-down devices are enabled.

1.8.2.10 PF[7:0] — Port F I/O Signals

PF[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected
and enabled on per signal basis. Out of reset the pull-down devices are enabled.

1.8.2.11 PG[7:0] — Port G I/O Signals

PG[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected
and enabled on per signal basis. Out of reset the pull-down devices are enabled.

1.8.2.12 PH[7:0] — Port H I/O Signals

PH[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected
and enabled on per signal basis. Out of reset the pull-down devices are enabled.

1.8.2.13 PP[7:0] — Port P I/O Signals

PP[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected
and enabled on per signal basis. Out of reset the pull devices are disabled.

1.8.2.14 PS[7:0] / KWS[7:0] — Port S I/O signals

PS[7:0] are general-purpose input or output signals. The signals can be configured on per signal basis as
interrupt inputs with wake-up capability (KWS[7:0]). These signals can have a pull-up or pull-down
device selected and enabled on per signal basis. The signals can be configured on per signals basis as open
drain output. Out of reset the pull-up devices are enabled.

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1.8.2.15 PT[7:0] / KWT[7:0] — Port T I/O signals

PT[7:0] are general-purpose input or output signals. The signals can be configured on per signal basis as
interrupt inputs with wake-up capability (KWT[7:0]). These signals can have a pull-up or pull-down
device selected and enabled on per signal basis. Out of reset the pull devices are disabled.

1.8.2.16 PU[7:0] — Port U I/O Signals

PU[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected
and enabled on per signal basis. They can have a slew rate enabled per signal basis also. Out of reset the
pull devices are disabled.

1.8.2.17 PV[7:0] — Port V I/O Signals

PV[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected
and enabled on per signal basis. They can have a slew rate enabled per signal basis also. Out of reset the
pull devices are disabled.

1.8.2.18 AN0_[7:0] — ADC0 Input Signals

AN0_[7:0] are the analog inputs of the Analog-to-Digital Converters.

1.8.2.19 VRH, VRL — ADC0 Reference Signals

VRH and VRL are the reference voltage input pins for the analog-to-digital converter.

1.8.2.20 SPI0 Signals

1.8.2.20.1 SS0 Signal

This signal is associated with the slave select SS functionality of the serial peripheral interface SPI0.

1.8.2.20.2 SCK0 Signal

This signal is associated with the serial clock SCK functionality of the serial peripheral interface SPI0.

1.8.2.20.3 MISO0 Signal

This signal is associated with the MISO functionality of the serial peripheral interface SPI0. This signal
acts as master input during master mode or as slave output during slave mode.

1.8.2.20.4 MOSI0 Signal

This signal is associated with the MOSI functionality of the serial peripheral interface SPI0. This signal
acts as master output during master mode or as slave input during slave mode

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1.8.2.21 SCI[1:0] Signals

1.8.2.21.1 RXD[1:0] Signals

These signals are associated with the receive functionality of the serial communication interfaces
(SCI[1:0]).

1.8.2.21.2 TXD[1:0] Signals

These signals are associated with the transmit functionality of the serial communication interfaces
(SCI[1:0]).

1.8.2.22 CAN0 Signals

1.8.2.22.1 RXCAN0 Signal

This signal is associated with the receive functionality of the scalable controller area network controller
(MSCAN0).

1.8.2.22.2 TXCAN0 Signal

This signal is associated with the transmit functionality of the scalable controller area network controller
(MSCAN0).

1.8.2.23 Timer IOC0_[7:0] & IOC1_[7:0] Signals

The signals IOC0_[7:0] are associated with the input capture or output compare functionality of the timer
(TIM0) module.

The signals IOC1_[7:0] are associated with the input capture or output compare functionality of the timer
(TIM1) module.

1.8.2.24 PWM[7:0] Signals

The signals PWM[7:0] are associated with the PWM module digital channel outputs.

1.8.2.25 LCD Signals

1.8.2.25.1 FP[39:0] Signals

These signals are associated with the segment LCD frontplane driver output.

1.8.2.25.2 BP[3:0] Signals

These signals are associate the segment LCD backplane driver output.

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Chapter 1 Device Overview MC9S12ZVH-Family

1.8.2.26 RTC Signals

1.8.2.26.1 RTC_CAL Signal

The signal can be the R TC output clock CALCLK for external clock calibration or external 1HZ standard
clock input for on chip clock calibration.

1.8.2.27 SSG0 Signals

1.8.2.27.1 SGT0 Signals

The signal is from SSG0 output, it contain tone or tone mixed with amplitude digital output.

1.8.2.27.2 SGA0 Signals

The signal is from SSG0 output, it contain the amplitude digital output.

1.8.2.28 IIC0 Signals

1.8.2.28.1 SDA0 Signal

This signal is associated with the serial data pin of IIC0.

1.8.2.28.2 SCL0 Signal

This signal is associated with the serial clock pin of IIC0.

1.8.2.29 MC Signals

1.8.2.29.1 M0C0M, M0C0P, M0C1M and M0C1P Signals

These signal are associated with the high current PWM out pin for the motor driver.

1.8.2.29.2 M1C0M, M1C0P, M1C1M and M1C1P Signals

These signal are associated with the high current PWM out pin for the motor driver.

1.8.2.29.3 M2C0M, M2C0P, M2C1M and M2C1P Signals

These signal are associated with the high current PWM out pin for the motor driver.

1.8.2.29.4 M3C0M, M3C0P, M3C1M and M3C1P Signals

These signal are associated with the high current PWM out pin for the motor driver.

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40 Freescale Semiconductor

Chapter 1 Device Overview MC9S12ZVH-Family

1.8.2.30 SSD[3:0] Signals

1.8.2.30.1 M0COSM, M0COSP, M0SINM and M0SINP Signals

These signal are used to measure the back EMF to calibrate the pointer reset position which are associated
with SSD[0].

1.8.2.30.2 M1COSM, M1COSP, M1SINM and M1SINP Signals

These signal are used to measure the back EMF to calibrate the pointer reset position which are associated
with SSD[1].

1.8.2.30.3 M2COSM, M2COSP, M2SINM and M2SINP Signals

These signal are used to measure the back EMF to calibrate the pointer reset position which are associated
with SSD[2].

1.8.2.30.4 M3COSM, M3COSP, M3SINM and M3SINP Signals

These signal are used to measure the back EMF to calibrate the pointer reset position which are associated
with SSD[3].

1.8.2.31 Interrupt Signals — IRQ and XIRQ

IRQ is a maskable level or falling edge sensitive input. XIRQ is a non-maskable level-sensitive interrupt.

1.8.2.32 Oscillator and Clock Signals

1.8.2.32.1 4-20MHZ main Oscillator Pins — EXTAL and XTAL

EXT AL and XT AL are the crystal driver . On reset, the OSC is not enabled, all the d evice clocks are derived
from the internal reference clock. EXTAL is the oscillator input. XTAL is the oscillator output.

1.8.2.32.2 32.768KHZ Oscillator Pins — 32K_EXTAL and 32K_XTAL

32K_EXTAL and 32K_XTAL are the 32.768KHZ crystal driver. On reset the OSC is not enabled.
32K_EXTAL is the oscillator input. 32K_XTAL is the oscillator output. Figure 1-3 is the 32K OSC
connection diagram. Refer to the Appendix T able L-1., “OSC32K DC Electrical Specifications for the Cx,
Cy and RF requirement. Both R TC and LCD clock source can from the 32K OSC. The OSC enable control
is from the RTC. If the RTCCTL2’s CLKSRC is set, then it will enable the 32K OSC. After enable the
OSC, it needs to wait enough time before enable the RTC and LCD. Refer to Appendix Table L-2.,

“OSC32K Frequency Specifications for the startup time requirement.

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Freescale Semiconductor 41

Chapter 1 Device Overview MC9S12ZVH-Family

32K OSC

32K_XTAL 32K_EXTAL

C

x

C

y

Crystal or Resonator

R

F

R

s

Figure 1-3. 32K OSC Crystal/Resonator Connection

1.8.2.32.3 API_EXTCLK

This signal is associated with the output of the API.

1.8.2.32.4 ECLK

This signal is associated with the output of the divided bus clock (ECLK).

NOTE

This feature is only intended for debug purposes at room temperature.
It must not be used for clocking external devices in an application.

1.8.2.33 BDC and Debug Signals

1.8.2.33.1 BKGD — Background Debug signal

The BKGD signal is used as a pseudo-open-drain signal for the background debug communication. The
BKGD signal has an internal pull-up device.

1.8.2.33.2 PDO — Profiling Data Output

This is the profiling data output signal used when the DBG module profiling feature is enabled. This signal
is output only and provides a serial, encoded data stream that can be used by external development tools
to reconstruct the internal CPU code flow.

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42 Freescale Semiconductor

Chapter 1 Device Overview MC9S12ZVH-Family

1.8.2.33.3 PDOCLK — Profiling Data Output Clock

This is the PDO clock signal used when the DBG module profiling feature is enabled. This signal is output
only. During code profiling this is the clock signal that can be used by external development tools to
sample the PDO signal.

1.8.2.33.4 DBGEEV — External Event Input

This signal is the DBG external event input. It is input only . W ithin the DBG module, it allows an external
event to force a state sequencer transition, or trace buffer entry, or to gate trace buffer entries. A falling
edge at the external event signal constitutes an event. Rising edges have no effect. The maximum
frequency of events is half the internal core bus frequency.

1.8.2.34 CAN Physical Layer Signals(CANPHY0)

1.8.2.34.1 CANH0 — CAN Bus High Pin0

The CANH0 signal either connects directly to CAN bus high line or through an optional external common
mode choke.

1.8.2.34.2 CANL0 — CAN Bus Low Pin0

The CANL0 signal either connects directly to CAN bus low line or through an optional external common
mode choke.

1.8.2.34.3 SPLIT0 — CAN Bus Termination Pin0

The SPLIT0 pin can drive a 2.5 V bias for bus termination purpose (CAN bus middle point). Usage of this
pin is optional and depends on bus termination strategy for a given bus network.

1.8.2.34.4 CPTXD0

This is the CAN physical layer transmitter input signal.

1.8.2.34.5 CPRXD0

This is the CAN physical layer receiver output signal.

1.8.3 VSENSE - Voltage Sensor Input

This pin can be connected to the supply (Battery) line for voltage measurements. The voltage present at
this input is scaled down by an internal voltage divider , and can be routed to the internal ADC via an analog
multiplexer. The pin itself is protected against reverse battery connections. T o protect the pin from external
fast transients an external resistor is needed.

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Freescale Semiconductor 43

Chapter 1 Device Overview MC9S12ZVH-Family

1.8.4 BCTLC

BCTLC provides the base current of an external bipolar that supplies an external or internal CAN physical
interface.

1.8.5 VDDC

This is connect to the output voltage of the external bipolar. It is the feed back pin to the MCU also. When
VDDC is not used, it must be shorted with VDDX and user must keep the EXTCON in CPMUVREGCTL
be enabled.

1.8.6 BCTL

BCTL provides the base current of an external bipolar of the VDDM, VDDA and VDDX supplies.

1.8.7 Power Supply Pins

The power and ground pins are described below . Because fast signal transitions place high, short-duration
current demands on the power supply , use bypass capacitors with high-frequency characteristics and place
them as close to the MCU as possible.

NOTE

All ground pins must be connected together in the application.

1.8.7.1 VDDX1, VDDX2, VDDX3, VSSX1, VSSX2, VSSX3 — Digital I/O Power and
Ground Pins

VDDX1 is a dedicated voltage regulator output for the digital I/O drivers. It must be connected externally
to the VDDX2 and VDDX3 pin, which supplies the VDDX domain pads. The VSSX1, VSSX2 and
VSSX3 pins are the ground pin for the digital I/O drivers.

Bypass requirements on VDDX1/VSSX1, VDDX2/VSSX2 and VDDX3/VSSX3 depend on how heavily
the MCU pins are loaded.

1.8.7.2 VDDA, VSSA — External Power Supply Pins for ADC and VREG

These are the power supply and ground pins for the analog-to-digital converter and the voltage regulator.

1.8.7.3 VDDM1, VDDM2, VSSM1, VSSM2 — External Power Supply Pins for
Motor PAD

These are the power supply and ground pins for the motor driver pads. It should be supply by external
power transistor.

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44 Freescale Semiconductor

Chapter 1 Device Overview MC9S12ZVH-Family

1.8.7.4 VLCD- Power Supply Reference Pin for LCD driver

VLCD is the voltage reference pin for the LCD driver. Adjusting the voltage on this pin will change the
display contrast.

1.8.7.5 VDD, VSS2 — Core Power and Ground Pin

The VDD voltage supply of nominally 1.8V is generated by the internal voltage regulator. The return
current path is through the VSS2 pin.

1.8.7.6 VDDF, VSS1 — NVM Power and Ground Pin

The VDDF voltage supply of nominally 2.8V is generated by the internal voltage regulator. The return
current path is through the VSS1 pin.

1.8.7.7 VSSC — CANPHY0 Ground Pin

VSSC is the ground pin for the CAN physical layer CANPHY0.

1.8.7.8 VSUP — Voltage Supply Pin f or Voltage Regulator

VSUP is the 12V/18V supply voltage pin for the on chip voltage regulator. This is the voltage supply input
from which the voltage regulator generates the on chip voltage supplies. It must be protected externally
against a reverse battery connection.

1.9 Package and Pinouts

The MC9S12ZVH-Family will be offered in 100 pin and 144 pin LQFP packages.

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Freescale Semiconductor 45

Chapter 1 Device Overview MC9S12ZVH-Family

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

3738394041424344454647484950515253545556575859606162636465666768697071

72

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

FP26 / PG2
FP25 / PG1
FP24 / PG0

VLCD

FP23 / PF7

KWT7 / IOC1_7 / PT7

NC
NC

M0COSM / M0C0M / IOC0_0 / PU0

M0COSP / M0C0P / PU1

M0SINM / M0C1M / IOC0_1 / PU2

M0SINP / M0C1P / PU3

VDDM1

VSSM1

M1COSM / M1C0M / IOC0_2 / PU4

M1COSP / M1C0P / PU5

M1SINM / M1C1M / IOC0_3 / PU6

M1SINP / M1C1P / PU7

M2COSM / M2C0M / IOC0_4 / PV0

M2COSP / M2C0P / PV1

M2SINM / M2C1M / ICO0_5 / PV2

M2SINP / M2C1P / PV3

VDDM2

VSSM2

M3COSM / M3C0M / IOC0_6 / PV4

M3COSP / M3C0P / PV5

M3SINM / M3C1M / IOC0_7 / PV6

M3SINP / M3C1P / PV7

NC
NC

KWT6 / IOC1_6 / ECLK / PT6

FP22 / PF6
FP21 / PF5
FP20 / PF4
FP19 / PF3
FP18 / PF2

BKGD / MODC

PC7 / TXD1
PC6 / RXD1

PC5 / SGA0
PC4 / SGT0
PT4 / PDO / IOC1_4 / KWT4
PT3 / PDOCLK / IOC1_3 / KWT3
PT2 / DBGEEV / IOC1_2 / KWT2
PT1 / RTC_CAL / IOC1_1 / KWT1
PT0 / API_EXTCLK / IOC1_0 / KWT0
VSSX2
VDDX2
PS7 / TXD0 / IRQ

/ KWS7

PS6 / RXD0 / XIRQ

/ KWS6
PS5 / (TXCAN0) / SDA0 / KWS5
PS4 / (RXCAN0) / SCL0 / KWS4
PS3 / SS0

/ KWS3
PS2 / SCK0 / KWS2
PS1 / MOSI0 / KWS1
PS0 / MISO0 / KWS0
BCTLC
BCTL
VSENSE
NC
NC

SPLIT0

NC

CANL0

NC
VSSC
NC

CANH0

NC
VDDC
NC
VSUP

FP17 / PF1

FP16 / PF0

FP15 / PD7

FP14 / PD6

FP13 / PD5

FP12 / PD4

FP11 / PD3

FP10 / PD2

FP9 / PD1

FP8 / PD0

FP7 / (PWM6) / PA7

FP6 / (PWM4) / PA6

FP5 / (PWM2) / PA5

FP4 / (PWM0) / PA4

FP3 / (SDA0) / PA3

FP2 / (SCL0) / PA2

FP1 / PA1

FP0 / PA0

TEST

PWM1 / PP1

PWM3 / PP3

(RXD1) / PWM5 / PP5

(TXD1) / PWM7 / PP7

VSS1

VDDF

RXCAN0 / PC0

TXCAN0 / PC1

CPRXD0 / PC2

CPTXD0 / PC3

RESET

EXTAL / PE0

XTAL / PE1

VSSX1

VDDX1

PWM6 / PP6

KWT5 / IOC1_5 / PT5

PG3 / FP27

PG4 / FP28

PG5 / FP29

PG6 / FP30

PG7 / FP31

PH0 / FP32

PH1 / FP33

PH2 / FP34

PH3 / FP35

PH4 / FP36

PH5 / FP37

PH6 / FP38

PH7 / FP39

VSSX3

VDDX3

PB0 / BP0

PB1 / BP1

PB2 / BP2

PB3 / BP3

PP4 / PWM4

PP2 / PWM2

PP0 / PWM0

VDD

VSS2

PE3 / 32K_XTAL

PE2 / 32K_EXTAL

VSSA / VRL

VDDA / VRH

PAD7 / AN0_7 / KWAD7

PAD6 / AN0_6 / KWAD6

PAD5 / AN0_5 / KWAD5

PAD4 / AN0_4 / KWAD4

PAD3 / AN0_3 / KWAD3

PAD2 / AN0_2 / KWAD2

PAD1 / AN0_1 / KWAD1

PAD0 / AN0_0 / KWAD0

144 LQFP

Top view

1. signal with () means that this is an alternative routing option location for this signal.

2. signal with bold means that it is avaialbe on 144 pin only

46 Freescale Semiconductor

Figure 1-4. MC9S12ZVH-Family 144-pin LQFP pin out 1

S12ZVH Family Reference Manual, Rev. 1.05

2

Chapter 1 Device Overview MC9S12ZVH-Family

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

26272829303132333435363738394041424344454647484950

100

9998979695949392919089888786858483828180797877

76

FP27 / PG3
FP26 / PG2
FP25 / PG1
FP24 / PG0

VLCD

FP23 / PF7

KWT7 / IOC1_7 / PT7

M0COSM / M0C0M / IOC0_0 / PU0

M0COSP / M0C0P / PU1

M0SINM / M0C1M / IOC0_1 / PU2

M0SINP / M0C1P / PU3

VDDM1

VSSM1

M1COSM / M1C0M / IOC0_2 / PU4

M1COSP / M1C0P / PU5

M1SINM / M1C1M / IOC0_3 / PU6

M1SINP / M1C1P / PU7

NC
NC

KWT6 / IOC1_6 / ECLK / PT6

FP22 / PF6
FP21 / PF5
FP20 / PF4
FP19 / PF3
FP18 / PF2

BKGD / MODC
PC5 / SGA0
PC4 / SGT0
PT4 / PDO / IOC1_4 / KWT4
PT3 / PDOCLK / IOC1_3 / KWT3
PT2 / DBGEEV / IOC1_2 / KWT2
PT1 / RTC_CAL / IOC1_1 / KWT1
PT0 / API_EXTCLK / IOC1_0 / KWT0
VSSX2
VDDX2
PS7 / TXD0 / IRQ

/ KWS7

PS6 / RXD0 / XIRQ

/ KWS6
PS5 / (TXCAN0) / SDA0 / KWS5
PS4 / (RXCAN0) / SCL0 / KWS4
PS3 / SS0

/ KWS3
PS2 / SCK0 / KWS2
PS1 / MOSI0 / KWS1
PS0 / MISO0 / KWS0
BCTLC
BCTL
VSENSE
VSSC
VDDC
NC
VSUP

FP17 / PF1

FP16 / PF0

FP15 / PD7

FP14 / PD6

FP13 / PD5

FP12 / PD4

FP11 / PD3

FP7 / (PWM6) / PA7

FP6 / (PWM4) / PA6

FP5 / (PWM2) / PA5

FP4 / (PWM0) / PA4

FP3 / (SDA0) / PA3

FP2 / (SCL0) / PA2

TEST

PWM1 / PP1

PWM3 / PP3

(RXD1) / PWM5 / PP5

(TXD1) / PWM7 / PP7

VSS1

VDDF

RESET

EXTAL / PE0

XTAL / PE1

VSSX1

VDDX1

PG4 / FP28

PG5 / FP29

PG6 / FP30

PG7 / FP31

PH0 / FP32

PH1 / FP33

PH2 / FP34

PH3 / FP35

PH4 / FP36

VSSX3

VDDX3

PB0 / BP0

PB1 / BP1

PB2 / BP2

PB3 / BP3

VDD

VSS2

PE3 / 32K_XTAL

PE2 / 32K_EXTAL

VSSA / VRL

VDDA / VRH

PAD3 / AN0_3 / KWAD3

PAD2 / AN0_2 / KWAD2

PAD1 / AN0_1 / KWAD1

PAD0 / AN0_0 / KWAD0

100 LQFP

Top view

1

Power

Supply

Internal Pull

Resistor

CTRL

PPSG

PPSG

LQFP

Option

144 100 Pin

1 2 PG2 FP26 — — — — VDDX PERG/

2 3 PG1 FP25 — — — — VDDX PERG/

1. signal with () means that this is an alternative routing option location for this signal.

Figure 1-5. MC9S12ZVH-Family 100-pin LQFP pin out

1st

Func.

Func.

Table 1-7. Pin Summary

Function

2nd

Func.

3rd

4th

Func.

5th

Func.

S12ZVH Family Reference Manual , Rev. 1.05

Freescale Semiconductor 47

Reset

State

Pull

Down

Pull

Down

Chapter 1 Device Overview MC9S12ZVH-Family

Table 1-7. Pin Summary

LQFP

Option

144 100 Pin

1st

Func.

2nd

Func.

Function

3rd

Func.

4th

Func.

5th

Func.

Power

Supply

3 4 PG0 FP24 — — — — VDDX PERG/

Internal Pull

Resistor

CTRL

PPSG

Reset

State

Pull

Down

4 5 VLCD — — — — — VDDX — —

5 6 PF7 FP23 — — — — VDDX PERF/

PPSF

6 7 PT7 IOC1_7 KWT7 — — — V

DDX

PERT/

Pull

Down

Disabled

PPST

7— — — — — — — — — —

8— — — — — — — — — —

9 8 PU0 IOC0_0 M0C0M M0COSM — — VDDM PERU/

Disabled

PPSU

10 9 PU1 — M0C0P M0COSP — — VDDM PERU/

Disabled

PPSU

11 10 PU2 IOC0_1 M0C1M M0SINM — — VDDM PERU/

Disabled

PPSU

12 11 PU3 — M0C1P M0SINP — — VDDM PERU/

Disabled

PPSU

13 12 VDDM1 — — — — — — — —

14 13 VSSM1 — — — — — VDDM — —

15 14 PU4 IOC0_2 M1C0M M1COSM — — VDDM PERU/

Disabled

PPSU

16 15 PU5 — M1C0P M1COSP — — VDDM PERU/

Disabled

PPSU

17 16 PU6 IOC0_3 M1C1M M1SINM — — VDDM PERU/

Disabled

PPSU

18 17 PU7 — M1C1P M1SINP — — VDDM PERU/

Disabled

PPSU

19 — PV0 IOC0_4 M2C0M M2COSM — — VDDM PER V/

Disabled

PPSV

20 — PV1 — M2C0P M2COSP — — VDDM PER V/

Disabled

PPSV

21 — PV2 IOC0_5 M2C1M M2SINM — — VDDM PER V/

Disabled

PPSV

22 — PV3 — M2C1P M2SINP — — VDDM PER V/

Disabled

PPSV

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48 Freescale Semiconductor

Table 1-7. Pin Summary

Chapter 1 Device Overview MC9S12ZVH-Family

LQFP

Option

144 100 Pin

1st

Func.

2nd

Func.

Function

3rd

Func.

4th

Func.

5th

Func.

Power

Supply

Internal Pull

Resistor

CTRL

Reset

State

23 — VDDM2 — — — — — — — —

24 — VSSM2 — — — — — VDDM — —

25 — PV4 IOC0_6 M3C0M M3COSM — — VDDM PER V/

Disabled

PPSV

26 — PV5 — M3C0P M3COSP — — VDDM PER V/

Disabled

PPSV

27 — PV6 IOC0_7 M3C1M M3SINM — — VDDM PER V/

Disabled

PPSV

28 — PV7 — M3C1P M3SINP — — VDDM PER V/

Disabled

PPSV

29 18 — — — — — — — — —

30 19 — — — — — — — — —

31 20 PT6 ECLK IOC1_6 KWT6 — — V

DDX

PERT/

Disabled

PPST

32 21 PF6 FP22 — — — — VDDX PERF/

PPSF

33 22 PF5 FP21 — — — — VDDX PERF/

PPSF

34 23 PF4 FP20 — — — — VDDX PERF/

PPSF

35 24 PF3 FP19 — — — — VDDX PERF/

PPSF

36 25 PF2 FP18 — — — — VDDX PERF/

PPSF

37 26 PF1 FP17 — — — — VDDX PERF/

PPSF

38 27 PF0 FP16 — — — — VDDX PERF/

PPSF

39 28 PD7 FP15 — — — — VDDX PERD/

PPSD

40 29 PD6 FP14 — — — — VDDX PERD/

PPSD

41 30 PD5 FP13 — — — — VDDX PERD/

PPSD

Pull

Down

Pull

Down

Pull

Down

Pull

Down

Pull

Down

Pull

Down

Pull

Down

Pull

Down

Pull

Down

Pull

Down

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Freescale Semiconductor 49

Chapter 1 Device Overview MC9S12ZVH-Family

Table 1-7. Pin Summary

LQFP

Option

144 100 Pin

1st

Func.

2nd

Func.

Function

3rd

Func.

4th

Func.

5th

Func.

Power

Supply

CTRL

42 31 PD4 FP12 — — — — VDDX PERD/

PPSD

43 32 PD3 FP11 — — — — VDDX PERD/

PPSD

44 — PD2 FP10 — — — — VDDX PERD/

PPSD

45 — PD1 FP9 — — — — VDDX PERD/

PPSD

46 — PD0 FP8 — — — — VDDX PERD/

PPSD

47 33 PA7 (PWM6) FP7 — — — VDDX PERA/

PPSA

48 34 PA6 (PWM4) FP6 — — — VDDX PERA/

PPSA

49 35 PA5 (PWM2) FP5 — — — VDDX PERA/

PPSA

Internal Pull

Resistor

Reset

State

Pull

Down

Pull

Down

Pull

Down

Pull

Down

Pull

Down

Pull

Down

Pull

Down

Pull

Down

50 36 PA4 (PWM0) FP4 — — — VDDX PERA/

PPSA

51 37 PA3 (SDA0) FP3 — — — VDDX PERA/

PPSA

52 38 PA2 (SCL0) FP2 — — — VDDX PERA/

PPSA

53 — PA1 FP1 — — — — VDDX PERA/

PPSA

54 — PA0 FP0 — — — — VDDX PERA/

PPSA

Pull

Down

Pull

Down

Pull

Down

Pull

Down

Pull

Down

55 39 TEST — — — — — VDDX — —

56 40 PP1 PWM1 — — — — V

DDX

PERP/

Disabled

PPSP

57 41 PP3 PWM3 — — — — V

DDX

PERP/

Disabled

PPSP

58 42 PP5 PWM5 (RXD1) — — — V

DDX

PERP/

Disabled

PPSP

59 43 PP7 PWM7 (TXD1) — — — V

DDX

PERP/

Disabled

PPSP

60 44 VSS1 — — — — — — — —

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50 Freescale Semiconductor

Table 1-7. Pin Summary

Chapter 1 Device Overview MC9S12ZVH-Family

LQFP

Option

144 100 Pin

1st

Func.

2nd

Func.

Function

3rd

Func.

4th

Func.

5th

Func.

61 45 VDDF — — — — — V

62 — PC0 RXCAN0 — — — — V

Power

Supply

DDF

DDX

Internal Pull

Resistor

CTRL

Reset

State

——

PERC/

Disabled

PPSC

63 — PC1 TXCAN0 — — — — V

DDX

PERC/

Disabled

PPSC

64 — PC2 CPRXD0 — — — — V

DDX

PERC/

Disabled

PPSC

65 — PC3 CPTXD0 — — — — V

DDX

PERC/

Disabled

PPSC

66 46 RESET — — — — — V

67 47 PE0 EXTAL — — — — V

68 48 PE1 XTAL — — — — V

DDX

DDX

DDX

TEST pin Pull Up

PERE/

PPSE

Down

PERE/

PPSE

Down

69 49 VSSX1 — — — — — — — —

Pull

Pull

70 50 VDDX1 — — — — — V

71 — PP6 PWM6 — — — — V

DDX

DDX

——

PERP/

Disabled

PPSP

72 — PT5 IOC1_5 KWT5 — — — V

DDX

PERT/

Disabled

PPST

73 51 VSUP — — — — — V

SUP

——

74 52 — — — — — — — — —

75 53 VDDC — — — — — — — —

76 — — — — — — — — — —

77 — CANH0 — — — — — — — —

78 — — — — — — — — — —

79 54 VSSC — — — — — — — —

80 — — — — — — — — — —

81 — CANL0 — — — — — — — —

82 — — — — — — — — — —

83 — SPLIT0 — — — — — — — —

84 — — — — — — — — — —

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Chapter 1 Device Overview MC9S12ZVH-Family

Table 1-7. Pin Summary

LQFP

Option

144 100 Pin

1st

Func.

2nd

Func.

Function

3rd

Func.

4th

Func.

5th

Func.

Power

Supply

Internal Pull

Resistor

CTRL

Reset

State

85 — — — — — — — — — —

86 55 VSENS

—— — ———— —

E

87 56 BCTL — — — — — — — —

88 57 BCTLC — — — — — — — —

89 58 PS0 MISO0 KWS0 — — — V

DDX

PERS/

Pull Up

PPSS

90 59 PS1 MOSI0 KWS1 — — — V

DDX

PERS/

Pull Up

PPSS

91 60 PS2 SCK0 KWS2 — — — V

DDX

PERS/

Pull Up

PPSS

92 61 PS3 SS

0 KWS3 — — — V

DDX

PERS/

Pull Up

PPSS

93 62 PS4 (RXCAN

0)

SCL0 KWS4 — — V

DDX

PERS/

PPSS

Pull Up

94 63 PS5 (TXCAN

0)

95 64 PS6 RXD0 XIRQ

SDA0 KWS5 — — V

KWS6 — — V

DDX

DDX

PERS/

PPSS

PERS/

Pull Up

Pull Up

PPSS

96 65 PS7 TXD0 IRQ

KWS7 — — V

DDX

PERS/

Pull Up

PPSS

97 66 VDDX2 — — — — — V

DDX

——

98 67 VSSX2 — — — — — — — —

99 68 PT0 API_EXT

CLK

100 69 PT1 RTC_CALIOC1_1 KWT1 — — V

IOC1_0 KWT0 — — V

DDX

DDX

PERT/

PPST

PERT/

Disabled

Disabled

PPST

101 70 PT2 DBGEEV IOC1_2 KWT2 — — V

DDX

PERT/

Disabled

PPST

102 71 PT3 PDOCLK IOC1_3 KWT3 — — V

DDX

PERT/

Disabled

PPST

103 72 PT4 PDO IOC1_4 KWT2 — — V

DDX

PERT/

Disabled

PPST

104 73 PC4 SGT0 — — — — V

DDX

PERC/

Disabled

PPSC

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52 Freescale Semiconductor

Table 1-7. Pin Summary

Chapter 1 Device Overview MC9S12ZVH-Family

LQFP

Option

144 100 Pin

1st

Func.

2nd

Func.

Function

3rd

Func.

4th

Func.

5th

Func.

Power

Supply

105 74 PC5 SGA0 — — — — V

DDX

Internal Pull

Resistor

CTRL

PERC/

Reset

State

Disabled

PPSC

106 — PC6 RXD1 — — — — V

DDX

PERC/

Disabled

PPSC

107 — PC7 TXD1 — — — — V

DDX

PERC/

Disabled

PPSC

108 75 BKGD MODC — — — — VDDA Pull Up

109 76 PAD0 AN0_0 KWAD0 — — — V

DDA

PER1AD/

Disabled

PPS1AD

110 77 PAD1 AN0_1 KWAD1 — — — V

DDA

PER1AD/

Disabled

PPS1AD

111 78 PAD2 AN0_2 KWAD2 — — — V

DDA

PER1AD/

Disabled

PPS1AD

112 79 PAD3 AN0_3 KWAD3 — — — V

DDA

PER1AD/

Disabled

PPS1AD

113 — PAD4 AN0_4 KWAD4 — — — V

DDA

PER1AD/

Disabled

PPS1AD

114 — PAD5 AN0_5 KWAD5 — — — V

DDA

PER1AD/

Disabled

PPS1AD

115 — PAD6 AN0_6 KWAD6 — — — V

DDA

PER1AD/

Disabled

PPS1AD

116 — PAD7 AN0_7 KWAD7 — — — V

DDA

PER1AD/

Disabled

PPS1AD

117 80 VDDA — — — — — V

DDA

——

118 81 VSSA — — — — — — — —

119 82 PE2 32K_EX

TAL

120 83 PE3 32K_XT

AL

————V

————V

DDX

DDX

PERE/

PPSE

PERE/

PPSE

Pull

Down

Pull

Down

121 84 VSS2 — — — — — — — —

122 85 VDD — — — — — V

123 — PP0 PWM0 — — — — V

DD

DDX

——

PERP/

Disabled

PPSP

124 — PP2 PWM2 — — — — V

DDX

PERP/

Disabled

PPSP

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Chapter 1 Device Overview MC9S12ZVH-Family

Table 1-7. Pin Summary

LQFP

Option

144 100 Pin

1st

Func.

2nd

Func.

Function

3rd

Func.

4th

Func.

5th

Func.

Power

Supply

125 — PP4 PWM4 — — — — V

DDX

Internal Pull

Resistor

CTRL

PERP/

Reset

State

Disabled

PPSP

126 86 PB3 BP3 — — — — V

127 87 PB2 BP2 — — — — V

128 88 PB1 BP1 — — — — V

129 89 PB0 BP0 — — — — V

130 90 VDDX3 — — — — — V

DDX

DDX

DDX

DDX

DDX

PERB/

PPSB

PERB/

PPSB

PERB/

PPSB

PERB/

PPSB

Pull

Down

Pull

Down

Pull

Down

Pull

Down

——

131 91 VSSX3 — — — — — — — —

132 — PH7 FP39 — — — — VDDX PERH/

PPSH

133 — PH6 FP38 — — — — VDDX PERH/

PPSH

Pull

Down

Pull

Down

134 — PH5 FP37 — — — — VDDX PERH/

PPSH

135 92 PH4 FP36 — — — — VDDX PERH/

PPSH

136 93 PH3 FP35 — — — — VDDX PERH/

PPSH

137 94 PH2 FP34 — — — — VDDX PERH/

PPSH

138 95 PH1 FP33 — — — — VDDX PERH/

PPSH

139 96 PH0 FP32 — — — — VDDX PERH/

PPSH

140 97 PG7 FP31 — — — — VDDX PERG/

PPSG

141 98 PG6 FP30 — — — — VDDX PERG/

PPSG

142 99 PG5 FP29 — — — — VDDX PERG/

PPSG

143 100 PG4 FP28 — — — — VDDX PERG/

PPSG

Pull

Down

Pull

Down

Pull

Down

Pull

Down

Pull

Down

Pull

Down

Pull

Down

Pull

Down

Pull

Down

Pull

Down

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54 Freescale Semiconductor

Table 1-7. Pin Summary

Chapter 1 Device Overview MC9S12ZVH-Family

LQFP

Option

144 100 Pin

144 1 PG3 FP27 — — — — VDDX PERG/

1st

Func.

2nd

Func.

Function

3rd

Func.

4th

Func.

5th

Func.

Power

Supply

Internal Pull

Resistor

CTRL

PPSG

Reset

State

Pull

Down

1.10 Modes of Operation

The MCU can operate in different modes. These are described in 1.10.1 Chip Configuration Modes. The MCU can operate in different power modes to facilitate power saving when full system performance

is not required. These are described in 1.10.3 Low Power Modes.
Some modules feature a software programmable option to freeze the module status whilst the background

debug module is active to facilitate debugging. This is referred to as freeze mode at module level.

1.10.1 Chip Configuration Modes

The different modes and the security state of the MCU affect the debug features (enabled or disabled).
The operating mode out of reset is determined by the state of the MODC signal during reset (Table 1-8).

The MODC bit in the MODE register shows the current operating mode and provides limited mode
switching during operation. The state of the MODC signal is latched into this bit on the rising edge of
RESET

Table 1-8. Chip Modes

Chip Modes MODC

Normal single chip 1

Special single chip 0

1.10.1.1 Normal Single-Chip Mode

This mode is intended for normal device operation. The opcode from the on-chip memory is being
executed after reset (requires the reset vector to be programmed correctly). The processor program is
executed from internal memory.

1.10.1.2 Special Single-Chip Mode

This mode is used for debugging operation, boot-strapping, or security related operations. The background
debug mode BDM is active on leaving reset in this mode.

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Chapter 1 Device Overview MC9S12ZVH-Family

1.10.2 Debugging Modes

The background debug mode (BDM) can be activated by the BDC module or directly when resetting into
Special Single-Chip mode. Detailed information can be found in the BDC module section.
Writing to internal memory locations using the debugger, whilst code is running or at a breakpoint, can
change the flow of application code.
The MC9S12ZVH-Family supports BDC communication throughout the device Stop mode. During Stop
mode, writes to control registers can alter the operation and lead to unexpected results. It is thus
recommended not to reconfigure the peripherals during STOP using the debugger.

1.10.3 Low Power Modes

The device has two dynamic-power modes (run and wait) and two static low-power modes stop and pseudo
stop). For a detailed description refer to Chapter 7, “S12 Clock, Reset and Power Management Unit

(S12CPMU_UHV_V6)“ .

• Dynamic power mode: Run
— Run mode is the main full performance operating mode with the entire device clocked. The user

can configure the device operating speed through selection of the clock source and the phase
locked loop (PLL) frequency. To save power, unused peripherals must not be enabled.

• Dynamic power mode: Wait
— This mode is entered when the CPU executes the WAI instruction. In this mode the CPU does

not execute instructions. The internal CPU clock is switched off. All peripherals can be active
in system wait mode. For further power consumption reduction, the peripherals can
individually turn off their local clocks. Asserting RESET, XIRQ, IRQ, or any other interrupt
that is not masked ends system wait mode.

• Static power mode Pseudo-stop:
— In this mode the system clocks are stopped but the oscillator is still running and the real time

interrupt (RTI), watchdog (COP), RTC, LCD and Autonomous Periodic Interrupt (API) may
be enabled. Other peripherals are turned off. This mode consumes more current than system
STOP mode but, as the oscillator continues to run, the full speed wake up time from this mode
is significantly shorter.

• Static power mode: Stop
— The oscillator is stopped in this mode. By default, all clocks are switched off and all counters

and dividers remain frozen. The Autonomous Periodic Interrupt (API), Key Wake-Up, RTC,
CAN and the CAN physical layer transceiver modules may be enabled to wake the device.

— If the BDC is enabled in Stop mode, the VREG remains in full performance mode and the

CPMU continues operation as in run mode. With BDC enabled and BDCCIS bit set, then all
clocks remain active to allow BDC access to internal peripherals. If the BDC is enabled and
BDCCIS is clear, then the BDCSI clock remains active, but bus and core clocks are disabled.

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With the BDC enabled during S top, the VREG fu ll performance mode and clock activity lead
to higher current consumption than with BDC disabled

— If the BDC is enabled in Stop mode, then the voltage monitoring remains enabled.

1.11 Security

The MCU security mechanism prevents unauthorized access to the flash memory. It must be emphasized
that part of the security must lie with the application code. An extreme example would be application code
that dumps the contents of the internal memory. This would defeat the purpose of security. Also, if an
application has the capability of downloading code through a serial port and then executing that code (e.g.
an application containing bootloader code), then this capability could potentially be used to read the
EEPROM and Flash memory contents even when the microcontroller is in the secure state. In this
example, the security of the application could be enhanced by requiring a response authentication before
any code can be downloaded.

Device security details are also described in the 21.5 Security.

1.11.1 Features

The security features of the S12Z chip family are:

• Prevent external access of the non-volatile memories (Flash, EEPROM) content

• Restrict execution of NVM commands

• Prevent BDC access of internal resources

1.11.2 Securing the Microcontroller

The chip can be secured by programming the security bits located in the options/security byte in the Flash
memory array. These non-volatile bits keep the device secured through reset and power-down.

This byte can be erased and programmed like any other Flash location. Two bits of this byte are used for
security (SEC[1:0]). The contents of this byte are copied into the Flash security register (FSEC) during a
reset sequence.

The meaning of the security bits SEC[1:0] is shown in Table 1-9. For security reasons, the state of device
security is controlled by two bits. To put the device in unsecured mode, these bits must be programmed to
SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put
the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’.

Table 1-9. Security Bits

SEC[1:0] Security State

00 1 (secured)

01 1 (secured)

10 0 (unsecured)

11 1 (secured)

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Chapter 1 Device Overview MC9S12ZVH-Family

NOTE

Please refer to the 21.5 Security for more security byte details.

1.11.3 Operation of the Secured Microcontroller

By securing the device, unauthorized access to the EEPROM and Flash memory contents is prevented.
Secured operation has the following effects on the microcontroller:

1.11.3.1 Normal Single Chip Mode (NS)

• Background Debug Controller (BDC) operation is completely disabled.

• Execution of Flash and EEPROM commands is restricted (described in flash block description).

1.11.3.2 Special Single Chip Mode (SS)

• Background Debug Controller (BDC) commands are restricted

• Execution of Flash and EEPROM commands is restricted (described in flash block description).

In special single chip mode the device is in active BDM after reset. In special single chip mode on a secure
device, only the BDC mass erase and BDC control and status register commands are possible. BDC access
to memory mapped resources is disabled. The BDC can only be used to erase the EEPROM and Flash
memory without giving access to their contents.

1.11.4 Unsecuring the Microcontroller

Unsecuring the microcontroller can be done using three different methods:

1. Backdoor key access

2. Reprogramming the security bits

3. Complete memory erase

1.11.4.1 Unsecuring the MCU Using the Backdoor Key Access

In normal single chip mode, security can be temporarily disabled using the backdoor key access method.
This method requires that:

• The backdoor key has been programmed to a valid value.

• The KEYEN[1:0] bits within the Flash options/security byte select ‘enabled’.

• The application program programmed into the microcontroller has the capability to write to the
backdoor key locations.

The backdoor key values themselves would not normally be stored within the application data, which
means the application program would have to be designed to receive the backdoor key values from an
external source (e.g. through a serial port).

The backdoor key access method allows debugging of a secured microcontroller without having to erase
the Flash. This is particularly useful for failure analysis.

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Chapter 1 Device Overview MC9S12ZVH-Family

NOTE

No word backdoor key word is allowed to have the value 0x0000 or
0xFFFF.

1.11.5 Reprogramming the Security Bits

In normal single chip mode, security can also be disabled by erasing and reprogramming the security bits
within Flash options/security byte to the unsecured value. Because the erase operation will erase the entire
sector from (0xFF_FE00–0xFF_FFFF), the backdoor key and the interrupt vectors will also be erased; this
method is not recommended for normal single chip mode. The application software can only erase and
program the Flash options/security byte if the Flash sector containing the Flash options/security byte is not
protected (see Flash protection). Thus Flash protection is a useful means of preventing this method. The
microcontroller will enter the unsecured state after the next reset following the programming of the
security bits to the unsecured value.

This method requires that:

• The application software previously programmed into the microcontroller has been designed to
have the capability to erase and program the Flash options/security byte.

• The Flash sector containing the Flash options/security byte is not protected.

1.11 .6 Complete Memory Erase

The microcontroller can be unsecured by erasing the entire EEPROM and Flash memory contents. If
ERASE_FLASH is successfully completed, then the Flash unsecures the device and programs the security
byte automatically.

1.12 Resets and Interrupts

1.12.1 Resets

Table 1-10. lists all reset sources and the vector locations. Resets are explained in detail in the Chapter 7,

“S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V6)“.

Table 1-10. Reset Sources and Vector Locations

Vector Address Reset Source

0xFFFFFC Power-On Reset (POR) None None

Low Voltage Reset (LVR) None None

External pin RESET

Clock monitor reset None CPMUOSC[OSCE]

CCR

Mask

None None

Local Enable

COP watchdog reset None CR[2:0] in CPMUCOP register

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Chapter 1 Device Overview MC9S12ZVH-Family

1.12.2 Interrupt Vectors

Table 1-11 lists all interrupt sources and vectors in the default order of priority. The interrupt module

description provides an Interrupt Vector Base register (IVBR) to relocate the vectors.

Table 1-11. Interrupt Vector Locations (Sheet 1 of 3)

Vector Address

Vector base + 0x1F8 Unimplemented page1 op-code trap

Vector base + 0x1F4 Unimplemented page2 op-code trap

Vector base + 0x1F0 Software interrupt instruction (SWI) None None - -

Vector base + 0x1EC System call interrupt instruction

Vector base + 0x1E8 Machine exception None None - -

Vector base + 0x1E4

Vector base + 0x1E0

Vector base + 0x1DC Spurious interrupt — None - -

Vector base + 0x1D8 XIRQ interrupt request X bit None Yes Yes

Vector base + 0x1D4 IRQ

Vector base + 0x1D0 RTI time-out interrupt I bit CPMUINT (RTIE)

Vector base + 0x1CC TIM0 timer channel 0 I bit TIM0TIE (C0I) No Yes

Vector base + 0x1C8 TIM0 timer channel 1 I bit TIM0TIE (C1I) No Yes

(1)

Interrupt Source

(SPARE)

(TRAP)

(SYS)

interrupt request I bit IRQCR(IRQEN) Yes Yes

CCR

Mask

None None - -

None None - -

None None - -

Reserved

Reserved

Local Enable

Wake up

from STOP

See CPMU

section

Wak e up

from WAIT

Yes

Vector base + 0x1C4 TIM0 timer channel 2 I bit TIM0TIE (C2I) No Yes

Vector base + 0x1C0 TIM0 timer channel 3 I bit TIM0TIE (C3I) No Yes

Vector base + 0x1BC TIM0 timer channel 4 I bit TIM0TIE (C4I) No Yes

Vector base + 0x1B8 TIM0 timer channel 5 I bit TIM0TIE (C5I) No Yes

Vector base + 0x1B4 TIM0 timer channel 6 I bit TIM0TIE (C6I) No Yes

Vector base + 0x1B0 TIM0 timer channel 7 I bit TIM0TIE (C7I) No Yes

Vector base + 0x1AC TIM0 timer overflow I bit TIM0TSCR2(TOI) No Yes

Vector base + 0x1A8 TIM0 Pulse accumulator A overflow I bit TIM0PACTL(PAOVI) No Yes

Vector base + 0x1A4 TIM0 Pulse accumulator input edge I bit TIM0PACTL(PAI) No Yes

Vector base + 0x1A0 SPI0 I bit SPI0CR1 (SPIE, SPTIE) No Yes

Vector base + 0x19C SCI0 I bit SCI0CR2 Yes Yes

Vector base + 0x198 SCI1 I bit SCI1CR2 Yes Yes

Vector base + 0x194

Vector base + 0x190

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Chapter 1 Device Overview MC9S12ZVH-Family

Table 1-11. Interrupt Vector Locations (Sheet 2 of 3)

Vector Address

(1)

Interrupt Source

CCR

Mask

Local Enable

Vector base + 0x18C ADC0 Error I bit ADC0EIE(IA_EIE,CMD_EIE,

Wake up

from STOP

No Yes

Wak e up

from WAIT

EOL_EIE,TRIG_EIE,RSTAR_

EIE,LDOK_EIE)

ADC0IE(CONIF_OIE)

Vector base + 0x188 ADC0 conversion sequence abort I bit ADC0IE(SEQAR_IE) No Yes

Vector base + 0x184 ADC0 conversion complete I bit ADC0CONIE[15:0] No Yes

Vector base + 0x180

Oscillator status interrupt I bit CPMUINT (OSCIE) No Yes

Vector base + 0x17C PLL lock interrupt I bit CPMUINT (LOCKIE) No Yes

Vector base + 0x178

to

Reserved

Vector base + 0x174

Vector base + 0x170 RAM error I bit ECCIE (SBEEIE) No Yes

Vector base + 0x16C

to

Reserved

Vector base + 0x168

Vector base + 0x164 FLASH error I bit FERCNFG (SFDIE) No Yes

Vector base + 0x160 FLASH command I bit FCNFG (CCIE) No Yes

Vector base + 0x15C CAN0 wake-up I bit CAN0RIER (WUPIE) Yes Yes

Vector base + 0x158 CAN0 errors I bit CAN0RIER (CSCIE, OVRIE) No Yes

Vector base + 0x154 CAN0 receive I bit CAN0RIER (RXFIE) No Yes

Vector base + 0x150 CAN0 transmit I bit CAN0RIER (TXEIE[2:0]) No Yes

Vector base + 0x14C

to

Reserved

Vector base + 0x144

Vector base + 0x140 BATS supply voltage monitor interrupt I bit BATIE (BVHIE,BVLIE) No Yes

Vector base + 0x13C

to

Reserved

Vector base + 0x130

Vector base + 0x12C Port T interrupt I bit PIET(PIET[7:0]) Yes Yes

Vector base + 0x128 CANPHY0 Interrupt (CP0I) I bit CP0IE(CPVFIE, CPOCIE) No Yes

Vector base + 0x124 Port S interrupt I bit PIES(PIES[7:0]) Yes Yes

Vector base + 0x120

to

Reserved

Vector base + 0x108

Vector base + 0x104 Low-voltage interrupt (LVI) I bit CPMUCTRL (LVIE) No Yes

Vector base + 0x100 Autonomous periodical interrupt

(API)

I bit

CPMUAPICTRL (APIE)

Yes Ye s

Vector base + 0xFC High temperature interrupt I bit CPMUHTCTL(HTIE) No Yes

Vector base + 0xF8

Reserved

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Chapter 1 Device Overview MC9S12ZVH-Family

Table 1-11. Interrupt Vector Locations (Sheet 3 of 3)

Vector Address

Vector base + 0xF4 Port AD interrupt I bit PIEADL(PIEADL[7:0]) Yes Yes

Vector base + 0xF0

to

Vector base + 0xB8

Vector base + 0xB4 IIC I bit IIC0IBCR(IBIE) No Yes

Vector base + 0xB0 Reserved

Vector base + 0xAC TIM1 timer channel 0 I bit TIM1TIE (C0I) No Yes

Vector base + 0xA8 TIM1 timer channel 1 I bit TIM1TIE (C1I) No Yes

Vector base + 0xA4 TIM1 timer channel 2 I bit TIM1TIE (C2I) No Yes

Vector base + 0xA0 TIM1 timer channel 3 I bit TIM1TIE (C3I) No Yes

Vector base + 0x9C TIM1 timer channel 4 I bit TIM1TIE (C4I) No Yes

Vector base + 0x98 TIM1 timer channel 5 I bit TIM1TIE (C5I) No Yes

Vector base + 0x94 TIM1 timer channel 6 I bit TIM1TIE (C6I) No Yes

Vector base + 0x90 TIM1 timer channel 7 I bit TIM1TIE (C7I) No Yes

Vector base + 0x8C TIM1 timer overflow I bit TIM1TSCR2(TOI) No Yes

Vector base + 0x88 TIM1 Pulse accumulator A overflow I bit TIM1PACTL(PAOVI) No Yes

Vector base + 0x84 TIM1 Pulse accumulator input edge I bit TIM1PACTL(PAI) No Yes

(1)

Interrupt Source

CCR

Mask

Local Enable

Reserved

Wake up

from STOP

Wak e up

from WAIT

Vector base + 0x80

to

Vector base + 0x7C

Vector base + 0x78 Motor Control Timer Overflow I bit MCCTL1(MCOCIE) No Yes

Vector base + 0x74 SSD0 I bit MDC0CTL(MCZIE,AOVIE) No Yes

Vector base + 0x70 SSD1 I bit MDC1CTL(MCZIE,AOVIE) No Yes

Vector base + 0x6C SSD2 I bit MDC2CTL(MCZIE,AOVIE) No Yes

Vector base + 0x68 SSD3 I bit MDC3CTL(MCZIE,AOVIE) No Yes

Vector base + 0x64 RTC I bit RTCCTL4(HRIE,MINIE,SECI

Vector base + 0x60 SSG0 Ready For Next Data(RNDI) I bit SSG0IE(RNDIE) No Yes

Vector base + 0x5C

to

Vector base + 0x10

1. 15 bits vector address based

Reserved

Yes Ye s

E,COMPIE,TB0IE)

Reserved

1.12.3 Effects of Reset

When a reset occurs, MCU registers and control bits are initialized. For RTC block, some registers are
power on reset only. Refer to the respective block sections for register reset states.

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On each reset, the Flash module executes a reset sequence to load Flash configuration registers

1.12.3.1 Flash Configuration Reset Sequence Phase

On each reset, the Flash module will hold CPU activity while loading Flash module registers from the
Flash memory. If double faults are detected in the reset phase, Flash module protection and security may
be active on leaving reset. This is explained in more detail in 21.6 Initialization.

1.12.3.2 Reset While Flash Command Active

If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.

1.12.3.3 I/O Pins

Refer to Chapter 2, “Port Integration Module (S12ZVHPIMV0)“ for reset configurations of all peripheral
module ports.

1.12.3.4 RAM

The system RAM arrays, including their ECC syndromes, are initialized following a power on reset, but
not out of warm reset. All other RAM arrays are not initialized out of any type of reset.

With the exception of resets resulting from low voltage conditions, the RAM content is unaltered by a reset
occurrence.

1.13 COP Configuration

The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register are loaded from the
Flash configuration field byte at global address 0xFF_FE0E during the reset sequence. See Table 1-12 and

Table 1-13 for coding

Table 1-12. Initial COP Rate Configuration

NV[2:0] in

FOPT Register

000 111

001 110

010 101

011 100

100 011

101 010

110 001

111 000

CR[2:0] in

COPCTL Register

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Chapter 1 Device Overview MC9S12ZVH-Family

Table 1-13. Initial WCOP Configuration

NV[3] in

FOPT Register

10

01

WCOP in

COPCTL Register

1.14 ADC0 Internal Channels

Table 1-14 lists the internal sources which are connected to these special conversion channels.

Table 1-14. ADC0 Channel Assignment

ADC0CMD_1 CH_SEL[5:0]

[5][4][3][2][1][0]

0 0 1 0 0 0 Internal_0 ADC temperature sensor

0 0 1 0 0 1 Internal_1 Bandgap Voltage V

0 0 1 0 1 0 Internal_2 RESERVED

0 0 1 0 1 1 Internal_3 RESERVED

0 0 1 1 0 0 Internal_4 V

0 0 1 1 0 1 Internal_5 RESERVED

0 0 1 1 1 0 Internal_6 RESERVED

0 0 1 1 1 1 Internal_7 RESERVED

Analog Input

Channel

Usage

or

or V

SUP

BG

Vreg temperature sensor

V

HT(see Chapter 7, “S12

Clock, Reset and Power

Management Unit

(S12CPMU_UHV_V6)“ on how

to config)

SENSE

selectable in BATS

module

1.15 The ADC0 VRH/VRL

The ADC0 offers two possible sources for both reference voltages VRH[1:0] and VRL[1:0]. On the
MC9S12ZVH-Family only VRH[1], VRL[1] sources are connected at device level(to VDDA, VSSA
respectively), the VRH[0], VRL[0] sources are not connected. Thus the application must set both
VRH_SEL and VRL_SEL in the 10.4.2.16 ADC Command Register 1 (ADCCMD_1) to 1.

1.16 The ADC0 Conversion Resolution

The MC9S12ZVH-Family only support 10 and 8 bit conversion resolution, although ADC block guide still
has 12 bit related descrition.

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V

RH

StoredReference

ConvertedReference

------------------------------------------------------ -5V=

Result ConvertedADInput

StoredReference 5V

ConvertedReference 2n

------------------------------------------------------------------=

1.17 ADC Result Reference

MCUs of the MC9S12ZVH-Family are able to measure the internal reference voltage VBG(see Table 1-

14). VBG is a constant voltage with a narrow distribution over temperature and external voltage supply (see
Table I-1).

A 10-bit right justified ADC conversion result of VBG is provided at address 0x1F_C040/0x1F_C041 in
the NVM’s IFR for reference.The measurement conditions of the reference conversion are listed in

Section A.1.9, “ADC Conversion Result Reference“”. By measuring the voltage VBG (see Table 1-14) and

comparing the result to the reference value in the IFR, it is possible to determine the ADC’s reference
voltage VRH in the application environment:

The exact absolute value of an analog conversion can be determined as follows:

With:

ConvertedADInput: Result of the analog to digital conversion of the desired pin
ConvertedReference: Result of channel “Internal_1” conversion
StoredReference: Value in IFR location 0x1F_C040/0x1F_C041
n: ADC resolution (10 bit)

1.18 BDC Clock Source Connectivity

The BDC clock, BDCCLK, is mapped to the IRCCLK generated in CPMU module. On 0N65E device, the
BDCFCLK is mapped to the Core clock. On 1N65E device, the BDCFCLK is mapped to the bus clock.

1.19 FTMRZ Connectivity

The soc_erase_all_req input to the flash module is driven directly by a BDC erase flash request resulting
from the BDC ERASE_FLASH command.

The FTMRZ FCLKDIV register is forced to 0x05 by the BDC ERASE_FLASH command. This
configures the clock frequency correctly for the initial bus frequency on leaving reset. The bus frequency
must not be changed before launching the ERASE_FLASH command.

1.20 RTC Clock Source

The RTC has three clock source, the 32K OSC, main OSC, refer to 18.4.2 RTC Control Register 2

(RTCCTL2) for more information. On 1N65E device, it also has IRC clock source. When select main

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Chapter 1 Device Overview MC9S12ZVH-Family

OSC, user need to config the registers in CPMU block, refer to Chapter 7, “S12 Clock, Reset and Power

Management Unit (S12CPMU_UHV_V6)“ for more detailed information. And main OSC will be stop if

silicon enter full stop mode. On 1N65E device, if the clock source is from IRC, it will be stop if silicon
enter stop mode.

1.21 LCD Clock Source Connectivity

The LCD’s clock is connected to the RTC’s RTCCLK output.User need to set the RTCCTL2[RTCPS] to
get the expect RTCCLK frequency if it uses the main OSC as clock source. Refer to 18.4.2 RTC Control

Register 2 (RTCCTL2) for more information.

1.22 32K OSC enable control

The 32K OSC enable is controlled by the RTCCTL2[CLKSRC] in 18.4.2 RTC Control Register 2

(RTCCTL2). Setting it to 1 enable the 32K OSC. Setting it to 1 also selects the 32K OSC as the LCD and

RTC clock source. RTCCTL2 is write one time only in NSC mode, once enable the 32K OSC, it will be
not able to switch off.

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Chapter 2 Port Integration Module (S12ZVHPIMV0)

Revision History

Rev. No.

(Item No.)

V00.01 18 Mar 2011 • Initial Version

V00.09 18 Mar 2012 • update the MODRR0 related description

V00.10 12 Oct 2012 • fix typos, add XIRQ function explain

Date (Submitted

By)

Sections

Affected

Substantial Change(s)

2.1 Introduction

2.1.1 Overview

The S12ZVH-family port integration module establishes the interface between the peripheral modules and
the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and
multiplexing on shared pins.

This document covers:

• 8-pin port A associated with the LCD FP[7:0] and rerouting of PWM0, PWM2, PWM4, PWM6
channels and rerouting of IIC

• 4-pin port B associated with the LCD BP[3:0]

• 8-pin port C associated with MSCAN0, SCI1, SSG0 and CANPHY0’s CPTXD0&CPRXD0

• 8-pin port D associated with LCD FP[15:8]

• 4-pin port E associated with the external 4-20MHZ oscillator and 32.768KHZ oscillator

• 8-pin port F associated with LCD FP[23:16]

• 8-pin port G associated with LCD FP[31:24]

• 8-pin port H associated with LCD FP[39:32]

• 8-pin port P associated with 8 PWM channels; associated with the rerouting SCI1 function also.

• 8-pin port S associated with SCI0, IIC0, SPI0 modules and rerouting of MSCAN0. PS7 and PS6
also associated with IRQ, XIRQ interrupt inputs; associated with the key wakeup functions also

• 8-pin port T with the key wakeup function and 8 TIM1 channels, also associated with
— API_EXTCLK

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— DBG external signals PDO, PDOCLK and DBGEEV
— ECLK output

• 8-pin port AD associated with 8 ADC0 channels; associated with the key wakeup function also

• 8-pin port U associated with SSD0, SSD1, 2 Motor controls and 4 TIM0 channels

• 8-pin port V associated with SSD2, SSD3 , 2 Motor controls and 4 TIM0 channels

Most I/O pins can be configured by register bits to select data direction and to enable and select pullup or
pulldown devices.

NOTE

This document assumes the availability of all features (144-pin package
option). Some functions are not available on lower pin count package
options. Refer to the pin-out summary in the SOC Guide.

2.1.2 Features

The PIM includes these distinctive registers:

• Data registers and data direction registers for ports A, B, C, D, E, F, G, H, T, S, P, AD, U and V
when used as general-purpose I/O

• Control registers to enable pull devices and select pullups/pulldowns on ports A, B, C, D, E, F, G,
H, T, S, P, AD, U and V

• Single control register bit to enable pullups on BKGD pin

• Control register to enable open-drain (wired-or) mode on port S and port A (only PA3, PA2)

• Control register to enable digital input buffers on port AD

• Control register to enable the slew rate control on Port U and V

• Interrupt flag register for pin interrupts on port S, T and AD

• Control register to configure IRQ pin operation

• Control register to enable ECLK output

• Control register to enable the RTC_CAL input or output

• Routing registers to support signal relocation on external pins and control internal routings:
— IIC0 to alternative pins
— SCI1 to alternative pins
— Various CAN0-CANPHY0 routing options supporting standalone use and conformance testing
— MSCAN0 to alternative pins
— PWM0, PWM2, PWM4, PWM6 to alternative pins
— rerouting the RTC_CAL to TIM1 channel
— rerouting the RXD0 and RXD1 to TIM1 channel for the baud rate detection

A standard port pin has the following minimum features:

• Input/output selection

• 5V output drive

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• 5V digital and analog input

• Input with selectable pullup or pulldown device

Optional features supported on dedicated pins:

• Open drain for wired-or connections

• Interrupt input with glitch filtering

• Slew rate control on motor pads

2.2 External Signal Description

This section lists and describes the signals that do connect off-chip.

Table 2-1 shows all pins with the pins and functions that are controlled by the PIM. Routing options are

denoted in parenthesis.

NOTE

If there is more than one function associated with a pin, the output priority
is indicated by the position in the table from top (highest priority) to bottom
(lowest priority).

Port Pin Name

- BKGD MODC

Pin Function

& Priority

Table 2-1. Pin Functions and Priorities

I/O Description Routing Register

(1)

(2)

BKGD I/O S12ZBDC communication

I MODC input during RESET BKGD

Pin

Function

after Reset

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Chapter 2 Port Integration Module (S12ZVHPIMV0)

Port Pin Name

Pin Function

& Priority

I/O Description Routing Register

(1)

Function

after Reset

A PA7 FP7 O LCD FP7 signal GPIO

(PWM6) O PWM channel 6 PWM6RR

PTA[7] I/O General-purpose

PA6 FP6 O LCD FP6 signal

(PWM4) O PWM channel 4 PWM4RR

PTA[6] I/O General-purpose

PA5 FP5 O LCD FP5 signal

(PWM2) O PWM channel 2 PWM2RR

PTA[5] I/O General-purpose

PA4 FP4 O LCD FP4 signal

(PWM0) O PWM channel 0 PWM6RR

PTA[4] I/O General-purpose

PA3 FP3 O LCD FP3 signal

(SDA0) I/O SDA of IIC0 signal IIC0RR

PTA[3] I/O General-purpose

PA2 FP2 O LCD FP2 signal

(SCL0) I/O SCL of IIC0 signal IIC0RR

PTA[2] I/O General-purpose

PA1 FP1 O LCD FP1 signal

PTA[1] I/O General-purpose

PA0 FP0 O LCD FP0 signal

PTA[0] I/O General-purpose

B PB3 BP3 O LCD BP3 signals GPIO

PTB[3] I/O General-purpose

PB2 BP2 O LCD BP2 signal

PTB[2] I/O General-purpose

PB1 BP1 O LCD BP1 signal

PTB[1] I/O General-purpose

PB0 BP0 O LCD BP0 signal

PTB[0] I/O General-purpose

Pin

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Chapter 2 Port Integration Module (S12ZVHPIMV0)

Port Pin Name

Pin Function

& Priority

I/O Description Routing Register

(1)

Function

after Reset

C PC7 TXD1 O TXD of SCI1 GPIO

PTC[7] I/O General-purpose

PC6 RXD1 I RXD of SCI1

PTC[6] I/O General-purpose

PC5 SGA0 O SGA of SSG0

PTC[5] I/O General-purpose

PC4 SGT0 O SGT of SSG0

PTC[4] I/O General-purpose

PC3 CPTXD0 I TXD of CANPHY0 C0CP0RR3-0

PTC[3] I/O General-purpose

PC2 CPRXD0 O RXD of CANPHY0 C0CP0RR3-0

PTC[2] I/O General-purpose

PC1 TXCAN0 O TX of MSCAN0 C0CP0RR3-0

PTC[1] I/O General-purpose

PC0 RXCAN0 I RX of MSCAN0 C0CP0RR3-0

PTC[0] I/O General-purpose

D PD7 FP15 O LCD FP15 signal GPIO

PTD[7] I/O General-purpose

PD6 FP14 O LCD FP14 signal

PTD[6] I/O General-purpose

PD5 FP13 O LCD FP13 signal

PTD[5] I/O General-purpose

PD4 FP12 O LCD FP12 signal

PTD[4] I/O General-purpose

PD3 FP11 O LCD FP11 signal

PTD[3] I/O General-purpose

PD2 FP10 O LCD FP10 signal

PTD[2] I/O General-purpose

PD1 FP9 O LCD FP9 signal

PTD[1] I/O General-purpose

PD0 FP8 O LCD FP8 signal

PTD[0] I/O General-purpose

Pin

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Chapter 2 Port Integration Module (S12ZVHPIMV0)

Port Pin Name

Pin Function

& Priority

I/O Description Routing Register

(1)

Function

after Reset

PE3 32K_XTAL - 32K OSC signal

PTE[3] I/O General-purpose

PE2 32K_EXTAL - 32K OSC signal

E

PE1 XTAL - CPMU OSC signal

PTE[2] I/O General-purpose

GPIO

PTE[1] I/O General-purpose

PE0 EXTAL - CPMU OSC signal

PTE[0] I/O General-purpose

F PF7 FP23 O LCD FP23 signal GPIO

PTF[7] I/O General-purpose

PF6 FP22 O LCD FP22 signal

PTF[6] I/O General-purpose

PF5 FP21 O LCD FP21 signal

PTF[5] I/O General-purpose

PF4 FP20 O LCD FP20 signal

PTF[4] I/O General-purpose

PF3 FP19 O LCD FP19 signal

PTF[3] I/O General-purpose

PF2 FP18 O LCD FP18 signal

PTF[2] I/O General-purpose

PF1 FP17 O LCD FP17 signal

PTF[1] I/O General-purpose

PF0 FP16 O LCD FP16 signal

PTF[0] I/O General-purpose

Pin

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Chapter 2 Port Integration Module (S12ZVHPIMV0)

Port Pin Name

Pin Function

& Priority

I/O Description Routing Register

(1)

Function

after Reset

G PG7 FP31 O LCD FP31 signal GPIO

PTG[7] I/O General-purpose

PG6 FP30 O LCD FP30 signal

PTG[6] I/O General-purpose

PG5 FP29 O LCD FP29 signal

PTG[5] I/O General-purpose

PG4 FP28 O LCD FP28 signal

PTG[4] I/O General-purpose

PG3 FP27 O LCD FP27 signal

PTG[3] I/O General-purpose

PG2 FP26 O LCD FP26 signal

PTG[2] I/O General-purpose

PG1 FP25 O LCD FP25 signal

PTG[1] I/O General-purpose

PG0 FP24 O LCD FP24 signal

PTG[0] I/O General-purpose

H PH7 FP39 O LCD FP39 signal GPIO

PTH[7] I/O General-purpose

PH6 FP38 O LCD FP38 signal

PTH[6] I/O General-purpose

PH5 FP37 O LCD FP37 signal

PTH[5] I/O General-purpose

PH4 FP36 O LCD FP36 signal

PTH[4] I/O General-purpose

PH3 FP35 O LCD FP35 signal

PTH[3] I/O General-purpose

PH2 FP34 O LCD FP34 signal

PTH[2] I/O General-purpose

PH1 FP33 O LCD FP33 signal

PTH[1] I/O General-purpose

PH0 FP32 O LCD FP32 signal

PTH[0] I/O General-purpose

Pin

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Chapter 2 Port Integration Module (S12ZVHPIMV0)

Port Pin Name

Pin Function

& Priority

I/O Description Routing Register

(1)

Function

after Reset

P PP7 (TXD1) O TXD of SCI1 SCI1RR GPIO

PWM7 O PWM channel 7

PP[7] I/O General-purpose

PP6 PWM6 O PWM channel 6

PP[6] I/O General-purpose

PP5 (RXD1) O RXD of SCI1 SCI1RR

PWM5 O PWM channel 5

PP[5] I/O General-purpose

PP4 PWM4 O PWM channel 4

PP[4] I/O General-purpose

PP3 PWM3 O PWM channel 3

PP[3] I/O General-purpose

PP2 PWM2 O PWM channel 2

PP[2] I/O General-purpose

PP1 PWM1 O PWM channel 1

PP[1] I/O General-purpose

PP0 PWM0 O PWM channel 0

PP[0] I/O General-purpose

S PS7 IRQ

O IRQ interrupt input GPIO

TXD0 I/O TXD of SCI0

PTS[7]/KWS[7] I/O General-purpose; with interrupt and wakeup

PS6 XIRQ

O XIRQ interrupt input

(3)

RXD0 I/O RXD of SCI0

PTS[6]/KWS[6] I/O General-purpose; with interrupt and wakeup

PS5 SDA0 O SDA of IIC0

(TXCAN0) I/O TX of MSCAN0 C0CP0RR3-0

PTS[5]/KWS[5] I/O General-purpose; with interrupt and wakeup

PS4 SCL0 O SCL of IIC0

(RXCAN) I/O RX of MSCAN0 C0CP0RR3-0

PTS[4]/KWS[4] I/O General-purpose; with interrupt and wakeup

PS3 S

S0 I/O SPI0 slave select

PTS[3]/KWS[3] I/O General-purpose; with interrupt and wakeup

PS2 SCK0 I/O SPI0 serial clock

PTS[2]/KWS[2] I/O General-purpose; with interrupt and wakeup

PS1 MOSI0 I/O SPI0 master out/slave in

PTS[1]/KWS[1] I/O General-purpose; with interrupt and wakeup

PS0 MISO0 I/O SPI0 master in/slave out

PTS[0]/KWS[0] I/O General-purpose; with interrupt and wakeup

Pin

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Chapter 2 Port Integration Module (S12ZVHPIMV0)

Port Pin Name

Pin Function

& Priority

I/O Description Routing Register

(1)

Function

after Reset

T PT7 IOC1_7 O TIM1 channel 7 GPIO

PTT[7]/KWT[7] I/O General-purpose; with interrupt and wakeup

PT6 IOC1_6 I/O TIM1 channel 6

ECLK O Free running clock output

PTT[6]/KWT[6] I/O General-purpose; with interrupt and wakeup

PT5 IOC1_5 I/O TIM1 channel 5

PTT[5]/KWT[5] I/O General-purpose; with interrupt and wakeup

PT4 IOC1_4 I/O TIM1 channel 4

PDO O DBG profiling data output

PTT[4]/KWT[4] I/O General-purpose; with interrupt and wakeup

PT3 IOC1_3 I/O TIM1 channel 3

PDOCLK O DBG profiling clock

PTT[3]/KWT[3] I/O General-purpose; with interrupt and wakeup

PT2 IOC1_2 I/O TIM1 channel 2

DBGEEV I DBG external event input

PTT[2]/KWT[2] I/O General-purpose; with interrupt and wakeup

PT1 IOC1_1 I/O TIM1 channel 1

RTC_CAL I/O RTC CALCLK output or external 1HZ input

PTT[1]/KWT[1] I/O General-purpose; with interrupt and wakeup

PT0 (IOC1_0) I/O TIM1 channel 0 T1IC0RR1-0

API_EXTCLK O API clock output

PTT[0]/KWT[0] I/O General-purpose; with interrupt and wakeup

Pin

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Chapter 2 Port Integration Module (S12ZVHPIMV0)

Port Pin Name

PAD7 AN0_7 I ADC0 analog input 7

PAD6 AN0_6 I ADC0 analog input 6

PAD5 AN0_5 I ADC0 analog input 5

PAD4 AN0_4 I ADC0 analog input 4

AD

PAD3 AN0_3 I ADC0 analog input 3

PAD2 AN0_2 I ADC0 analog input 2

PAD1 AN0_1 I ADC0 analog input 1

PAD0 AN0_0 I ADC0 analog input 0

Pin Function

& Priority

(1)

PTADL[7]/
KWADL[7]

PTADL[6]/
KWADL[6]

PTADL[5]/
KWADL[5]

PTADL[4]/
KWADL[4]

PTADL[3]/
KWADL[3]

PTADL[2]/
KWADL[2]

PTADL[1]/
KWADL[1]

PTADL[0]/
KWADL[0]

I/O Description Routing Register

I/O General-purpose; with interrupt and wakeup

I/O General-purpose; with interrupt and wakeup

I/O General-purpose; with interrupt and wakeup

I/O General-purpose; with interrupt and wakeup

I/O General-purpose; with interrupt and wakeup

I/O General-purpose; with interrupt and wakeup

I/O General-purpose; with interrupt and wakeup

I/O General-purpose; with interrupt and wakeup

Pin

Function

after Reset

GPIO

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Chapter 2 Port Integration Module (S12ZVHPIMV0)

Port Pin Name

Pin Function

& Priority

I/O Description Routing Register

(1)

Function

after Reset

U PU[7] M1SINP I/O SSD1 Sine+ Node GPIO

M1C1P O Motor control output for motor 1

PTU[7] I/O General purpose

PU[6] M1SINM I/O SSD1 Sine- Node

M1C1M O Motor control output for motor 1

IOC0_3 I/O TIM0 channel 3

PTU[6] I/O General purpose

PU[5] M1COSP I/O SSD1 Cosine+ Node

M1C0P O Motor control output for motor 1

PTU[5] I/O General purpose

PU[4] M1COSM I/O SSD1 Cosine- Node

M1C0M O Motor control output for motor 1

IOC0_2 I/O TIM0 channel2

PTU[4] I/O General purpose

PU[3] M0SINP I/O SSD0 Sine+ Node

M0C1P O Motor control output for motor 0

PTU[3] I/O General purpose

PU[2] M0SINM I/O SSD0 Sine- Node

M0C1M O Motor control output for motor 0

IOC0_1 I/O TIM0 channel 1

PTU[2] I/O General purpose

PU[1] M0COSP I/O SSD0 Cosine+ Node

M0C0P O Motor control output for motor 0

PTU[1] I/O General purpose

PU[0] M0COSM I/O SSD0 Cosine- Node

M0C0M O Motor control output for motor 0

IOC0_0 I/O TIM0 channel 0

PTU[0] I/O General purpose

Pin

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Chapter 2 Port Integration Module (S12ZVHPIMV0)

Port Pin Name

PV[7] M3SINP I/O SSD3 Sine+ Node GPIO

PV[6] M3SINM I/O SSD3 Sine- Node

PV[5] M3COSP I/O SSD3 Cosine+ Node

PV[4] M3COSM I/O SSD3 cosine- node

V

1. Signals in parenthesis denote alternative module routing pins

2. Function active when RESET

3. The interrupt is enabled by clearing the X mask bit in the CPU CCR. The pin is forced to input upon first clearing of the X bit
and is held in this state until reset. A stop or wait recovery with the X bit set (refer to S12ZCPU reference manual) is not
available.

PV3 M2SINP I/O SSD2 sine+ node

PV2 M2SINM I/O SSD2 sine- node

PV1 M2COSP I/O SSD2 cosine+ node

PV0 M2COSM I/O SSD2 cosine- node

Pin Function

& Priority

M3C1P O Motor control output for motor 3

PTV[7] I/O General purpose

M3C1M O Motor control output for motor 3

IOC0_7 I/O TIM0 channel 7

PTV[6] I/O General purpose

M3C0P O Motor control output for motor 3

PTV[5] I/O General purpose

M3C0M O Motor control output for motor 3

IOC0_6 I/O TIM0 channel 6

PTV[4] I/O General purpose

M2C1P O Motor control output for Motor 2

PTV[3] I/O General purpose

M2C1M O Motor control output for Motor 2

IOC0_5 I/O TIM0 channel 5

PTV[2] I/O General purpose

M2C0P O Motor control output for Motor 2

PTV[1] I/O General purpose

M2C0M O Motor control output for Motor 2

IOC0_4 I/O TIM0 channel 4

PTV[0] I/O General purpose

asserted.

I/O Description Routing Register

(1)

Pin

Function

after Reset

2.3 Memory Map and Register Definition

This section provides a detailed description of all port integration module registers.

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2.3.1 Register Map

Chapter 2 Port Integration Module (S12ZVHPIMV0)

Global

Address

0x0200 MODRR0

0x0201 MODRR1

0x0202 MODRR2

0x0203–
0x0207

0x0208 ECLKCTL

0x0209 IRQCR

0x020A PIMMISC

Register

Name

Reserved

Bit 76 5 4 3 2 1Bit 0

R0 0 0 0

W

R0 0 0 0

W

R0 0

W

R00000000

W

R

NECLK

W

R

IRQE IRQEN

W

R0 0 0 0 0 0 0

W

0000000

SCI1RR IIC0RR

000000

C0CP0RR3C0CP0RR2C0CP0RR1C0CP0RR

0

PWM6RR PWM4RR PWM2RR PWM0RR

00

T1IC0RR1 T1IC0RR0

CALCLKE

N

0x020B–
0x020D

0x020E

0x020F

0x0210–
0x021F

0x0220 PTA

0x0221 PTB

0x0222 PTIA

0x0223 PTIB

Reserved

Reserved

Reserved

Reserved

R00000000

W

R

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

W

R

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

W

R00000000

W

R

PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0

W

R0 0 0 0

W

R PTIA7 PTIA6 PTIA5 PTIA4 PTIA3 PTIA2 PTIA1 PTIA0

W

R 0 0 0 0 PTIB3 PTIB2 PTIB1 PTIB0

W

PTB3 PTB2 PTB1 PTB0

S12ZVH Family Reference Manual , Rev. 1.05

Freescale Semiconductor 79

Chapter 2 Port Integration Module (S12ZVHPIMV0)

Global

Address

Register

Name

0x0224 DDRA

0x0225 DDRB

0x0226 PERA

0x0227 PERB

0x0228 PPSA

0x0229 PPSB

0x022A–
0x023D

Reserved

Bit 76 5 4 3 2 1Bit 0

R

DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0

W

R0 0 0 0

W

R

PERA7 PERA6 PERA5 PERA4 PERA3 PERA2 PERA1 PERA0

W

R0 0 0 0

W

R

PPSA7 PPSA6 PPSA5 PPSA4 PPSA3 PPSA2 PPSA1 PPSA0

W

DDRB3 DDRB2 DDRB1 DDRB0

PERB3 PERB2 PERB1 PERB0

R0 0 0 0

W

PPSB3 PPSB2 PPSB1 PPSB0

R00000000

W

0x023E WOMA

0x023F Reserved

0x0240 PTC

0x0241 PTD

0x0242 PTIC

0x0243 PTID

0x0244 DDRC

0x0245 DDRD

R0 0 0 0

W

WOMA3 WOMA2

00

R00000000

W

R

PTC7 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0

W

R

PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0

W

R PTIC7 PTIC6 PTIC5 PTIC4 PTIC3 PTIC2 PTIC1 PTIC0

W

R PTID7 PTID6 PTID5 PTID4 PTID3 PTID2 PTID1 PTID0

W

R

DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0

W

R

DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0

W

0x0246 PERC

R

PERC7 PERC6 PERC5 PERC4 PERC3 PERC2 PERC1 PERC0

W

S12ZVH Family Reference Manual, Rev. 1.05

80 Freescale Semiconductor

Chapter 2 Port Integration Module (S12ZVHPIMV0)

Global

Address

Register

Name

0x0247 PERD

0x0248 PPSC

0x0249 PPSD

0x024A–
0x025F

Reserved

0x0260 PTE

0x0261 PTF

0x0262 PTIE

Bit 76 5 4 3 2 1Bit 0

R

PERD7 PERD6 PERD5 PERD4 PERD3 PERD2 PERD1 PERD0

W

R

PPSC7 PPSC6 PPSC5 PPSC4 PPSC3 PPSC2 PPSC1 PPSC0

W

R

PPSD7 PPSD6 PPSD5 PPSD4 PPSD3 PPSD2 PPSD1 PPSD0

W

R00000000

W

R0 0 0 0

W

R

PTF7 PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0

W

PTE3 PTE2 PTE1 PTE0

R 0 0 0 0 PTIE3 PTIE2 PTIE1 PTIE0

W

0x0263 PTIF

0x0264 DDRE

0x0265 DDRF

0x0266 PERE

0x0267 PERF

0x0268 PPSE

0x0269 PPSF

0x026A–
0x027F

Reserved

R PTIF7 PTIF6 PTIF5 PTIF4 PTIF3 PTIF2 PTIF1 PTIF0

W

R0 0 0 0

W

R

DDRF7 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0

W

R0 0 0 0

W

R

PERF7 PERF6 PERF5 PERF4 PERF3 PERF2 PERF1 PERF0

W

DDRE3 DDRE2 DDRE1 DDRE0

PERE3 PERE2 PERE1 PERE0

R0 0 0 0

W

R

PPSF7 PPSF6 PPSF5 PPSF4 PPSF3 PPSF2 PPSF1 PPSF0

W

PPSE3 PPSE2 PPSE1 PPSE0

R00000000

W

0x0280 Reserved

R00000000

W

S12ZVH Family Reference Manual , Rev. 1.05

Freescale Semiconductor 81

Chapter 2 Port Integration Module (S12ZVHPIMV0)

Global

Address

Register

Name

0x0281 PTADL

0x0282 Reserved

0x0283 PTIADL

0x0284 Reserved

0x0285 DDRADL

0x0286 Reserved

0x0287 PERADL

Bit 76 5 4 3 2 1Bit 0

R

PTADL7 PTADL6 PTADL5 PTADL4 PTADL3 PTADL2 PTADL1 PTADL0

W

R00000000

W

R PTIADL7 PTIADL6 PTIADL5 PTIADL4 PTIADL3 PTIADL2 PTIADL1 PTIADL0

W

R00000000

W

R

DDRADL7 DDRADL6 DDRADL5 DDRADL4 DDRADL3 DDRADL2 DDRADL1 DDRADL0

W

R00000000

W

R

PERADL7 PERADL6 PERADL5 PERADL4 PERADL3 PERADL2 PERADL1 PERADL0

W

0x0288 Reserved

0x0289 PPSADL

0x028A–
0x028B

Reserved

0x028C Reserved

0x028D PIEADL

0x028E Reserved

0x028F PIFADL

0x0290–
0x0298

Reserved

R00000000

W

R

PPSADL7 PPSADL6 PPSADL5 PPSADL4 PPSADL3 PPSADL2 PPSADL1 PPSADL0

W

R00000000

W

R00000000

W

R

PIEADL7 PIEADL6 PIEADL5 PIEADL4 PIEADL3 PIEADL2 PIEADL1 PIEADL0

W

R00000000

W

R

PIFADL7 PIFADL6 PIFADL5 PIFADL4 PIFADL3 PIFADL2 PIFADL1 PIFADL0

W

R00000000

W

0x0299 DIENADL

R

DIENADL7 DIENADL6 DIENADL5 DIENADL4 DIENADL3 DIENADL2 DIENADL1 DIENADL0

W

S12ZVH Family Reference Manual, Rev. 1.05

82 Freescale Semiconductor

Chapter 2 Port Integration Module (S12ZVHPIMV0)

Global

Address

0x029A–
0x02BF

Register

Name

Reserved

W

0x02C0 PTT R

W

0x02C1

PTIT

W

0x02C2 DDRT R

W

0x02C3 PERT R

W

0x02C4 PPST R

W

0x02C5 Reserved

W

Bit 76 5 4 3 2 1Bit 0

R00000000

PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0

R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0

DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0

PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0

PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0

R00000000

0x02C6 PIET

0x02C7 PIFT

0x02C8–
0x02CF

Reserved

0x02D0 PTS

0x02D1 PTIS

0x02D2 DDRS

0x02D3 PERS

0x02D4 PPSS

R

PIET7 PIET6 PIET5 PIET4 PIET3 PIET2 PIET1 PIET0

W

R

PIFT7 PIFT6 PIFT5 PIFT4 PIFT3 PIFT2 PIFT1 PIFT0

W

R00000000

W

R

PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0

W

R PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0

W

R

DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0

W

R

PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0

W

R

PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0

W

0x02D5 Reserved

W

S12ZVH Family Reference Manual , Rev. 1.05

Freescale Semiconductor 83

R00000000

Chapter 2 Port Integration Module (S12ZVHPIMV0)

Global

Address

Register

Name

0x02D6 PIES

0x02D7 PIFS

0x02D8–
0x02DE

Reserved

0x02DF WOMS

0x02E0–
0x02EF

Reserved

0x02F0 PTP

0x02F1 PTIP

Bit 76 5 4 3 2 1Bit 0

R

PIES7 PIES6 PIES5 PIES4 PIES3 PIES2 PIES1 PIES0

W

R

PIFS7 PIFS6 PIFS5 PIFS4 PIFS3 PIFS2 PIFS1 PIFS0

W

R00000000

W

R

WOMS7WOMS6WOMS5WOMS4WOMS3WOMS2WOMS1WOMS0

W

R00000000

W

R

PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0

W

R PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0

W

0x02F2 DDRP

0x02F3 PERP

0x02F4 PPSP

0x02F5–
0x02FF

Reserved

0x0300 PTH

0x0301 PTIH

0x0302 DDRH

0x0303 PERH

R

DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0

W

R

PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0

W

R

PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0

W

R00000000

W

R

PTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0

W

R PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0

W

R

DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0

W

R

PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0

W

0x0304 PPSH

R

PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0

W

S12ZVH Family Reference Manual, Rev. 1.05

84 Freescale Semiconductor

Chapter 2 Port Integration Module (S12ZVHPIMV0)

Global

Address

0x0305–
0x030F

0x0310–
0x031F

Register

Name

Reserved

Reserved

0x0320 PTG

0x0321 PTIG

0x0322 DDRG

0x0323 PERG

0x0324 PPSG

Bit 76 5 4 3 2 1Bit 0

R00000000

W

R00000000

W

R

PTG7 PTG6 PTG5 PTG4 PTG3 PTG2 PTG1 PTG0

W

R

PTIG7 PTIG6 PTIG5 PTIG4 PTIG3 PTIG2 PTIG1 PTIG0

W

R

DDRG7 DDRG6 DDRG5 DDRG4 DDRG3 DDRG2 DDRG1 DDRG0

W

R

PERG7 PERG6 PERG5 PERG4 PERG3 PERG2 PERG1 PERG0

W

R

PPSG7 PPSG6 PPSG5 PPSG4 PPSG3 PPSG2 PPSG1 PPSG0

W

0x0325–
0x032F

Reserved

0x0350 PTU

0x0351 PTIU

0x0352 DDRU

0x0353 PERU

0x0354 PPSU

0x0355–
0x035D

Reserved

0x035E SRRU

R00000000

W

R

PTU7 PTU6 PTU5 PTU4 PTU3 PTU2 PTU1 PTU0

W

R PTIU7 PTIU6 PTIU5 PTIU4 PTIU3 PTIU2 PTIU1 PTIU0

W

R

DDRU7 DDRU6 DDRU5 DDRU4 DDRU3 DDRU2 DDRU1 DDRU0

W

R

PERU7 PERU6 PERU5 PERU4 PERU3 PERU2 PERU1 PERU0

W

R

PPSU7 PPSU6 PPSU5 PPSU4 PPSU3 PPSU2 PPSU1 PPSU0

W

R00000000

W

R

SRRU7 SRRU6 SRRU5 SRRU4 SRRU3 SRRU2 SRRU1 SRRU0

W

0x035F Reserved

R00000000

W

S12ZVH Family Reference Manual , Rev. 1.05

Freescale Semiconductor 85

Chapter 2 Port Integration Module (S12ZVHPIMV0)

Global

Address

0x0360 PTV

0x0361 PTIV

0x0362 DDRV

0x0363 PERV

0x0364 PPSV

0x0365–
0x036D

0x036E SRRV

Register

Name

Reserved

Bit 76 5 4 3 2 1Bit 0

R

PTV7 PTV6 PTV5 PTV4 PTV3 PTV2 PTV1 PTV0

W

R PTIV7 PTIV6 PTIV5 PTIV4 PTIV3 PTIV2 PTIV1 PTIV0

W

R

DDRV7 DDRV6 DDRV5 DDRV4 DDRV3 DDRV2 DDRV1 DDRV0

W

R

PERV7 PERV6 PERV5 PERV4 PERV3 PERV2 PERV1 PERV0

W

R

PPSV7 PPSV6 PPSV5 PPSV4 PPSV3 PPSV2 PPSV1 PPSV0

W

R00000000

W

R

SRRV7 SRRV6 SRRV5 SRRV4 SRRV3 SRRV2 SRRV1 SRRV0

W

0x036F Reserved

0x0370–
0x037F

Reserved

R00000000

W

R00000000

W

2.3.2 Register Descriptions

This section describes the details of all configuration registers.

• If not stated differently, writing to reserved bits has no effect and read returns zero.

• All register read accesses are synchronous to internal clocks.

• All registers can be written at any time, however a specific configuration might not become active.
E.g. a pullup device does not become active while the port is used as a push-pull output.

• General-purpose data output availability depends on prioritization; input data registers always
reflect the pin status independent of the use.

• Pull-device availability, pull-device polarity, wired-or mode, key-wake up functionality are
independent of the prioritization unless noted differently.

• The description of registers PTx, PTIx, DDRx, DIENx, PERx, PPSx, SRRx, WOMx, PIEx and
PIFx generically assumes a fully implemented 8-bit register . For availability of individual bits refer
to Section 2.3.1, “Register Map”.

S12ZVH Family Reference Manual, Rev. 1.05

86 Freescale Semiconductor

2.3.2.1 Module Routing Register 0 (MODRR0)

Chapter 2 Port Integration Module (S12ZVHPIMV0)

Address 0x0200 Access: User read/write

76543210

R0000

W

— — — — CAN0-CANPHY0 (see Figure 2-2)

Reset00000000

C0CP0RR3 C0CP0RR2 C0CP0RR1 C0CP0RR0

Figure 2-1. Module Routing Register 0 (MODRR0)

1. Read: Anytime
Write: Once in normal, anytime in special mode

For routing options refer to Figure 2-2.

.

Field Description

3

C0CP0RR3

2

C0CP0RR2

1

C0CP0RR1

Module Routing Register—
When set to 1, the internal interface is visible on the alternate external pins.

Module Routing Register—
When set to 1, the internal interface is visible on external pins.

Module Routing Register—
When set to 1, the internal interface is opened and CPTXD0 and RXCAN0 are routed to external pins.

Table 2-2. Module Routing Register 0 Field Descriptions

(1)

0

C0CP0RR0

Module Routing Register—
When set to 1, CPTXD0 is driven by CANPHY0 internal register bit CPDR1.

Table 2-3. Preferred Interface Configurations

C0CP0RR[3:0] Signal Routing Description

0 0 0 0 TXCAN0->CPTXD0

CPRXD0->RXCAN0

0 0 0 1 CPDR1->CPTXD0

CPRXD0->RXCAN0

0100 TXCAN0-

>CPTXD0,PC1

CPRXD0-

>RXCAN0,PC2

0110 TXCAN0->PC1

PC3->CPTXD0
CPRXD0->PC2
PC0->RXCAN0

MSCAN0 connects to CANPHY0, interface internal

only

CPDR1 connects to CPTXD0, interface internal only

Probe mode, MCSAN0 connects to CANPHY0,

interface visible on 2 external pins

Conformance test mode, interface opened and all 4

signals routed externally

(1)

S12ZVH Family Reference Manual , Rev. 1.05

Freescale Semiconductor 87

Chapter 2 Port Integration Module (S12ZVHPIMV0)

MSCAN0

CANPHY0

TXCAN0

RXCAN0

CPTXD0

CPRXD0

PC2/CPRXD0

PC3/CPTXD0

PC1/TXCAN0

PC0/RXCAN0

0

1

0

1

0

1

1

0

1

0

CPDR1

C0CP0RR0

SPLIT0

CANH0

CANL0

0

1

0

1

PS5/(TXCAN0)

PS4/(RXCAN0)

C0CP0RR1

C0CP0RR2 C0CP0RR3

C0CP0RR[3:0] Signal Routing Description

1110 TXCAN0->PS5

PC3->CPTXD0
CPRXD0->PC2
PS4->RXCAN0

Conformance test mode, interface opened and all 4

signals routed externally

1

1. if CANPHY is not enabled, then PC3/PC2 will be controlled by other functions. The
configure can be use for standalone MSCAN connection.

Figure 2-2. MSCAN0-CANPHY0 Routing Options Illustration

S12ZVH Family Reference Manual, Rev. 1.05

88 Freescale Semiconductor

2.3.2.2 Module Routing Register 1 (MODRR1)

Chapter 2 Port Integration Module (S12ZVHPIMV0)

Address 0x0201 Access: User read/write

76543210

R0000

W

— — — — PWM6 PWM4 PWM2 PWM0

Reset00000000

PWM6RR PWM4RR PWM2RR PWM0RR

Figure 2-3. Module Routing Register 1 (MODRR1)

1. Read: Anytime
Write: Once in normal, anytime in special mode

Table 2-4. MODRR1 Routing Register Field Descriptions

Field Description

3

PWM6RR

2

PWM4RR

Module Routing Register — PWM6 routing

PWM channel 6 can be configured for PP6 or PA7.

1 PWM6 to PA7
0 PWM6 to PP6

Module Routing Register — PWM4 routing

PWM channel 4 can be configured for PP4 or PA6.

(1)

1

PWM2RR

0

PWM0RR

1 PWM4 to PA6
0 PWM4 to PP4

Module Routing Register — PWM2 routing

PWM channel 2 can be configured for PP2 or PA5.

1 PWM2 to PA5
0 PWM2 to PP2

Module Routing Register — PWM0 routing

PWM channel can be configured for PP0 or PA4.

1 PWM0 to PA4
0 PWM0 to PP0

S12ZVH Family Reference Manual , Rev. 1.05

Freescale Semiconductor 89

Chapter 2 Port Integration Module (S12ZVHPIMV0)

2.3.2.3 Module Routing Register 2 (MODRR2)

Address 0x0202 Access: User read/write

76543210

R0 0

SCI1RR IIC0RR

W

SCI1 IIC0 TI M1 IC0

Reset00000000

00

T1IC0RR1 T1IC0RR0

Figure 2-4. Module Routing Register 2 (MODRR2)

1. Read: Anytime
Write: Once in normal, anytime in special mode

Table 2-5. MODRR2 Routing Register Field Descriptions

Field Description

5

SCI1RR

4

IIC0RR

Module Routing Register — SCI1 routing

1 TXD1 on PP7; RXD1 on PP5
0 TXD1 on PC7; RXD1 on PC6

Module Routing Register — IIC0 routing

1 SCL0 on PA2; SDA0 on PA3
0 SCL0 on PS4; SDA0 on PS5

(1)

1-0

T1IC0RR1-0

Module Routing Register — TIM1 IC0 routing

11 TIM1 input capture channel 0 is connected to RXD1
10 TIM1 input capture channel 0 is connected to RXD0
01 TIM1 input capture channel 0 is connected to RTC’s CALCLK
00 TIM1 input capture channel 0 is connected to PT0

S12ZVH Family Reference Manual, Rev. 1.05

90 Freescale Semiconductor

2.3.2.4 ECLK Control Register (ECLKCTL)

Chapter 2 Port Integration Module (S12ZVHPIMV0)

Address 0x0208 Access: User read/write

76543210

R

NECLK

W

Reset:10000000

0000000

(1)

Figure 2-5. ECLK Control Register (ECLKCTL)

1. Read: Anytime
Write: Anytime

Table 2-6. ECLKCTL Register Field Descriptions

Field Description

7

NECLK

No ECLK — Disable ECLK output

This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate equivalent to the
internal bus clock.

1 ECLK disabled
0 ECLK enabled

2.3.2.5 IRQ Control Register (IRQCR)

Address 0x0209 Access: User read/write

76543210

R

IRQE IRQEN

W

Reset00000000

000000

Figure 2-6. IRQ Control Register (IRQCR)

1. Read: Anytime
Write:

IRQE: Once in normal mode, anytime in special mode

IR QEN: Anytime

(1)

S12ZVH Family Reference Manual , Rev. 1.05

Freescale Semiconductor 91

Chapter 2 Port Integration Module (S12ZVHPIMV0)

Table 2-7. IRQCR Register Field Descriptions

Field Description

7

IRQE

6

IRQEN

IRQ select edge sensitive only —

pin configured to respond only to falling edges. Falling edges on the IRQ pin are detected anytime when

1 IRQ

IRQE=1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.

configured for low level recognition

0 IRQ
IRQ enable —

1 IRQ pin is connected to interrupt logic

pin is disconnected from interrupt logic

0 IRQ

2.3.2.6 PIM Miscellaneous Register (PIMMISC)

Address 0x020A Access: User read/write

76543210

R0000000

W

Reset00000000

Figure 2-7. PIM Miscellaneous Register (PIMMISC)

1. Read: Anytime
Write:Anytime

Table 2-8. PIM Miscellaneous Register Field Descriptions

CALCLKEN

(1)

Field Description

0

CALCLKE

N

RTC_CAL output Enable — Activate the RTC CALCLK output on PT1

1 CALCLK output on PT1 enabled
0 CALCLK output on PT1 disabled

S12ZVH Family Reference Manual, Rev. 1.05

92 Freescale Semiconductor

2.3.2.7 Reserved Register PIM Test Register

Chapter 2 Port Integration Module (S12ZVHPIMV0)

Address 0x020E Access: User read/write

76543210

R

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

W

Resetxxxxxxxx

Figure 2-8. Reserved Register

1. Read: Anytime
Write: Only in special mode

These reserved registers are designed for factory test purposes only and are
not intended for general user access. Writing to these registers when in
special modes can alter the modules functionality

Address 0x020F Access: User read/write

76543210

R

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

W

Resetxxxxxxxx

(1)

(1)

1. Read: Anytime

Figure 2-9. Reserved Register

Write: Only in special mode

NOTE

These reserved registers are designed for factory test purposes only and are
not intended for general user access. Writing to these registers when in
special modes can alter the modules functionality

2.3.2.8 Port C Polarity Select Register

Address 0x0248 PPSC Access: User read/write

76543210

R

PPSx7 PPSx6 PPSx5 PPSx4 PPSx3 PPSx2 PPSx1 PPSx0

W

Reset00000000

Figure 2-10. Port C Polarity Select Register

1. Read: Anytime
Write: Anytime

(1)

S12ZVH Family Reference Manual , Rev. 1.05

Freescale Semiconductor 93

Chapter 2 Port Integration Module (S12ZVHPIMV0)

Table 2-9. Port C Polarity Select Register Field Descriptions

Field Description

7-1

PPSC

0

PPSC

Pull Polarity Select — Configure pull device on input pin

This bits select a pullup or a pulldown device if enabled on the associated port input pin.

1 pulldown device selected
0 pullup device selected

Port P Pull Polarity Select — Configure pull device on input pin

This bit selects a pullup or a pulldown device if enabled on the associated port input pin.

If MSCAN0 is active and routing to this pin, a pullup device can be activated on the RXCAN0 input; attempting to
select a pulldown disables the pull-device.

1 pulldown device selected
0 pullup device selected

2.3.2.9 Port S Polarity Select Register

Address 0x02D4 PPSS Access: User read/write

76543210

R

PPSx7 PPSx6 PPSx5 PPSx4 PPSx3 PPSx2 PPSx1 PPSx0

W

(1)

Reset00000000

Figure 2-11. Port S Polarity Select Register

1. Read: Anytime
Write: Anytime

S12ZVH Family Reference Manual, Rev. 1.05

94 Freescale Semiconductor

Table 2-10. Port S Polarity Select Register Field Descriptions

Field Description

Chapter 2 Port Integration Module (S12ZVHPIMV0)

7-5

PPSS

4

PPSS

3-0

PPSS

Pull Polarity Select — Configure pull device and pin interrupt edge polarity on input pin

This bits select a pullup or a pulldown device if enabled on the associated port input pin.

1 pulldown device selected; rising edge selected
0 pullup device selected; falling edge selected

Port P Pull Polarity Select — Configure pull device and pin interrupt edge polarity on input pin

This bit selects a pullup or a pulldown device if enabled on the associated port input pin.

If MSCAN0 is active and routing to this pin, a pullup device can be activated on the RXCAN0 input; attempting to
select a pulldown disables the pull-device.

1 pulldown device selected; rising edge selected
0 pullup device selected; falling edge selected

Pull Polarity Select — Configure pull device and pin interrupt edge polarity on input pin

This bit selects a pullup or a pulldown device if enabled on the associated port input pin.
This bit also selects the polarity of the active interrupt edge.

1 pulldown device selected; rising edge selected
0 pullup device selected; falling edge selected

2.3.2.10 Port Data Register

Address 0x0220 PTA

0x0221 PTB
0x0240 PTC
0x0241 PTD
0x0260 PTE
0x0261 PTF
0x0281 PTADL
0x02C0 PTT
0x02D0 PTS
0x02F0 PTP
0x0300 PTH
0x0320 PTG
0x0350 PTU
0x0360 PTV

76543210

R

PTx7 PTx6 PTx5 PTx4 PTx3 PTx2 PTx1 PTx0

W

Reset00000000

Access: User read/write

Figure 2-12. Port Data Register

1. Read: Anytime. The data source is depending on the data direction value.
Write: Anytime

(1)

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Chapter 2 Port Integration Module (S12ZVHPIMV0)

Table 2-11. Port Data Register Field Descriptions

Field Description

7-0

PTx

Port — General purpose input/output data

This register holds the value driven out to the pin if the pin is used as a general purpose output.
When not used with the alternative function (refer to Ta b le 2 -1 ), these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.

2.3.2.11 Port Input Register

Address 0x0222 PTIA

0x0223 PTIB
0x0242 PTIC
0x0243 PTID
0x0262 PTIE
0x0263 PTIF
0x0283 PTIADL
0x02C1 PTIT
0x02D1 PTIS
0x02F1 PTIP
0x0301 PTIH
0x0321 PTIG
0x0351 PTIU
0x0361 PTIV

76543210

R PTIx7 PTIx6 PTIx5 PTIx4 PTIx3 PTIx2 PTIx1 PTIx0

Access: User read only

(1)

W

Reset00000000

Figure 2-13. Port Input Register

1. Read: Anytime
Write:Never

Table 2-12. Port Input Register Field Descriptions

Field Description

7-0

PTIx

Port Input — Data input

A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.

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2.3.2.12 Data Direction Register

Chapter 2 Port Integration Module (S12ZVHPIMV0)

Address 0x0224 DDRA

0x0225 DDRB
0x0244 DDRC
0x0245 DDRD
0x0264 DDRE
0x0265 DDRF
0x0285 DDRADL
0x02C2 DDRT
0x02D2 DDRS
0x02F2 DDRP
0x0302 DDRH
0x0322 DDRG
0x0352 DDRU
0x0362 DDRV

76543210

R

DDRx7 DDRx6 DDRx5 DDRx4 DDRx3 DDRx2 DDRx1 DDRx0

W

Reset00000000

Access: User read/write

Figure 2-14. Data Direction Register

1. Read: Anytime
Write: Anytime

Table 2-13. Data Direction Register Field Descriptions

(1)

Field Description

7-0

DDRx

Data Direction — Select general-purpose data direction

This bit determines whether the pin is a general-purpose input or output.

1 Associated pin is configured as output
0 Associated pin is configured as input

NOTE

Due to internal synchronization circuits, it can take up to two bus clock
cycles until the correct value is read on port data and port input registers,
when changing the data direction register.

The general-purpose data direction configuration can be overruled by an enabled peripheral function
shared on the same pin (Table 2-22). If more then one peripheral function is available and enabled at the
same time, the highest ranked module according the predefined priority scheme in Table 2-1 will take
precedence on the pin.

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Chapter 2 Port Integration Module (S12ZVHPIMV0)

2.3.2.13 Digital Input Enable Register

Address 0x0299 DIENADL Access: User read/write

76543210

R

DIENx7 DIENx6 DIENx5 DIENx4 DIENx3 DIENx2 DIENx1 DIENx0

W

Reset00000000

Figure 2-15. Digital Input Enable Register

1. Read: Anytime
Write: Anytime

Table 2-14. Digital Input Enable Register Field Descriptions

Field Description

7-0

DIENx

Digital Input Enable — Input buffer control

This bit controls the digital input function. If set to 1 the input buffers are enabled and the pin can be used with the
digital function. If the pin is used with an analog function this bit shall be cleared to avoid shoot-through current.

1 Associated pin is configured as digital input
0 Associated pin digital input is disabled

(1)

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2.3.2.14 Pull Device Enable Register

Chapter 2 Port Integration Module (S12ZVHPIMV0)

Address 0x0226 PERA

0x0227 PERB
0x0246 PERC
0x0247 PERD
0x0266 PERE
0x0267 PERF
0x0287 PERADL
0x02C3 PERT
0x02D3 PERS
0x02F3 PERP
0x0303 PERH
0x0323 PERG
0x0353 PERU
0x0363 PERV

76543210

R

PERx7 PERx6 PERx5 PERx4 PERx3 PERx2 PERx1 PERx0

W

Reset

Ports B, E: 0 0 0 0 1 1 1 1

Ports C, P T,

ADL, U, V:

Others:11111111

00000000

Access: User read/write

(1)

1. Read: Anytime
Write: Anytime

Table 2-15. Pull Device Register Field Descriptions

Field Description

Figure 2-16. Pull Device Enable Register

7-0

PERx

Pull Enable — Activate pull device on input pin

This bit controls whether a pull device on the associated port input or open-drain output pin is active. If a pin is used
as push-pull output this bit has no effect. The polarity is selected by the related polarity select register bit. On open­drain output pins only a pullup device can be enabled.

1 Pull device enabled
0 Pull device disabled

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Chapter 2 Port Integration Module (S12ZVHPIMV0)

2.3.2.15 Polarity Select Register

Address 0x0228 PPSA

Access: User read/write

(1)

0x0229 PPSB
0x0248 PPSC
0x0249 PPSD
0x0268 PPSE
0x0269 PPSF
0x0289 PPSADL
0x02C4 PPST
0x02D4 PPSS
0x02F4 PPSP
0x0304 PPSH
0x0324 PPSG
0x0354 PPSU
0x0364 PPSV

76543210

R

PPSx7 PPSx6 PPSx5 PPSx4 PPSx3 PPSx2 PPSx1 PPSx0

W

Reset

Ports B, E:00001111

Ports A, D,

F, G, H :

11111111

Others:00000000

1. Read: Anytime
Write: Anytime

Table 2-16. Polarity Select Register Field Descriptions

Field Description

Figure 2-17. Polarity Select Register

7-0

PPSx

Pull Polarity Select — Configure pull device and pin interrupt edge polarity on input pin

This bit selects a pullup or a pulldown device if enabled on the associated port input pin.
If a port has interrupt functionality this bit also selects the polarity of the active edge.

If MSCAN0 is active a pullup device can be activated on the RXCAN0 input; attempting to select a pulldown disables
the pull-device.

1 Pulldown device selected; rising edge selected
0 Pullup device selected; falling edge selected

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