NXP Semiconductors MC9S12G Reference Manual

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S12 Microcontrollers

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MC9S12G Family Reference Manual and Dat a Sheet

MC9S12GRMV1

Rev.1.27

October 23, 2017

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To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:

nxp.com/

A full list of family members and options is included in the appendices.

MC9S12G Family Reference Manual Rev.1.27

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The following revision history table summarizes changes contained in this document.

Revision History

Date

Nov, 2012 1.18

Nov, 2012 1.19 • Corrected order of chapters

Jan, 2013 1.20

Jan, 2013 1.21

Jan, 2013 1.22

Revision

Level

• Added Chapter 12, “Analog-to-Digital Converter (ADC12B8CV2)”

• Added Chapter 14, “Analog-to-Digital Converter (ADC12B12CV2)”

• Updated Chapter 11, “Analog-to-Digital Converter (ADC10B8CV2)” (Reason: Spec update)

• Updated Chapter 13, “Analog-to-Digital Converter (ADC10B12CV2)” (Reason: Spec update)

• Updated Chapter 15, “Analog-to-Digital Converter (ADC10B16CV2)” (Reason: Spec update)

• Updated Chapter 16, “Analog-to-Digital Converter (ADC12B16CV2)” (Reason: Spec update)

• Updated Appendix A, “Electrical Characteristics” (Reason: Added AEC Grade 0 spec)

• Updated Appendix C, “Ordering and Shipping Information” (Reason: Added temperature option W)

• Separated description of 8-channel timer

• Updated Appendix A, “Electrical Characteristics” (Reason: Updated electricals)

• Updated Chapter 1, “Device Overview MC9S12G-Family” (Reason: added KGD option for the S12GA192 and the S12GA240)

• Updated Appendix A, “Electrical Characteristics” (Reason: Updated electricals)

• Up[dated Appendix C, “Ordering and Shipping Information” (Reason: Added KGD information)

• Added Appendix D, “Package and Die Information” (Reason: Added KGD information)

Description

Feb, 2013 1.23

Jul, 2014 1.24

Aug, 2014 1.25 • Fixed issues with hidden text throughout the document

Jun, 2017 1.26

Oct, 2017 1.27

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• Updated Appendix C, “Ordering and Shipping Information” (Reason: Removed KGD information)

• Updated Chapter 1, “Device Overview MC9S12G-Family” (Reason: Spec update)

• Fixed wordingFixed typos and formatting, improved wording

• Updated Appendix A, “Electrical Characteristics” (Reason: Updated electricals)

• Updated Chapter 17, “Digital Analog Converter (DAC_8B5V)” (Reason: Spec update)

• Updated Chapter 1, “Device Overview MC9S12G-Family (added mask set information to Table 1-5)

• Updated Appendix A, “Electrical Characteristics (updated Table A-44 and Table A-45)

MC9S12G Family Reference Manual Rev.1.27

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This document contains information for all constituent modules, with the exception of the CPU. For CPU

information please refer to CPU12-1 in the CPU12 & CPU12X Reference Manual

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Chapter 1 Device Overview MC9S12G-Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Chapter 2 Port Integration Module (S12GPIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . .149

Chapter 3 5V Analog Comparator (ACMPV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249

Chapter 4 Reference Voltage Attenuator (RVAV1) . . . . . . . . . . . . . . . . . . . . . . . . . .255

Chapter 5 S12G Memory Map Controller (S12GMMCV1) . . . . . . . . . . . . . . . . . . . . .259

Chapter 6 Interrupt Module (S12SINTV1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273

Chapter 7 Background Debug Module (S12SBDMV1) . . . . . . . . . . . . . . . . . . . . . . .281

Chapter 8 S12S Debug Module (S12SDBGV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305

Chapter 9 Security (S12XS9SECV2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347

Chapter 10 S12 Clock, Reset and Power Management Unit (S12CPMU) . . . . . . . . .353

Chapter 11 Analog-to-Digital Converter (ADC10B8CV2) . . . . . . . . . . . . . . . . . . . . . .405

Chapter 12 Analog-to-Digital Converter (ADC12B8CV2) . . . . . . . . . . . . . . . . . . . . . .429

Chapter 13 Analog-to-Digital Converter (ADC10B12CV2) . . . . . . . . . . . . . . . . . . . . .455

Chapter 14 Analog-to-Digital Converter (ADC12B12CV2) . . . . . . . . . . . . . . . . . . . . .481

Chapter 15 Analog-to-Digital Converter (ADC10B16CV2) . . . . . . . . . . . . . . . . . . . . .507

Chapter 16 Analog-to-Digital Converter (ADC12B16CV2) . . . . . . . . . . . . . . . . . . . . .533

Chapter 17 Digital Analog Converter (DAC_8B5V). . . . . . . . . . . . . . . . . . . . . . . . . . .559

Chapter 18 Scalable Controller Area Network (S12MSCANV3). . . . . . . . . . . . . . . . .569

Chapter 19 Pulse-Width Modulator (S12PWM8B8CV2) . . . . . . . . . . . . . . . . . . . . . . .623

Chapter 20 Serial Communication Interface (S12SCIV5). . . . . . . . . . . . . . . . . . . . . .653

Chapter 21 Serial Peripheral Interface (S12SPIV5). . . . . . . . . . . . . . . . . . . . . . . . . . .691

Chapter 22 Timer Module (TIM16B6CV3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .719

Chapter 23 Timer Module (TIM16B8CV3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .737

Chapter 24 16 KByte Flash Module (S12FTMRG16K1V1) . . . . . . . . . . . . . . . . . . . . .765

Chapter 25 32 KByte Flash Module (S12FTMRG32K1V1) . . . . . . . . . . . . . . . . . . . . .813

Chapter 26 48 KByte Flash Module (S12FTMRG48K1V1) . . . . . . . . . . . . . . . . . . . . .865

Chapter 27 64 KByte Flash Module (S12FTMRG64K1V1) . . . . . . . . . . . . . . . . . . . . .917

Chapter 28 96 KByte Flash Module (S12FTMRG96K1V1) . . . . . . . . . . . . . . . . . . . . .969

Chapter 29 128 KByte Flash Module (S12FTMRG128K1V1) . . . . . . . . . . . . . . . . . .1021

Chapter 30 192 KByte Flash Module (S12FTMRG192K2V1) . . . . . . . . . . . . . . . . . .1073

Chapter 31 240 KByte Flash Module (S12FTMRG240K2V1) . . . . . . . . . . . . . . . . . .1125

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Appendix A Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1177

Appendix B Detailed Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1233

Appendix C Ordering and Shipping Information . . . . . . . . . . . . . . . . . . . . . . . . . . . .1253

Appendix D Package and Die Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1255

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Chapter 1

Device Overview MC9S12G-Family

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

1.2.1 MC9S12G-Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

1.2.2 Chip-Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

1.3 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

1.3.1 S12 16-Bit Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.3.2 On-Chip Flash with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.3.3 On-Chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.3.4 Port Integration Module (PIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.3.5 Main External Oscillator (XOSCLCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

1.3.6 Internal RC Oscillator (IRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

1.3.7 Internal Phase-Locked Loop (IPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

1.3.8 System Integrity Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

1.3.9 Timer (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

1.3.10 Pulse Width Modulation Module (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

1.3.11 Controller Area Network Module (MSCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

1.3.12 Serial Communication Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1.3.13 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1.3.14 Analog-to-Digital Converter Module (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1.3.15 Reference Voltage Attenuator (RVA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.3.16 Digital-to-Analog Converter Module (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.3.17 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.3.18 On-Chip Voltage Regulator (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.3.19 Background Debug (BDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.3.20 Debugger (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.4 Key Performance Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

1.6 Family Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

1.6.1 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

1.7 Signal Description and Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

1.7.1 Pin Assignment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

1.7.2 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

1.7.3 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

1.8 Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

1.8.1 S12GN16 and S12GN32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

1.8.2 S12GNA16 and S12GNA32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

1.8.3 S12GN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

1.8.4 S12G48 and S12G64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

1.8.5 S12GA48 and S12GA64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

1.8.6 S12G96 and S12G128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

1.8.7 S12GA96 and S12GA128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

1.8.8 S12G192 and S12G240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

1.8.9 S12GA192 and S12GA240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

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1.9 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

1.10 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

1.10.1 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

1.10.2 Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

1.11 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

1.12 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

1.12.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

1.12.2 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

1.12.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

1.13 COP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

1.14 Autonomous Clock (ACLK) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

1.15 ADC External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

1.16 ADC Special Conversion Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

1.17 ADC Result Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

1.18 ADC VRH/VRL Signal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

1.19 BDM Clock Source Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Chapter 2

Port Integration Module (S12GPIMV1)

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

2.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

2.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

2.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

2.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

2.2 PIM Routing - External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

2.2.1 Package Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

2.2.2 Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

2.2.3 Signals and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

2.3 PIM Routing - Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

2.3.1 Pin BKGD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

2.3.2 Pins PA7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

2.3.3 Pins PB7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

2.3.4 Pins PC7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

2.3.5 Pins PD7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

2.3.6 Pins PE1-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

2.3.7 Pins PT7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

2.3.8 Pins PS7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

2.3.9 Pins PM3-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

2.3.10 Pins PP7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

2.3.11 Pins PJ7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

2.3.12 Pins AD15-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

2.4 PIM Ports - Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

2.4.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

2.4.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

2.4.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

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2.5 PIM Ports - Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

2.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

2.5.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

2.5.3 Pin Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

2.5.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

2.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

2.6.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

2.6.2 Port Data and Data Direction Register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

2.6.3 Enabling IRQ edge-sensitive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

2.6.4 ADC External Triggers ETRIG3-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

2.6.5 Emulation of Smaller Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Chapter 3

5V Analog Comparator (ACMPV1)

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

3.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

3.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

3.4 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

3.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

3.6 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

3.6.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

3.6.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

3.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Chapter 4

Reference Voltage Attenuator (RVAV1)

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

4.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

4.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

4.4 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

4.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

4.6 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

4.6.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

4.6.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

4.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Chapter 5

S12G Memory Map Controller (S12GMMCV1)

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

5.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

5.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

5.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

5.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

5.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

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5.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

5.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

5.4.1 MCU Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

5.4.2 Memory Map Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

5.4.3 Unimplemented and Reserved Address Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

5.4.4 Prioritization of Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

5.4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Chapter 6

Interrupt Module (S12SINTV1)

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

6.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

6.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

6.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

6.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

6.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

6.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

6.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

6.4.1 S12S Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

6.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

6.4.3 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

6.4.4 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

6.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

6.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

6.5.2 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

6.5.3 Wake Up from Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

Chapter 7

Background Debug Module (S12SBDMV1)

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

7.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

7.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

7.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

7.3.3 Family ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

7.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

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7.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

7.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

7.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

7.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

7.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

7.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

7.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

7.4.9 SYNC — Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

7.4.10 Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

7.4.11 Serial Communication Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

Chapter 8

S12S Debug Module (S12SDBGV2)

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

8.1.1 Glossary Of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

8.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

8.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

8.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

8.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

8.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

8.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

8.4.1 S12SDBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

8.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

8.4.3 Match Modes (Forced or Tagged) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

8.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

8.4.5 Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

8.4.6 Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

8.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

8.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

8.5.1 State Machine scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

8.5.2 Scenario 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340

8.5.3 Scenario 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

8.5.4 Scenario 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

8.5.5 Scenario 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

8.5.6 Scenario 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

8.5.7 Scenario 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

8.5.8 Scenario 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

8.5.9 Scenario 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

8.5.10 Scenario 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

8.5.11 Scenario 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

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Chapter 9

Security (S12XS9SECV2)

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

9.1.3 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

9.1.4 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

9.1.5 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

9.1.6 Reprogramming the Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

9.1.7 Complete Memory Erase (Special Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

Chapter 10

S12 Clock, Reset and Power Management Unit (S12CPMU)

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

10.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

10.1.3 S12CPMU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

10.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

10.2.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

10.2.2 EXTAL and XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

10.2.3 VDDR — Regulator Power Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

10.2.4 VSS — Ground Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

10.2.5 VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 360

10.2.6 VDDX, VSSX— Pad Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

10.2.7 VDD — Internal Regulator Output Supply (Core Logic) . . . . . . . . . . . . . . . . . . . . . . . 361

10.2.8 VDDF — Internal Regulator Output Supply (NVM Logic) . . . . . . . . . . . . . . . . . . . . . 361

10.2.9 API_EXTCLK — API external clock output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

10.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

10.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389

10.4.1 Phase Locked Loop with Internal Filter (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389

10.4.2 Startup from Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

10.4.3 Stop Mode using PLLCLK as Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

10.4.4 Full Stop Mode using Oscillator Clock as Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . . . 391

10.4.5 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

10.4.6 System Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

10.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

10.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

10.5.2 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

10.5.3 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

10.5.4 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

10.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398

10.6.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398

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10.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400

10.7.1 General Initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400

10.7.2 Application information for COP and API usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400

Chapter 11

Analog-to-Digital Converter (ADC10B8CV2)

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

11.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

11.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408

11.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

11.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

11.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

11.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

11.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

11.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

Chapter 12

Analog-to-Digital Converter (ADC12B8CV2)

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

12.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

12.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

12.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

12.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

12.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

12.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

12.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

Chapter 13

Analog-to-Digital Converter (ADC10B12CV2)

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

13.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

13.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

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13.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

13.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

13.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

13.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

13.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

13.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

13.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

Chapter 14

Analog-to-Digital Converter (ADC12B12CV2)

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

14.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

14.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

14.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

14.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488

14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

14.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

14.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

14.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

14.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

Chapter 15

Analog-to-Digital Converter (ADC10B16CV2)

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

15.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

15.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

15.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

15.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

15.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

15.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

15.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

15.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

15.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

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Chapter 16

Analog-to-Digital Converter (ADC12B16CV2)

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

16.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

16.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

16.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

16.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

16.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

16.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

16.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558

16.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558

Chapter 17

Digital Analog Converter (DAC_8B5V)

17.1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559

17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559

17.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

17.2.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

17.2.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

17.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

17.3.1 DACU Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

17.3.2 AMP Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

17.3.3 AMPP Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

17.3.4 AMPM Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562

17.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562

17.4.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562

17.4.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

17.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

17.5.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

17.5.2 Mode “Off” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565

17.5.3 Mode “Operational Amplifier” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565

17.5.4 Mode “Unbuffered DAC” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

17.5.5 Mode “Unbuffered DAC with Operational Amplifier” . . . . . . . . . . . . . . . . . . . . . . . . . 566

17.5.6 Mode “Buffered DAC” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

17.5.7 Analog output voltage calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

Chapter 18

Scalable Controller Area Network (S12MSCANV3)

18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569

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18.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570

18.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570

18.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

18.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

18.2.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

18.2.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

18.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

18.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

18.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574

18.3.3 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603

18.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603

18.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604

18.4.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607

18.4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

18.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

18.4.6 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619

18.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619

18.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621

18.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621

18.5.2 Bus-Off Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621

Chapter 19

Pulse-Width Modulator (S12PWM8B8CV2)

19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623

19.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623

19.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623

19.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624

19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624

19.2.1 PWM7 - PWM0 — PWM Channel 7 - 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624

19.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

19.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

19.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640

19.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640

19.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643

19.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

19.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

Chapter 20

Serial Communication Interface (S12SCIV5)

20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653

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20.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653

20.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

20.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

20.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

20.2.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

20.2.2 RXD — Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

20.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

20.3.1 Module Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656

20.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656

20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

20.4.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668

20.4.2 LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

20.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

20.4.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

20.4.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672

20.4.6 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677

20.4.7 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685

20.4.8 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

20.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

20.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

20.5.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

20.5.3 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687

20.5.4 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

20.5.5 Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

Chapter 21

Serial Peripheral Interface (S12SPIV5)

21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

21.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

21.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

21.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692

21.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692

21.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

21.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

21.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

21.2.3 SS

21.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

21.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

21.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

21.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695

21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

21.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704

21.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

21.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

— Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

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21.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712

21.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713

21.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714

21.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715

Chapter 22

Timer Module (TIM16B6CV3)

22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719

22.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719

22.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720

22.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720

22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721

22.2.1 IOC5 - IOC0 — Input Capture and Output Compare Channel 5-0 . . . . . . . . . . . . . . . . 721

22.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721

22.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721

22.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721

22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733

22.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734

22.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735

22.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735

22.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736

22.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736

22.6.1 Channel [5:0] Interrupt (C[5:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736

22.6.2 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736

Chapter 23

Timer Module (TIM16B8CV3)

23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737

23.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737

23.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738

23.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738

23.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741

23.2.1 IOC7 — Input Capture and Output Compare Channel 7 . . . . . . . . . . . . . . . . . . . . . . . . 741

23.2.2 IOC6 - IOC0 — Input Capture and Output Compare Channel 6-0 . . . . . . . . . . . . . . . . 741

23.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741

23.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741

23.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742

23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758

23.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760

23.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760

23.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760

23.4.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761

23.4.5 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762

23.4.6 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762

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23.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762

23.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762

23.6.1 Channel [7:0] Interrupt (C[7:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763

23.6.2 Pulse Accumulator Input Interrupt (PAOVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763

23.6.3 Pulse Accumulator Overflow Interrupt (PAOVF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763

23.6.4 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763

Chapter 24

16 KByte Flash Module (S12FTMRG16K1V1)

24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765

24.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766

24.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766

24.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767

24.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768

24.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769

24.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769

24.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772

24.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789

24.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789

24.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789

24.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789

24.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789

24.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . 794

24.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795

24.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809

24.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

24.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

24.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

24.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

24.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 811

24.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 812

24.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812

Chapter 25

32 KByte Flash Module (S12FTMRG32K1V1)

25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813

25.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814

25.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814

25.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815

25.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816

25.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817

25.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817

25.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820

25.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839

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25.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839

25.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839

25.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840

25.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840

25.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . 845

25.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846

25.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860

25.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861

25.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861

25.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861

25.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861

25.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 862

25.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 863

25.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863

Chapter 26

48 KByte Flash Module (S12FTMRG48K1V1)

26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865

26.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866

26.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866

26.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868

26.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868

26.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869

26.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869

26.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873

26.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892

26.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892

26.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892

26.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893

26.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893

26.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . 898

26.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899

26.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913

26.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914

26.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914

26.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914

26.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914

26.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 915

26.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 916

26.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916

Chapter 27

64 KByte Flash Module (S12FTMRG64K1V1)

27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917

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27.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918

27.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918

27.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919

27.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920

27.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921

27.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921

27.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924

27.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943

27.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943

27.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943

27.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944

27.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944

27.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . 949

27.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950

27.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964

27.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965

27.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965

27.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965

27.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965

27.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 966

27.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 967

27.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967

Chapter 28

96 KByte Flash Module (S12FTMRG96K1V1)

28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969

28.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970

28.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970

28.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971

28.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972

28.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973

28.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973

28.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976

28.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995

28.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995

28.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995

28.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996

28.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996

28.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . 1001

28.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002

28.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016

28.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017

28.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017

28.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017

28.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017

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28.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1018

28.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . 1019

28.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019

Chapter 29

128 KByte Flash Module (S12FTMRG128K1V1)

29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021

29.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022

29.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023

29.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023

29.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024

29.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025

29.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025

29.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029

29.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047

29.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047

29.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047

29.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048

29.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048

29.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . 1053

29.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054

29.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068

29.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069

29.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069

29.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069

29.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069

29.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1070

29.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . 1071

29.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071

Chapter 30

192 KByte Flash Module (S12FTMRG192K2V1)

30.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073

30.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074

30.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074

30.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075

30.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076

30.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077

30.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077

30.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081

30.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099

30.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099

30.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099

30.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100

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30.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100

30.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . 1105

30.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106

30.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119

30.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120

30.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120

30.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121

30.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121

30.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1122

30.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . 1122

30.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122

Chapter 31

240 KByte Flash Module (S12FTMRG240K2V1)

31.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125

31.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126

31.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126

31.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127

31.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128

31.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129

31.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129

31.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133

31.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151

31.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151

31.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151

31.4.3 Internal NVM resource (NVMRES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152

31.4.4 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152

31.4.5 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . 1157

31.4.6 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1158

31.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171

31.4.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172

31.4.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172

31.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173

31.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173

31.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1174

31.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . 1174

31.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174

Appendix A

Electrical Characteristics

A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178

A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178

A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178

A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179

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A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179

A.1.5 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179

A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180

A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1181

A.1.8 Power Dissipation and Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183

A.2 I/O Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187

A.3 Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191

A.3.1 Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191

A.4 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196

A.4.1 ADC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196

A.4.2 Factors Influencing Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197

A.4.3 ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198

A.4.4 ADC Temperature Sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208

A.5 ACMP Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208

A.6 DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210

A.7 NVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211

A.7.1 Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211

A.7.2 NVM Reliability Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1216

A.8 Phase Locked Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217

A.8.1 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217

A.8.2 Electrical Characteristics for the PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219

A.9 Electrical Characteristics for the IRC1M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219

A.10 Electrical Characteristics for the Oscillator (XOSCLCP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1221

A.11 Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222

A.12 Electrical Specification for Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223

A.13 Chip Power-up and Voltage Drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225

A.14 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226

A.15 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227

A.15.1 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227

A.15.2 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229

A.16 ADC Conversion Result Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231

Appendix B

Detailed Register Address Map

B.1 Detailed Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233

Appendix C

Ordering and Shipping Information

C.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253

Appendix D

Package and Die Information

D.1 100 LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256

D.2 64 LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259

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D.3 48 LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262

D.4 48 QFN Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264

D.5 32 LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267

D.6 20 TSSOP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270

D.7 KGD Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273

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Chapter 1 Device Overview MC9S12G-Family

Revision History

Version Number

Rev 0.27 1-Apr-2011 • Typos and formatting Rev 0.28 11-May-2011 • Rev 0.29 10-Jan-2011 • Corrected Figure 1-4 Rev 0.30 10-Feb-2012 • Updated Ta b le 1 -5(added mask set 1N75C)

Rev 0.31 15-Mar-2012 • Updated Tab l e 1- 1 (added S12GSA devices)

Rev 0.32 07-May-2012 • Updated Section 1.19, “BDM Clock Source Connectivity”

Rev 0.33 27-Sep-2012 • Corrected Figure 1-4

Rev 0.34 25-Jan-2013 Added KGD option for the S12GA192 and the S12GA240

Rev 0.35 02-Jul-2014 • Corrected Ta ble 1 -2 Rev 0.36 14-Jun-2017 • Extended Table 1-5

Revision

Date

Description of Changes

• Typos and formatting

• Updated Figure 1-1

• Updated Ta bl e 1 -5 (added S12GA devices)

• Added Section 1.8.2, “S12GNA16 and S12GNA32”

• Added Section 1.8.5, “S12GA48 and S12GA64”

• Added Section 1.8.7, “S12GA96 and S12GA128”

• Typos and formatting

• Corrected Figure 1-5

• Corrected Figure 1-6

• Updated Ta bl e 1 -1

• Corrected Ta bl e 1 - 2

• Corrected Ta bl e 1 - 6

1.1 Introduction

The MC9S12G-Family is an optimized, automotive, 16-bit microcontroller product line focused on low-cost, high-performance, and low pin-count. This family is intended to bridge between high-end 8-bit microcontrollers and high-performance 16-bit microcontrollers, such as the MC9S12XS-Family. The MC9S12G-Family is targeted at generic automotive applications requiring CAN or LIN/J2602 communication. T ypical examples of these applications include body controllers, occupant detection, door modules, seat controllers, RKE receivers, smart actuators, lighting modules, and smart junction boxes.

The MC9S12G-Family uses many of the same features found on the MC9S12XS- and MC9S12P-Family , including error correction code (ECC) on flash memory, a fast analog-to-digital converter (ADC) and a frequency modulated phase locked loop (IPLL) that improves the EMC performance.

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Device Overview MC9S12G-Family

The MC9S12G-Family is optimized for lower program memory sizes down to 16k. In order to simplify customer use it features an EEPROM with a small 4 bytes erase sector size.

The MC9S12G-Family deliver all the advantages and efficiencies of a 16-bit MCU while retaining the low cost, power consumption, EMC, and code-size efficiency advantages currently enjoyed by users of NXP’ s existing 8-bit and 16-bit MCU families. Like the MC9S12XS-Family, the MC9S12G-Family run 16-bit wide accesses without wait states for all peripherals and memories. The MC9S12G-Family is available in 100-pin LQFP, 64-pin LQFP, 48-pin LQFP/QFN, 32-pin LQFP and 20-pin TSSOP package options and aims to maximize the amount of functionality especially for the lower pin count packages. In addition to the I/O ports available in each module, further I/O ports are available with interrupt capability allowing wake-up from stop or wait modes.

1.2 Features

This section describes the key features of the MC9S12G-Family.

1.2.1 MC9S12G-Family Comparison

Table 1-1 provides a summary of different members of the MC9S12G-Family and their features. This

information is intended to provide an understanding of the range of functionality offered by this microcontroller family.

Table 1-1. MC9S12G-Family Overview

Feature

S12GN16

S12GNA16

S12GN32

S12GNA32

S12GN48

S12G48

S12GA48

S12G64

S12GA64

S12G96

S12GA96

S12G128

S12GA128

S12G192

S12GA192

S12G240

S12GA240

CPU CPU12V1

Flash memory [kBytes]

EEPROM [kBytes] 0.5 0.5 1 1 1.5 1.5 1.5 2233444444

RAM [kBytes] 112244444888811111111

MSCAN ————— 111111111111

SCI 11112222233333333

SPI 11112222233333333

16-Bit Timer channels

8-Bit PWM channels66666666688888888

10-Bit ADC channels 8 — 8 — 12 12 — 12 — 12 — 12 — 16 — 16 —

12-Bit ADC channels — 8 — 8 — — 12 — 12 — 12 — 12 — 16 — 16

Temperature Sensor——————————————Yes—Yes

RVA ——————————————YES—YES

8-Bit DAC —————————————— 2 — 2

16 16 32 32 48 48 48 64 64 96 96 128 128 192 192 240 240

66666666688888888

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Table 1-1. MC9S12G-Family Overview

Feature

S12GN16

S12GNA16

S12GN32

S12GNA32

S12GN48

S12G48

S12GA48

S12G64

S12GA64

ACMP (analog comparator)

PLL Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

External osc Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

Internal 1 MHz RC oscillator

20-pin TSSOP Yes—Yes——————————————

32-pin LQFP Yes—Yes—YesYes—Yes—————————

48-pin LQFP Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

48-pin QFN YesYesYesYes—————————————

64-pin LQFP ————YesYesYesYesYesYesYesYesYesYesYesYesYes

100-pin LQFP —————————YesYesYesYesYesYesYesYes

KGD ——————————————Yes—Yes

Supply voltage 3.13 V – 5.5 V

Execution speed Static – 25 MHz

Not all peripherals are available in all package types

111111111————————

Yes Ye s Yes Ye s Ye s Yes Ye s Ye s Yes Ye s Ye s Yes Ye s Ye s Yes Ye s Ye s

S12G96

S12GA96

S12G128

S12GA128

S12G192

S12GA192

S12G240

S12GA240

Table 1-2shows the maximum number of peripherals or peripheral channels per package type. Not all

peripherals are available at the same time. The maximum number of peripherals is also limited by the device chosen as per Table 1-1.

Table 1-2. Maximum Peripheral Availability per Package

Peripheral 20 TSSOP 32 LQFP 48 QFN 48 LQFP 64 LQFP 100 LQFP KGD (Die)

MSC AN — Yes — Yes Ye s Ye s Yes

SCI 0 Yes Yes Yes Ye s Ye s Ye s Yes

SCI1 — Yes Yes Yes Yes Yes Yes

SCI2 — — — Yes Yes Yes Yes

SPI0 Yes Yes Yes Yes Yes Yes Yes

SPI1 — — — Yes Yes Yes Yes

SPI2 — — — — Yes Yes Yes

Timer Channels 4 = 0 … 3 6 = 0 … 5 6 = 0 … 5 8 = 0 … 7 8 = 0 … 7 8 = 0 … 7 8 = 0 … 7

8-Bit PWM Channels 4 = 0 … 3 6 = 0 … 5 6 = 0 … 5 8 = 0 … 7 8 = 0 … 7 8 = 0 … 7 8 = 0 … 7

ADC channels 6 = 0 … 5 8 = 0 … 7 8 = 0 … 7 12 = 0 … 11 16 = 0 … 15 16 = 0 … 15 16 = 0 … 15

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Table 1-2. Maximum Peripheral Availability per Package

Peripheral 20 TSSOP 32 LQFP 48 QFN 48 LQFP 64 LQFP 100 LQFP KGD (Die)

DAC0 — — — Yes Yes Yes Yes

DAC1 — — — Yes Yes Yes Yes

ACM P Yes Yes Yes Ye s Ye s — —

Total GPIO 14 26 40 40 54 86 86

1.2.2 Chip-Level Features

On-chip modules available within the family include the following features:

• S12 CPU core

• Up to 240 Kbyte on-chip flash with ECC

• Up to 4 Kbyte EEPROM with ECC

• Up to 11 Kbyte on-chip SRAM

• Phase locked loop (IPLL) frequency multiplier with internal filter

• 4–16 MHz amplitude controlled Pierce oscillator

• 1 MHz internal RC oscillator

• Timer module (TIM) supporting up to eight channels that provide a range of 16-bit input capture, output compare, counter, and pulse accumulator functions

• Pulse width modulation (PWM) module with up to eight x 8-bit channels

• Up to 16-channel, 10 or 12-bit resolution successive approximation analog-to-digital converter (ADC)

• Up to two 8-bit digital-to-analog converters (DAC)

• Up to one 5V analog comparator (ACMP)

• Up to three serial peripheral interface (SPI) modules

• Up to three serial communication interface (SCI) modules supporting LIN communications

• Up to one multi-scalable controller area network (MSCAN) module (supporting CAN protocol

2.0A/B)

• On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages

• Autonomous periodic interrupt (API)

• Precision fixed voltage reference for ADC conversions

• Optional reference voltage attenuator module to increase ADC accuracy

1.3 Module Features

The following sections provide more details of the modules implemented on the MC9S12G-Family family .

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1.3.1 S12 16-Bit Central Processor Unit (CPU)

S12 CPU is a high-speed 16-bit processing unit:

• Full 16-bit data paths supports efficient arithmetic operation and high-speed math execution

• Includes many single-byte instructions. This allows much more efficient use of ROM space.

• Extensive set of indexed addressing capabilities, including: — Using the stack pointer as an indexing register in all indexed operations — Using the program counter as an indexing register in all but auto increment/decrement mode — Accumulator offsets using A, B, or D accumulators — Automatic index predecrement, preincrement, postdecrement, and postincrement (by –8 to +8)

1.3.2 On-Chip Flash with ECC

On-chip flash memory on the MC9S12G-Family family features the following:

• Up to 240 Kbyte of program flash memory — 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit error correction

and double fault detection — Erase sector size 512 bytes — Automated program and erase algorithm — User margin level setting for reads — Protection scheme to prevent accidental program or erase

• Up to 4 Kbyte EEPROM — 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction

and double fault detection — Erase sector size 4 bytes — Automated program and erase algorithm — User margin level setting for reads

1.3.3 On-Chip SRAM

• Up to 11 Kbytes of general-purpose RAM

1.3.4 Port Integration Module (PIM)

• Data registers and data direction registers for ports A, B, C, D, E, T, S, M, P , J and AD when used as general-purpose I/O

• Control registers to enable/disable pull devices and select pullups/pulldowns on ports T, S, M, P , J and AD on per-pin basis

• Single control register to enable/disable pull devices on ports A, B, C, D and E, on per-port basis and on BKGD pin

• Control registers to enable/disable open-drain (wired-or) mode on ports S and M

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Device Overview MC9S12G-Family

• Interrupt flag register for pin interrupts on ports P, J and AD

• Control register to configure IRQ pin operation

• Routing register to support programmable signal redirection in 20 TSSOP only

• Routing register to support programmable signal redirection in 100 LQFP package only

• Package code register preset by factory related to package in use, writable once after reset. Also includes bit to reprogram routing of API_EXTCLK in all packages.

• Control register for free-running clock outputs

•

1.3.5 Main External Oscillator (XOSCLCP)

• Loop control Pierce oscillator using a 4 MHz to 16 MHz crystal — Current gain control on amplitude output — Signal with low harmonic distortion — Low power — Good noise immunity — Eliminates need for external current limiting resistor — Transconductance sized for optimum start-up margin for typical crystals — Oscillator pins can be shared w/ GPIO functionality

1.3.6 Internal RC Oscillator (IRC)

• Trimmable internal reference clock. — Frequency: 1 MHz — Trimmed accuracy over –40°C to +125°C ambient temperature range:

1.0% for temperature option C and V (see Table A-4) 1.3% for temperature option M (see Table A-4)

1.3.7 Internal Phase-Locked Loop (IPLL)

• Phase-locked-loop clock frequency multiplier — No external components required — Reference divider and multiplier allow large variety of clock rates — Automatic bandwidth control mode for low-jitter operation — Automatic frequency lock detector — Configurable option to spread spectrum for reduced EMC radiation (frequency modulation) — Reference clock sources:

– External 4–16 MHz resonator/crystal (XOSCLCP) – Internal 1 MHz RC oscillator (IRC)

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1.3.8 System Integrity Support

• Power-on reset (POR)

• System reset generation

• Illegal address detection with reset

• Low-voltage detection with interrupt or reset

• Real time interrupt (RTI)

• Computer operating properly (COP) watchdog — Configurable as window COP for enhanced failure detection — Initialized out of reset using option bits located in flash memory

• Clock monitor supervising the correct function of the oscillator

1.3.9 Timer (TIM)

• Up to eight x 16-bit channels for input capture or output compare

• 16-bit free-running counter with 7-bit precision prescaler

• In case of eight channel timer Version an additional 16-bit pulse accumulator is available

1.3.10 Pulse Width Modulation Module (PWM)

• Up to eight channel x 8-bit or up to four channel x 16-bit pulse width modulator — Programmable period and duty cycle per channel — Center-aligned or left-aligned outputs — Programmable clock select logic with a wide range of frequencies

1.3.11 Controller Area Network Module (MSCAN)

• 1 Mbit per second, CAN 2.0 A, B software compatible — Standard and extended data frames — 0–8 bytes data length — Programmable bit rate up to 1 Mbps

• Five receive buffers with FIFO storage scheme

• Three transmit buffers with internal prioritization

• Flexible identifier acceptance filter programmable as: — 2 x 32-bit — 4 x 16-bit — 8 x 8-bit

• Wakeup with integrated low pass filter option

• Loop back for self test

• Listen-only mode to monitor CAN bus

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• Bus-off recovery by software intervention or automatically

• 16-bit time stamp of transmitted/received messages

1.3.12 Serial Co mmunication Interface Module (SCI)

• Up to three SCI modules

• Full-duplex or single-wire operation

• Standard mark/space non-return-to-zero (NRZ) format

• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths

• 13-bit baud rate selection

• Programmable character length

• Programmable polarity for transmitter and receiver

• Active edge receive wakeup

• Break detect and transmit collision detect supporting LIN 1.3, 2.0, 2.1 and SAE J2602

1.3.13 Serial Periph eral Interface Module (SPI)

• Up to three SPI modules

• Configurable 8- or 16-bit data size

• Full-duplex or single-wire bidirectional

• Double-buffered transmit and receive

• Master or slave mode

• MSB-first or LSB-first shifting

• Serial clock phase and polarity options

1.3.14 Analog-to-Digital Converter Module (ADC)

Up to 16-channel, 10-bit/12-bit1 analog-to-digital converter

— 3 us conversion time —8-/10 — Left or right justified result data — Wakeup from low power modes on analog comparison > or <= match — Continuous conversion mode — External triggers to initiate conversions via GPIO or peripheral outputs such as PWM or TIM — Multiple channel scans — Precision fixed voltage reference for ADC conversions

-bit resolution

—

• Pins can also be used as digital I/O including wakeup capability

1. 12-bit resolution only available on S12GA192 and S12GA240 devices.

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1.3.15 Reference Voltage Attenuator (RVA)

• Attenuation of ADC reference voltage with low long-term drift

1.3.16 Digital-to-Analog Converter Module (DAC)

• 1 digital-analog converter channel (per module) with: — 8 bit resolution — full and reduced output voltage range — buffered or unbuffered analog output voltage usable

• operational amplifier stand alone usable

1.3.17 Analog Comparator (ACMP)

• Low offset, low long-term offset drift

• Selectable interrupt on rising, falling, or rising and falling edges of comparator output

• Option to output comparator signal on an external pin

• Option to trigger timer input capture events

1.3.18 On-Chip Voltage Regulator (VREG)

• Linear voltage regulator with bandgap reference

• Low-voltage detect (LVD) with low-voltage interrupt (LVI)

• Power-on reset (POR) circuit

• Low-voltage reset (LVR)

1.3.19 Background Debug (BDM)

• Non-intrusive memory access commands

• Supports in-circuit programming of on-chip nonvolatile memory

1.3.20 Debugger (DBG)

• Trace buffer with depth of 64 entries

• Three comparators (A, B and C) — Access address comparisons with optional data comparisons — Program counter comparisons — Exact address or address range comparisons

• Two types of comparator matches — Tagged This matches just before a specific instruction begins execution — Force This is valid on the first instruction boundary after a match occurs

• Four trace modes

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Device Overview MC9S12G-Family

• Four stage state sequencer

1.4 Key Performance Parameters

The key performance parameters of S12G devices feature:

• Continuous Operating voltage of 3.15 V to 5.5 V

• Operating temperature (TA) of –40°C to 125°C

• Junction temperature (TJ) of up to 150°C

• Bus frequency (f

• Packaging: — 100-pin LQFP, 0.5 mm pitch, 14 mm x 14 mm outline — 64-pin LQFP, 0.5 mm pitch, 10 mm x 10 mm outline — 48-pin LQFP, 0.5 mm pitch, 7 mm x 7 mm outline — 48-pin QFN, 0.5 mm pitch, 7 mm x 7 mm outline — 32-pin LQFP, 0.8 mm pitch, 7 mm x 7 mm outline — 20 TSSOP, 0.65 mm pitch, 4.4 mm x 6.5 mm outline — Known good die (KGD), unpackaged

) of dc to 25 MHz

Bus

1.5 Block Diagram

Figure 1-1 shows a block diagram of the MC9S12G-Family.

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1K … 11K bytes RAM

RESET

EXTAL

XTAL

0.5K … 4K bytes EEPROM with ECC

BKGD

VDDR

Real Time Interrupt

Clock Monitor

Single-wire Background

TEST

Debug Module

ADC

Interrupt Module

(WU Int)

SCI0

PS3

PS0 PS1 PS2

PTS

AN[15:0]

PAD [15:0]

8...16 ch.

16-bit 6 … 8 channel Timer

TIM

Asynchronous Serial IF

8-bit 6 … 8 channel Pulse Width Modulator

PWM

PB[7:0]

PTB

PA[7:0]

PTA

16K … 240K bytes Flash with ECC

CPU12-V1

COP Watchdog

PLL with Frequency

Modulation option

Debug Module 3 comparators

64 Byte Trace Buffer

Reset Generation

and Test Entry

RXD

TXD

PJ2

PTJ (Wake-up Int)

CAN

PM3

PM0 PM1 PM2

PTM

msCAN 2.0B

RXCAN

TXCAN

Auton. Periodic Int.

PJ7

PJ6

PT3

PT0 PT1 PT2

PTT

PT7

PT4 PT5 PT6

PP3

PP0 PP1 PP2

PTP (Wake-up Int)

PP7

PP4 PP5

PWM3

PWM0 PWM1 PWM2

PWM4 PWM5

IOC3

IOC0 IOC1 IOC2

IOC7

IOC4 IOC5 IOC6

VDDA VSSA VRH

VDDX1/VSSX1 VDDX2/VSSX2

PJ0 PJ1

3-5V IO Supply

VSS

Low Power Pierce

Oscillator

PP6

PWM6 PWM7

SCI1 Asynchronous Serial IF

RXD

TXD

MOSI

SCK

MISO

SPI0

Synchronous Serial IF

PS4 PS5 PS6 PS7

SCI2 Asynchronous Serial IF

RXD

TXD

Voltage Regulator

Input: 3.13V – 5.5V

Block Diagram shows the maximum configuration!

MOSI

SCK

MISO

SPI1

Synchronous Serial IF

MOSI

SCK

MISO

SPI2

Synchronous Serial IF

PJ3 PJ4 PJ5

PD[7:0]

PTD

PC[7:0]

PTC

VDDX3/VSSX3

Not all pins or all peripherals are available on all devices and packages.

Rerouting options are not shown.

PE0

PTE

PE1

PTAD

Analog-Digital Converter

ACMP

Analog Comparator

DAC0

Digital-Analog Converter

AMPM AMP

DACU

AMPP

DAC1

Digital-Analog

Converter

12-bit or 10-bit

RVA

Internal RC Oscillator

Size

(Bytes)

Figure 1-1. MC9S12G-Family Block Diagram

1.6 Family Memory Map

Table 1-3 shows the MC9S12G-Family register memory map.

Table 1-3. Device Register Memory Map

Address Module

0x0000–0x0009 PIM (Port Integration Module

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Device Overview MC9S12G-Family

Address Module

Size

(Bytes)

0x000A–0x000B MMC (Memory Map Control) 2

0x000C–0x000D PIM (Port Integration Module) 2

0x000E–0x000F Reserved 2

0x0010–0x0017 MMC (Memory Map Control) 8

0x0018–0x0019 Reserved 2

0x001A–0x001B Device ID register 2

0x001C–0x001F PIM (Port Integration Module) 4

0x0020–0x002F DBG (Debug Module) 16

0x0030–0x0033 Reserved 4

0x0034–0x003F CPMU (Clock and Power Management) 12

0x0040–0x006F TIM (Timer Module <= 8 channels) 48

0x0070–0x009F ADC (Analog to Digital Converter <= 16 channels) 48

0x00A0–0x00C7 PWM (Pulse-Width Modulator <= 8 channels) 40

0x00C8–0x00CF SCI0 (Serial Communication Interface) 8

0x00D0–0x00D7 SCI1 (Serial Communication Interface)

0x00D8–0x00DF SPI0 (Serial Peripheral Interface) 8

0x00E0–0x00E7 Reserved 8

0x00E8–0x00EF SCI2 (Serial Communication Interface)

0x00F0–0x00F7 SPI1 (Serial Peripheral Interface)

0x00F8–0x00FF SPI2 (Serial Peripheral Interface)

0x0100–0x0113 FTMRG control registers 20

0x0114–0x011F Reserved 12

0x0120 INT (Interrupt Module) 1

0x0121–0x013F Reserved 31

0x0140–0x017F CAN

0x0180–0x023F Reserved 192

0x0240–0x025F PIM (Port Integration Module) 32

0x0260–0x0261 ACMP (Analog Comparator)

0x0262–0x0275 PIM (Port Integration Module) 20

0x0276 RVA (Reference Voltage Attenuator)

0x0277–0x027F PIM (Port Integration Module) 9

0x0280–0x02EF Reserved 112

0x02F0–0x02FF CPMU (Clock and Power Management) 16

0x0300–0x03BF Reserved 192

0x03C0–0x03C7 DAC0 (Digital to Analog Converter)

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Address Module

0x03C8–0x03CF DAC1 (Digital to Analog Converter)

0x03D0–0x03FF Reserved 48

The SCI1 is not available on the S12GN8, S12GN16, S12GN32, and S12GN32 devices

The SCI2 is not available on the S12GN8, S12GN16, S12GN32, S12GN32, S12G48, and S12G64 devices

The SPI1 is not available on the S12GN8, S12GN16, S12GN24, and S12GN32 devices

The SPI2 is not available on the S12GN8, S12GN16, S12GN32, S12GN32, S12G48, and S12G64 devices

The CAN is not available on the S12GN8, S12GN16, S12GN24, S12GN32, and S12GN48 devices

The ACMP is only available on the S12GN8, S12GN16, S12GN24, S12GN32, S12GN48,S12GN48, S12G48, and S12G64 devices

The RVA is only available on the S12GA192 and S12GA240 devices

DAC0 and DAC1 are only available on the S12GA192 and S12GA240 devices

Size

(Bytes)

NOTE

Reserved register space shown in Table 1-3 is not allocated to any module. This register space is reserved for future use. W riting to these loc ations has no effect. Read access to these locations returns zero.

Figure 1-2 shows S12G CPU and BDM local address translation to the global memor y map as a graphical

representation. In conjunction Table 1-4 shows the address ranges and mapping to 256K global memory space for P-Flash, EEPROM and RAM. The whole 256K global memory space is visible through the P-Flash window located in the 64k local memory map located at 0x8000 - 0xBFFF using the PPAGE register.

Table 1-4. MC9S12G-Family Memory Parameters

Feature S12GN16 S12GN32

P-Flash size 16KB 32KB 48KB 64KB 96KB 128KB 192KB 240KB

PF_LOW 0x3C000 0x38000 0x34000 0x30000 0x28000 0x20000 0x10000 0x04000

PF_LOW_UNP (unpaged)

PPAGES

EEPROM [Bytes]

EEPROM_HI 0x05FF 0x07FF 0x09FF 0x0BFF 0x0FFF 0x13FF 0x13FF 0x13FF

0xC0000x80000x4000—————

0x0E -

0x0F

512 1024 1536 2048 3072 4096 4096 4096

0x0F

S12G48

S12GN48

0x0D -

0x0F

S12G64 S12G96 S12G128

0x0C -

0x0F

0x0A -

0x0F

0x08 -

0x0F

S12G192

S12GA192

0x04 -

0x0F

S12G240

S12GA240

0x01 -

0x0F

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Table 1-4. MC9S12G-Family Memory Parameters

Feature S12GN16 S12GN32

S12G48

S12GN48

S12G64 S12G96 S12G128

S12G192

S12GA192

S12G240

S12GA240

RAM [Bytes] 1024 2048 4096 4096 8192 8192 11264 11264

RAM_LOW 0x3C00 0x3800 0x3000 0x3000 0x2000 0x2000 0x1400 0x1400

Unpaged Flash space left

Unpaged Flash

While for memory sizes <64K the whole 256k space could be addressed using the PPAGE, it is more efficient to use

— — — 0x0C00-

0x2FFF

— — — 9KB 4KB 3KB — —

0x1000-

0x1FFF

0x1400-

0x1FFF

——

an unpaged memory model

Page 0xC

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Paging Window

0x3_FFFF

Local CPU and BDM

Memory Map Global Memory Map

0xFFFF

0xC000

0x0_0400

0x0_0000

0x3_C000

0x0000

0x8000

0x0400

0x4000

0x0_4000

Paging Window

Flash

Space

Flash

Space

RAM

Unimplemented

Flash Space

Internal

NVM

Resources

Internal

NVM

Resources

Flash Space

EEPROM

Page 0x1

Page 0xF

Page 0xD

Page 0xC

Page 0xE

Page 0xF

Page 0xD

Page 0xC

NVMRES=0

NVMRES=1

Flash Space

Page 0x2

0x3_0000

0x3_4000

0x3_8000

0x0_8000

RAM

Device Overview MC9S12G-Family

Figure 1-2. MC9S12G Global Memory Map

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1.6.1 Part ID Assignments

The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B). The read-only value is a unique part ID for each revision of the chip. Table 1-5 shows the assigned part ID number and Mask Set number.

Table 1-5. Assigned Part ID Numbers

Device Mask Set Number Part ID

MC9S12GA240 0N95B 0xF080

MC9S12G240 0N95B 0xF080

MC9S12GA192 0N95B 0xF080

MC9S12G192 0N95B 0xF080

MC9S12GA128

MC9S12G128

MC9S12GA96

MC9S12G96

MC9S12GA64

MC9S12G64

MC9S12GA48

MC9S12G48

MC9S12GN48

MC9S12GNA32

MC9S12GN32

0N51A 0xF180

0N42V 0xF180

0N51A 0xF180

0N42V 0xF180

0N51A 0xF180

0N42V 0xF180

0N51A 0xF180

0N42V 0xF180

0N75C 0xF280

0N55V 0xF280

0N75C

0N55V

1N75C

1N55V

0xF280

0xF281

0N75C 0xF280

0N55V 0xF280

0N75C

0N55V

1N75C

1N55V

0N75C

0N55V

1N75C

1N55V

0xF280

0xF281

0xF280

0xF281

0N48A 0xF380

0N57V 0xF380

0N48A

0N57V

1N48A

1N57V

0xF380

0xF381

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Table 1-5. Assigned Part ID Numbers

Device Mask Set Number Part ID

Device Overview MC9S12G-Family

MC9S12GNA16

MC9S12GN16

Only available in 48-pin LQFP and 64-pin LQFP

Only available in 32-pin LQFP

Only available in 48-pin LQFP and 48-pin QFN

Only available in 20-pin TSSOP and 32-pin LQFP

0N48A 0xF380

0N57V 0xF380

0N48A

0N57V

1N48A

1N57V

0xF380

0xF381

1.7 Signal Description and Device Pinouts

This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. It is built from the signal description sections of the individual IP blocks on the device.

1.7.1 Pin Assignment Overview

Table 1-6 provides a summary of which ports are available for each package option.

Table 1-6. Port Availability by Package Option

Port 20 TSSOP 32 LQFP

Port AD/ADC Channels 6 8 12 16 16 16

Port A pins 000088

Port B pins 000088

Port C pins 000088

Port D pins 000088

Port E pins 222222

Port J 004888

Port M 022444

Port P 046888

Port S 468888

Port T 246888

MC9S12G Family Reference Manual Rev.1.27

48 LQFP

48 QFN

64 LQFP 100 LQFP KGD (Die)

NXP Semiconductors 45

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Device Overview MC9S12G-Family

Table 1-6. Port Availability by Package Option

Port 20 TSSOP 32 LQFP

Sum of Ports 142640548686

I/O Power Pairs VDDX/VSSX 1/1 1/1 1/1 1/1 3/3 3/3

48 LQFP

48 QFN

64 LQFP 100 LQFP KGD (Die)

NOTE

To avoid current drawn from floating inputs, the input buffers of all non-bonded pins are disabled.

1.7.2 Detailed Signal Descriptions

This section describes the signal properties. The relation between signals and package pins is described in section 1.8 Device Pinouts.

1.7.2.1 RESET — External Reset Signal

The RESET signal is an active low bidirectional control signal. It acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset. The RESET pin has an internal pull-up device.

1.7.2.2 TEST — Test Pin

This input only pin is reserved for factory test. This pin has an internal pull-down device.

NOTE

The TEST pin must be tied to ground in all applications.

1.7.2.3 BKGD / MODC — Background Debug and Mode Pin

The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET

. The BKGD pin has an internal pull-up device.

1.7.2.4 EXTAL, XTAL — Oscillator Signal

EXTAL and XTAL are the crystal driver and external clock signals. On reset all the device clocks are derived from the internal reference clock. XTAL is the oscillator output.

1.7.2.5 PAD[15:0] / KWAD[15:0] — Port AD Input Pins of ADC

PAD[15:0] are general-purpose input or output signals. These signals can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull devices are disabled.

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Device Overview MC9S12G-Family

1.7.2.6 PA[7:0] — Port A I/O Signals

PA[7:0] are general-purpose input or output signals. The signals can have pull-up devices, enabled by a single control bit for this signal group. Out of reset the pull-up devices are disabled .

1.7.2.7 PB[7:0] — Port B I/O Signals

PB[7:0] are general-purpose input or output signals. The signals can have pull-up devices, enabled by a single control bit for this signal group. Out of reset the pull-up devices are disabled .

1.7.2.8 PC[7:0] — Port C I/O Signals

PC[7:0] are general-purpose input or output signals. The signals can have pull-up devices, enabled by a single control bit for this signal group. Out of reset the pull-up devices are disabled .

1.7.2.9 PD[7:0] — Port D I/O Signals

PD[7:0] are general-purpose input or output signals. The signals can have pull-up device, enabled by a single control bit for this signal group. Out of reset the pull-up devices are disabled.

1.7.2.10 PE[1:0] — Port E I/O Signals

PE[1:0] are general-purpose input or output signals. The signals can have pull-down device, enabled by a single control bit for this signal group. Out of reset the pull-down devices are enabled.

1.7.2.11 PJ[7:0] / KWJ[7:0] — Port J I/O Signals

PJ[7:0] are general-purpose input or output signals. The signals can be configured on per signal basis as interrupt inputs with wakeup capability (KWJ[7:0]). They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull devices are enabled .

1.7.2.12 PM[3:0] — Port M I/O Signals

PM[3:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull devices are disabled. The signals can be configured on per pin basis to open-drain mode.

1.7.2.13 PP[7:0] / KWP[7:0] — Port P I/O Signals

PP[7:0] are general-purpose input or output signals. The signals can be configured on per signal basis as interrupt inputs with wakeup capability (KWP[7:0]). They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull devices are disabled .

1.7.2.14 PS[7:0] — Port S I/O Signals

PS[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull-up devices are enabled. The signals can be configured on per pin basis in open-drain mode.

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1.7.2.15 PT[7:0] — Port TI/O Signals

PT[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull devices are disabled .

1.7.2.16 AN[15:0] — ADC Input Signals

AN[15:0] are the analog inputs of the Analog-to-Digital Converter.

1.7.2.17 ACMP Signals

1.7.2.17.1 ACMPP — Non-Inverting Analog Comparator Input

ACMPP is the non-inverting input of the analog comparator.

1.7.2.17.2 ACMPM — Inverting Analog Comparator Input

ACMPM is the inverting input of the analog comparator.

1.7.2.17.3 ACMPO — Analog Comparator Output

ACMPO is the output of the analog comparator.

1.7.2.18 DAC Signals

1.7.2.18.1 DACU[1:0] Output Pins

These analog pins is used for the unbuffered analog output Voltages from the DAC0 and the DAC1 resistor network output, when the according mode is selected.

1.7.2.18.2 AMP[1:0] Output Pins

These analog pins are used for the buffered analog outputs Voltage from the operational amplifier outputs, when the according mode is selected.

1.7.2.18.3 AMPP[1:0] Input Pins

These analog input pins areused as input signals for the operational amplifiers positive input pins when the according mode is selected.

1.7.2.18.4 AMPM[1:0] Input Pins

These analog input pins are used as input signals for the operational amplifiers negative input pin when the according mode is selected.

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1.7.2.19 SPI Signals

1.7.2.19.1 SS[2:0] Signals

Those signals are associated with the slave select SS functionality of the serial peripheral interfaces SPI2-0.

1.7.2.19.2 SCK[2:0] Signals

Those signals are associated with the serial clock SCK functionality of the serial peripheral interfaces SPI2-0.

1.7.2.19.3 MISO[2:0] Signals

Those signals are associated with the MISO functionality of the serial peripheral interfaces SPI2-0. They act as master input during master mode or as slave output during slave mode.

1.7.2.19.4 MOSI[2:0] Signals

Those signals are associated with the MOSI functionality of the serial peripheral interfaces SPI2-0. They act as master output during master mode or as slave input during slave mode.

1.7.2.20 SCI Signals

1.7.2.20.1 RXD[2:0] Signals

Those signals are associated with the receive functionality of the serial communication interfaces SCI2-0.

1.7.2.20.2 TXD[2:0] Signals

Those signals are associated with the transmit functionality of the serial communication interfaces SCI2-0.

1.7.2.21 CAN signals

1.7.2.21.1 RXCAN Signal

This signal is associated with the receive functionality of the scalable controller area network controller (MSCAN).

1.7.2.21.2 TXCAN Signal

This signal is associated with the transmit functionality of the scalable controller area network controller (MSCAN).

1.7.2.22 PWM[7:0] Signals

The signals PWM[7:0] are associated with the PWM module outputs.

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Device Overview MC9S12G-Family

1.7.2.23 Internal Clock outputs

1.7.2.23.1 ECLK

This signal is associated with the output of the divided bus clock (ECLK).

NOTE

This feature is only intended for debug purposes at room temperature. It must not be used for clocking external devices in an application.

1.7.2.23.2 ECLKX2

This signal is associated with the output of twice the bus clock (ECLKX2).

NOTE

This feature is only intended for debug purposes at room temperature. It must not be used for clocking external devices in an application.

1.7.2.23.3 API_EXTCLK

This signal is associated with the output of the API clock (API_EXTCLK).

1.7.2.24 IOC[7:0] Signals

The signals IOC[7:0] are associated with the input capture or output compare functionality of the timer (TIM) module.

1.7.2.25 IRQ

This signal is associated with the maskable IRQ interrupt.

1.7.2.26 XIRQ

This signal is associated with the non-maskable XIRQ interrupt.

1.7.2.27 ETRIG[3:0]

These signals are inputs to the Analog-to-Digital Converter . Their purpose is to trigger ADC conversions.

1.7.3 Power Supply Pins

MC9S12G power and ground pins are described below. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible.

NOTE

All ground pins must be connected together in the application.

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1.7.3.1 VDDX[3:1]/VDDX, VSSX[3:1]/VSSX— Power and Ground Pins for I/O Drivers

External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are loaded. All VDDX pins are connected together internally. All VSSX pins are connected together internally.

NOTE

Not all VDDX[3:1]/VDDX and VSSX[3:1]VSSX pins are available on all packages. Refer to section 1.8 Device Pinouts for further details.

1.7.3.2 VDDR — Power Pin for Internal Voltage Regulator

Power supply input to the internal voltage regulator.

NOTE

On some packages VDDR is bonded to VDDX and the pin is named VDDXR. Refer to section 1.8 Device Pinouts for further details.

1.7.3.3 VSS — Core Ground Pin

The voltage supply of nominally 1.8V is derived from the internal voltage regulator. The return current path is through the VSS pin.

1.7.3.4 VDDA, VSSA — Power Supply Pins for DAC,ACMP, RVA, ADC and Voltage Regulator

These are the power supply and ground input pins for the digital-to-analog converter, the analog comparator, the reference voltage attenuator, the analog-to-digital converter and the voltage regulator.

NOTE

On some packages VDDA is connected with VDDXR and the common pin is named VDDXRA. On some packages the VSSA is connected to VSSX and the common pin is named VSSXA. See section Section 1.8, “Device Pinouts” for further details.

1.7.3.5 VRH — Reference Voltage Input Pin

VRH is the reference voltage input pin for the digital-to-analog converter and the analog-to-digital converter. Refer to Section 1.18, “ADC VRH/VRL Signal Connection” for further details.

On some packages VRH is tied to VDDA or VDDXRA. Refer to section 1.8

Device Pinouts for further details.

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1.7.3.6 Power and Ground Connection Summary

Table 1-7. Power and Ground Connection Summary

Mnemonic Nominal Voltage Description

VDDR 3.15V – 5.0 V External power supply for internal voltage regulator.

VSS 0V Return ground for the logic supply generated by the internal regulator

VDDX

[3:1]

VSSX

[3:1]

VDDX 3.15V – 5.0 V External power supply for I/O drivers, All packages except 100-pin feature 1 I/O supply.

VSSX 0V Return ground for I/O drivers. All packages except 100-pin provide 1 I/O ground pin.

VDDA 3.15V – 5.0 V External power supply for the analog-to-digital converter and for the reference circuit of the

VSSA 0V Return ground for VDDA analog supply

VDDXR 3.15V – 5.0 V External power supply for I/O drivers and internal voltage regulator. For the 48-pin package

VDDXRA 3.15V – 5.0 V External power supply for I/O drivers, internal voltage regulator and analog-to-digital

VSSXA 0V Return ground for I/O driver and VDDA analog supply

3.15V – 5.0 V External power supply for I/O drivers. The 100-pin package features 3 I/O supply pins.

0V Return ground for I/O drivers. The100-pin package provides 3 ground pins

internal voltage regulator.

the VDDX and VDDR supplies are combined on one pin.

converter. For the 20- and 32-pin package the VDDX, VDDR and VDDA supplies are combined on one pin.

VRH 3.15V – 5.0 V Reference voltage for the analog-to-digital converter.

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1.8 Device Pinouts

1 2 3 4 5 6 7 8 9

20 19 18 17 16 15 14 13 12 11

S12GN16 S12GN32

20-Pin TSSOP

PS5/IOC2/MOSI0 PS4/ETRIG2/PWM2/RXD0/MISO0 PAD5/KWAD5/ETRIG3/PWM3/IOC3/TXD0/AN5/ACMPM PAD4/KWAD4/ETRIG2/PWM2/IOC2/RXD0/AN4/ACMPP PAD3/KWAD3/AN3/ACMPO PAD2/KWAD2/AN2 PAD1/KWAD1/AN1 PAD0/KWAD0/AN0 PT0/IOC0/XIRQ PT1/IOC1/IRQ

SCK0/IOC3/PS6

SS0

/TXD0/PWM3/ECLK/API_EXTCLK/ETRIG3/PS7

RESET

VRH/VDDXRA

VSSXA

EXTAL/RXD0/PWM0/IOC2/ETRIG0/PE0

VSS

XTAL/TXD0/PWM1/IOC3/ETRIG1/PE1

TEST

BKGD

1.8.1 S12GN16 and S12GN32

1.8.1.1 Pinout 20-Pin TSSOP

Figure 1-3. 20-Pin TSSOP Pinout for S12GN16 and S12GN32

Table 1-8. 20-Pin TSSOP Pinout for S12GN16 and S12GN32

Device Overview MC9S12G-Family

Function

<----lowest-----PRIORITY-----highest---->

Package

2nd

Func.

3rd

Func.

4th

Func

5th

Func

6th

Func

7th

Func

8th

Func

1 PS6 IOC3 SCK0 — — — — — V

2 PS7 ETRIG3 API_EXTCLKECLK PWM3 TXD0 SS0

—V

3 RESET — — — — — — — V

Power

Supply

DDX

Internal Pull

Resistor

CTRL

PERS/PPSS Up

PULLUP

4 VDDXRA VRH — — — — — — — — —

5 VSSXA — — — — — — — — — —

6 PE0

ETRIG0 PWM0 IOC2 RXD0 EXTAL — — V

DDX

PUCR/PDPEE Down

7 VSS — — — — — — — — — —

8 PE1

9 TEST — — — — — — — N.A. RESET

10 BKGD MODC — — — — — — V

11 PT1 IOC1 IRQ

12 PT0 IOC0 XIRQ

13 PAD0 KWAD0 AN0 — — — — — V

14 PAD1 KWAD1 AN1 — — — — — V

15 PAD2 KWAD2 AN2 — — — — — V

NXP Semiconductors 53

ETRIG1 PWM1 IOC3 TXD0 XTAL — — PUCR/PDPEE Down

pin Down

Always on Up

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

—————V

MC9S12G Family Reference Manual Rev.1.27

DDX

DDA

Reset

State

Page 52

Device Overview MC9S12G-Family

Table 1-8. 20-Pin TSSOP Pinout for S12GN16 and S12GN32

Function

<----lowest-----PRIORITY-----highest---->

Package

2nd

Func.

3rd

Func.

4th

Func

5th

Func

6th

Func

7th

Func

8th

Func

16 PAD3 KWAD3 AN3 ACMPO — — — — V

17 PAD4 KWAD4 ETRIG2 PWM2 IOC2 RXD0 AN4 ACMPP V

18 PAD5 KWAD5 ETRIG3 PWM3 IOC3 TXD0 AN5 ACMPM V

19 PS4 ETRIG2 PWM2 RXD0 MISO0 — — — V

20 PS5 IOC2 MOSI0 — — — — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

Power

Supply

DDA

DDX

Internal Pull

Resistor

CTRL

Reset

State

PER1AD/PPS1AD Disabled

PERS/PPSS Up

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1.8.1.2 Pinout 32-Pin LQFP

1 2 3 4 5 6 7 8

10111213141516

24 23 22 21 20 19 18 17

32313029282726

S12GN16 s12GN32

32-Pin LQFP

PAD7/KWAD7/AN7/ACMPM PAD6/KWAD6/AN6/ACMPP PAD5/KWAD5/AN5/ACMPO PAD4/KWAD4/AN4 PAD3/KWAD3/AN3 PAD2/KWAD2/AN2 PAD1/KWAD1/AN1 PAD0/KWAD0/AN0

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

IOC3/PT3

IOC2/PT2

IRQ

/IOC1/PT1

XIRQ

/IOC0/PT0

RESET

VRH/VDDXRA

VSSXA

EXTAL/PE0

VSS

XTAL/PE1

TEST

BKGD

PM1

PM0

PS7/API_EXTCLK/ECLK/PWM5/SS0

PS6/IOC5/SCK0

PS5/IOC4/MOSI0

PS4/PWM4/MISO0

PS1/TXD0

PS0/RXD0

Device Overview MC9S12G-Family

Figure 1-4. 32-Pin LQFP OPinout for S12GN16 and S12GN32

Package Pin Pin

1 RESET — — — — V

Table 1-9. 32-Pin LQFP OPinout for S12GN16 and S12GN32

<----lowest-----PRIORITY-----highest---->

2nd

Func.

Function

3rd

Func.

4th

Func

5th

Func

Power

Supply

DDX

Internal Pull

Resistor

CTRL

PULLUP

Reset

State

2VDDXRAVRH — — —— — —

3 VSSXA — — — — — — —

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Device Overview MC9S12G-Family

Table 1-9. 32-Pin LQFP OPinout for S12GN16 and S12GN32

Package Pin Pin

4PE0

Function

<----lowest-----PRIORITY-----highest---->

2nd

Func.

EXTAL — — — — PUCR/PDPEE Down

3rd

Func.

4th

Func

5th

Func

Power

Supply

Internal Pull

Resistor

CTRL

Reset

State

5VSS— ———— — —

6PE11XTAL — — — — PUCR/PDPEE Down

7 TEST — — — — N.A. RESET

8 BKGD MODC — — — V

9 PP0 KWP0 ETRIG0 API_EXTCLKPWM0 V

10 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

11 PP2 KWP2 ETRIG2 PWM2 — V

12 PP3 KWP3 ETRIG3 PWM3 — V

13 PT3 IOC3 — — — V

14 PT2 IOC2 — — — V

15 PT1 IOC1 IRQ

16 PT0 IOC0 XIRQ

——V

17 PAD0 KWAD0 AN0 — — V

18 PAD1 KWAD1 AN1 — — V

19 PAD2 KWAD2 AN2 — — V

20 PAD3 KWAD3 AN3 — — V

21 PAD4 KWAD4 AN4 — — V

22 PAD5 KWAD5 AN5 ACMPO — V

23 PAD6 KWAD6 AN6 ACMPP — V

24 PAD7 KWAD7 AN7 ACMPM — V

25 PS0 RXD0 — — — V

26 PS1 TXD0 — — — V

27 PS4 PWM4 MISO0 — — V

28 PS5 IOC4 MOSI0 — — V

29 PS6 IOC5 SCK0 — — V

30 PS7 API_EXTCLK ECLK PWM5 SS0

31 PM0 — — — — V

DDX

DDA

DDX

PUCR/BKPUE Up

PERP/PPSP Disabled

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

PERS/PPSS Up

PERM/PPSM Disabled

pin Down

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Device Overview MC9S12G-Family

1 2 3 4 5 6 7 8

9 10 11 12

1314151617181920212223

36 35 34 33 32 31 30 29 28 27 26 25

4847464544434241403938

S12GN16 S12GN32

48-Pin LQFP/QFN

PAD7/KWAD7/AN7 PAD6/KWAD6/AN6 PAD5/KWAD5/AN5 PAD4/KWAD4/AN4 PAD11/KWAD11/ACMPM PAD3/KWAD3/AN3 PAD10/KWAD10/ACMPP PAD2/KWAD2/AN2 PAD9/KWAD9/ACMPO PAD1/KWAD1/AN1 PAD8/KWAD8 PAD0/KWAD0/AN0

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM4/KWP4/PP4

PWM5/KWP5/PP5

IOC5/PT5

IOC4/PT4

IOC3/PT3

IOC2/PT2

IRQ

/IOC1/PT1

XIRQ

/IOC0/PT0

RESET

VDDXR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST KWJ0/PJ0 KWJ1/PJ1 KWJ2/PJ2 KWJ3/PJ3

BKGD

PM1

PM0

PS7/API_EXTCLK/ECLK/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3

PS2

PS1/TXD0

PS0/RXD0

VSSA

VDDA/VRH

Table 1-9. 32-Pin LQFP OPinout for S12GN16 and S12GN32

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

5th

Func

32 PM1 — — — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

Power

Supply

DDX

Internal Pull

Resistor

CTRL

PERM/PPSM Disabled

1.8.1.3 Pinout 48-Pin LQFP/QFN

Reset

State

Figure 1-5. 48-Pin LQFP/QFN Pinout for S12GN16 and S12GN32

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Table 1-10. 48-Pin LQFP/QFN Pinout for S12GN16 and S12GN32

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

1 RESET — — — — V

5th

Func

Power

Supply

DDX

Internal Pull

Resistor

CTRL

PULLUP

Reset

State

2VDDXR——— —— — —

3 VSSX — — — — — — —

4PE0

EXTAL — — — V

DDX

PUCR/PDPEE Down

5VSS——— —— — —

6PE1

7 TEST — — — — N.A. RESET

8 PJ0 KWJ0 — — — V

9 PJ1 KWJ1 — — — V

10 PJ2 KWJ2 — — — V

11 PJ3 KW J3 — — — V

12 BKGD MODC — — — V

13 PP0 KWP0 ETRIG0 API_EXTCLKPWM0 V

XTAL — — — V

DDX

PUCR/PDPEE Down

pin Down

DDX

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

14 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

15 PP2 KWP2 ETRIG2 PWM2 — V

16 PP3 KWP3 ETRIG3 PWM3 — V

17 PP4 KWP4 PWM4 — — V

18 PP5 KWP5 PWM5 — — V

19 PT5 IOC5 — — — V

20 PT4 IOC4 — — — V

21 PT3 IOC3 — — — V

22 PT2 IOC2 — — — V

23 PT1 IOC1 IRQ

24 PT0 IOC0 XIRQ

——V

25 PAD0 KWAD0 AN0 — — V

26 PAD8 KWAD8 — — — V

27 PAD1 KWAD1 AN1 — — V

MC9S12G Family Reference Manual Rev.1.2 7

DDX

DDA

PERP/PPSP Disabled

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

58 NXP Semiconductors

Page 57

Device Overview MC9S12G-Family

Table 1-10. 48-Pin LQFP/QFN Pinout for S12GN16 and S12GN32

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

28 PAD9 KWAD9 ACMPO — — V

29 PAD2 KWAD2 AN2 — — V

30 PAD10 KWAD10 ACMPP V

31 PAD3 KWAD3 AN3 — — V

32 PAD11 KWAD11 ACMPM V

33 PAD4 KWAD4 AN4 — — V

34 PAD5 KWAD5 AN5 — — V

35 PAD6 KWAD6 AN6 — — V

36 PAD7 KWAD7 AN7 — — V

5th

Power

Supply

DDA

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER1AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

Internal Pull

Resistor

CTRL

37 VDDA VRH — — — — — —

38 VSSA — — — — — — —

39 PS0 RXD0 — — — V

40 PS1 TXD0 — — — V

41 PS2 — — — — V

42 PS3 — — — — V

43 PS4 MISO0 — — — V

44 PS5 MOSI0 — — — V

45 PS6 SCK0 — — — V

46 PS7 API_EXTCLKECLK SS0

—V

DDX

PERS/PPSS Up

Reset

State

47PM0——— —V

48PM1——— —V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

DDX

PERM/PPSM Disabled

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 59

Page 58

Device Overview MC9S12G-Family

1 2 3 4 5 6 7 8

9 10 11 12

1314151617181920212223

36 35 34 33 32 31 30 29 28 27 26 25

4847464544434241403938

S12GNA16 S12GNA32

48-Pin LQFP/QFN

PAD7/KWAD7/AN7 PAD6/KWAD6/AN6 PAD5/KWAD5/AN5 PAD4/KWAD4/AN4 PAD11/KWAD11/ACMPM PAD3/KWAD3/AN3 PAD10/KWAD10/ACMPP PAD2/KWAD2/AN2 PAD9/KWAD9/ACMPO PAD1/KWAD1/AN1 PAD8/KWAD8 PAD0/KWAD0/AN0

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM4/KWP4/PP4

PWM5/KWP5/PP5

IOC5/PT5

IOC4/PT4

IOC3/PT3

IOC2/PT2

IRQ

/IOC1/PT1

XIRQ

/IOC0/PT0

RESET

VDDXR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST KWJ0/PJ0 KWJ1/PJ1 KWJ2/PJ2 KWJ3/PJ3

BKGD

PM1

PM0

PS7/API_EXTCLK/ECLK/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3

PS2

PS1/TXD0

PS0/RXD0

VSSA

VDDA/VRH

1.8.2 S12GNA16 and S12GNA32

1.8.2.1 Pinout 48-Pin LQFP/QFN

Package Pin Pin

Figure 1-6. 48-Pin LQFP/QFN Pinout for S12GNA16 and S12GNA32

Table 1-11. 48-Pin LQFP/QFN Pinout for S12GNA16 and S12GNA32

<----lowest-----PRIORITY-----highest---->

2nd

Func.

Function

3rd

Func.

1 RESET — — — — V

4th

Func

Power

5th

Supply

Func

DDX

Internal Pull

Resistor

CTRL

PULLUP

Reset

State

MC9S12G Family Reference Manual Rev.1.2 7

60 NXP Semiconductors

Page 59

Device Overview MC9S12G-Family

Table 1-11. 48-Pin LQFP/QFN Pinout for S12GNA16 and S12GNA32

Package Pin Pin

Function

<----lowest-----PRIORITY-----highest---->

2nd

Func.

3rd

Func.

4th

Func

5th

Func

Power

Supply

Internal Pull

Resistor

CTRL

Reset

State

2VDDXR——— —— — —

3 VSSX — — — — — — —

4PE01EXTAL — — — V

DDX

PUCR/PDPEE Down

5VSS——— —— — —

6PE1

7 TEST — — — — N.A. RESET

8 PJ0 KWJ0 — — — V

9 PJ1 KWJ1 — — — V

10 PJ2 KWJ2 — — — V

11 PJ3 KW J3 — — — V

12 BKGD MODC — — — V

13 PP0 KWP0 ETRIG0 API_EXTCLKPWM0 V

XTAL — — — V

DDX

PUCR/PDPEE Down

pin Down

DDX

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

14 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

15 PP2 KWP2 ETRIG2 PWM2 — V

16 PP3 KWP3 ETRIG3 PWM3 — V

17 PP4 KWP4 PWM4 — — V

18 PP5 KWP5 PWM5 — — V

19 PT5 IOC5 — — — V

20 PT4 IOC4 — — — V

21 PT3 IOC3 — — — V

22 PT2 IOC2 — — — V

23 PT1 IOC1 IRQ

24 PT0 IOC0 XIRQ

——V

25 PAD0 KWAD0 AN0 — — V

26 PAD8 KWAD8 — — — V

27 PAD1 KWAD1 AN1 — — V

28 PAD9 KWAD9 ACMPO — — V

29 PAD2 KWAD2 AN2 — — V

DDX

DDA

PERP/PPSP Disabled

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 61

Page 60

Device Overview MC9S12G-Family

Table 1-11. 48-Pin LQFP/QFN Pinout for S12GNA16 and S12GNA32

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

30 PAD10 KWAD10 ACMPP V

31 PAD3 KWAD3 AN3 — — V

32 PAD11 KWAD11 ACMPM V

33 PAD4 KWAD4 AN4 — — V

34 PAD5 KWAD5 AN5 — — V

35 PAD6 KWAD6 AN6 — — V

36 PAD7 KWAD7 AN7 — — V

5th

Power

Supply

DDA

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER1AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

Internal Pull

Resistor

CTRL

37 VDDA VRH — — — — — —

38 VSSA — — — — — — —

39 PS0 RXD0 — — — V

40 PS1 TXD0 — — — V

41 PS2 — — — — V

42 PS3 — — — — V

43 PS4 MISO0 — — — V

44 PS5 MOSI0 — — — V

45 PS6 SCK0 — — — V

46 PS7 API_EXTCLKECLK SS0

—V

DDX

PERS/PPSS Up

Reset

State

47PM0——— —V

48PM1——— —V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

DDX

PERM/PPSM Disabled

1.8.3 S12GN48

1.8.3.1 Pinout 32-Pin LQFP

MC9S12G Family Reference Manual Rev.1.2 7

62 NXP Semiconductors

Page 61

Device Overview MC9S12G-Family

1 2 3 4 5 6 7 8

10111213141516

24 23 22 21 20 19 18 17

32313029282726

S12GN48

32-Pin LQFP

PAD7/KWAD7/AN7/ACMPM PAD6/KWAD6/AN6/ACMPP PAD5/KWAD5/AN5/ACMPO PAD4/KWAD4/AN4 PAD3/KWAD3/AN3 PAD2/KWAD2/AN2 PAD1/KWAD1/AN1 PAD0/KWAD0/AN0

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

IOC3/PT3

IOC2/PT2

IRQ

/IOC1/PT1

XIRQ

/IOC0/PT0

RESET

VRH/VDDXRA

VSSXA

EXTAL/PE0

VSS

XTAL/PE1

TEST

BKGD

PM1/TXD1

PM0/RXD1

PS7/API_EXTCLK/ECLK/PWM5/SS0

PS6/IOC5/SCK0

PS5/IOC4/MOSI0

PS4/PWM4/MISO0

PS1/TXD0

PS0/RXD0

Figure 1-7. 32-Pin LQFP Pinout for S12GN48

Table 1-12. 32-Pin LQFP Pinout for S12GN48

<----lowest-----PRIORITY-----highest---->

2nd

Func.

Function

Package Pin Pin

1 RESET — — — — V

2VDDXRAVRH — — —— — —

3 VSSXA — — — — — — —

4PE0

EXTAL — — — — PUCR/PDPEE Down

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 63

3rd

Func.

4th

Func

5th

Func

Power

Supply

DDX

Internal Pull

Resistor

CTRL

PULLUP

Reset

State

Page 62

Device Overview MC9S12G-Family

Table 1-12. 32-Pin LQFP Pinout for S12GN48

Package Pin Pin

Function

<----lowest-----PRIORITY-----highest---->

2nd

Func.

3rd

Func.

4th

Func

5th

Func

Power

Supply

Internal Pull

Resistor

CTRL

Reset

State

5VSS— ———— — —

6PE1

7 TEST — — — — N.A. RESET

8 BKGD MODC — — — V

9 PP0 KWP0 ETRIG0 API_EXTCLKPWM0 V

10 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

11 PP2 KWP2 ETRIG2 PWM2 — V

12 PP3 KWP3 ETRIG3 PWM3 — V

13 PT3 IOC3 — — — V

14 PT2 IOC2 — — — V

15 PT1 IOC1 IRQ

16 PT0 IOC0 XIRQ

17 PAD0 KWAD0 AN0 — — V

18 PAD1 KWAD1 AN1 — — V

19 PAD2 KWAD2 AN2 — — V

20 PAD3 KWAD3 AN3 — — V

21 PAD4 KWAD4 AN4 — — V

22 PAD5 KWAD5 AN5 ACMPO — V

23 PAD6 KWAD6 AN6 ACMPP — V

24 PAD7 KWAD7 AN7 ACMPM — V

25 PS0 RXD0 — — — V

26 PS1 TXD0 — — — V

27 PS4 PWM4 MISO0 — — V

28 PS5 IOC4 MOSI0 — — V

29 PS6 IOC5 SCK0 — — V

30 PS7 API_EXTCLK ECLK PWM5 SS0

31 PM0 RXD1 — — — V

32 PM1 TXD1 — — — V

XTAL — — — — PUCR/PDPEE Down

pin Down

DDX

——V

DDX

DDA

DDX

PUCR/BKPUE Up

PERP/PPSP Disabled

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

PERS/PPSS Up

PERM/PPSM Disabled

MC9S12G Family Reference Manual Rev.1.2 7

64 NXP Semiconductors

Page 63

Device Overview MC9S12G-Family

1 2 3 4 5 6 7 8

9 10 11 12

1314151617181920212223

36 35 34 33 32 31 30 29 28 27 26 25

4847464544434241403938

S12GN48

48-Pin LQFP

PAD7/KWAD7/AN7 PAD6/KWAD6/AN6 PAD5/KWAD5/AN5 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11/ACMPM PAD3/KWAD3/AN3 PAD10/KWAD10/AN10/ACMPP PAD2/KWAD2/AN2 PAD9/KWAD9/AN9/ACMPO PAD1/KWAD1/AN1 PAD8/KWAD8/AN8 PAD0/KWAD0/AN0

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM4/KWP4/PP4

PWM5/KWP5/PP5

IOC5/PT5

IOC4/PT4

IOC3/PT3

IOC2/PT2

IRQ

/IOC1/PT1

XIRQ

/IOC0/PT0

RESET

VDDXR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1

SCK1/KWJ2/PJ2

SS1

/KWJ3/PJ3

BKGD

PM1

PM0

PS7/API_EXTCLK/ECLK/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

VSSA

VDDA/VRH

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

1.8.3.2 Pinout 48-Pin LQFP

Figure 1-8. 48-Pin LQFP Pinout for S12GN48

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 65

Page 64

Device Overview MC9S12G-Family

Table 1-13. 48-Pin LQFP Pinout for S12GN48

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

1 RESET — — — — V

5th

Func

Power

Supply

DDX

Internal Pull

Resistor

CTRL

PULLUP

Reset

State

2VDDXR——— —— — —

3 VSSX — — — — — — —

4PE0

EXTAL — — — V

DDX

PUCR/PDPEE Down

5VSS——— —— — —

6PE1

7 TEST — — — — N.A. RESET

8 PJ0 KWJ0 MISO1 — — V

9 PJ1 KWJ1 MOSI1 — — V

10 PJ2 KWJ2 SCK1 — — V

11 PJ3 KWJ3 SS1

12 BKGD MODC — — — V

13 PP0 KWP0 ETRIG0 API_EXTCLKPWM0 V

XTAL — — — V

DDX

PUCR/PDPEE Down

pin Down

DDX

——V

DDX

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

14 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

15 PP2 KWP2 ETRIG2 PWM2 — V

16 PP3 KWP3 ETRIG3 PWM3 — V

17 PP4 KWP4 PWM4 — — V

18 PP5 KWP5 PWM5 — — V

19 PT5 IOC5 — — — V

20 PT4 IOC4 — — — V

21 PT3 IOC3 — — — V

22 PT2 IOC2 — — — V

23 PT1 IOC1 IRQ

24 PT0 IOC0 XIRQ

——V

25 PAD0 KWAD0 AN0 — — V

26 PAD8 KWAD8 AN8 — — V

27 PAD1 KWAD1 AN1 — — V

MC9S12G Family Reference Manual Rev.1.2 7

DDX

DDA

PERP/PPSP Disabled

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

66 NXP Semiconductors

Page 65

Table 1-13. 48-Pin LQFP Pinout for S12GN48

Device Overview MC9S12G-Family

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

28 PAD9 KWAD9 AN9 ACMPO — V

29 PAD2 KWAD2 AN2 — — V

30 PAD10 KWAD10 AN10 ACMPP V

31 PAD3 KWAD3 AN3 — — V

32 PAD11 KWAD11 AN11 ACMPM V

33 PAD4 KWAD4 AN4 — — V

34 PAD5 KWAD5 AN5 — — V

35 PAD6 KWAD6 AN6 — — V

36 PAD7 KWAD7 AN7 — — V

5th

Power

Supply

DDA

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER1AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

Internal Pull

Resistor

CTRL

37 VDDA VRH — — — — — —

38 VSSA — — — — — — —

39 PS0 RXD0 — — — V

40 PS1 TXD0 — — — V

41 PS2 RXD1 — — — V

42 PS3 TXD1 — — — V

43 PS4 MISO0 — — — V

44 PS5 MOSI0 — — — V

45 PS6 SCK0 — — — V

46 PS7 API_EXTCLKECLK SS0

—V

DDX

PERS/PPSS Up

Reset

State

47PM0——— —V

48PM1——— —V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

DDX

PERM/PPSM Disabled

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 67

Page 66

Device Overview MC9S12G-Family

1 2 3 4 5 6 7 8 9

11 12 13 14 15 16

171819202122232425262728293031

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

646362616059585756555453525150

S12GN48

64-Pin LQFP

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM4/KWP4/PP4

PWM5/KWP5/PP5

KWP6/PP6

KWP7/PP7

PT7

PT6

IOC5/PT5

IOC4/PT4

IOC3/PT3

IOC2/PT2

IRQ

/IOC1/PT1

XIRQ

/IOC0/PT0

KWJ6/PJ6 KWJ5/PJ5 KWJ4/PJ4

RESET

VDDX VDDR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1

SCK1/KWJ2/PJ2

SS1

/KWJ3/PJ3

BKGD

PJ7/KWJ7

PM3

PM2

PM1

PM0

PS7/API_EXTCLK/ECLK/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

VSSA

VDDA

VRH

PAD15/KWAD15 PAD7/KWAD7/AN7 PAD14/KWAD14 PAD6/KWAD6/AN6 PAD13/KWAD13 PAD5/KWAD5/AN5 PAD12/KWAD12 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11/ACMPM PAD3/KWAD3/AN3 PAD10/KWAD10/AN10/ACMPP PAD2/KWAD2/AN2 PAD9/KWAD9/AN9/ACMPO PAD1/KWAD1/AN1 PAD8/KWAD8/AN8 PAD0/KWAD0/AN0

1.8.3.3 Pinout 64-Pin LQFP

Figure 1-9. 64-Pin LQFP Pinout for S12GN48

MC9S12G Family Reference Manual Rev.1.2 7

68 NXP Semiconductors

Page 67

Table 1-14. 64-Pin LQFP Pinout for S12GN48

Device Overview MC9S12G-Family

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

1 PJ6 KWJ6 — — — V

2 PJ5 KWJ5 — — — V

3 PJ4 KWJ4 — — — V

4 RESET — — — — V

5th

Func

Power

Supply

DDX

Internal Pull

Resistor

CTRL

PERJ/PPSJ Up

PULLUP

5 VDDX — — — — — — —

6 VDDR — — — — — — —

7 VSSX — — — — — — —

8 PE0

EXTAL — — — V

DDX

PUCR/PDPEE Down

9 VSS — — — — — — —

10 PE1

11 TEST — — — — N.A. RESET

12 PJ0 KWJ0 MISO1 — — V

13 PJ1 KWJ1 MOSI1 — — V

14 PJ2 KWJ2 SCK1 — — V

15 PJ3 KWJ3 SS1

16 BKGD MODC — — — V

17 PP0 KWP0 ETRIG0 API_EXTCLKPWM0 V

XTAL — — — V

DDX

PUCR/PDPEE Down

pin Down

DDX

——V

DDX

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

Reset

State

18 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

19 PP2 KWP2 ETRIG2 PWM2 — V

20 PP3 KWP3 ETRIG3 PWM3 — V

21 PP4 KWP4 PWM4 — — V

22 PP5 KWP5 PWM5 — — V

23 PP6 KWP6 — — V

24 PP7 KWP7 — — V

25PT7————V

26PT6————V

27 PT5 IOC5 — — — V

DDX

PERP/PPSP Disabled

PERT/PPST Disabled

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 69

Page 68

Device Overview MC9S12G-Family

Table 1-14. 64-Pin LQFP Pinout for S12GN48

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

28 PT4 IOC4 — — — V

29 PT3 IOC3 — — — V

30 PT2 IOC2 — — — V

31 PT1 IOC1 IRQ

32 PT0 IOC0 XIRQ

——V

33 PAD0 KWAD0 AN0 — — V

34 PAD8 KWAD8 AN8 — — V

35 PAD1 KWAD1 AN1 — — V

36 PAD9 KWAD9 AN9 ACMPO — V

37 PAD2 KWAD2 AN2 — — V

38 PAD10 KWAD10 AN10 ACMPP — V

39 PAD3 KWAD3 AN3 — — V

40 PAD11 KWAD11 AN11 ACMPM — V

41 PAD4 KWAD4 AN4 — — V

42 PAD12 KWAD12 — — — V

43 PAD5 KWAD5 AN5 — — V

44 PAD13 KWAD13 — — — V

45 PAD6 KWAD6 AN6 — — V

46 PAD14 KWAD14 — — V

47 PAD7 KWAD7 AN7 — — V

48 PAD15 KWAD15 — — V

5th

Func

Power

Supply

DDX

DDA

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0ADPPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

Internal Pull

Resistor

CTRL

Reset

State

PERT/PPST Disabled

49VRH————— — —

50 VDDA — — — — — — —

51 VSSA — — — — — — —

52 PS0 RXD0 — — — V

53 PS1 TXD0 — — — V

54 PS2 RXD1 — — — V

55 PS3 TXD1 — — — V

56 PS4 MISO0 — — — V

DDX

PERS/PPSS Up

MC9S12G Family Reference Manual Rev.1.2 7

70 NXP Semiconductors

Page 69

Table 1-14. 64-Pin LQFP Pinout for S12GN48

Device Overview MC9S12G-Family

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

5th

Func

57 PS5 MOSI0 — — — V

58 PS6 SCK0 — — — V

59 PS7 API_EXTCLKECLK SS0

—V

60PM0————V

61PM1————V

62PM2————V

63PM3————V

64 PJ7 KWJ7 — — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

Power

Supply

DDX

PERM/PPSM Disabled

Internal Pull

Resistor

CTRL

PERS/PPSS Up

PERJ/PPSJ Up

Reset

State

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 71

Page 70

Device Overview MC9S12G-Family

1 2 3 4 5 6 7 8

10111213141516

24 23 22 21 20 19 18 17

32313029282726

S12G48 S12G64

32-Pin LQFP

PAD7/KWAD7/AN7/ACMPM PAD6/KWAD6/AN6/ACMPP PAD5/KWAD5/AN5/ACMPO PAD4/KWAD4/AN4 PAD3/KWAD3/AN3 PAD2/KWAD2/AN2 PAD1/KWAD1/AN1 PAD0/KWAD0/AN0

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

IOC3/PT3

IOC2/PT2

IRQ

/IOC1/PT1

XIRQ

/IOC0/PT0

RESET

VRH/VDDXRA

VSSXA

EXTAL/PE0

VSS

XTAL/PE1

TEST

BKGD

PM1/TXD1/TXCAN

PM0/RXD1/RXCAN

PS7/API_EXTCLK/ECLK/PWM5/SS0

PS6/IOC5/SCK0

PS5/IOC4/MOSI0

PS4/PWM4/MISO0

PS1/TXD0

PS0/RXD0

1.8.4 S12G48 and S12G64

1.8.4.1 Pinout 32-Pin LQFP

Figure 1-10. 32-Pin LQFP Pinout for S12G48 and S12G64

Table 1-15. 32-Pin LQFP Pinout for S12G48 and S12G64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

1 RESET — — — — V

3rd

Func.

4th

Func

5th

Func

Power

Supply

DDX

Internal Pull

Resistor

CTRL

PULLUP

Reset

State

MC9S12G Family Reference Manual Rev.1.2 7

72 NXP Semiconductors

Page 71

Device Overview MC9S12G-Family

Table 1-15. 32-Pin LQFP Pinout for S12G48 and S12G64

Package Pin Pin

Function

<----lowest-----PRIORITY-----highest---->

2nd

Func.

3rd

Func.

4th

Func

5th

Func

Power

Supply

Internal Pull

Resistor

CTRL

Reset

State

2VDDXRAVRH — — —— — —

3 VSSXA — — — — — — —

4PE01EXTAL — — — — PUCR/PDPEE Down

5VSS— ———— — —

6PE1

7 TEST — — — — N.A. RESET

8 BKGD MODC — — — V

9 PP0 KWP0 ETRIG0 API_EXTCLKPWM0 V

10 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

11 PP2 KWP2 ETRIG2 PWM2 — V

12 PP3 KWP3 ETRIG3 PWM3 — V

13 PT3 IOC3 — — — V

14 PT2 IOC2 — — — V

15 PT1 IOC1 IRQ

16 PT0 IOC0 XIRQ

17 PAD0 KWAD0 AN0 — — V

18 PAD1 KWAD1 AN1 — — V

19 PAD2 KWAD2 AN2 — — V

20 PAD3 KWAD3 AN3 — — V

21 PAD4 KWAD4 AN4 — — V

22 PAD5 KWAD5 AN5 ACMPO — V

23 PAD6 KWAD6 AN6 ACMPP — V

24 PAD7 KWAD7 AN7 ACMPM — V

25 PS0 RXD0 — — — V

26 PS1 TXD0 — — — V

27 PS4 PWM4 MISO0 — — V

28 PS5 IOC4 MOSI0 — — V

29 PS6 IOC5 SCK0 — — V

XTAL — — — — PUCR/PDPEE Down

pin Down

DDX

——V

DDX

DDA

DDX

PUCR/BKPUE Up

PERP/PPSP Disabled

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

PERS/PPSS Up

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 73

Page 72

Device Overview MC9S12G-Family

Table 1-15. 32-Pin LQFP Pinout for S12G48 and S12G64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

5th

Func

30 PS7 API_EXTCLK ECLK PWM5 SS0

31 PM0 RXD1 RXCAN — — V

32 PM1 TXD1 TXCAN — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

Power

Supply

DDX

Internal Pull

Resistor

CTRL

PERS/PPSS Up

PERM/PPSM Disabled

Reset

State

MC9S12G Family Reference Manual Rev.1.2 7

74 NXP Semiconductors

Page 73

1.8.4.2 Pinout 48-Pin LQFP

1 2 3 4 5 6 7 8

9 10 11 12

1314151617181920212223

36 35 34 33 32 31 30 29 28 27 26 25

4847464544434241403938

S12G48 S12G64

48-Pin LQFP

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM4/KWP4/PP4

PWM5/KWP5/PP5

IOC5/PT5

IOC4/PT4

IOC3/PT3

IOC2/PT2

IRQ

/IOC1/PT1

XIRQ

/IOC0/PT0

RESET

VDDXR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1

SCK1/KWJ2/PJ2

SS1

/KWJ3/PJ3

BKGD

PM1/TXCAN

PM0/RXCAN

PS7/API_EXTCLK/ECLK/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

VSSA

VDDA/VRH

Device Overview MC9S12G-Family

Package Pin Pin

Figure 1-11. 48-Pin LQFP Pinout for S12G48 and S12G64

Table 1-16. 48-Pin LQFP Pinout for S12G48 and S12G64

<----lowest-----PRIORITY-----highest---->

2nd

Func.

Function

3rd

Func.

1 RESET — — — — V

2VDDXR——— —— — —

Func

4th

5th

Func

Power

Supply

DDX

Internal Pull

Resistor

CTRL

PULLUP

Reset

State

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 75

Page 74

Device Overview MC9S12G-Family

Table 1-16. 48-Pin LQFP Pinout for S12G48 and S12G64

Package Pin Pin

Function

<----lowest-----PRIORITY-----highest---->

2nd

Func.

3rd

Func.

4th

Func

5th

Func

Power

Supply

Internal Pull

Resistor

CTRL

Reset

State

3 VSSX — — — — — — —

4PE0

EXTAL — — — V

DDX

PUCR/PDPEE Down

5VSS——— —— — —

6PE11XTAL — — — V

DDX

7 TEST — — — — N.A. RESET

8 PJ0 KWJ0 — MISO1 — V

9 PJ1 KWJ1 — MOSI1 — V

10 PJ2 KWJ2 — SCK1 — V

11 PJ3 KWJ3 — SS1

—V

12 BKGD MODC — — — V

13 PP0 KWP0 ETRIG0 API_EXTCLKPWM0 V

14 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

15 PP2 KWP2 ETRIG2 PWM2 — V

16 PP3 KWP3 ETRIG3 PWM3 — V

17 PP4 KWP4 PWM4 — — V

18 PP5 KWP5 PWM5 — — V

19 PT5 IOC5 — — — V

20 PT4 IOC4 — — — V

21 PT3 IOC3 — — — V

22 PT2 IOC2 — — — V

23 PT1 IOC1 IRQ

24 PT0 IOC0 XIRQ

——V

25 PAD0 KWAD0 AN0 — — V

26 PAD8 KWAD8 AN8 — — V

27 PAD1 KWAD1 AN1 — — V

28 PAD9 KWAD9 AN9 ACMPO — V

29 PAD2 KWAD2 AN2 — — V

30 PAD10 KWAD10 AN10 ACMPP V

DDX

DDA

PUCR/PDPEE Down

pin Down

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

MC9S12G Family Reference Manual Rev.1.2 7

76 NXP Semiconductors

Page 75

Device Overview MC9S12G-Family

Table 1-16. 48-Pin LQFP Pinout for S12G48 and S12G64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

31 PAD3 KWAD3 AN3 — — V

32 PAD11 KWAD11 AN11 ACMPM V

33 PAD4 KWAD4 AN4 — — V

34 PAD5 KWAD5 AN5 — — V

35 PAD6 KWAD6 AN6 — — V

36 PAD7 KWAD7 AN7 — — V

5th

Power

Supply

DDA

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER1AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

Internal Pull

Resistor

CTRL

37 VDDA VRH — — — — — —

38 VSSA — — — — — — —

39 PS0 RXD0 — — — V

40 PS1 TXD0 — — — V

41 PS2 RXD1 — — — V

42 PS3 TXD1 — — — V

43 PS4 MISO0 — — — V

44 PS5 MOSI0 — — — V

45 PS6 SCK0 — — — V

46 PS7 API_EXTCLKECLK SS0

—V

DDX

PERS/PPSS Up

Reset

State

47 PM0 RXCAN — — — V

48 PM1 TXCAN — — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

DDX

PERM/PPSM Disabled

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 77

Page 76

Device Overview MC9S12G-Family

1 2 3 4 5 6 7 8 9

11 12 13 14 15 16

171819202122232425262728293031

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

646362616059585756555453525150

S12G48 S12G64

64-pin LQFP

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM4/KWP4/PP4

PWM5/KWP5/PP5

KWP6/PP6

KWP7/PP7

PT7

PT6

IOC5/PT5

IOC4/PT4

IOC3/PT3

IOC2/PT2

IRQ

/IOC1/PT1

XIRQ

/IOC0/PT0

KWJ6/PJ6 KWJ5/PJ5 KWJ4/PJ4

RESET

VDDX VDDR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1

SCK1/KWJ2/PJ2

SS1

/KWJ3/PJ3

BKGD

PJ7/KWJ7

PM3

PM2

PM1/TXCAN

PM0/RXCAN

PS7/API_EXTCLK/ECLK/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

VSSA

VDDA

VRH

1.8.4.3 Pinout 64-Pin LQFP

Figure 1-12. 64-Pin LQFP Pinout for S12G48 and S12G64

MC9S12G Family Reference Manual Rev.1.2 7

78 NXP Semiconductors

Page 77

Device Overview MC9S12G-Family

Table 1-17. 64-Pin LQFP Pinout for S12G48 and S12G64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

1 PJ6 KWJ6 — — — V

2 PJ5 KWJ5 — — — V

3 PJ4 KWJ4 — — — V

4 RESET — — — — V

5th

Func

Power

Supply

DDX

Internal Pull

Resistor

CTRL

PERJ/PPSJ Up

PULLUP

5 VDDX — — — — — — —

6 VDDR — — — — — — —

7 VSSX — — — — — — —

8 PE0

EXTAL — — — V

DDX

PUCR/PDPEE Down

9 VSS — — — — — — —

10 PE1

11 TEST — — — — N.A. RESET

12 PJ0 KWJ0 MISO1 — — V

13 PJ1 KWJ1 MOSI1 — — V

14 PJ2 KWJ2 SCK1 — — V

15 PJ3 KWJ3 SS1

16 BKGD MODC — — — V

17 PP0 KWP0 ETRIG0 API_EXTCLKPWM0 V

XTAL — — — V

DDX

PUCR/PDPEE Down

pin Down

DDX

——V

DDX

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

Reset

State

18 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

19 PP2 KWP2 ETRIG2 PWM2 — V

20 PP3 KWP3 ETRIG3 PWM3 — V

21 PP4 KWP4 PWM4 — — V

22 PP5 KWP5 PWM5 — — V

23 PP6 KWP6 — — — V

24 PP7 KWP7 — — — V

25PT7————V

26PT6————V

27 PT5 IOC5 — — — V

DDX

PERP/PPSP Disabled

PERT/PPST Disabled

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 79

Page 78

Device Overview MC9S12G-Family

Table 1-17. 64-Pin LQFP Pinout for S12G48 and S12G64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

28 PT4 IOC4 — — — V

29 PT3 IOC3 — — — V

30 PT2 IOC2 — — — V

31 PT1 IOC1 IRQ

32 PT0 IOC0 XIRQ

——V

33 PAD0 KWAD0 AN0 — — V

34 PAD8 KWAD8 AN8 — — V

35 PAD1 KWAD1 AN1 — — V

36 PAD9 KWAD9 AN9 ACMPO — V

37 PAD2 KWAD2 AN2 — — V

38 PAD10 KWAD10 AN10 ACMPP V

39 PAD3 KWAD3 AN3 — — V

40 PAD11 KWAD11 AN11 ACMPM V

41 PAD4 KWAD4 AN4 — — V

42 PAD12 KWAD12 — — — V

43 PAD5 KWAD5 AN5 — — V

44 PAD13 KWAD13 — — — V

45 PAD6 KWAD6 AN6 — — V

46 PAD14 KWAD14 — — — V

47 PAD7 KWAD7 AN7 — — V

48 PAD15 KWAD15 — — — V

5th

Func

Power

Supply

DDX

DDA

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0ADPPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

Internal Pull

Resistor

CTRL

Reset

State

PERT/PPST Disabled

49VRH————— — —

50 VDDA — — — — — — —

51 VSSA — — — — — — —

52 PS0 RXD0 — — — V

53 PS1 TXD0 — — — V

54 PS2 RXD1 — — — V

55 PS3 TXD1 — — — V

56 PS4 MISO0 — — — V

DDX

PERS/PPSS Up

MC9S12G Family Reference Manual Rev.1.2 7

80 NXP Semiconductors

Page 79

Device Overview MC9S12G-Family

Table 1-17. 64-Pin LQFP Pinout for S12G48 and S12G64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

5th

Func

57 PS5 MOSI0 — — — V

58 PS6 SCK0 — — — V

59 PS7 API_EXTCLKECLK SS0

—V

60 PM0 RXCAN — — — V

61 PM1 TXCAN — — — V

62PM2————V

63PM3————V

64 PJ7 KWJ7 — — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

Power

Supply

DDX

PERM/PPSM Disabled

Internal Pull

Resistor

CTRL

PERS/PPSS Up

PERJ/PPSJ Up

Reset

State

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 81

Page 80

Device Overview MC9S12G-Family

1 2 3 4 5 6 7 8

9 10 11 12

1314151617181920212223

36 35 34 33 32 31 30 29 28 27 26 25

4847464544434241403938

S12GA48 S12GA64

48-Pin LQFP

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM4/KWP4/PP4

PWM5/KWP5/PP5

IOC5/PT5

IOC4/PT4

IOC3/PT3

IOC2/PT2

IRQ

/IOC1/PT1

XIRQ

/IOC0/PT0

RESET

VDDXR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1

SCK1/KWJ2/PJ2

SS1

/KWJ3/PJ3

BKGD

PM1/TXCAN

PM0/RXCAN

PS7/API_EXTCLK/ECLK/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

VSSA

VDDA/VRH

1.8.5 S12GA48 and S12GA64

1.8.5.1 Pinout 48-Pin LQFP

Package Pin Pin

Figure 1-13. 48-Pin LQFP Pinout for S12GA48 and S12GA64

Table 1-18. 48-Pin LQFP Pinout for S12GA48 and S12GA64

<----lowest-----PRIORITY-----highest---->

2nd

Func.

Function

3rd

Func.

1 RESET — — — — V

4th

Func

Power

5th

Supply

Func

DDX

Internal Pull

Resistor

CTRL

PULLUP

Reset

State

MC9S12G Family Reference Manual Rev.1.2 7

82 NXP Semiconductors

Page 81

Device Overview MC9S12G-Family

Table 1-18. 48-Pin LQFP Pinout for S12GA48 and S12GA64

Package Pin Pin

Function

<----lowest-----PRIORITY-----highest---->

2nd

Func.

3rd

Func.

4th

Func

5th

Func

Power

Supply

Internal Pull

Resistor

CTRL

Reset

State

2VDDXR——— —— — —

3 VSSX — — — — — — —

4PE01EXTAL — — — V

DDX

PUCR/PDPEE Down

5VSS——— —— — —

6PE1

7 TEST — — — — N.A. RESET

8 PJ0 KWJ0 — MISO1 — V

9 PJ1 KWJ1 — MOSI1 — V

10 PJ2 KWJ2 — SCK1 — V

11 PJ3 KWJ3 — SS1

12 BKGD MODC — — — V

13 PP0 KWP0 ETRIG0 API_EXTCLKPWM0 V

XTAL — — — V

DDX

PUCR/PDPEE Down

pin Down

DDX

—V

DDX

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

14 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

15 PP2 KWP2 ETRIG2 PWM2 — V

16 PP3 KWP3 ETRIG3 PWM3 — V

17 PP4 KWP4 PWM4 — — V

18 PP5 KWP5 PWM5 — — V

19 PT5 IOC5 — — — V

20 PT4 IOC4 — — — V

21 PT3 IOC3 — — — V

22 PT2 IOC2 — — — V

23 PT1 IOC1 IRQ

24 PT0 IOC0 XIRQ

——V

25 PAD0 KWAD0 AN0 — — V

26 PAD8 KWAD8 AN8 — — V

27 PAD1 KWAD1 AN1 — — V

28 PAD9 KWAD9 AN9 ACMPO — V

29 PAD2 KWAD2 AN2 — — V

DDX

DDA

PERP/PPSP Disabled

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 83

Page 82

Device Overview MC9S12G-Family

Table 1-18. 48-Pin LQFP Pinout for S12GA48 and S12GA64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

30 PAD10 KWAD10 AN10 ACMPP V

31 PAD3 KWAD3 AN3 — — V

32 PAD11 KWAD11 AN11 ACMPM V

33 PAD4 KWAD4 AN4 — — V

34 PAD5 KWAD5 AN5 — — V

35 PAD6 KWAD6 AN6 — — V

36 PAD7 KWAD7 AN7 — — V

5th

Power

Supply

DDA

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER1AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

Internal Pull

Resistor

CTRL

37 VDDA VRH — — — — — —

38 VSSA — — — — — — —

39 PS0 RXD0 — — — V

40 PS1 TXD0 — — — V

41 PS2 RXD1 — — — V

42 PS3 TXD1 — — — V

43 PS4 MISO0 — — — V

44 PS5 MOSI0 — — — V

45 PS6 SCK0 — — — V

46 PS7 API_EXTCLKECLK SS0

—V

DDX

PERS/PPSS Up

Reset

State

47 PM0 RXCAN — — — V

48 PM1 TXCAN — — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

DDX

PERM/PPSM Disabled

MC9S12G Family Reference Manual Rev.1.2 7

84 NXP Semiconductors

Page 83

1.8.5.2 Pinout 64-Pin LQFP

1 2 3 4 5 6 7 8 9

11 12 13 14 15 16

171819202122232425262728293031

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

646362616059585756555453525150

S12GA48 S12GA64

64-pin LQFP

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM4/KWP4/PP4

PWM5/KWP5/PP5

KWP6/PP6

KWP7/PP7

PT7

PT6

IOC5/PT5

IOC4/PT4

IOC3/PT3

IOC2/PT2

IRQ

/IOC1/PT1

XIRQ

/IOC0/PT0

KWJ6/PJ6 KWJ5/PJ5 KWJ4/PJ4

RESET

VDDX VDDR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1

SCK1/KWJ2/PJ2

SS1

/KWJ3/PJ3

BKGD

PJ7/KWJ7

PM3

PM2

PM1/TXCAN

PM0/RXCAN

PS7/API_EXTCLK/ECLK/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

VSSA

VDDA

VRH

Device Overview MC9S12G-Family

Figure 1-14. 64-Pin LQFP Pinout for S12GA48 and S12GA64

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 85

Page 84

Device Overview MC9S12G-Family

Table 1-19. 64-Pin LQFP Pinout for S12GA48 and S12GA64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

1 PJ6 KWJ6 — — — V

2 PJ5 KWJ5 — — — V

3 PJ4 KWJ4 — — — V

4 RESET — — — — V

5th

Func

Power

Supply

DDX

Internal Pull

Resistor

CTRL

PERJ/PPSJ Up

PULLUP

5 VDDX — — — — — — —

6 VDDR — — — — — — —

7 VSSX — — — — — — —

8 PE0

EXTAL — — — V

DDX

PUCR/PDPEE Down

9 VSS — — — — — — —

10 PE1

11 TEST — — — — N.A. RESET

12 PJ0 KWJ0 MISO1 — — V

13 PJ1 KWJ1 MOSI1 — — V

14 PJ2 KWJ2 SCK1 — — V

15 PJ3 KWJ3 SS1

16 BKGD MODC — — — V

17 PP0 KWP0 ETRIG0 API_EXTCLKPWM0 V

XTAL — — — V

DDX

PUCR/PDPEE Down

pin Down

DDX

——V

DDX

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

Reset

State

18 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

19 PP2 KWP2 ETRIG2 PWM2 — V

20 PP3 KWP3 ETRIG3 PWM3 — V

21 PP4 KWP4 PWM4 — — V

22 PP5 KWP5 PWM5 — — V

23 PP6 KWP6 — — — V

24 PP7 KWP7 — — — V

25PT7————V

26PT6————V

27 PT5 IOC5 — — — V

DDX

PERP/PPSP Disabled

PERT/PPST Disabled

MC9S12G Family Reference Manual Rev.1.2 7

86 NXP Semiconductors

Page 85

Device Overview MC9S12G-Family

Table 1-19. 64-Pin LQFP Pinout for S12GA48 and S12GA64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

28 PT4 IOC4 — — — V

29 PT3 IOC3 — — — V

30 PT2 IOC2 — — — V

31 PT1 IOC1 IRQ

32 PT0 IOC0 XIRQ

——V

33 PAD0 KWAD0 AN0 — — V

34 PAD8 KWAD8 AN8 — — V

35 PAD1 KWAD1 AN1 — — V

36 PAD9 KWAD9 AN9 ACMPO — V

37 PAD2 KWAD2 AN2 — — V

38 PAD10 KWAD10 AN10 ACMPP V

39 PAD3 KWAD3 AN3 — — V

40 PAD11 KWAD11 AN11 ACMPM V

41 PAD4 KWAD4 AN4 — — V

42 PAD12 KWAD12 — — — V

43 PAD5 KWAD5 AN5 — — V

44 PAD13 KWAD13 — — — V

45 PAD6 KWAD6 AN6 — — V

46 PAD14 KWAD14 — — — V

47 PAD7 KWAD7 AN7 — — V

48 PAD15 KWAD15 — — — V

5th

Func

Power

Supply

DDX

DDA

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0ADPPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

Internal Pull

Resistor

CTRL

Reset

State

PERT/PPST Disabled

49VRH————— — —

50 VDDA — — — — — — —

51 VSSA — — — — — — —

52 PS0 RXD0 — — — V

53 PS1 TXD0 — — — V

54 PS2 RXD1 — — — V

55 PS3 TXD1 — — — V

56 PS4 MISO0 — — — V

DDX

PERS/PPSS Up

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 87

Page 86

Device Overview MC9S12G-Family

Table 1-19. 64-Pin LQFP Pinout for S12GA48 and S12GA64

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

5th

Func

57 PS5 MOSI0 — — — V

58 PS6 SCK0 — — — V

59 PS7 API_EXTCLKECLK SS0

—V

60 PM0 RXCAN — — — V

61 PM1 TXCAN — — — V

62PM2————V

63PM3————V

64 PJ7 KWJ7 — — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

Power

Supply

DDX

PERM/PPSM Disabled

Internal Pull

Resistor

CTRL

PERS/PPSS Up

PERJ/PPSJ Up

Reset

State

MC9S12G Family Reference Manual Rev.1.2 7

88 NXP Semiconductors

Page 87

1.8.6 S12G96 and S12G128

1 2 3 4 5 6 7 8

9 10 11 12

1314151617181920212223

36 35 34 33 32 31 30 29 28 27 26 25

4847464544434241403938

S12G96

S12G128

48-Pin LQFP

PAD7/KWAD7/AN7 PAD6/KWAD6/AN6 PAD5/KWAD5/AN5 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11 PAD3/KWAD3/AN3 PAD10/KWAD10/AN10 PAD2/KWAD2/AN2 PAD9/KWAD9/AN9 PAD1/KWAD1/AN1 PAD8/KWAD8/AN8 PAD0/KWAD0/AN0

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM4/KWP4/PP4

PWM5/KWP5/PP5

IOC5/PT5

IOC4/PT4

IOC3/PT3

IOC2/PT2

IRQ

/IOC1/PT1

XIRQ

/IOC0/PT0

RESET

VDDXR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST

MISO1/PWM6/KWJ0/PJ0

MOSI1/IOC6/KWJ1/PJ1

SCK1/IOC7/KWJ2/PJ2 SS1

/PWM7/KWJ3/PJ3

BKGD

PM1/TXD2/TXCAN

PM0/RXD2/RXCAN

PS7/API_EXTCLK/ECLK/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

VSSA

VDDA/VRH

1.8.6.1 Pinout 48-Pin LQFP

Device Overview MC9S12G-Family

Package Pin Pin

Figure 1-15. 48-Pin LQFP Pinout for S12G96 and S12G128

Table 1-20. 48-Pin LQFP Pinout for S12G96 and S12G128

<----lowest-----PRIORITY-----highest---->

2nd

Func.

Function

3rd

Func.

1 RESET — — — — V

4th

Func

Power

5th

Supply

Func

DDX

Internal Pull

Resistor

CTRL

PULLUP

Reset

State

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 89

Page 88

Device Overview MC9S12G-Family

Table 1-20. 48-Pin LQFP Pinout for S12G96 and S12G128

Package Pin Pin

Function

<----lowest-----PRIORITY-----highest---->

2nd

Func.

3rd

Func.

4th

Func

5th

Func

Power

Supply

Internal Pull

Resistor

CTRL

Reset

State

2VDDXR——— —— — —

3 VSSX — — — — — — —

4PE0

EXTAL — — — V

DDX

PUCR/PDPEE Down

5VSS——— —— — —

6PE1

7 TEST — — — — N.A. RESET

8 PJ0 KWJ0 PWM6 MISO1 — V

9 PJ1 KWJ1 IOC6 MOSI1 — V

10 PJ2 KWJ2 IOC7 SCK1 — V

11 PJ3 KWJ3 PWM7 SS1

12 BKGD MODC — — — V

13 PP0 KWP0 ETRIG0 API_EXTCLKPWM0 V

XTAL — — — V

DDX

PUCR/PDPEE Down

pin Down

DDX

—V

DDX

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

14 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

15 PP2 KWP2 ETRIG2 PWM2 — V

16 PP3 KWP3 ETRIG3 PWM3 — V

17 PP4 KWP4 PWM4 — — V

18 PP5 KWP5 PWM5 — — V

19 PT5 IOC5 — — — V

20 PT4 IOC4 — — — V

21 PT3 IOC3 — — — V

22 PT2 IOC2 — — — V

23 PT1 IOC1 IRQ

24 PT0 IOC0 XIRQ

——V

25 PAD0 KWAD0 AN0 — — V

26 PAD8 KWAD8 AN8 — — V

27 PAD1 KWAD1 AN1 — — V

28 PAD9 KWAD9 AN9 — V

29 PAD2 KWAD2 AN2 — — V

DDX

DDA

PERP/PPSP Disabled

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

MC9S12G Family Reference Manual Rev.1.2 7

90 NXP Semiconductors

Page 89

Device Overview MC9S12G-Family

Table 1-20. 48-Pin LQFP Pinout for S12G96 and S12G128

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

30 PAD10 KWAD10 AN10 V

31 PAD3 KWAD3 AN3 — — V

32 PAD11 KWAD11 AN11 — — V

33 PAD4 KWAD4 AN4 — — V

34 PAD5 KWAD5 AN5 — — V

35 PAD6 KWAD6 AN6 — — V

36 PAD7 KWAD7 AN7 — — V

5th

Power

Supply

DDA

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER1AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

Internal Pull

Resistor

CTRL

37 VDDA VRH — — — — — —

38 VSSA — — — — — — —

39 PS0 RXD0 — — — V

40 PS1 TXD0 — — — V

41 PS2 RXD1 — — — V

42 PS3 TXD1 — — — V

43 PS4 MISO0 — — — V

44 PS5 MOSI0 — — — V

45 PS6 SCK0 — — — V

46 PS7 API_EXTCLKECLK SS0

—V

DDX

PERS/PPSS Up

Reset

State

47 PM0 RXD2 RXCAN — — V

48 PM1 TXD2 TXCAN — — V

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

DDX

PERM/PPSM Disabled

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 91

Page 90

Device Overview MC9S12G-Family

1 2 3 4 5 6 7 8 9

11 12 13 14 15 16

171819202122232425262728293031

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

646362616059585756555453525150

S12G96

S12G128

64-Pin LQFP

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM4/KWP4/PP4

PWM5/KWP5/PP5

PWM6/KWP6/PP6

PWM7/KWP7/PP7

IOC7/PT7

IOC6/PT6

IOC5/PT5

IOC4/PT4

IOC3/PT3

IOC2/PT2

IRQ

/IOC1/PT1

XIRQ

/IOC0/PT0

SCK2/KWJ6/PJ6 MOSI2/KWJ5/PJ5 MISO2/KWJ4/PJ4

RESET

VDDX VDDR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1

SCK1/KWJ2/PJ2

SS1

/KWJ3/PJ3

BKGD

PJ7/KWJ7/SS2

PM3/TXD2

PM2/RXD2

PM1/TXCAN

PM0/RXCAN

PS7/API_EXTCLK/ECLK/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

VSSA

VDDA

VRH

PAD15/KWAD15 PAD7/KWAD7/AN7 PAD14/KWAD14 PAD6/KWAD6/AN6 PAD13/KWAD13 PAD5/KWAD5/AN5 PAD12/KWAD12 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11 PAD3/KWAD3/AN3 PAD10/KWAD10/AN10 PAD2/KWAD2/AN2 PAD9/KWAD9/AN9 PAD1/KWAD1/AN1 PAD8/KWAD8/AN8 PAD0/KWAD0/AN0

1.8.6.2 Pinout 64-Pin LQFP

Figure 1-16. 64-Pin LQFP Pinout for S12G96 and S12G128

MC9S12G Family Reference Manual Rev.1.2 7

92 NXP Semiconductors

Page 91

Device Overview MC9S12G-Family

Table 1-21. 64-Pin LQFP Pinout for S12G96 and S12G128

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

1 PJ6 KWJ6 SCK2 — — V

2 PJ5 KWJ5 MOSI2 — — V

3 PJ4 KWJ4 MISO2 — — V

4 RESET — — — — V

5th

Func

Power

Supply

DDX

Internal Pull

Resistor

CTRL

PERJ/PPSJ Up

PULLUP

5 VDDX — — — — — — —

6 VDDR — — — — — — —

7 VSSX — — — — — — —

8 PE0

EXTAL — — — V

DDX

PUCR/PDPEE Down

9 VSS — — — — — — —

10 PE1

11 TEST — — — — N.A. RESET

12 PJ0 KWJ0 MISO1 — — V

13 PJ1 KWJ1 MOSI1 — — V

14 PJ2 KWJ2 SCK1 — — V

15 PJ3 KWJ3 SS1

16 BKGD MODC — — — V

17 PP0 KWP0 ETRIG0 API_EXTCLKPWM0 V

XTAL — — — V

DDX

PUCR/PDPEE Down

pin Down

DDX

——V

DDX

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

Reset

State

18 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

19 PP2 KWP2 ETRIG2 PWM2 — V

20 PP3 KWP3 ETRIG3 PWM3 — V

21 PP4 KWP4 PWM4 — — V

22 PP5 KWP5 PWM5 — — V

23 PP6 KWP6 PWM6 — — V

24 PP7 KWP7 PWM7 — — V

25 PT7 IOC7 — — — V

26 PT6 IOC6 — — — V

27 PT5 IOC5 — — — V

DDX

PERP/PPSP Disabled

PERT/PPST Disabled

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 93

Page 92

Device Overview MC9S12G-Family

Table 1-21. 64-Pin LQFP Pinout for S12G96 and S12G128

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

28 PT4 IOC4 — — — V

29 PT3 IOC3 — — — V

30 PT2 IOC2 — — — V

31 PT1 IOC1 IRQ

32 PT0 IOC0 XIRQ

——V

33 PAD0 KWAD0 AN0 — — V

34 PAD8 KWAD8 AN8 — — V

35 PAD1 KWAD1 AN1 — — V

36 PAD9 KWAD9 AN9 — — V

37 PAD2 KWAD2 AN2 — — V

38 PAD10 KWAD10 AN10 — — V

39 PAD3 KWAD3 AN3 — — V

40 PAD11 KWAD11 AN11 — — V

41 PAD4 KWAD4 AN4 — — V

42 PAD12 KWAD12 — — V

43 PAD5 KWAD5 AN5 — — V

44 PAD13 KWAD13 — — V

45 PAD6 KWAD6 AN6 — — V

46 PAD14 KWAD14 — — V

47 PAD7 KWAD7 AN7 — — V

48 PAD15 KWAD15 — — V

5th

Func

Power

Supply

DDX

DDA

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0ADPPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

Internal Pull

Resistor

CTRL

Reset

State

PERT/PPST Disabled

49VRH————— — —

50 VDDA — — — — — — —

51 VSSA — — — — — — —

52 PS0 RXD0 — — — V

53 PS1 TXD0 — — — V

54 PS2 RXD1 — — — V

55 PS3 TXD1 — — — V

56 PS4 MISO0 — — — V

DDX

PERS/PPSS Up

MC9S12G Family Reference Manual Rev.1.2 7

94 NXP Semiconductors

Page 93

Device Overview MC9S12G-Family

Table 1-21. 64-Pin LQFP Pinout for S12G96 and S12G128

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

4th

Func

5th

Func

57 PS5 MOSI0 — — — V

58 PS6 SCK0 — — — V

59 PS7 API_EXTCLKECLK SS0

—V

60 PM0 RXCAN — — — V

61 PM1 TXCAN — — — V

62 PM2 RXD2 — — — V

63 PM3 TXD2 — — — V

64 PJ7 KWJ7 SS2

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

——V

Power

Supply

DDX

PERM/PPSM Disabled

Internal Pull

Resistor

CTRL

PERS/PPSS Up

PERJ/PPSJ Up

Reset

State

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 95

Page 94

Device Overview MC9S12G-Family

1 2 3 4 5 6 7 8 9

11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

26272829303132333435363738394041424344454647484950

VRH PC7 PC6 PC5 PC4 PAD15/KWAD15/ PAD7/KWAD7/AN7 PAD14/KWAD14 PAD6/KWAD6/AN6 PAD13/KWAD13 PAD5/KWAD5/AN5 PAD12/KWAD12 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11 PAD3/KWAD3/AN3 PAD10/KWAD10/AN10 PAD2/KWAD2/AN2 PAD9/KWAD9/AN9 PAD1/KWAD1/AN1 PAD8/KWAD8/AN8 PAD0/KWAD0/AN0 PC3 PC2 PC1 PC0

API_EXTCLK/PB1

ECLKX2/PB2

PB3

PWM0/ETRIG0/KWP0/PP0

PWM1/ETRIG1/KWP1/PP1

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM4/KWP4/PP4

PWM5/KWP5/PP5

PWM6/KWP6/PP6

PWM7/KWP7/PP7

VDDX3

VSSX3

IOC7/PT7

IOC6/PT6

IOC5/PT5

IOC4/PT4

IOC3/PT3

IOC2/PT2

IOC1/PT1

IOC0/PT0

IRQ

/PB4

XIRQ

/PB5

PB6

PB7

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

100

9998979695949392919089888786858483828180797877

SCK2/KWJ6/PJ6 MOSI2/KWJ5/PJ5 MISO2/KWJ4/PJ4

PA0 PA1 PA2

PA3 RESET VDDX1

VDDR

VSSX1

EXTAL/PE0

VSS

XTAL/PE1

TEST

PA4

PA5

PA6

PA7

MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1

SCK1/KWJ2/PJ2

SS1

/KWJ3/PJ3

BKGD

ECLK/PB0

PJ7/KWJ7/SS2

PM3/TXD2

PM2/RXD2

PD7

PD6

PD5

PD4

PM1/TXCAN

PM0/RXCAN

VDDX2

VSSX2

PS7/API_EXTCLK/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

PD3

PD2

PD1

PD0

VSSA

VDDA

S12G96

S12G128

100-Pin LQFP

1.8.6.3 Pinout 100-Pin LQFP

96 NXP Semiconductors

Figure 1-17. 100-Pin LQFP Pinout for S12G96 and S12G128

MC9S12G Family Reference Manual Rev.1.2 7

Page 95

Device Overview MC9S12G-Family

Table 1-22. 100-Pin LQFP Pinout for S12G96 and S12G128

Function

Package Pin Pin

<----lowest-----PRIORITY-----highest---->

2nd

Func.

3rd

Func.

4th

Func.

Power

Supply

1 PJ6 KWJ6 SCK2 — V

2 PJ5 KWJ5 MOSI2 — V

3 PJ4 KWJ4 MISO2 — V

4 PA0———V

5 PA1———V

6 PA2———V

7 PA3———V

8 RESET — — — V

DDX

PUCR/PUPAE Disabled

Internal Pull

Resistor

CTRL

Reset

State

PERJ/PPSJ Up

PULLUP

9 VDDX1 — — — — — —

10VDDR———— — —

11 VSSX1 — — — — — —

12 PE0

EXTAL — — V

DDX

PUCR/PDPEE Down

13VSS———— — —

14 PE1

15 TEST — — — N.A. RESET

XTAL — — V

DDX

PUCR/PDPEE Down

pin Down

16PA4———V

17PA5———V

18PA6———V

19PA7———V

20 PJ0 KWJ0 MISO1 — V

21 PJ1 KWJ1 MOSI1 — V

22 PJ2 KWJ2 SCK1 — V

23 PJ3 KWJ3 SS1

—V

24 BKGD MODC — — V

25 PB0 ECLK — — V

26 PB1 API_EXTC

——V

DDX

PUCR/PUPAE Disabled

PERJ/PPSJ Up

PUCR/BKPUE Up

PUCR/PUPBE Disabled

27 PB2 ECLKX2 — — V

DDX

PUCR/PUPBE Disabled

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 97

Page 96

Device Overview MC9S12G-Family

Table 1-22. 100-Pin LQFP Pinout for S12G96 and S12G128

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

28 PB3 — — — V

29 PP0 KWP0 ETRIG0 PWM0 V

30 PP1 KWP1 ETRIG1 PWM1 V

31 PP2 KWP2 ETRIG2 PWM2 V

32 PP3 KWP3 ETRIG3 PWM3 V

33 PP4 KWP4 PWM4 — V

34 PP5 KWP5 PWM5 — V

35 PP6 KWP6 PWM6 — V

36 PP7 KWP7 PWM7 — V

4th

Power

Supply

DDX

PUCR/PUPBE Disabled

Internal Pull

Resistor

CTRL

PERP/PPSP Disabled

37 VDDX3 — — — — — —

38 VSSX3 — — — — — —

39 PT7 IOC7 — — V

40 PT6 IOC6 — — V

41 PT5 IOC5 — — V

42 PT4 IOC4 — — V

43 PT3 IOC3 — — V

44 PT2 IOC2 — — V

45 PT1 IOC1 — — V

46 PT0 IOC0 — — V

47 PB4 IRQ

48 PB5 XIRQ

——V

49 PB6 — — — V

50 PB7 — — — V

51PC0———V

52PC1———V

53PC2———V

54PC3———V

55 PAD0 KWAD0 AN0 — V

56 PAD8 KWAD8 AN8 — V

DDX

DDA

PERT/PPST Disabled

PUCR/PUPBE Disabled

PUCR/PUPCE Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

Reset

State

MC9S12G Family Reference Manual Rev.1.2 7

98 NXP Semiconductors

Page 97

Device Overview MC9S12G-Family

Table 1-22. 100-Pin LQFP Pinout for S12G96 and S12G128

Function

Package Pin Pin

<----lowest-----PRIORITY-----highest---->

2nd

Func.

3rd

Func.

4th

Func.

Power

Supply

57 PAD1 KWAD1 AN1 — V

58 PAD9 KWAD9 AN9 — V

59 PAD2 KWAD2 AN2 — V

60 PAD10 KWAD10 AN10 — V

61 PAD3 KWAD3 AN3 — V

62 PAD11 KWAD11 AN11 — V

63 PAD4 KWAD4 AN4 — V

64 PAD12 KWAD12 — — V

65 PAD5 KWAD5 AN5 — V

66 PAD13 KWAD13 — — V

67 PAD6 KWAD6 AN6 — V

68 PAD14 KWAD14 — — V

69 PAD7 KWAD7 AN7 — V

70 PAD15 KWAD15 — — V

71PC4———V

72 PC5 — — V

73 PC6 — — V

74 PC7 — — V

DDA

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PUCR/PUPCE Disabled

Internal Pull

Resistor

CTRL

Reset

State

75VRH———— — —

76VDDA———— — —

77 VSSA — — — — — —

78PD0———V

79PD1———V

80PD2———V

81PD3———V

82 PS0 RXD0 — — V

83 PS1 TXD0 — — V

84 PS2 RXD1 — — V

85 PS3 TXD1 — — V

DDX

PUCR/PUPDE Disabled

PERS/PPSS Up

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 99

Page 98

Device Overview MC9S12G-Family

Table 1-22. 100-Pin LQFP Pinout for S12G96 and S12G128

Function

<----lowest-----PRIORITY-----highest---->

Package Pin Pin

2nd

Func.

3rd

Func.

86 PS4 MISO0 — — V

87 PS5 MOSI0 — — V

88 PS6 SCK0 — — V

89 PS7 API_EXTC

SS0

Power

4th

—V

Supply

DDX

Internal Pull

Resistor

CTRL

PERS/PPSS Up

90 VSSX2 — — — — — —

91 VDDX2 — — — — — —

92 PM0 RXCAN — — V

93 PM1 TXCAN — — V

94PD4———V

95PD5———V

96PD6———V

97PD7———V

98 PM2 RXD2 — — V

99 PM3 TXD2 — — V

100 PJ7 KWJ7 SS2

The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled

—V

DDX

PERM/PPSM Disabled

PUCR/PUPDE Disabled

PERM/PPSM Disabled

PERJ/PPSJ Up

Reset

State

MC9S12G Family Reference Manual Rev.1.2 7

100 NXP Semiconductors

Page 99

1.8.7 S12GA96 and S12GA128

1 2 3 4 5 6 7 8

9 10 11 12

1314151617181920212223

36 35 34 33 32 31 30 29 28 27 26 25

4847464544434241403938

S12GA96

S12GA128

48-Pin LQFP

PAD7/KWAD7/AN7 PAD6/KWAD6/AN6 PAD5/KWAD5/AN5 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11 PAD3/KWAD3/AN3 PAD10/KWAD10/AN10 PAD2/KWAD2/AN2 PAD9/KWAD9/AN9 PAD1/KWAD1/AN1 PAD8/KWAD8/AN8 PAD0/KWAD0/AN0

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0

PWM1/ECLKX2/ETRIG1/KWP1/PP1

PWM2/ETRIG2/KWP2/PP2

PWM3/ETRIG3/KWP3/PP3

PWM4/KWP4/PP4

PWM5/KWP5/PP5

IOC5/PT5

IOC4/PT4

IOC3/PT3

IOC2/PT2

IRQ

/IOC1/PT1

XIRQ

/IOC0/PT0

RESET

VDDXR

VSSX

EXTAL/PE0

VSS

XTAL/PE1

TEST

MISO1/PWM6/KWJ0/PJ0

MOSI1/IOC6/KWJ1/PJ1

SCK1/IOC7/KWJ2/PJ2 SS1

/PWM7/KWJ3/PJ3

BKGD

PM1/TXD2/TXCAN

PM0/RXD2/RXCAN

PS7/API_EXTCLK/ECLK/SS0

PS6/SCK0

PS5/MOSI0

PS4/MISO0

PS3/TXD1

PS2/RXD1

PS1/TXD0

PS0/RXD0

VSSA

VDDA/VRH

1.8.7.1 Pinout 48-Pin LQFP

Device Overview MC9S12G-Family

Package Pin Pin

Figure 1-18. 48-Pin LQFP Pinout for S12GA96 and S12GA128

Table 1-23. 48-Pin LQFP Pinout for S12GA96 and S12GA128

<----lowest-----PRIORITY-----highest---->

2nd

Func.

Function

3rd

Func.

1 RESET — — — — V

4th

Func

Power

5th

Supply

Func

DDX

Internal Pull

Resistor

CTRL

PULLUP

Reset

State

MC9S12G Family Reference Manual Rev.1.27

NXP Semiconductors 101

Page 100

Device Overview MC9S12G-Family

Table 1-23. 48-Pin LQFP Pinout for S12GA96 and S12GA128

Package Pin Pin

Function

<----lowest-----PRIORITY-----highest---->

2nd

Func.

3rd

Func.

4th

Func

5th

Func

Power

Supply

Internal Pull

Resistor

CTRL

Reset

State

2VDDXR——— —— — —

3 VSSX — — — — — — —

4PE0

EXTAL — — — V

DDX

PUCR/PDPEE Down

5VSS——— —— — —

6PE1

7 TEST — — — — N.A. RESET

8 PJ0 KWJ0 PWM6 MISO1 — V

9 PJ1 KWJ1 IOC6 MOSI1 — V

10 PJ2 KWJ2 IOC7 SCK1 — V

11 PJ3 KWJ3 PWM7 SS1

12 BKGD MODC — — — V

13 PP0 KWP0 ETRIG0 API_EXTCLKPWM0 V

XTAL — — — V

DDX

PUCR/PDPEE Down

pin Down

DDX

—V

DDX

PERJ/PPSJ Up

PUCR/BKPUE Up

PERP/PPSP Disabled

14 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V

15 PP2 KWP2 ETRIG2 PWM2 — V

16 PP3 KWP3 ETRIG3 PWM3 — V

17 PP4 KWP4 PWM4 — — V

18 PP5 KWP5 PWM5 — — V

19 PT5 IOC5 — — — V

20 PT4 IOC4 — — — V

21 PT3 IOC3 — — — V

22 PT2 IOC2 — — — V

23 PT1 IOC1 IRQ

24 PT0 IOC0 XIRQ

——V

25 PAD0 KWAD0 AN0 — — V

26 PAD8 KWAD8 AN8 — — V

27 PAD1 KWAD1 AN1 — — V

28 PAD9 KWAD9 AN9 — V

29 PAD2 KWAD2 AN2 — — V

DDX

DDA

PERP/PPSP Disabled

PERT/PPST Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

PER0AD/PPS0AD Disabled

PER1AD/PPS1AD Disabled

MC9S12G Family Reference Manual Rev.1.2 7

102 NXP Semiconductors