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NXP Semiconductors MC9S08SU16, MC9S08SU16VFK, MC9S08SU8VFK Reference Manual

MC9S08SU16 Reference Manual
Supports: MC9S08SU16VFK MC9S08SU8VFK
Document Number: MC9S08SU16RM
Rev. 5, 4/2017
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
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Contents
Section number Title Page
About This Document
1.1 Overview.......................................................................................................................................................................33
1.1.1 Purpose...........................................................................................................................................................33
1.1.2 Audience........................................................................................................................................................ 33
1.2 Conventions.................................................................................................................................................................. 33
1.2.1 Numbering systems........................................................................................................................................33
1.2.2 Typographic notation..................................................................................................................................... 34
1.2.3 Special terms.................................................................................................................................................. 34
Introduction
2.1 Introduction...................................................................................................................................................................35
2.2 Module functional categories........................................................................................................................................35
2.2.1 S08L core modules.........................................................................................................................................36
2.2.2 System modules............................................................................................................................................. 36
2.2.3 Memories and memory interfaces..................................................................................................................37
2.2.4 Clocks.............................................................................................................................................................37
2.2.5 Security and integrity modules...................................................................................................................... 37
2.2.6 Analog modules............................................................................................................................................. 38
2.2.7 Timer modules............................................................................................................................................... 38
2.2.8 Communication interfaces............................................................................................................................. 39
2.2.9 Human-machine interfaces............................................................................................................................ 39
2.3 MCU block diagram..................................................................................................................................................... 40
2.4 Orderable part numbers.................................................................................................................................................41
Memory
3.1 Memory map.................................................................................................................................................................43
3.2 Reset and interrupt vector assignments.........................................................................................................................44
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3.3 Register addresses assignments.................................................................................................................................... 46
3.4 Random-access memory (RAM).................................................................................................................................. 51
3.5 Flash memory................................................................................................................................................................51
3.6 System register file....................................................................................................................................................... 52
Interrupt
4.1 Interrupts.......................................................................................................................................................................53
4.1.1 Interrupt stack frame...................................................................................................................................... 54
4.1.2 Hardware nested interrupt.............................................................................................................................. 55
4.1.2.1 Interrupt priority level register...................................................................................................57
4.1.2.2 Interrupt priority level comparator set....................................................................................... 57
4.1.2.3 Interrupt priority mask update and restore mechanism..............................................................57
4.1.2.4 Integration and application of the IPC....................................................................................... 58
4.2 IPC memory map and register descriptions..................................................................................................................59
4.2.1 IPC Status and Control Register (IPC_SC)....................................................................................................59
4.2.2 Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)...................................................................... 60
4.2.3
4.3 IRQ................................................................................................................................................................................61
4.3.1 Features.......................................................................................................................................................... 62
4.4 IRQ Memory Map and Register Descriptions.............................................................................................................. 63
4.4.1 Interrupt Pin Request Status and Control Register (IRQ_SC)....................................................................... 63
Interrupt Level Setting Registers n (IPC_ILRSn)..........................................................................................61
4.3.1.1 Configuration options................................................................................................................ 62
4.3.1.2 Edge and level sensitivity.......................................................................................................... 63
Clock management
5.1 Clock module................................................................................................................................................................65
5.2 System clock distribution..............................................................................................................................................65
5.3 Internal clock source (ICS)........................................................................................................................................... 67
5.4 20 kHz low-power oscillator (LPO)............................................................................................................................. 68
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5.5 Peripheral clock gating................................................................................................................................................. 68
Power Management
6.1 Introduction...................................................................................................................................................................71
6.2 Features.........................................................................................................................................................................71
6.2.1 Run mode....................................................................................................................................................... 71
6.2.2 Wait mode...................................................................................................................................................... 72
6.2.3 Stop mode...................................................................................................................................................... 72
6.2.4 Active BDM enabled in stop mode................................................................................................................72
6.2.5 Power modes behaviors................................................................................................................................. 73
6.3 Bandgap reference........................................................................................................................................................ 74
Signal multiplexing and signal descriptions
7.1 Introduction...................................................................................................................................................................75
7.2 Port control and interrupt module features................................................................................................................... 75
7.3 Signal multiplexing constraints.................................................................................................................................... 75
7.4 Pinout............................................................................................................................................................................76
7.4.1 Signal multiplexing and pin assignments.......................................................................................................76
7.4.2 Signal description table.................................................................................................................................. 77
7.4.3 Pinout ............................................................................................................................................................ 81
Port Control (PORT)
8.1 Introduction...................................................................................................................................................................83
8.2 Port data and data direction...........................................................................................................................................84
8.3 Internal pullup/pulldown enable................................................................................................................................... 84
8.4 Input glitch filter........................................................................................................................................................... 85
8.5 Memory map and register definition.............................................................................................................................86
8.5.1 Port A Data Register (PORT_PTAD)............................................................................................................ 86
8.5.2 Port B Data Register (PORT_PTBD)............................................................................................................ 87
8.5.3 Port C Data Register (PORT_PTCD)............................................................................................................ 87
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8.5.4 Port A Direction Register (PORT_PTADD)................................................................................................. 88
8.5.5 Port B Direction Register (PORT_PTBDD).................................................................................................. 89
8.5.6 Port C Direction Register (PORT_PTCDD).................................................................................................. 89
8.5.7 Port A Pullup Enable Register (PORT_PTAPE)........................................................................................... 90
8.5.8 Port B Pullup/Pulldown Enable Register (PORT_PTBPE)........................................................................... 91
8.5.9 Port C Pullup Enable Register (PORT_PTCPE)............................................................................................91
8.5.10 Port B High Drive Strength Selection Register (PORT_PTBHD)................................................................ 92
8.5.11 Port Clock Division Register (PORT_FCLKDIV)........................................................................................ 92
8.5.12 Port Filter Register 0 (PORT_IOFLT0).........................................................................................................93
8.5.13 Port Filter Register 1 (PORT_IOFLT1).........................................................................................................94
8.5.14 Port Filter Register 2 (PORT_IOFLT2).........................................................................................................95
System Integration Module (SIM)
9.1 Chip specific windowed COP.......................................................................................................................................97
9.2 System device identification (SDID)............................................................................................................................98
9.3 Universally unique identification (UUID)....................................................................................................................98
9.4 Reset and system initialization......................................................................................................................................98
9.5 Computer operating properly (COP) watchdog............................................................................................................99
9.6 System options..............................................................................................................................................................100
9.6.1 BKGD pin...................................................................................................................................................... 100
9.6.2 RESET_b pin enable...................................................................................................................................... 101
9.7 System interconnection.................................................................................................................................................101
9.7.1 Inter Module Crossbar Switch (XBAR).........................................................................................................101
9.7.2 Module to module interconnects....................................................................................................................103
9.8 Memory map and register definition.............................................................................................................................104
9.8.1 System Reset Status Register (SIM_SRS)..................................................................................................... 105
9.8.2 System Background Debug Force Reset Register (SIM_SBDFR)................................................................ 107
9.8.3 System Device Identification Register: High (SIM_SDIDH)........................................................................107
9.8.4 System Device Identification Register: Low (SIM_SDIDL).........................................................................108
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9.8.5 System Options Register 1 (SIM_SOPT1).................................................................................................... 108
9.8.6 System Options Register 2 (SIM_SOPT2).................................................................................................... 110
9.8.7 System Port A Pin Multiplexing Control Register: Low (SIM_MUXPTAL)............................................... 111
9.8.8 System Port A Pin Multiplexing Control Register: High (SIM_MUXPTAH).............................................. 112
9.8.9 System Port B Pin Multiplexing Control Register: Low (SIM_MUXPTBL)............................................... 113
9.8.10 System Port B Pin Multiplexing Control Register: High (SIM_MUXPTBH).............................................. 114
9.8.11 System Port C Pin Multiplexing Control Register: Low (SIM_MUXPTCL)............................................... 116
9.8.12 System Clock Gating Control 1 Register (SIM_SCGC1)..............................................................................116
9.8.13 System Clock Gating Control 2 Register (SIM_SCGC2)..............................................................................117
9.8.14 System Clock Gating Control 3 Register (SIM_SCGC3)..............................................................................119
9.8.15 System Clock Divider Register (SIM_SCDIV).............................................................................................120
9.8.16
9.8.17 Illegal Address Register: High (SIM_ILLAH).............................................................................................. 122
9.8.18 Illegal Address Register: Low (SIM_ILLAL)............................................................................................... 122
9.8.19 Universally Unique Identifier Register 0 (SIM_UUID0).............................................................................. 123
9.8.20 Universally Unique Identifier Register 1 (SIM_UUID1).............................................................................. 123
9.8.21 Universally Unique Identifier Register 2 (SIM_UUID2).............................................................................. 124
9.8.22 Universally Unique Identifier Register 3 (SIM_UUID3).............................................................................. 124
9.8.23 Universally Unique Identifier Register 4 (SIM_UUID4).............................................................................. 125
9.8.24 Universally Unique Identifier Register 5 (SIM_UUID5).............................................................................. 125
9.8.25 Universally Unique Identifier Register 6 (SIM_UUID6).............................................................................. 126
9.8.26 Universally Unique Identifier Register 7 (SIM_UUID7).............................................................................. 126
System POR Register (SIM_PORREGn)...................................................................................................... 121
Chapter 10
Central processor unit
10.1 Introduction...................................................................................................................................................................127
10.1.1 Features.......................................................................................................................................................... 127
10.2 Programmer's Model and CPU Registers..................................................................................................................... 128
10.2.1 Accumulator (A)............................................................................................................................................ 128
10.2.2 Index Register (H:X)......................................................................................................................................129
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10.2.3 Stack Pointer (SP).......................................................................................................................................... 129
10.2.4 Program Counter (PC)................................................................................................................................... 130
10.2.5 Condition Code Register (CCR).................................................................................................................... 130
10.3 Addressing Modes........................................................................................................................................................ 131
10.3.1 Inherent Addressing Mode (INH)..................................................................................................................132
10.3.2 Relative Addressing Mode (REL)..................................................................................................................132
10.3.3 Immediate Addressing Mode (IMM).............................................................................................................132
10.3.4 Direct Addressing Mode (DIR)......................................................................................................................133
10.3.5 Extended Addressing Mode (EXT)................................................................................................................133
10.3.6 Indexed Addressing Mode............................................................................................................................. 134
10.3.6.1 Indexed, No Offset (IX).............................................................................................................134
10.3.6.2 Indexed, No Offset with Post Increment (IX+)..........................................................................134
10.3.6.3 Indexed, 8-Bit Offset (IX1)........................................................................................................134
10.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+).................................................................... 135
10.3.6.5 Indexed, 16-Bit Offset (IX2)......................................................................................................135
10.3.6.6 SP-Relative, 8-Bit Offset (SP1)................................................................................................. 135
10.3.6.7 SP-Relative, 16-Bit Offset (SP2)............................................................................................... 136
10.3.7 Memory to memory Addressing Mode..........................................................................................................136
10.3.7.1 Direct to Direct...........................................................................................................................136
10.3.7.2 Immediate to Direct................................................................................................................... 136
10.3.7.3 Indexed to Direct, Post Increment..............................................................................................136
10.3.7.4 Direct to Indexed, Post-Increment............................................................................................. 137
10.4 Operation modes...........................................................................................................................................................137
10.4.1 Stop mode...................................................................................................................................................... 137
10.4.2 Wait mode......................................................................................................................................................137
10.4.3 Background mode.......................................................................................................................................... 138
10.4.4 Security mode................................................................................................................................................ 139
10.5 HCS08 V6 Opcodes......................................................................................................................................................141
10.6 Special Operations........................................................................................................................................................141
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10.6.1 Reset Sequence.............................................................................................................................................. 141
10.6.2 Interrupt Sequence......................................................................................................................................... 141
10.7 Instruction Set Summary...............................................................................................................................................142
Chapter 11
Flash Memory Module (FTMRH)
11.1 Introduction...................................................................................................................................................................155
11.2 Feature...........................................................................................................................................................................155
11.2.1 Flash memory features...................................................................................................................................155
11.2.2 Other flash module features........................................................................................................................... 156
11.3 Functional description...................................................................................................................................................156
11.3.1 Modes of operation........................................................................................................................................ 156
11.3.1.1 Wait mode..................................................................................................................................156
11.3.1.2 Stop mode.................................................................................................................................. 156
11.3.2 Flash block read access..................................................................................................................................156
11.3.3 Flash memory map.........................................................................................................................................157
11.3.4 Flash initialization after system reset.............................................................................................................157
11.3.5 Flash command operations.............................................................................................................................157
11.3.5.1 Writing the FCLKDIV register..................................................................................................158
11.3.5.2 Command write sequence.......................................................................................................... 160
11.3.6 Flash interrupts...............................................................................................................................................162
11.3.6.1 Description of flash interrupt operation.....................................................................................162
11.3.7 Protection....................................................................................................................................................... 162
11.3.8 Security.......................................................................................................................................................... 165
11.3.8.1 Unsecuring the MCU using backdoor key access......................................................................166
11.3.8.2 Unsecuring the MCU using BDM............................................................................................. 167
11.3.8.3 Mode and security effects on flash command availability.........................................................167
11.3.9 Flash commands.............................................................................................................................................167
11.3.9.1 Flash commands.........................................................................................................................167
11.3.10 Flash command summary.............................................................................................................................. 168
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11.3.10.1 Erase Verify All Blocks command............................................................................................ 169
11.3.10.2 Erase Verify Block command.................................................................................................... 169
11.3.10.3 Erase Verify Flash Section command........................................................................................ 170
11.3.10.4 Read once command.................................................................................................................. 171
11.3.10.5 Program Flash command........................................................................................................... 172
11.3.10.6 Program Once command............................................................................................................173
11.3.10.7 Erase All Blocks command........................................................................................................174
11.3.10.8 Erase flash block command....................................................................................................... 174
11.3.10.9 Erase flash sector command.......................................................................................................175
11.3.10.10 Unsecure flash command........................................................................................................... 176
11.3.10.11 Verify backdoor access key command.......................................................................................177
11.3.10.12 Set user margin level command................................................................................................. 177
11.3.10.13 Set factory margin level command............................................................................................ 179
11.4 Memory map and register definition.............................................................................................................................180
11.4.1 Flash Clock Divider Register (FTMRH_FCLKDIV).................................................................................... 181
11.4.2 Flash Security Register (FTMRH_FSEC)..................................................................................................... 182
11.4.3 Flash CCOB Index Register (FTMRH_FCCOBIX)......................................................................................183
11.4.4 Flash Configuration Register (FTMRH_FCNFG).........................................................................................183
11.4.5 Flash Status Register (FTMRH_FSTAT)...................................................................................................... 184
11.4.6 Flash Protection Register (FTMRH_FPROT)............................................................................................... 185
11.4.7 Flash Common Command Object Register:High (FTMRH_FCCOBHI)......................................................186
11.4.8 Flash Common Command Object Register: Low (FTMRH_FCCOBLO).................................................... 187
11.4.9 Flash Option Register (FTMRH_FOPT)....................................................................................................... 187
Chapter 12
Internal Clock Source (ICS)
12.1 Introduction...................................................................................................................................................................189
12.1.1 Features.......................................................................................................................................................... 189
12.1.2 Block diagram................................................................................................................................................190
12.1.3 Modes of operation........................................................................................................................................ 190
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12.1.3.1 FLL engaged internal (FEI)....................................................................................................... 190
12.1.3.2 FLL engaged external (FEE)......................................................................................................190
12.1.3.3 FLL bypassed internal (FBI)......................................................................................................191
12.1.3.4 FLL bypassed internal low power (FBILP)............................................................................... 191
12.1.3.5 FLL bypassed external (FBE)....................................................................................................191
12.1.3.6 FLL bypassed external low power (FBELP)............................................................................. 191
12.1.3.7 Stop (STOP)...............................................................................................................................191
12.2 External signal description............................................................................................................................................191
12.3 Register definition.........................................................................................................................................................192
12.3.1 ICS Control Register 1 (ICS_C1).................................................................................................................. 192
12.3.2 ICS Control Register 2 (ICS_C2).................................................................................................................. 193
12.3.3 ICS Control Register 3 (ICS_C3).................................................................................................................. 194
12.3.4 ICS Control Register 4 (ICS_C4).................................................................................................................. 195
12.3.5 ICS Status Register (ICS_S).......................................................................................................................... 196
12.4 Functional description...................................................................................................................................................197
12.4.1 Operational modes......................................................................................................................................... 197
12.4.1.1 FLL engaged internal (FEI)....................................................................................................... 197
12.4.1.2 FLL engaged external (FEE)......................................................................................................198
12.4.1.3 FLL bypassed internal (FBI)......................................................................................................198
12.4.1.4 FLL bypassed internal low power (FBILP)............................................................................... 198
12.4.1.5 FLL bypassed external (FBE)....................................................................................................199
12.4.1.6 FLL bypassed external low power (FBELP)............................................................................. 199
12.4.1.7 Stop............................................................................................................................................ 199
12.4.2 Mode switching..............................................................................................................................................199
12.4.3 Bus frequency divider.................................................................................................................................... 200
12.4.4 Low-power field usage...................................................................................................................................200
12.4.5 Internal reference clock..................................................................................................................................200
12.4.6 Fixed frequency clock....................................................................................................................................201
12.4.7 FLL lock and clock monitor...........................................................................................................................201
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12.4.7.1 FLL clock lock...........................................................................................................................201
12.4.7.2 External reference clock monitor...............................................................................................202
12.5 Initialization/application information........................................................................................................................... 202
12.5.1 Initializing FEI mode..................................................................................................................................... 202
12.5.2 Initializing FBI mode.....................................................................................................................................202
12.5.3 Initializing FEE mode.................................................................................................................................... 203
12.5.4 Initializing FBE mode....................................................................................................................................203
Chapter 13
Modulo Timer (MTIM)
13.1 Chip specific modulo timer...........................................................................................................................................205
13.2 Introduction...................................................................................................................................................................205
13.3 Features ........................................................................................................................................................................206
13.3.1 Block Diagram .............................................................................................................................................. 206
13.3.2 Modes of Operation ...................................................................................................................................... 207
13.3.2.1 MTIM16 in Wait Mode .............................................................................................................207
13.3.2.2 MTIM16 in Stop Modes............................................................................................................ 207
13.3.2.3 MTIM16 in Active Background Mode ..................................................................................... 208
13.4 External Signal Description .........................................................................................................................................208
13.4.1 TCLK — External Clock Source Input into MTIM16 ................................................................................. 208
13.5 Memory Map and Register Descriptions......................................................................................................................209
13.5.1 MTIM16 status and control register (MTIM_SC)......................................................................................... 209
13.5.2 MTIM16 clock configuration register (MTIM_CLK)...................................................................................210
13.5.3 MTIM16 counter register high (MTIM_CNTH)........................................................................................... 211
13.5.4 MTIM16 counter register low (MTIM_CNTL).............................................................................................212
13.5.5 MTIM16 modulo register high (MTIM_MODH)..........................................................................................213
13.5.6 MTIM16 modulo register low (MTIM_MODL)........................................................................................... 214
13.6 Functional Description .................................................................................................................................................214
13.6.1 MTIM16 Operation Example ........................................................................................................................216
Chapter 14
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Power Management Controller (PMC)
14.1 Chip specific power management controller ............................................................................................................... 217
14.2 Introduction...................................................................................................................................................................217
14.3 Features.........................................................................................................................................................................218
14.4 Overview.......................................................................................................................................................................218
14.5 Modes of operation.......................................................................................................................................................219
14.5.1 Reduced performance mode...........................................................................................................................219
14.5.2 Full performance mode.................................................................................................................................. 220
14.6 External signal description............................................................................................................................................220
14.6.1 VDD...............................................................................................................................................................220
14.6.2 VDDX............................................................................................................................................................ 220
14.6.3 VREFH...........................................................................................................................................................220
14.6.4 VDDF.............................................................................................................................................................221
14.6.5 VDD1.8..........................................................................................................................................................221
14.7 Memory map and register definition.............................................................................................................................221
14.7.1 Control Register (PMC_CTRL).....................................................................................................................222
14.7.2 Reset Flags Register (PMC_RST)................................................................................................................. 223
14.7.3 Temperature Control and Status Register (PMC_TPCTRLSTAT)............................................................... 223
14.7.4 Temperature Offset Step Trim Register (PMC_TPTM)................................................................................224
14.7.5 RC Oscillator Offset Step Trim Register (PMC_RC20KTRM).................................................................... 225
14.7.6 Low Voltage Control and Status Register 1 (system 5 V) (PMC_LVCTLSTAT1)......................................226
14.7.7 Low Voltage Control and Status Register 2 (V
14.7.8 V
Configuration Register (PMC_VREFHCFG).................................................................................... 227
REFH
) (PMC_LVCTLSTAT2)............................................. 227
REFH
14.7.9 VREFH Low Voltage Warning (LVW) Configuration Register (PMC_VREFHLVW)...............................228
14.7.10 Status Register (PMC_STAT)....................................................................................................................... 228
14.8 Functional description...................................................................................................................................................229
14.8.1 Voltage regulators..........................................................................................................................................229
14.8.1.1 VREGVDDX............................................................................................................................. 229
14.8.1.2 VREGVDDF..............................................................................................................................229
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14.8.1.3 VREGVDD................................................................................................................................ 230
14.8.1.4 VREGVREFH............................................................................................................................230
14.8.2 Power-on reset................................................................................................................................................230
14.8.3 Low voltage reset (LVR)............................................................................................................................... 230
14.8.3.1 LVR in low power mode............................................................................................................231
14.8.4 Low voltage warning (LVW).........................................................................................................................231
14.8.4.1 LVW on VDDX/VDDA............................................................................................................ 231
14.8.4.2 LVW on VREFH....................................................................................................................... 231
14.8.4.3 LVW in low power mode...........................................................................................................231
14.8.5 High-accuracy reference voltage....................................................................................................................232
14.8.6 Temperature sensor........................................................................................................................................232
14.8.6.1 High temperature warning......................................................................................................... 232
14.8.7 Low-power RC oscillator...............................................................................................................................233
14.9 Application information................................................................................................................................................233
Chapter 15
Keyboard Interrupts (KBI)
15.1 Chip specific KBI information......................................................................................................................................235
15.2 Introduction...................................................................................................................................................................235
15.2.1 Features.......................................................................................................................................................... 235
15.2.2 Modes of Operation....................................................................................................................................... 235
15.2.2.1 KBI in Wait mode......................................................................................................................236
15.2.2.2 KBI in Stop modes.....................................................................................................................236
15.2.3 Block Diagram............................................................................................................................................... 236
15.3 External signals description..........................................................................................................................................237
15.4 Register definition.........................................................................................................................................................237
15.5 Memory Map and Registers..........................................................................................................................................237
15.5.1 KBI Status and Control Register (KBI_SC).................................................................................................. 238
15.5.2 KBI Pin Enable Register (KBI_PE)...............................................................................................................239
15.5.3 KBI Edge Select Register (KBI_ES)............................................................................................................. 239
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15.6 Functional Description..................................................................................................................................................240
15.6.1 Edge-only sensitivity......................................................................................................................................240
15.6.2 Edge and level sensitivity.............................................................................................................................. 240
15.6.3 KBI Pullup Resistor....................................................................................................................................... 240
15.6.4 KBI initialization............................................................................................................................................241
Chapter 16
Cyclic redundancy check (CRC)
16.1 Chip specific cyclic redundancy check (CRC).............................................................................................................243
16.2 Introduction...................................................................................................................................................................243
16.2.1 Features.......................................................................................................................................................... 244
16.2.2 Block diagram................................................................................................................................................244
16.2.3 Modes of operation........................................................................................................................................ 244
16.2.3.1 Run mode................................................................................................................................... 244
16.2.3.2 Low-power modes (Wait or Stop)............................................................................................. 245
16.3 Memory map and register descriptions.........................................................................................................................245
16.3.1 CRC Data register: High 1 (CRC_DH1)........................................................................................................245
16.3.2 CRC Data register: High 0 (CRC_DH0)........................................................................................................246
16.3.3 CRC Data register: Low 1 (CRC_DL1).........................................................................................................247
16.3.4 CRC Data register: Low 0 (CRC_DL0).........................................................................................................247
16.3.5 CRC Polynomial Register: High 1 (CRC_PH1)............................................................................................248
16.3.6 CRC Polynomial Register: High 0 (CRC_PH0)............................................................................................249
16.3.7 CRC Polynomial Register: Low 1 (CRC_PL1)............................................................................................. 249
16.3.8 CRC Polynomial Register: Low 0 (CRC_PL0)............................................................................................. 250
16.3.9 CRC Control register (CRC_CTRL)..............................................................................................................250
16.4 Functional description...................................................................................................................................................251
16.4.1 CRC initialization/reinitialization..................................................................................................................251
16.4.2 CRC calculations............................................................................................................................................252
16.4.2.1 16-bit CRC................................................................................................................................. 252
16.4.2.2 32-bit CRC................................................................................................................................. 252
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16.4.3 Transpose feature........................................................................................................................................... 253
16.4.3.1 Types of transpose..................................................................................................................... 253
16.4.4 CRC result complement.................................................................................................................................254
Chapter 17
Analog-to-digital converter (ADC)
17.1 Chip-specific ADC information....................................................................................................................................255
17.1.1 Analog-to-digital converter (ADC)................................................................................................................255
17.1.2 ADC channel assignments............................................................................................................................. 256
17.1.3 ADC analog supply and reference connections............................................................................................. 257
17.1.4 Alternate clock............................................................................................................................................... 257
17.1.5 Hardware trigger............................................................................................................................................ 258
17.1.6 Temperature sensor........................................................................................................................................258
17.2 Introduction...................................................................................................................................................................259
17.2.1 Features.......................................................................................................................................................... 259
17.2.2 Block Diagram............................................................................................................................................... 260
17.3 External Signal Description..........................................................................................................................................260
17.3.1 Analog Power (VDDA)................................................................................................................................. 261
17.3.2 Analog Ground (VSSA).................................................................................................................................261
17.3.3 Voltage Reference High (VREFH)................................................................................................................261
17.3.4 Voltage Reference Low (VREFL)................................................................................................................. 261
17.3.5 Analog Channel Inputs (ADx)....................................................................................................................... 261
17.4 ADC Control Registers.................................................................................................................................................262
17.4.1
17.4.2
17.4.3
17.4.4
17.4.5
Status and Control Register 1 (ADCx_SC1)..................................................................................................262
Status and Control Register 2 (ADCx_SC2)..................................................................................................264
Status and Control Register 3 (ADCx_SC3)..................................................................................................265
Status and Control Register 4 (ADCx_SC4)..................................................................................................266
Conversion Result High Register (ADCx_RH)............................................................................................. 267
17.4.6
17.4.7
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Conversion Result Low Register (ADCx_RL).............................................................................................. 268
Compare Value High Register (ADCx_CVH)...............................................................................................269
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17.4.8
17.5 Functional description...................................................................................................................................................270
17.5.1 Clock select and divide control......................................................................................................................270
17.5.2 Hardware trigger............................................................................................................................................ 271
17.5.3 Conversion control.........................................................................................................................................271
17.5.4 Automatic compare function..........................................................................................................................274
17.5.5 FIFO operation...............................................................................................................................................275
17.5.6 MCU wait mode operation.............................................................................................................................279
17.5.7 MCU Stop mode operation............................................................................................................................ 279
Compare Value Low Register (ADCx_CVL)................................................................................................269
17.5.3.1 Initiating conversions.................................................................................................................271
17.5.3.2 Completing conversions.............................................................................................................272
17.5.3.3 Aborting conversions................................................................................................................. 272
17.5.3.4 Power control............................................................................................................................. 273
17.5.3.5 Sample time and total conversion time......................................................................................273
17.5.7.1 Stop mode with ADACK disabled.............................................................................................279
17.5.7.2 Stop mode with ADACK enabled..............................................................................................279
17.6 Initialization information..............................................................................................................................................280
17.6.1 ADC module initialization example.............................................................................................................. 280
17.6.1.1 Initialization sequence................................................................................................................280
17.6.1.2 Pseudo-code example.................................................................................................................281
17.6.2 ADC FIFO module initialization example.....................................................................................................281
17.6.2.1 Pseudo-code example.................................................................................................................282
17.7 Application information................................................................................................................................................283
17.7.1 External pins and routing............................................................................................................................... 283
17.7.1.1 Analog supply pins.....................................................................................................................283
17.7.1.2 Analog reference pins................................................................................................................ 283
17.7.1.3 Analog input pins.......................................................................................................................284
17.7.2 Sources of error..............................................................................................................................................285
17.7.2.1 Sampling error............................................................................................................................285
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17.7.2.2 Pin leakage error........................................................................................................................ 285
17.7.2.3 Noise-induced errors..................................................................................................................285
17.7.2.4 Code width and quantization error.............................................................................................286
17.7.2.5 Linearity errors...........................................................................................................................287
17.7.2.6 Code jitter, non-monotonicity, and missing codes.....................................................................287
Chapter 18
Chip-specific ACMP information
18.1 CMP configuration information....................................................................................................................................289
18.2 ACMP in stop mode..................................................................................................................................................... 290
18.3 ....................................................................................................................................................................................... 0
18.3.1 ........................................................................................................................................................................ 0
18.3.2 ........................................................................................................................................................................ 0
18.4 Introduction...................................................................................................................................................................290
18.5 CMP Features................................................................................................................................................................291
18.6 6-bit DAC Key Features............................................................................................................................................... 291
18.7 ANMUX Key Features.................................................................................................................................................292
18.8 CMP, DAC, and ANMUX Diagram.............................................................................................................................292
18.9 CMP Block Diagram.....................................................................................................................................................293
18.10 Memory Map/Register Definitions...............................................................................................................................295
18.10.1 CMP Control Register 0 (CMP_CR0)........................................................................................................... 295
18.10.2 CMP Control Register 1 (CMP_CR1)........................................................................................................... 296
18.10.3 CMP Filter Period Register (CMP_FPR).......................................................................................................297
18.10.4 CMP Status and Control Register (CMP_SCR)............................................................................................ 298
18.10.5 DAC Control Register (CMP_DACCR)........................................................................................................299
18.10.6 MUX Control Register (CMP_MUXCR)......................................................................................................300
18.10.7 MUX Pin Enable Register (CMP_MUXPE)................................................................................................. 301
18.11 CMP Functional Description........................................................................................................................................ 301
18.11.1 CMP Functional Modes................................................................................................................................. 301
18.11.1.1 Disabled Mode (# 1).................................................................................................................. 303
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18.11.1.2 Continuous Mode (#s 2A & 2B)................................................................................................ 303
18.11.1.3 Sampled, Non-Filtered Mode (#s 3A & 3B)..............................................................................304
18.11.1.4 Sampled, Filtered Mode (#s 4A & 4B)...................................................................................... 306
18.11.1.5 Windowed Mode (#s 5A & 5B)................................................................................................. 308
18.11.1.6 Windowed/Resampled Mode (# 6)............................................................................................ 310
18.11.1.7 Windowed/Filtered Mode (#7)...................................................................................................310
18.11.2 Power Modes..................................................................................................................................................311
18.11.2.1 Wait Mode Operation.................................................................................................................311
18.11.2.2 Stop Mode Operation................................................................................................................. 311
18.11.2.3 Background Debug Mode Operation......................................................................................... 312
18.11.3 Startup and Operation.................................................................................................................................... 312
18.11.4 Low Pass Filter...............................................................................................................................................313
18.11.4.1 Enabling Filter Modes................................................................................................................313
18.11.4.2 Latency Issues............................................................................................................................ 314
18.12 CMP Interrupts..............................................................................................................................................................315
18.13 Digital to Analog Converter Block Diagram................................................................................................................315
18.14 DAC Functional Description........................................................................................................................................ 316
18.14.1 Voltage Reference Source Select...................................................................................................................316
18.15 DAC Resets...................................................................................................................................................................316
18.16 DAC Clocks..................................................................................................................................................................316
18.17 DAC Interrupts..............................................................................................................................................................316
Chapter 19
FlexTimer Module (FTM)
19.1 Chip specific FlexTimer module.................................................................................................................................. 317
19.2 Introduction...................................................................................................................................................................318
19.2.1 FlexTimer philosophy....................................................................................................................................318
19.2.2 Features.......................................................................................................................................................... 318
19.2.3 Modes of operation........................................................................................................................................ 319
19.2.4 Block diagram................................................................................................................................................319
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19.3 Signal description..........................................................................................................................................................320
19.3.1 EXTCLK — FTM external clock.................................................................................................................. 321
19.3.2 CHn — FTM channel (n) I/O pin.................................................................................................................. 321
19.4 Memory map and register definition.............................................................................................................................321
19.4.1 Module memory map.....................................................................................................................................321
19.4.2 Register descriptions......................................................................................................................................321
19.4.3
19.4.4
19.4.5
19.4.6
19.4.7
19.4.8
19.4.9
19.4.10
19.5 Functional Description..................................................................................................................................................329
19.5.1 Clock Source..................................................................................................................................................329
19.5.2 Prescaler.........................................................................................................................................................330
19.5.3 Counter...........................................................................................................................................................330
Status and Control (FTMx_SC)..................................................................................................................... 322
Counter High (FTMx_CNTH)....................................................................................................................... 323
Counter Low (FTMx_CNTL)........................................................................................................................ 324
Modulo High (FTMx_MODH)...................................................................................................................... 324
Modulo Low (FTMx_MODL)....................................................................................................................... 325
Channel Status and Control (FTMx_CnSC).................................................................................................. 326
Channel Value High (FTMx_CnVH).............................................................................................................327
Channel Value Low (FTMx_CnVL)..............................................................................................................328
19.5.1.1 Counter Clock Source................................................................................................................ 329
19.5.3.1 Up counting................................................................................................................................331
19.5.3.2 Up-down counting......................................................................................................................331
19.5.3.3 Free running counter.................................................................................................................. 332
19.5.3.4 Counter reset.............................................................................................................................. 332
19.5.4 Input capture mode.........................................................................................................................................332
19.5.5 Output compare mode....................................................................................................................................333
19.5.6 Edge-aligned PWM (EPWM) mode.............................................................................................................. 335
19.5.7 Center-aligned PWM (CPWM) mode............................................................................................................336
19.5.8 Update of the registers with write buffers......................................................................................................338
19.5.8.1 MODH:L registers..................................................................................................................... 338
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19.5.8.2 CnVH:L registers....................................................................................................................... 339
19.5.9 BDM mode.....................................................................................................................................................339
19.6 Reset overview..............................................................................................................................................................339
19.7 FTM Interrupts..............................................................................................................................................................341
19.7.1 Timer overflow interrupt................................................................................................................................341
19.7.2 Channel (n) interrupt......................................................................................................................................341
Chapter 20
Pules Width Timer (PWT)
20.1 Chip specific pules width timer.................................................................................................................................... 343
20.2 Introduction...................................................................................................................................................................344
20.2.1 Features.......................................................................................................................................................... 344
20.2.2 Modes of operation........................................................................................................................................ 344
20.2.3 Block diagram................................................................................................................................................345
20.3 External signal description............................................................................................................................................345
20.3.1 Overview........................................................................................................................................................345
20.3.2 PWTIN[3:0] — pulse width timer capture inputs..........................................................................................346
20.3.3 ALTCLK— alternative clock source for counter.......................................................................................... 346
20.4 Memory Map and Register Descriptions......................................................................................................................346
20.4.1
20.4.2
20.4.3
20.4.4
20.4.5
20.4.6
20.4.7
20.4.8
20.5 Functional description...................................................................................................................................................352
Pulse Width Timer Control and Status Register (PWTx_CS)....................................................................... 347
Pulse Width Timer Control Register (PWTx_CR)........................................................................................ 348
Pulse Width Timer Positive Pulse Width Register: High (PWTx_PPH).......................................................349
Pulse Width Timer Positive Pulse Width Register: Loq (PWTx_PPL).........................................................350
Pulse Width Timer Negative Pulse Width Register: High (PWTx_NPH).....................................................350
Pulse Width Timer Negative Pulse Width Register: Low (PWTx_NPL)......................................................351
Pulse Width Timer Counter Register: High (PWTx_CNTH)........................................................................ 351
Pulse Width Timer Counter Register: Low (PWTx_CNTL)......................................................................... 351
20.5.1 PWT counter and PWT clock pre-scaler........................................................................................................352
20.5.2 Edge detection and capture control................................................................................................................352
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20.6 Reset overview..............................................................................................................................................................356
20.6.1 Description of reset operation........................................................................................................................356
20.7 Interrupts.......................................................................................................................................................................357
20.7.1 Description of interrupt operation..................................................................................................................357
20.7.2 Application examples.....................................................................................................................................358
20.8 Initialization/Application information..........................................................................................................................359
Chapter 21
Inter-Integrated Circuit (I2C)
21.1 Chip specific inter-integrated circuit............................................................................................................................ 361
21.2 Introduction...................................................................................................................................................................361
21.2.1 Features.......................................................................................................................................................... 362
21.2.2 Modes of operation........................................................................................................................................ 362
21.2.3 Block diagram................................................................................................................................................363
21.3 I2C signal descriptions..................................................................................................................................................364
21.4 Memory map/register definition...................................................................................................................................364
21.4.1 I2C Address Register 1 (I2C_A1)..................................................................................................................365
21.4.2 I2C Frequency Divider register (I2C_F)........................................................................................................365
21.4.3 I2C Control Register 1 (I2C_C1)...................................................................................................................366
21.4.4 I2C Status register (I2C_S)............................................................................................................................368
21.4.5 I2C Data I/O register (I2C_D)....................................................................................................................... 369
21.4.6 I2C Control Register 2 (I2C_C2)...................................................................................................................370
21.4.7 I2C Stop Control and Status Register (I2C_SCS)......................................................................................... 371
21.4.8 I2C Range Address register (I2C_RA).......................................................................................................... 372
21.4.9 I2C SMBus Control and Status register (I2C_SMB).....................................................................................373
21.4.10 I2C Address Register 2 (I2C_A2)..................................................................................................................374
21.4.11 I2C SCL Low Timeout Register High (I2C_SLTH)..................................................................................... 375
21.4.12 I2C SCL Low Timeout Register Low (I2C_SLTL).......................................................................................375
21.4.13 I2C Status register 2 (I2C_S2).......................................................................................................................376
21.5 Functional description...................................................................................................................................................376
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21.5.1 I2C protocol................................................................................................................................................... 376
21.5.1.1 START signal............................................................................................................................ 377
21.5.1.2 Slave address transmission.........................................................................................................378
21.5.1.3 Data transfers............................................................................................................................. 378
21.5.1.4 STOP signal............................................................................................................................... 379
21.5.1.5 Repeated START signal.............................................................................................................379
21.5.1.6 Arbitration procedure.................................................................................................................379
21.5.1.7 Clock synchronization................................................................................................................380
21.5.1.8 Handshaking...............................................................................................................................380
21.5.1.9 Clock stretching......................................................................................................................... 380
21.5.1.10 I2C divider and hold values....................................................................................................... 381
21.5.2 10-bit address................................................................................................................................................. 382
21.5.2.1 Master-transmitter addresses a slave-receiver........................................................................... 382
21.5.2.2 Master-receiver addresses a slave-transmitter........................................................................... 383
21.5.3 Address matching...........................................................................................................................................383
21.5.4 System management bus specification.......................................................................................................... 384
21.5.4.1 Timeouts.....................................................................................................................................384
21.5.4.2 FAST ACK and NACK............................................................................................................. 386
21.5.5 Resets............................................................................................................................................................. 387
21.5.6 Interrupts........................................................................................................................................................ 387
21.5.6.1 Byte transfer interrupt................................................................................................................ 388
21.5.6.2 Address detect interrupt............................................................................................................. 388
21.5.6.3 Stop Detect Interrupt..................................................................................................................388
21.5.6.4 Exit from low-power/stop modes...............................................................................................388
21.5.6.5 Arbitration lost interrupt............................................................................................................ 388
21.5.6.6 Timeout interrupt in SMBus...................................................................................................... 389
21.5.7 Address matching wake-up............................................................................................................................389
21.5.8 Double buffering mode.................................................................................................................................. 390
21.6 Initialization/application information........................................................................................................................... 391
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Chapter 22
Serial Communications Interface (SCI)
22.1 Chip specific serial communications interface.............................................................................................................395
22.2 Introduction...................................................................................................................................................................396
22.2.1 Features.......................................................................................................................................................... 396
22.2.2 Modes of operation........................................................................................................................................ 396
22.2.3 Block diagram................................................................................................................................................397
22.3 SCI signal descriptions................................................................................................................................................. 399
22.3.1 Detailed signal descriptions........................................................................................................................... 399
22.4 Register definition.........................................................................................................................................................399
22.4.1
22.4.2
22.4.3
22.4.4
22.4.5
22.4.6
22.4.7
22.4.8
22.5 Functional description...................................................................................................................................................409
22.5.1 Baud rate generation...................................................................................................................................... 410
22.5.2 Transmitter functional description.................................................................................................................410
22.5.3 Receiver functional description..................................................................................................................... 412
SCI Baud Rate Register: High (SCIx_BDH)................................................................................................. 400
SCI Baud Rate Register: Low (SCIx_BDL).................................................................................................. 401
SCI Control Register 1 (SCIx_C1).................................................................................................................401
SCI Control Register 2 (SCIx_C2).................................................................................................................403
SCI Status Register 1 (SCIx_S1)................................................................................................................... 404
SCI Status Register 2 (SCIx_S2)................................................................................................................... 406
SCI Control Register 3 (SCIx_C3).................................................................................................................407
SCI Data Register (SCIx_D)..........................................................................................................................409
22.5.2.1 Send break and queued idle....................................................................................................... 411
22.5.3.1 Data sampling technique............................................................................................................413
22.5.3.2 Receiver wake-up operation.......................................................................................................414
22.5.4 Interrupts and status flags.............................................................................................................................. 415
22.5.5 Baud rate tolerance.........................................................................................................................................416
22.5.5.1 Slow data tolerance.................................................................................................................... 416
22.5.5.2 Fast data tolerance......................................................................................................................418
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22.5.6 Additional SCI functions............................................................................................................................... 419
22.5.6.1 8- and 9-bit data modes..............................................................................................................419
22.5.6.2 Stop mode operation.................................................................................................................. 419
22.5.6.3 Loop mode................................................................................................................................. 419
22.5.6.4 Single-wire operation.................................................................................................................420
Chapter 23
Programmable Delay Block (PDB)
23.1 Chip specific programmable delay block..................................................................................................................... 421
23.2 Introduction...................................................................................................................................................................422
23.3 Features.........................................................................................................................................................................422
23.4 Block diagram...............................................................................................................................................................422
23.5 Mode of operation.........................................................................................................................................................423
23.5.1 Single shot delay mode ................................................................................................................................. 423
23.5.2 Continuous count mode................................................................................................................................. 424
23.6 Memory Map and Register Descriptions......................................................................................................................425
23.6.1 PDB Control Register 0 (PDB_CTRL0)........................................................................................................425
23.6.2 PDB Control Register 1 (PDB_CTRL1)........................................................................................................426
23.6.3 PDB0 Comparison Low Register (PDB_CMPL0)........................................................................................ 427
23.6.4 PDB0 Comparison High Register (PDB_CMPH0)....................................................................................... 428
23.6.5 PDB0 Counter High/Low (PDB_CNT0)....................................................................................................... 428
23.6.6 PDB1 Comparison Low Register (PDB_CMPL1)........................................................................................ 429
23.6.7 PDB1 Comparison High Register (PDB_CMPH1)....................................................................................... 429
23.6.8 PDB1 Counter High/Low (PDB_CNT1)....................................................................................................... 430
Chapter 24
Inter-peripheral Crossbar Switch (XBAR)
24.1 Introduction...................................................................................................................................................................431
24.2 Features.........................................................................................................................................................................431
24.3 Block diagram...............................................................................................................................................................431
24.4 Memory Map and Register Descriptions......................................................................................................................432
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24.4.1 External Mux Selection Register (XBAR_EXTMUX)................................................................................. 433
24.4.2
XBAR Selection Register (XBAR_SELn).................................................................................................... 434
Chapter 25
Gate Drive Unit (GDU)
25.1 Chip specific GDU information....................................................................................................................................435
25.2 Introduction...................................................................................................................................................................435
25.3 Features.........................................................................................................................................................................436
25.4 Block diagram...............................................................................................................................................................436
25.5 Modes of operation.......................................................................................................................................................437
25.6 Memory map and register definition.............................................................................................................................438
25.6.1 PHCMP0 Control Register 0 (GDU_PHCMP0CR0).................................................................................... 439
25.6.2 PHCMP0 Control Register 1 (GDU_PHCMP0CR1).................................................................................... 439
25.6.3 PHCMP0 Filter Period Register (GDU_PHCMP0FPR)................................................................................441
25.6.4 PHCMP0 Status and Control Register (GDU_PHCMP0SCR)......................................................................441
25.6.5 PHCMP1 Control Register 0 (GDU_PHCMP1CR0).................................................................................... 442
25.6.6 PHCMP1 Control Register 1 (GDU_PHCMP1CR1).................................................................................... 443
25.6.7 PHCMP1 Filter Period Register (GDU_PHCMP1FPR)................................................................................444
25.6.8 PHCMP1 Status and Control Register (GDU_PHCMP1SCR)......................................................................445
25.6.9 PHCMP2 Control Register 0 (GDU_PHCMP2CR0).................................................................................... 446
25.6.10 PHCMP2 Control Register 1 (GDU_PHCMP2CR1).................................................................................... 446
25.6.11 PHCMP2 Filter Period Register (GDU_PHCMP2FPR)................................................................................448
25.6.12 PHCMP2 Status and Control Register (GDU_PHCMP2SCR)......................................................................448
25.6.13 Clamp Control Register (GDU_CLMPCTRL)..............................................................................................449
25.6.14 I/O Control Register (GDU_IOCTRL)..........................................................................................................450
25.6.15 Virtual Network Phase Detection Control (GDU_PHASECTRL)................................................................451
25.6.16 Current Sensor and Overcurrent Protection Control Register (GDU_CURCTRL).......................................452
25.6.17 LIMIT0 CMP Control Register 0 (GDU_LIMIT0CR0)................................................................................452
25.6.18 LIMIT0 CMP Control Register 1 (GDU_LIMIT0CR1)................................................................................453
25.6.19 LIMIT0 CMP Filter Period Register (GDU_LIMIT0FPR)........................................................................... 454
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25.6.20 LIMIT0 CMP Status and Control Register (GDU_LIMIT0SCR).................................................................455
25.6.21 LIMIT0 DAC Control Register (GDU_LIMIT0DACCR)............................................................................ 456
25.6.22 LIMIT1 CMP Control Register 0 (GDU_LIMIT1CR0)................................................................................456
25.6.23 LIMIT1 CMP Control Register 1 (GDU_LIMIT1CR1)................................................................................457
25.6.24 LIMIT1 CMP Filter Period Register (GDU_LIMIT1FPR)........................................................................... 458
25.6.25 LIMIT1 CMP Status and Control Register (GDU_LIMIT1SCR).................................................................459
25.6.26 LIMIT1 DAC Control Register (GDU_LIMIT1DACCR)............................................................................ 460
25.6.27 PDCS and Clamp Status Register (GDU_STATREG)..................................................................................460
25.6.28 LIMIT CMP BIAS Register (GDU_SIGBIAS).............................................................................................461
25.7 Functional description...................................................................................................................................................461
25.7.1 Phase detection function descriptions............................................................................................................462
25.7.1.1 Phase detection diagram.............................................................................................................462
25.7.1.2 Phase detection descriptions...................................................................................................... 462
25.7.2 OpAMP function descriptions....................................................................................................................... 463
25.7.2.1 OpAMP diagram........................................................................................................................463
25.7.2.2 OpAMP descriptions..................................................................................................................464
25.7.3 Predrive function descriptions....................................................................................................................... 464
25.7.3.1 Predrive diagram........................................................................................................................464
25.7.3.2 Predrive descriptions..................................................................................................................465
25.7.4 GCMP functional description........................................................................................................................ 465
25.7.4.1 GCMP diagram.......................................................................................................................... 465
25.7.4.2 GCMP block diagram................................................................................................................ 466
25.7.4.3 GCMP functional modes............................................................................................................468
25.7.4.4 Power modes..............................................................................................................................477
25.7.4.5 Startup and operation................................................................................................................. 478
25.7.4.6 Low pass filter............................................................................................................................478
25.8 GCMP interrupts...........................................................................................................................................................480
Chapter 26
Pulse Width Modulator (PWM)
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26.1 Chip specific pulse width modulator............................................................................................................................ 481
26.2 Introduction...................................................................................................................................................................482
26.2.1 Overview........................................................................................................................................................482
26.2.2 Features.......................................................................................................................................................... 482
26.2.3 Modes of operation........................................................................................................................................ 483
26.2.4 Block diagram................................................................................................................................................483
26.3 Functional description...................................................................................................................................................485
26.3.1 Prescaler.........................................................................................................................................................485
26.3.2 Generator........................................................................................................................................................485
26.3.2.1 Alignment and compare output polarity.................................................................................... 486
26.3.2.2 Period......................................................................................................................................... 487
26.3.2.3 Pulse width duty cycle............................................................................................................... 487
26.3.3 Independent or complementary channel operation........................................................................................ 489
26.3.4 Deadtime generators...................................................................................................................................... 491
26.3.5 Asymmetric PWM output.............................................................................................................................. 493
26.3.6 Variable edge placement PWM output.......................................................................................................... 493
26.3.7 PWM output polarity..................................................................................................................................... 494
26.3.8 Generator loading...........................................................................................................................................497
26.3.8.1 Load enable................................................................................................................................497
26.3.8.2 Load frequency.......................................................................................................................... 497
26.3.8.3 Reload flag................................................................................................................................. 498
26.3.8.4 Initialization............................................................................................................................... 500
26.3.9 Fault protection.............................................................................................................................................. 501
26.3.9.1 Fault pin filter.............................................................................................................................502
26.3.9.2 Automatic fault clearing.............................................................................................................503
26.3.9.3 Manual fault clearing................................................................................................................. 503
26.4 Memory Map and Register Descriptions......................................................................................................................504
26.4.1 PWM Control Register: Low (PWM_CTRLL)............................................................................................. 506
26.4.2 PWM Control Register: High (PWM_CTRLH)............................................................................................ 507
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26.4.3 PWM Fault Control Register: Low (PWM_FCTRLL)..................................................................................508
26.4.4 PWM Fault Control Register: High (PWM_FCTRLH).................................................................................510
26.4.5 PWM Fault Status Acknowledge Register: Low (PWM_FLTACKL)..........................................................510
26.4.6 PWM Fault Status Acknowledge Register: High (PWM_FLTACKH).........................................................511
26.4.7 PWM Output Control Register: Low (PWM_OUTL)................................................................................... 513
26.4.8 PWM Output Control Register: High (PWM_OUTH)..................................................................................514
26.4.9 PWM Counter Register: Low (PWM_CNTRL)............................................................................................ 514
26.4.10 PWM Counter Register: High (PWM_CNTRH)...........................................................................................515
26.4.11 PWM Counter Register: Low (PWM_CMODL)...........................................................................................515
26.4.12 PWM Counter Register: High (PWM_CMODH)..........................................................................................516
26.4.13
26.4.14
26.4.15
26.4.16
26.4.17 PWM Disable Mapping Registers 1: Low (PWM_DMAP1L)......................................................................519
26.4.18 PWM Disable Mapping Registers 1: High (PWM_DMAP1H).....................................................................520
26.4.19 PWM Disable Mapping Registers 2: Low (PWM_DMAP2L)......................................................................520
26.4.20 PWM Configure Register: Low (PWM_CNFGL).........................................................................................520
26.4.21 PWM Configure Register: High (PWM_CNFGH)........................................................................................521
26.4.22 PWM Channel Control Register: Low (PWM_CCTRLL)............................................................................ 522
26.4.23 PWM Channel Control Register: High (PWM_CCTRLH)........................................................................... 524
26.4.24 PWM Pulse Edge Control Register: Low (PWM_PECTRLL)......................................................................524
26.4.25 PWM Compare Invert Register: High (PWM_CINVH)................................................................................525
26.5 Resets............................................................................................................................................................................526
PWM Value Register: Low (PWM_VALnL)................................................................................................516
PWM Value Register: High (PWM_VALnH)...............................................................................................517
PWM Deadtime Register: Low (PWM_DTIMnL)........................................................................................518
PWM Deadtime Register: High (PWM_DTIMnH).......................................................................................518
26.6 Clocks........................................................................................................................................................................... 526
26.7 Interrupts.......................................................................................................................................................................527
Chapter 27
Development support
27.1 Introduction...................................................................................................................................................................529
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27.1.1 Forcing active background.............................................................................................................................529
27.1.2 Features.......................................................................................................................................................... 529
27.2 Background debug controller (BDC)............................................................................................................................530
27.2.1 BKGD pin description................................................................................................................................... 531
27.2.2 Communication details.................................................................................................................................. 532
27.2.3 BDC commands............................................................................................................................................. 534
27.2.4 BDC hardware breakpoint............................................................................................................................. 537
27.3 On-chip debug system (DBG)...................................................................................................................................... 537
27.3.1 Comparators A and B.....................................................................................................................................538
27.3.2 Bus capture information and FIFO operation................................................................................................ 538
27.3.3 Change-of-flow information.......................................................................................................................... 539
27.3.4 Tag vs. force breakpoints and triggers...........................................................................................................540
27.3.5 Trigger modes................................................................................................................................................ 541
27.3.6 Hardware breakpoints.................................................................................................................................... 542
27.4 Memory map and register description.......................................................................................................................... 543
27.4.1 BDC Status and Control Register (BDC_SCR).............................................................................................543
27.4.2 BDC Breakpoint Match Register: High (BDC_BKPTH)..............................................................................545
27.4.3 BDC Breakpoint Register: Low (BDC_BKPTL).......................................................................................... 546
27.4.4 System Background Debug Force Reset Register (BDC_SBDFR)...............................................................546
Chapter 28
Debug module (DBG)
28.1 Introduction...................................................................................................................................................................549
28.1.1 Features.......................................................................................................................................................... 549
28.1.2 Modes of operation........................................................................................................................................ 550
28.1.3 Block diagram................................................................................................................................................550
28.2 Signal description..........................................................................................................................................................551
28.3 Memory map and registers............................................................................................................................................551
28.3.1 Debug Comparator A High Register (DBG_CAH)....................................................................................... 552
28.3.2 Debug Comparator A Low Register (DBG_CAL)........................................................................................ 553
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
30 NXP Semiconductors
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