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NXP Semiconductors MC9S08SU16, MC9S08SU16VFK, MC9S08SU8VFK Reference Manual

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MC9S08SU16 Reference Manual
Supports: MC9S08SU16VFK MC9S08SU8VFK
Document Number: MC9S08SU16RM
Rev. 5, 4/2017
MC9S08SU16 Reference Manual, Rev. 5, 4/2017
2 NXP Semiconductors
Contents
Section number Title Page
About This Document
1.1 Overview.......................................................................................................................................................................33
1.1.1 Purpose...........................................................................................................................................................33
1.1.2 Audience........................................................................................................................................................ 33
1.2 Conventions.................................................................................................................................................................. 33
1.2.1 Numbering systems........................................................................................................................................33
1.2.2 Typographic notation..................................................................................................................................... 34
1.2.3 Special terms.................................................................................................................................................. 34
Introduction
2.1 Introduction...................................................................................................................................................................35
2.2 Module functional categories........................................................................................................................................35
2.2.1 S08L core modules.........................................................................................................................................36
2.2.2 System modules............................................................................................................................................. 36
2.2.3 Memories and memory interfaces..................................................................................................................37
2.2.4 Clocks.............................................................................................................................................................37
2.2.5 Security and integrity modules...................................................................................................................... 37
2.2.6 Analog modules............................................................................................................................................. 38
2.2.7 Timer modules............................................................................................................................................... 38
2.2.8 Communication interfaces............................................................................................................................. 39
2.2.9 Human-machine interfaces............................................................................................................................ 39
2.3 MCU block diagram..................................................................................................................................................... 40
2.4 Orderable part numbers.................................................................................................................................................41
Memory
3.1 Memory map.................................................................................................................................................................43
3.2 Reset and interrupt vector assignments.........................................................................................................................44
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3.3 Register addresses assignments.................................................................................................................................... 46
3.4 Random-access memory (RAM).................................................................................................................................. 51
3.5 Flash memory................................................................................................................................................................51
3.6 System register file....................................................................................................................................................... 52
Interrupt
4.1 Interrupts.......................................................................................................................................................................53
4.1.1 Interrupt stack frame...................................................................................................................................... 54
4.1.2 Hardware nested interrupt.............................................................................................................................. 55
4.1.2.1 Interrupt priority level register...................................................................................................57
4.1.2.2 Interrupt priority level comparator set....................................................................................... 57
4.1.2.3 Interrupt priority mask update and restore mechanism..............................................................57
4.1.2.4 Integration and application of the IPC....................................................................................... 58
4.2 IPC memory map and register descriptions..................................................................................................................59
4.2.1 IPC Status and Control Register (IPC_SC)....................................................................................................59
4.2.2 Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)...................................................................... 60
4.2.3
4.3 IRQ................................................................................................................................................................................61
4.3.1 Features.......................................................................................................................................................... 62
4.4 IRQ Memory Map and Register Descriptions.............................................................................................................. 63
4.4.1 Interrupt Pin Request Status and Control Register (IRQ_SC)....................................................................... 63
Interrupt Level Setting Registers n (IPC_ILRSn)..........................................................................................61
4.3.1.1 Configuration options................................................................................................................ 62
4.3.1.2 Edge and level sensitivity.......................................................................................................... 63
Clock management
5.1 Clock module................................................................................................................................................................65
5.2 System clock distribution..............................................................................................................................................65
5.3 Internal clock source (ICS)........................................................................................................................................... 67
5.4 20 kHz low-power oscillator (LPO)............................................................................................................................. 68
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5.5 Peripheral clock gating................................................................................................................................................. 68
Power Management
6.1 Introduction...................................................................................................................................................................71
6.2 Features.........................................................................................................................................................................71
6.2.1 Run mode....................................................................................................................................................... 71
6.2.2 Wait mode...................................................................................................................................................... 72
6.2.3 Stop mode...................................................................................................................................................... 72
6.2.4 Active BDM enabled in stop mode................................................................................................................72
6.2.5 Power modes behaviors................................................................................................................................. 73
6.3 Bandgap reference........................................................................................................................................................ 74
Signal multiplexing and signal descriptions
7.1 Introduction...................................................................................................................................................................75
7.2 Port control and interrupt module features................................................................................................................... 75
7.3 Signal multiplexing constraints.................................................................................................................................... 75
7.4 Pinout............................................................................................................................................................................76
7.4.1 Signal multiplexing and pin assignments.......................................................................................................76
7.4.2 Signal description table.................................................................................................................................. 77
7.4.3 Pinout ............................................................................................................................................................ 81
Port Control (PORT)
8.1 Introduction...................................................................................................................................................................83
8.2 Port data and data direction...........................................................................................................................................84
8.3 Internal pullup/pulldown enable................................................................................................................................... 84
8.4 Input glitch filter........................................................................................................................................................... 85
8.5 Memory map and register definition.............................................................................................................................86
8.5.1 Port A Data Register (PORT_PTAD)............................................................................................................ 86
8.5.2 Port B Data Register (PORT_PTBD)............................................................................................................ 87
8.5.3 Port C Data Register (PORT_PTCD)............................................................................................................ 87
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8.5.4 Port A Direction Register (PORT_PTADD)................................................................................................. 88
8.5.5 Port B Direction Register (PORT_PTBDD).................................................................................................. 89
8.5.6 Port C Direction Register (PORT_PTCDD).................................................................................................. 89
8.5.7 Port A Pullup Enable Register (PORT_PTAPE)........................................................................................... 90
8.5.8 Port B Pullup/Pulldown Enable Register (PORT_PTBPE)........................................................................... 91
8.5.9 Port C Pullup Enable Register (PORT_PTCPE)............................................................................................91
8.5.10 Port B High Drive Strength Selection Register (PORT_PTBHD)................................................................ 92
8.5.11 Port Clock Division Register (PORT_FCLKDIV)........................................................................................ 92
8.5.12 Port Filter Register 0 (PORT_IOFLT0).........................................................................................................93
8.5.13 Port Filter Register 1 (PORT_IOFLT1).........................................................................................................94
8.5.14 Port Filter Register 2 (PORT_IOFLT2).........................................................................................................95
System Integration Module (SIM)
9.1 Chip specific windowed COP.......................................................................................................................................97
9.2 System device identification (SDID)............................................................................................................................98
9.3 Universally unique identification (UUID)....................................................................................................................98
9.4 Reset and system initialization......................................................................................................................................98
9.5 Computer operating properly (COP) watchdog............................................................................................................99
9.6 System options..............................................................................................................................................................100
9.6.1 BKGD pin...................................................................................................................................................... 100
9.6.2 RESET_b pin enable...................................................................................................................................... 101
9.7 System interconnection.................................................................................................................................................101
9.7.1 Inter Module Crossbar Switch (XBAR).........................................................................................................101
9.7.2 Module to module interconnects....................................................................................................................103
9.8 Memory map and register definition.............................................................................................................................104
9.8.1 System Reset Status Register (SIM_SRS)..................................................................................................... 105
9.8.2 System Background Debug Force Reset Register (SIM_SBDFR)................................................................ 107
9.8.3 System Device Identification Register: High (SIM_SDIDH)........................................................................107
9.8.4 System Device Identification Register: Low (SIM_SDIDL).........................................................................108
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9.8.5 System Options Register 1 (SIM_SOPT1).................................................................................................... 108
9.8.6 System Options Register 2 (SIM_SOPT2).................................................................................................... 110
9.8.7 System Port A Pin Multiplexing Control Register: Low (SIM_MUXPTAL)............................................... 111
9.8.8 System Port A Pin Multiplexing Control Register: High (SIM_MUXPTAH).............................................. 112
9.8.9 System Port B Pin Multiplexing Control Register: Low (SIM_MUXPTBL)............................................... 113
9.8.10 System Port B Pin Multiplexing Control Register: High (SIM_MUXPTBH).............................................. 114
9.8.11 System Port C Pin Multiplexing Control Register: Low (SIM_MUXPTCL)............................................... 116
9.8.12 System Clock Gating Control 1 Register (SIM_SCGC1)..............................................................................116
9.8.13 System Clock Gating Control 2 Register (SIM_SCGC2)..............................................................................117
9.8.14 System Clock Gating Control 3 Register (SIM_SCGC3)..............................................................................119
9.8.15 System Clock Divider Register (SIM_SCDIV).............................................................................................120
9.8.16
9.8.17 Illegal Address Register: High (SIM_ILLAH).............................................................................................. 122
9.8.18 Illegal Address Register: Low (SIM_ILLAL)............................................................................................... 122
9.8.19 Universally Unique Identifier Register 0 (SIM_UUID0).............................................................................. 123
9.8.20 Universally Unique Identifier Register 1 (SIM_UUID1).............................................................................. 123
9.8.21 Universally Unique Identifier Register 2 (SIM_UUID2).............................................................................. 124
9.8.22 Universally Unique Identifier Register 3 (SIM_UUID3).............................................................................. 124
9.8.23 Universally Unique Identifier Register 4 (SIM_UUID4).............................................................................. 125
9.8.24 Universally Unique Identifier Register 5 (SIM_UUID5).............................................................................. 125
9.8.25 Universally Unique Identifier Register 6 (SIM_UUID6).............................................................................. 126
9.8.26 Universally Unique Identifier Register 7 (SIM_UUID7).............................................................................. 126
System POR Register (SIM_PORREGn)...................................................................................................... 121
Chapter 10
Central processor unit
10.1 Introduction...................................................................................................................................................................127
10.1.1 Features.......................................................................................................................................................... 127
10.2 Programmer's Model and CPU Registers..................................................................................................................... 128
10.2.1 Accumulator (A)............................................................................................................................................ 128
10.2.2 Index Register (H:X)......................................................................................................................................129
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10.2.3 Stack Pointer (SP).......................................................................................................................................... 129
10.2.4 Program Counter (PC)................................................................................................................................... 130
10.2.5 Condition Code Register (CCR).................................................................................................................... 130
10.3 Addressing Modes........................................................................................................................................................ 131
10.3.1 Inherent Addressing Mode (INH)..................................................................................................................132
10.3.2 Relative Addressing Mode (REL)..................................................................................................................132
10.3.3 Immediate Addressing Mode (IMM).............................................................................................................132
10.3.4 Direct Addressing Mode (DIR)......................................................................................................................133
10.3.5 Extended Addressing Mode (EXT)................................................................................................................133
10.3.6 Indexed Addressing Mode............................................................................................................................. 134
10.3.6.1 Indexed, No Offset (IX).............................................................................................................134
10.3.6.2 Indexed, No Offset with Post Increment (IX+)..........................................................................134
10.3.6.3 Indexed, 8-Bit Offset (IX1)........................................................................................................134
10.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+).................................................................... 135
10.3.6.5 Indexed, 16-Bit Offset (IX2)......................................................................................................135
10.3.6.6 SP-Relative, 8-Bit Offset (SP1)................................................................................................. 135
10.3.6.7 SP-Relative, 16-Bit Offset (SP2)............................................................................................... 136
10.3.7 Memory to memory Addressing Mode..........................................................................................................136
10.3.7.1 Direct to Direct...........................................................................................................................136
10.3.7.2 Immediate to Direct................................................................................................................... 136
10.3.7.3 Indexed to Direct, Post Increment..............................................................................................136
10.3.7.4 Direct to Indexed, Post-Increment............................................................................................. 137
10.4 Operation modes...........................................................................................................................................................137
10.4.1 Stop mode...................................................................................................................................................... 137
10.4.2 Wait mode......................................................................................................................................................137
10.4.3 Background mode.......................................................................................................................................... 138
10.4.4 Security mode................................................................................................................................................ 139
10.5 HCS08 V6 Opcodes......................................................................................................................................................141
10.6 Special Operations........................................................................................................................................................141
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10.6.1 Reset Sequence.............................................................................................................................................. 141
10.6.2 Interrupt Sequence......................................................................................................................................... 141
10.7 Instruction Set Summary...............................................................................................................................................142
Chapter 11
Flash Memory Module (FTMRH)
11.1 Introduction...................................................................................................................................................................155
11.2 Feature...........................................................................................................................................................................155
11.2.1 Flash memory features...................................................................................................................................155
11.2.2 Other flash module features........................................................................................................................... 156
11.3 Functional description...................................................................................................................................................156
11.3.1 Modes of operation........................................................................................................................................ 156
11.3.1.1 Wait mode..................................................................................................................................156
11.3.1.2 Stop mode.................................................................................................................................. 156
11.3.2 Flash block read access..................................................................................................................................156
11.3.3 Flash memory map.........................................................................................................................................157
11.3.4 Flash initialization after system reset.............................................................................................................157
11.3.5 Flash command operations.............................................................................................................................157
11.3.5.1 Writing the FCLKDIV register..................................................................................................158
11.3.5.2 Command write sequence.......................................................................................................... 160
11.3.6 Flash interrupts...............................................................................................................................................162
11.3.6.1 Description of flash interrupt operation.....................................................................................162
11.3.7 Protection....................................................................................................................................................... 162
11.3.8 Security.......................................................................................................................................................... 165
11.3.8.1 Unsecuring the MCU using backdoor key access......................................................................166
11.3.8.2 Unsecuring the MCU using BDM............................................................................................. 167
11.3.8.3 Mode and security effects on flash command availability.........................................................167
11.3.9 Flash commands.............................................................................................................................................167
11.3.9.1 Flash commands.........................................................................................................................167
11.3.10 Flash command summary.............................................................................................................................. 168
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11.3.10.1 Erase Verify All Blocks command............................................................................................ 169
11.3.10.2 Erase Verify Block command.................................................................................................... 169
11.3.10.3 Erase Verify Flash Section command........................................................................................ 170
11.3.10.4 Read once command.................................................................................................................. 171
11.3.10.5 Program Flash command........................................................................................................... 172
11.3.10.6 Program Once command............................................................................................................173
11.3.10.7 Erase All Blocks command........................................................................................................174
11.3.10.8 Erase flash block command....................................................................................................... 174
11.3.10.9 Erase flash sector command.......................................................................................................175
11.3.10.10 Unsecure flash command........................................................................................................... 176
11.3.10.11 Verify backdoor access key command.......................................................................................177
11.3.10.12 Set user margin level command................................................................................................. 177
11.3.10.13 Set factory margin level command............................................................................................ 179
11.4 Memory map and register definition.............................................................................................................................180
11.4.1 Flash Clock Divider Register (FTMRH_FCLKDIV).................................................................................... 181
11.4.2 Flash Security Register (FTMRH_FSEC)..................................................................................................... 182
11.4.3 Flash CCOB Index Register (FTMRH_FCCOBIX)......................................................................................183
11.4.4 Flash Configuration Register (FTMRH_FCNFG).........................................................................................183
11.4.5 Flash Status Register (FTMRH_FSTAT)...................................................................................................... 184
11.4.6 Flash Protection Register (FTMRH_FPROT)............................................................................................... 185
11.4.7 Flash Common Command Object Register:High (FTMRH_FCCOBHI)......................................................186
11.4.8 Flash Common Command Object Register: Low (FTMRH_FCCOBLO).................................................... 187
11.4.9 Flash Option Register (FTMRH_FOPT)....................................................................................................... 187
Chapter 12
Internal Clock Source (ICS)
12.1 Introduction...................................................................................................................................................................189
12.1.1 Features.......................................................................................................................................................... 189
12.1.2 Block diagram................................................................................................................................................190
12.1.3 Modes of operation........................................................................................................................................ 190
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12.1.3.1 FLL engaged internal (FEI)....................................................................................................... 190
12.1.3.2 FLL engaged external (FEE)......................................................................................................190
12.1.3.3 FLL bypassed internal (FBI)......................................................................................................191
12.1.3.4 FLL bypassed internal low power (FBILP)............................................................................... 191
12.1.3.5 FLL bypassed external (FBE)....................................................................................................191
12.1.3.6 FLL bypassed external low power (FBELP)............................................................................. 191
12.1.3.7 Stop (STOP)...............................................................................................................................191
12.2 External signal description............................................................................................................................................191
12.3 Register definition.........................................................................................................................................................192
12.3.1 ICS Control Register 1 (ICS_C1).................................................................................................................. 192
12.3.2 ICS Control Register 2 (ICS_C2).................................................................................................................. 193
12.3.3 ICS Control Register 3 (ICS_C3).................................................................................................................. 194
12.3.4 ICS Control Register 4 (ICS_C4).................................................................................................................. 195
12.3.5 ICS Status Register (ICS_S).......................................................................................................................... 196
12.4 Functional description...................................................................................................................................................197
12.4.1 Operational modes......................................................................................................................................... 197
12.4.1.1 FLL engaged internal (FEI)....................................................................................................... 197
12.4.1.2 FLL engaged external (FEE)......................................................................................................198
12.4.1.3 FLL bypassed internal (FBI)......................................................................................................198
12.4.1.4 FLL bypassed internal low power (FBILP)............................................................................... 198
12.4.1.5 FLL bypassed external (FBE)....................................................................................................199
12.4.1.6 FLL bypassed external low power (FBELP)............................................................................. 199
12.4.1.7 Stop............................................................................................................................................ 199
12.4.2 Mode switching..............................................................................................................................................199
12.4.3 Bus frequency divider.................................................................................................................................... 200
12.4.4 Low-power field usage...................................................................................................................................200
12.4.5 Internal reference clock..................................................................................................................................200
12.4.6 Fixed frequency clock....................................................................................................................................201
12.4.7 FLL lock and clock monitor...........................................................................................................................201
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12.4.7.1 FLL clock lock...........................................................................................................................201
12.4.7.2 External reference clock monitor...............................................................................................202
12.5 Initialization/application information........................................................................................................................... 202
12.5.1 Initializing FEI mode..................................................................................................................................... 202
12.5.2 Initializing FBI mode.....................................................................................................................................202
12.5.3 Initializing FEE mode.................................................................................................................................... 203
12.5.4 Initializing FBE mode....................................................................................................................................203
Chapter 13
Modulo Timer (MTIM)
13.1 Chip specific modulo timer...........................................................................................................................................205
13.2 Introduction...................................................................................................................................................................205
13.3 Features ........................................................................................................................................................................206
13.3.1 Block Diagram .............................................................................................................................................. 206
13.3.2 Modes of Operation ...................................................................................................................................... 207
13.3.2.1 MTIM16 in Wait Mode .............................................................................................................207
13.3.2.2 MTIM16 in Stop Modes............................................................................................................ 207
13.3.2.3 MTIM16 in Active Background Mode ..................................................................................... 208
13.4 External Signal Description .........................................................................................................................................208
13.4.1 TCLK — External Clock Source Input into MTIM16 ................................................................................. 208
13.5 Memory Map and Register Descriptions......................................................................................................................209
13.5.1 MTIM16 status and control register (MTIM_SC)......................................................................................... 209
13.5.2 MTIM16 clock configuration register (MTIM_CLK)...................................................................................210
13.5.3 MTIM16 counter register high (MTIM_CNTH)........................................................................................... 211
13.5.4 MTIM16 counter register low (MTIM_CNTL).............................................................................................212
13.5.5 MTIM16 modulo register high (MTIM_MODH)..........................................................................................213
13.5.6 MTIM16 modulo register low (MTIM_MODL)........................................................................................... 214
13.6 Functional Description .................................................................................................................................................214
13.6.1 MTIM16 Operation Example ........................................................................................................................216
Chapter 14
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Power Management Controller (PMC)
14.1 Chip specific power management controller ............................................................................................................... 217
14.2 Introduction...................................................................................................................................................................217
14.3 Features.........................................................................................................................................................................218
14.4 Overview.......................................................................................................................................................................218
14.5 Modes of operation.......................................................................................................................................................219
14.5.1 Reduced performance mode...........................................................................................................................219
14.5.2 Full performance mode.................................................................................................................................. 220
14.6 External signal description............................................................................................................................................220
14.6.1 VDD...............................................................................................................................................................220
14.6.2 VDDX............................................................................................................................................................ 220
14.6.3 VREFH...........................................................................................................................................................220
14.6.4 VDDF.............................................................................................................................................................221
14.6.5 VDD1.8..........................................................................................................................................................221
14.7 Memory map and register definition.............................................................................................................................221
14.7.1 Control Register (PMC_CTRL).....................................................................................................................222
14.7.2 Reset Flags Register (PMC_RST)................................................................................................................. 223
14.7.3 Temperature Control and Status Register (PMC_TPCTRLSTAT)............................................................... 223
14.7.4 Temperature Offset Step Trim Register (PMC_TPTM)................................................................................224
14.7.5 RC Oscillator Offset Step Trim Register (PMC_RC20KTRM).................................................................... 225
14.7.6 Low Voltage Control and Status Register 1 (system 5 V) (PMC_LVCTLSTAT1)......................................226
14.7.7 Low Voltage Control and Status Register 2 (V
14.7.8 V
Configuration Register (PMC_VREFHCFG).................................................................................... 227
REFH
) (PMC_LVCTLSTAT2)............................................. 227
REFH
14.7.9 VREFH Low Voltage Warning (LVW) Configuration Register (PMC_VREFHLVW)...............................228
14.7.10 Status Register (PMC_STAT)....................................................................................................................... 228
14.8 Functional description...................................................................................................................................................229
14.8.1 Voltage regulators..........................................................................................................................................229
14.8.1.1 VREGVDDX............................................................................................................................. 229
14.8.1.2 VREGVDDF..............................................................................................................................229
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14.8.1.3 VREGVDD................................................................................................................................ 230
14.8.1.4 VREGVREFH............................................................................................................................230
14.8.2 Power-on reset................................................................................................................................................230
14.8.3 Low voltage reset (LVR)............................................................................................................................... 230
14.8.3.1 LVR in low power mode............................................................................................................231
14.8.4 Low voltage warning (LVW).........................................................................................................................231
14.8.4.1 LVW on VDDX/VDDA............................................................................................................ 231
14.8.4.2 LVW on VREFH....................................................................................................................... 231
14.8.4.3 LVW in low power mode...........................................................................................................231
14.8.5 High-accuracy reference voltage....................................................................................................................232
14.8.6 Temperature sensor........................................................................................................................................232
14.8.6.1 High temperature warning......................................................................................................... 232
14.8.7 Low-power RC oscillator...............................................................................................................................233
14.9 Application information................................................................................................................................................233
Chapter 15
Keyboard Interrupts (KBI)
15.1 Chip specific KBI information......................................................................................................................................235
15.2 Introduction...................................................................................................................................................................235
15.2.1 Features.......................................................................................................................................................... 235
15.2.2 Modes of Operation....................................................................................................................................... 235
15.2.2.1 KBI in Wait mode......................................................................................................................236
15.2.2.2 KBI in Stop modes.....................................................................................................................236
15.2.3 Block Diagram............................................................................................................................................... 236
15.3 External signals description..........................................................................................................................................237
15.4 Register definition.........................................................................................................................................................237
15.5 Memory Map and Registers..........................................................................................................................................237
15.5.1 KBI Status and Control Register (KBI_SC).................................................................................................. 238
15.5.2 KBI Pin Enable Register (KBI_PE)...............................................................................................................239
15.5.3 KBI Edge Select Register (KBI_ES)............................................................................................................. 239
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15.6 Functional Description..................................................................................................................................................240
15.6.1 Edge-only sensitivity......................................................................................................................................240
15.6.2 Edge and level sensitivity.............................................................................................................................. 240
15.6.3 KBI Pullup Resistor....................................................................................................................................... 240
15.6.4 KBI initialization............................................................................................................................................241
Chapter 16
Cyclic redundancy check (CRC)
16.1 Chip specific cyclic redundancy check (CRC).............................................................................................................243
16.2 Introduction...................................................................................................................................................................243
16.2.1 Features.......................................................................................................................................................... 244
16.2.2 Block diagram................................................................................................................................................244
16.2.3 Modes of operation........................................................................................................................................ 244
16.2.3.1 Run mode................................................................................................................................... 244
16.2.3.2 Low-power modes (Wait or Stop)............................................................................................. 245
16.3 Memory map and register descriptions.........................................................................................................................245
16.3.1 CRC Data register: High 1 (CRC_DH1)........................................................................................................245
16.3.2 CRC Data register: High 0 (CRC_DH0)........................................................................................................246
16.3.3 CRC Data register: Low 1 (CRC_DL1).........................................................................................................247
16.3.4 CRC Data register: Low 0 (CRC_DL0).........................................................................................................247
16.3.5 CRC Polynomial Register: High 1 (CRC_PH1)............................................................................................248
16.3.6 CRC Polynomial Register: High 0 (CRC_PH0)............................................................................................249
16.3.7 CRC Polynomial Register: Low 1 (CRC_PL1)............................................................................................. 249
16.3.8 CRC Polynomial Register: Low 0 (CRC_PL0)............................................................................................. 250
16.3.9 CRC Control register (CRC_CTRL)..............................................................................................................250
16.4 Functional description...................................................................................................................................................251
16.4.1 CRC initialization/reinitialization..................................................................................................................251
16.4.2 CRC calculations............................................................................................................................................252
16.4.2.1 16-bit CRC................................................................................................................................. 252
16.4.2.2 32-bit CRC................................................................................................................................. 252
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16.4.3 Transpose feature........................................................................................................................................... 253
16.4.3.1 Types of transpose..................................................................................................................... 253
16.4.4 CRC result complement.................................................................................................................................254
Chapter 17
Analog-to-digital converter (ADC)
17.1 Chip-specific ADC information....................................................................................................................................255
17.1.1 Analog-to-digital converter (ADC)................................................................................................................255
17.1.2 ADC channel assignments............................................................................................................................. 256
17.1.3 ADC analog supply and reference connections............................................................................................. 257
17.1.4 Alternate clock............................................................................................................................................... 257
17.1.5 Hardware trigger............................................................................................................................................ 258
17.1.6 Temperature sensor........................................................................................................................................258
17.2 Introduction...................................................................................................................................................................259
17.2.1 Features.......................................................................................................................................................... 259
17.2.2 Block Diagram............................................................................................................................................... 260
17.3 External Signal Description..........................................................................................................................................260
17.3.1 Analog Power (VDDA)................................................................................................................................. 261
17.3.2 Analog Ground (VSSA).................................................................................................................................261
17.3.3 Voltage Reference High (VREFH)................................................................................................................261
17.3.4 Voltage Reference Low (VREFL)................................................................................................................. 261
17.3.5 Analog Channel Inputs (ADx)....................................................................................................................... 261
17.4 ADC Control Registers.................................................................................................................................................262
17.4.1
17.4.2
17.4.3
17.4.4
17.4.5
Status and Control Register 1 (ADCx_SC1)..................................................................................................262
Status and Control Register 2 (ADCx_SC2)..................................................................................................264
Status and Control Register 3 (ADCx_SC3)..................................................................................................265
Status and Control Register 4 (ADCx_SC4)..................................................................................................266
Conversion Result High Register (ADCx_RH)............................................................................................. 267
17.4.6
17.4.7
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Conversion Result Low Register (ADCx_RL).............................................................................................. 268
Compare Value High Register (ADCx_CVH)...............................................................................................269
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17.4.8
17.5 Functional description...................................................................................................................................................270
17.5.1 Clock select and divide control......................................................................................................................270
17.5.2 Hardware trigger............................................................................................................................................ 271
17.5.3 Conversion control.........................................................................................................................................271
17.5.4 Automatic compare function..........................................................................................................................274
17.5.5 FIFO operation...............................................................................................................................................275
17.5.6 MCU wait mode operation.............................................................................................................................279
17.5.7 MCU Stop mode operation............................................................................................................................ 279
Compare Value Low Register (ADCx_CVL)................................................................................................269
17.5.3.1 Initiating conversions.................................................................................................................271
17.5.3.2 Completing conversions.............................................................................................................272
17.5.3.3 Aborting conversions................................................................................................................. 272
17.5.3.4 Power control............................................................................................................................. 273
17.5.3.5 Sample time and total conversion time......................................................................................273
17.5.7.1 Stop mode with ADACK disabled.............................................................................................279
17.5.7.2 Stop mode with ADACK enabled..............................................................................................279
17.6 Initialization information..............................................................................................................................................280
17.6.1 ADC module initialization example.............................................................................................................. 280
17.6.1.1 Initialization sequence................................................................................................................280
17.6.1.2 Pseudo-code example.................................................................................................................281
17.6.2 ADC FIFO module initialization example.....................................................................................................281
17.6.2.1 Pseudo-code example.................................................................................................................282
17.7 Application information................................................................................................................................................283
17.7.1 External pins and routing............................................................................................................................... 283
17.7.1.1 Analog supply pins.....................................................................................................................283
17.7.1.2 Analog reference pins................................................................................................................ 283
17.7.1.3 Analog input pins.......................................................................................................................284
17.7.2 Sources of error..............................................................................................................................................285
17.7.2.1 Sampling error............................................................................................................................285
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17.7.2.2 Pin leakage error........................................................................................................................ 285
17.7.2.3 Noise-induced errors..................................................................................................................285
17.7.2.4 Code width and quantization error.............................................................................................286
17.7.2.5 Linearity errors...........................................................................................................................287
17.7.2.6 Code jitter, non-monotonicity, and missing codes.....................................................................287
Chapter 18
Chip-specific ACMP information
18.1 CMP configuration information....................................................................................................................................289
18.2 ACMP in stop mode..................................................................................................................................................... 290
18.3 ....................................................................................................................................................................................... 0
18.3.1 ........................................................................................................................................................................ 0
18.3.2 ........................................................................................................................................................................ 0
18.4 Introduction...................................................................................................................................................................290
18.5 CMP Features................................................................................................................................................................291
18.6 6-bit DAC Key Features............................................................................................................................................... 291
18.7 ANMUX Key Features.................................................................................................................................................292
18.8 CMP, DAC, and ANMUX Diagram.............................................................................................................................292
18.9 CMP Block Diagram.....................................................................................................................................................293
18.10 Memory Map/Register Definitions...............................................................................................................................295
18.10.1 CMP Control Register 0 (CMP_CR0)........................................................................................................... 295
18.10.2 CMP Control Register 1 (CMP_CR1)........................................................................................................... 296
18.10.3 CMP Filter Period Register (CMP_FPR).......................................................................................................297
18.10.4 CMP Status and Control Register (CMP_SCR)............................................................................................ 298
18.10.5 DAC Control Register (CMP_DACCR)........................................................................................................299
18.10.6 MUX Control Register (CMP_MUXCR)......................................................................................................300
18.10.7 MUX Pin Enable Register (CMP_MUXPE)................................................................................................. 301
18.11 CMP Functional Description........................................................................................................................................ 301
18.11.1 CMP Functional Modes................................................................................................................................. 301
18.11.1.1 Disabled Mode (# 1).................................................................................................................. 303
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18.11.1.2 Continuous Mode (#s 2A & 2B)................................................................................................ 303
18.11.1.3 Sampled, Non-Filtered Mode (#s 3A & 3B)..............................................................................304
18.11.1.4 Sampled, Filtered Mode (#s 4A & 4B)...................................................................................... 306
18.11.1.5 Windowed Mode (#s 5A & 5B)................................................................................................. 308
18.11.1.6 Windowed/Resampled Mode (# 6)............................................................................................ 310
18.11.1.7 Windowed/Filtered Mode (#7)...................................................................................................310
18.11.2 Power Modes..................................................................................................................................................311
18.11.2.1 Wait Mode Operation.................................................................................................................311
18.11.2.2 Stop Mode Operation................................................................................................................. 311
18.11.2.3 Background Debug Mode Operation......................................................................................... 312
18.11.3 Startup and Operation.................................................................................................................................... 312
18.11.4 Low Pass Filter...............................................................................................................................................313
18.11.4.1 Enabling Filter Modes................................................................................................................313
18.11.4.2 Latency Issues............................................................................................................................ 314
18.12 CMP Interrupts..............................................................................................................................................................315
18.13 Digital to Analog Converter Block Diagram................................................................................................................315
18.14 DAC Functional Description........................................................................................................................................ 316
18.14.1 Voltage Reference Source Select...................................................................................................................316
18.15 DAC Resets...................................................................................................................................................................316
18.16 DAC Clocks..................................................................................................................................................................316
18.17 DAC Interrupts..............................................................................................................................................................316
Chapter 19
FlexTimer Module (FTM)
19.1 Chip specific FlexTimer module.................................................................................................................................. 317
19.2 Introduction...................................................................................................................................................................318
19.2.1 FlexTimer philosophy....................................................................................................................................318
19.2.2 Features.......................................................................................................................................................... 318
19.2.3 Modes of operation........................................................................................................................................ 319
19.2.4 Block diagram................................................................................................................................................319
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19.3 Signal description..........................................................................................................................................................320
19.3.1 EXTCLK — FTM external clock.................................................................................................................. 321
19.3.2 CHn — FTM channel (n) I/O pin.................................................................................................................. 321
19.4 Memory map and register definition.............................................................................................................................321
19.4.1 Module memory map.....................................................................................................................................321
19.4.2 Register descriptions......................................................................................................................................321
19.4.3
19.4.4
19.4.5
19.4.6
19.4.7
19.4.8
19.4.9
19.4.10
19.5 Functional Description..................................................................................................................................................329
19.5.1 Clock Source..................................................................................................................................................329
19.5.2 Prescaler.........................................................................................................................................................330
19.5.3 Counter...........................................................................................................................................................330
Status and Control (FTMx_SC)..................................................................................................................... 322
Counter High (FTMx_CNTH)....................................................................................................................... 323
Counter Low (FTMx_CNTL)........................................................................................................................ 324
Modulo High (FTMx_MODH)...................................................................................................................... 324
Modulo Low (FTMx_MODL)....................................................................................................................... 325
Channel Status and Control (FTMx_CnSC).................................................................................................. 326
Channel Value High (FTMx_CnVH).............................................................................................................327
Channel Value Low (FTMx_CnVL)..............................................................................................................328
19.5.1.1 Counter Clock Source................................................................................................................ 329
19.5.3.1 Up counting................................................................................................................................331
19.5.3.2 Up-down counting......................................................................................................................331
19.5.3.3 Free running counter.................................................................................................................. 332
19.5.3.4 Counter reset.............................................................................................................................. 332
19.5.4 Input capture mode.........................................................................................................................................332
19.5.5 Output compare mode....................................................................................................................................333
19.5.6 Edge-aligned PWM (EPWM) mode.............................................................................................................. 335
19.5.7 Center-aligned PWM (CPWM) mode............................................................................................................336
19.5.8 Update of the registers with write buffers......................................................................................................338
19.5.8.1 MODH:L registers..................................................................................................................... 338
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19.5.8.2 CnVH:L registers....................................................................................................................... 339
19.5.9 BDM mode.....................................................................................................................................................339
19.6 Reset overview..............................................................................................................................................................339
19.7 FTM Interrupts..............................................................................................................................................................341
19.7.1 Timer overflow interrupt................................................................................................................................341
19.7.2 Channel (n) interrupt......................................................................................................................................341
Chapter 20
Pules Width Timer (PWT)
20.1 Chip specific pules width timer.................................................................................................................................... 343
20.2 Introduction...................................................................................................................................................................344
20.2.1 Features.......................................................................................................................................................... 344
20.2.2 Modes of operation........................................................................................................................................ 344
20.2.3 Block diagram................................................................................................................................................345
20.3 External signal description............................................................................................................................................345
20.3.1 Overview........................................................................................................................................................345
20.3.2 PWTIN[3:0] — pulse width timer capture inputs..........................................................................................346
20.3.3 ALTCLK— alternative clock source for counter.......................................................................................... 346
20.4 Memory Map and Register Descriptions......................................................................................................................346
20.4.1
20.4.2
20.4.3
20.4.4
20.4.5
20.4.6
20.4.7
20.4.8
20.5 Functional description...................................................................................................................................................352
Pulse Width Timer Control and Status Register (PWTx_CS)....................................................................... 347
Pulse Width Timer Control Register (PWTx_CR)........................................................................................ 348
Pulse Width Timer Positive Pulse Width Register: High (PWTx_PPH).......................................................349
Pulse Width Timer Positive Pulse Width Register: Loq (PWTx_PPL).........................................................350
Pulse Width Timer Negative Pulse Width Register: High (PWTx_NPH).....................................................350
Pulse Width Timer Negative Pulse Width Register: Low (PWTx_NPL)......................................................351
Pulse Width Timer Counter Register: High (PWTx_CNTH)........................................................................ 351
Pulse Width Timer Counter Register: Low (PWTx_CNTL)......................................................................... 351
20.5.1 PWT counter and PWT clock pre-scaler........................................................................................................352
20.5.2 Edge detection and capture control................................................................................................................352
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20.6 Reset overview..............................................................................................................................................................356
20.6.1 Description of reset operation........................................................................................................................356
20.7 Interrupts.......................................................................................................................................................................357
20.7.1 Description of interrupt operation..................................................................................................................357
20.7.2 Application examples.....................................................................................................................................358
20.8 Initialization/Application information..........................................................................................................................359
Chapter 21
Inter-Integrated Circuit (I2C)
21.1 Chip specific inter-integrated circuit............................................................................................................................ 361
21.2 Introduction...................................................................................................................................................................361
21.2.1 Features.......................................................................................................................................................... 362
21.2.2 Modes of operation........................................................................................................................................ 362
21.2.3 Block diagram................................................................................................................................................363
21.3 I2C signal descriptions..................................................................................................................................................364
21.4 Memory map/register definition...................................................................................................................................364
21.4.1 I2C Address Register 1 (I2C_A1)..................................................................................................................365
21.4.2 I2C Frequency Divider register (I2C_F)........................................................................................................365
21.4.3 I2C Control Register 1 (I2C_C1)...................................................................................................................366
21.4.4 I2C Status register (I2C_S)............................................................................................................................368
21.4.5 I2C Data I/O register (I2C_D)....................................................................................................................... 369
21.4.6 I2C Control Register 2 (I2C_C2)...................................................................................................................370
21.4.7 I2C Stop Control and Status Register (I2C_SCS)......................................................................................... 371
21.4.8 I2C Range Address register (I2C_RA).......................................................................................................... 372
21.4.9 I2C SMBus Control and Status register (I2C_SMB).....................................................................................373
21.4.10 I2C Address Register 2 (I2C_A2)..................................................................................................................374
21.4.11 I2C SCL Low Timeout Register High (I2C_SLTH)..................................................................................... 375
21.4.12 I2C SCL Low Timeout Register Low (I2C_SLTL).......................................................................................375
21.4.13 I2C Status register 2 (I2C_S2).......................................................................................................................376
21.5 Functional description...................................................................................................................................................376
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21.5.1 I2C protocol................................................................................................................................................... 376
21.5.1.1 START signal............................................................................................................................ 377
21.5.1.2 Slave address transmission.........................................................................................................378
21.5.1.3 Data transfers............................................................................................................................. 378
21.5.1.4 STOP signal............................................................................................................................... 379
21.5.1.5 Repeated START signal.............................................................................................................379
21.5.1.6 Arbitration procedure.................................................................................................................379
21.5.1.7 Clock synchronization................................................................................................................380
21.5.1.8 Handshaking...............................................................................................................................380
21.5.1.9 Clock stretching......................................................................................................................... 380
21.5.1.10 I2C divider and hold values....................................................................................................... 381
21.5.2 10-bit address................................................................................................................................................. 382
21.5.2.1 Master-transmitter addresses a slave-receiver........................................................................... 382
21.5.2.2 Master-receiver addresses a slave-transmitter........................................................................... 383
21.5.3 Address matching...........................................................................................................................................383
21.5.4 System management bus specification.......................................................................................................... 384
21.5.4.1 Timeouts.....................................................................................................................................384
21.5.4.2 FAST ACK and NACK............................................................................................................. 386
21.5.5 Resets............................................................................................................................................................. 387
21.5.6 Interrupts........................................................................................................................................................ 387
21.5.6.1 Byte transfer interrupt................................................................................................................ 388
21.5.6.2 Address detect interrupt............................................................................................................. 388
21.5.6.3 Stop Detect Interrupt..................................................................................................................388
21.5.6.4 Exit from low-power/stop modes...............................................................................................388
21.5.6.5 Arbitration lost interrupt............................................................................................................ 388
21.5.6.6 Timeout interrupt in SMBus...................................................................................................... 389
21.5.7 Address matching wake-up............................................................................................................................389
21.5.8 Double buffering mode.................................................................................................................................. 390
21.6 Initialization/application information........................................................................................................................... 391
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Chapter 22
Serial Communications Interface (SCI)
22.1 Chip specific serial communications interface.............................................................................................................395
22.2 Introduction...................................................................................................................................................................396
22.2.1 Features.......................................................................................................................................................... 396
22.2.2 Modes of operation........................................................................................................................................ 396
22.2.3 Block diagram................................................................................................................................................397
22.3 SCI signal descriptions................................................................................................................................................. 399
22.3.1 Detailed signal descriptions........................................................................................................................... 399
22.4 Register definition.........................................................................................................................................................399
22.4.1
22.4.2
22.4.3
22.4.4
22.4.5
22.4.6
22.4.7
22.4.8
22.5 Functional description...................................................................................................................................................409
22.5.1 Baud rate generation...................................................................................................................................... 410
22.5.2 Transmitter functional description.................................................................................................................410
22.5.3 Receiver functional description..................................................................................................................... 412
SCI Baud Rate Register: High (SCIx_BDH)................................................................................................. 400
SCI Baud Rate Register: Low (SCIx_BDL).................................................................................................. 401
SCI Control Register 1 (SCIx_C1).................................................................................................................401
SCI Control Register 2 (SCIx_C2).................................................................................................................403
SCI Status Register 1 (SCIx_S1)................................................................................................................... 404
SCI Status Register 2 (SCIx_S2)................................................................................................................... 406
SCI Control Register 3 (SCIx_C3).................................................................................................................407
SCI Data Register (SCIx_D)..........................................................................................................................409
22.5.2.1 Send break and queued idle....................................................................................................... 411
22.5.3.1 Data sampling technique............................................................................................................413
22.5.3.2 Receiver wake-up operation.......................................................................................................414
22.5.4 Interrupts and status flags.............................................................................................................................. 415
22.5.5 Baud rate tolerance.........................................................................................................................................416
22.5.5.1 Slow data tolerance.................................................................................................................... 416
22.5.5.2 Fast data tolerance......................................................................................................................418
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22.5.6 Additional SCI functions............................................................................................................................... 419
22.5.6.1 8- and 9-bit data modes..............................................................................................................419
22.5.6.2 Stop mode operation.................................................................................................................. 419
22.5.6.3 Loop mode................................................................................................................................. 419
22.5.6.4 Single-wire operation.................................................................................................................420
Chapter 23
Programmable Delay Block (PDB)
23.1 Chip specific programmable delay block..................................................................................................................... 421
23.2 Introduction...................................................................................................................................................................422
23.3 Features.........................................................................................................................................................................422
23.4 Block diagram...............................................................................................................................................................422
23.5 Mode of operation.........................................................................................................................................................423
23.5.1 Single shot delay mode ................................................................................................................................. 423
23.5.2 Continuous count mode................................................................................................................................. 424
23.6 Memory Map and Register Descriptions......................................................................................................................425
23.6.1 PDB Control Register 0 (PDB_CTRL0)........................................................................................................425
23.6.2 PDB Control Register 1 (PDB_CTRL1)........................................................................................................426
23.6.3 PDB0 Comparison Low Register (PDB_CMPL0)........................................................................................ 427
23.6.4 PDB0 Comparison High Register (PDB_CMPH0)....................................................................................... 428
23.6.5 PDB0 Counter High/Low (PDB_CNT0)....................................................................................................... 428
23.6.6 PDB1 Comparison Low Register (PDB_CMPL1)........................................................................................ 429
23.6.7 PDB1 Comparison High Register (PDB_CMPH1)....................................................................................... 429
23.6.8 PDB1 Counter High/Low (PDB_CNT1)....................................................................................................... 430
Chapter 24
Inter-peripheral Crossbar Switch (XBAR)
24.1 Introduction...................................................................................................................................................................431
24.2 Features.........................................................................................................................................................................431
24.3 Block diagram...............................................................................................................................................................431
24.4 Memory Map and Register Descriptions......................................................................................................................432
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24.4.1 External Mux Selection Register (XBAR_EXTMUX)................................................................................. 433
24.4.2
XBAR Selection Register (XBAR_SELn).................................................................................................... 434
Chapter 25
Gate Drive Unit (GDU)
25.1 Chip specific GDU information....................................................................................................................................435
25.2 Introduction...................................................................................................................................................................435
25.3 Features.........................................................................................................................................................................436
25.4 Block diagram...............................................................................................................................................................436
25.5 Modes of operation.......................................................................................................................................................437
25.6 Memory map and register definition.............................................................................................................................438
25.6.1 PHCMP0 Control Register 0 (GDU_PHCMP0CR0).................................................................................... 439
25.6.2 PHCMP0 Control Register 1 (GDU_PHCMP0CR1).................................................................................... 439
25.6.3 PHCMP0 Filter Period Register (GDU_PHCMP0FPR)................................................................................441
25.6.4 PHCMP0 Status and Control Register (GDU_PHCMP0SCR)......................................................................441
25.6.5 PHCMP1 Control Register 0 (GDU_PHCMP1CR0).................................................................................... 442
25.6.6 PHCMP1 Control Register 1 (GDU_PHCMP1CR1).................................................................................... 443
25.6.7 PHCMP1 Filter Period Register (GDU_PHCMP1FPR)................................................................................444
25.6.8 PHCMP1 Status and Control Register (GDU_PHCMP1SCR)......................................................................445
25.6.9 PHCMP2 Control Register 0 (GDU_PHCMP2CR0).................................................................................... 446
25.6.10 PHCMP2 Control Register 1 (GDU_PHCMP2CR1).................................................................................... 446
25.6.11 PHCMP2 Filter Period Register (GDU_PHCMP2FPR)................................................................................448
25.6.12 PHCMP2 Status and Control Register (GDU_PHCMP2SCR)......................................................................448
25.6.13 Clamp Control Register (GDU_CLMPCTRL)..............................................................................................449
25.6.14 I/O Control Register (GDU_IOCTRL)..........................................................................................................450
25.6.15 Virtual Network Phase Detection Control (GDU_PHASECTRL)................................................................451
25.6.16 Current Sensor and Overcurrent Protection Control Register (GDU_CURCTRL).......................................452
25.6.17 LIMIT0 CMP Control Register 0 (GDU_LIMIT0CR0)................................................................................452
25.6.18 LIMIT0 CMP Control Register 1 (GDU_LIMIT0CR1)................................................................................453
25.6.19 LIMIT0 CMP Filter Period Register (GDU_LIMIT0FPR)........................................................................... 454
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25.6.20 LIMIT0 CMP Status and Control Register (GDU_LIMIT0SCR).................................................................455
25.6.21 LIMIT0 DAC Control Register (GDU_LIMIT0DACCR)............................................................................ 456
25.6.22 LIMIT1 CMP Control Register 0 (GDU_LIMIT1CR0)................................................................................456
25.6.23 LIMIT1 CMP Control Register 1 (GDU_LIMIT1CR1)................................................................................457
25.6.24 LIMIT1 CMP Filter Period Register (GDU_LIMIT1FPR)........................................................................... 458
25.6.25 LIMIT1 CMP Status and Control Register (GDU_LIMIT1SCR).................................................................459
25.6.26 LIMIT1 DAC Control Register (GDU_LIMIT1DACCR)............................................................................ 460
25.6.27 PDCS and Clamp Status Register (GDU_STATREG)..................................................................................460
25.6.28 LIMIT CMP BIAS Register (GDU_SIGBIAS).............................................................................................461
25.7 Functional description...................................................................................................................................................461
25.7.1 Phase detection function descriptions............................................................................................................462
25.7.1.1 Phase detection diagram.............................................................................................................462
25.7.1.2 Phase detection descriptions...................................................................................................... 462
25.7.2 OpAMP function descriptions....................................................................................................................... 463
25.7.2.1 OpAMP diagram........................................................................................................................463
25.7.2.2 OpAMP descriptions..................................................................................................................464
25.7.3 Predrive function descriptions....................................................................................................................... 464
25.7.3.1 Predrive diagram........................................................................................................................464
25.7.3.2 Predrive descriptions..................................................................................................................465
25.7.4 GCMP functional description........................................................................................................................ 465
25.7.4.1 GCMP diagram.......................................................................................................................... 465
25.7.4.2 GCMP block diagram................................................................................................................ 466
25.7.4.3 GCMP functional modes............................................................................................................468
25.7.4.4 Power modes..............................................................................................................................477
25.7.4.5 Startup and operation................................................................................................................. 478
25.7.4.6 Low pass filter............................................................................................................................478
25.8 GCMP interrupts...........................................................................................................................................................480
Chapter 26
Pulse Width Modulator (PWM)
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26.1 Chip specific pulse width modulator............................................................................................................................ 481
26.2 Introduction...................................................................................................................................................................482
26.2.1 Overview........................................................................................................................................................482
26.2.2 Features.......................................................................................................................................................... 482
26.2.3 Modes of operation........................................................................................................................................ 483
26.2.4 Block diagram................................................................................................................................................483
26.3 Functional description...................................................................................................................................................485
26.3.1 Prescaler.........................................................................................................................................................485
26.3.2 Generator........................................................................................................................................................485
26.3.2.1 Alignment and compare output polarity.................................................................................... 486
26.3.2.2 Period......................................................................................................................................... 487
26.3.2.3 Pulse width duty cycle............................................................................................................... 487
26.3.3 Independent or complementary channel operation........................................................................................ 489
26.3.4 Deadtime generators...................................................................................................................................... 491
26.3.5 Asymmetric PWM output.............................................................................................................................. 493
26.3.6 Variable edge placement PWM output.......................................................................................................... 493
26.3.7 PWM output polarity..................................................................................................................................... 494
26.3.8 Generator loading...........................................................................................................................................497
26.3.8.1 Load enable................................................................................................................................497
26.3.8.2 Load frequency.......................................................................................................................... 497
26.3.8.3 Reload flag................................................................................................................................. 498
26.3.8.4 Initialization............................................................................................................................... 500
26.3.9 Fault protection.............................................................................................................................................. 501
26.3.9.1 Fault pin filter.............................................................................................................................502
26.3.9.2 Automatic fault clearing.............................................................................................................503
26.3.9.3 Manual fault clearing................................................................................................................. 503
26.4 Memory Map and Register Descriptions......................................................................................................................504
26.4.1 PWM Control Register: Low (PWM_CTRLL)............................................................................................. 506
26.4.2 PWM Control Register: High (PWM_CTRLH)............................................................................................ 507
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26.4.3 PWM Fault Control Register: Low (PWM_FCTRLL)..................................................................................508
26.4.4 PWM Fault Control Register: High (PWM_FCTRLH).................................................................................510
26.4.5 PWM Fault Status Acknowledge Register: Low (PWM_FLTACKL)..........................................................510
26.4.6 PWM Fault Status Acknowledge Register: High (PWM_FLTACKH).........................................................511
26.4.7 PWM Output Control Register: Low (PWM_OUTL)................................................................................... 513
26.4.8 PWM Output Control Register: High (PWM_OUTH)..................................................................................514
26.4.9 PWM Counter Register: Low (PWM_CNTRL)............................................................................................ 514
26.4.10 PWM Counter Register: High (PWM_CNTRH)...........................................................................................515
26.4.11 PWM Counter Register: Low (PWM_CMODL)...........................................................................................515
26.4.12 PWM Counter Register: High (PWM_CMODH)..........................................................................................516
26.4.13
26.4.14
26.4.15
26.4.16
26.4.17 PWM Disable Mapping Registers 1: Low (PWM_DMAP1L)......................................................................519
26.4.18 PWM Disable Mapping Registers 1: High (PWM_DMAP1H).....................................................................520
26.4.19 PWM Disable Mapping Registers 2: Low (PWM_DMAP2L)......................................................................520
26.4.20 PWM Configure Register: Low (PWM_CNFGL).........................................................................................520
26.4.21 PWM Configure Register: High (PWM_CNFGH)........................................................................................521
26.4.22 PWM Channel Control Register: Low (PWM_CCTRLL)............................................................................ 522
26.4.23 PWM Channel Control Register: High (PWM_CCTRLH)........................................................................... 524
26.4.24 PWM Pulse Edge Control Register: Low (PWM_PECTRLL)......................................................................524
26.4.25 PWM Compare Invert Register: High (PWM_CINVH)................................................................................525
26.5 Resets............................................................................................................................................................................526
PWM Value Register: Low (PWM_VALnL)................................................................................................516
PWM Value Register: High (PWM_VALnH)...............................................................................................517
PWM Deadtime Register: Low (PWM_DTIMnL)........................................................................................518
PWM Deadtime Register: High (PWM_DTIMnH).......................................................................................518
26.6 Clocks........................................................................................................................................................................... 526
26.7 Interrupts.......................................................................................................................................................................527
Chapter 27
Development support
27.1 Introduction...................................................................................................................................................................529
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27.1.1 Forcing active background.............................................................................................................................529
27.1.2 Features.......................................................................................................................................................... 529
27.2 Background debug controller (BDC)............................................................................................................................530
27.2.1 BKGD pin description................................................................................................................................... 531
27.2.2 Communication details.................................................................................................................................. 532
27.2.3 BDC commands............................................................................................................................................. 534
27.2.4 BDC hardware breakpoint............................................................................................................................. 537
27.3 On-chip debug system (DBG)...................................................................................................................................... 537
27.3.1 Comparators A and B.....................................................................................................................................538
27.3.2 Bus capture information and FIFO operation................................................................................................ 538
27.3.3 Change-of-flow information.......................................................................................................................... 539
27.3.4 Tag vs. force breakpoints and triggers...........................................................................................................540
27.3.5 Trigger modes................................................................................................................................................ 541
27.3.6 Hardware breakpoints.................................................................................................................................... 542
27.4 Memory map and register description.......................................................................................................................... 543
27.4.1 BDC Status and Control Register (BDC_SCR).............................................................................................543
27.4.2 BDC Breakpoint Match Register: High (BDC_BKPTH)..............................................................................545
27.4.3 BDC Breakpoint Register: Low (BDC_BKPTL).......................................................................................... 546
27.4.4 System Background Debug Force Reset Register (BDC_SBDFR)...............................................................546
Chapter 28
Debug module (DBG)
28.1 Introduction...................................................................................................................................................................549
28.1.1 Features.......................................................................................................................................................... 549
28.1.2 Modes of operation........................................................................................................................................ 550
28.1.3 Block diagram................................................................................................................................................550
28.2 Signal description..........................................................................................................................................................551
28.3 Memory map and registers............................................................................................................................................551
28.3.1 Debug Comparator A High Register (DBG_CAH)....................................................................................... 552
28.3.2 Debug Comparator A Low Register (DBG_CAL)........................................................................................ 553
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30 NXP Semiconductors
Section number Title Page
28.3.3 Debug Comparator B High Register (DBG_CBH)........................................................................................554
28.3.4 Debug Comparator B Low Register (DBG_CBL).........................................................................................554
28.3.5 Debug Comparator C High Register (DBG_CCH)........................................................................................555
28.3.6 Debug Comparator C Low Register (DBG_CCL).........................................................................................556
28.3.7 Debug FIFO High Register (DBG_FH).........................................................................................................556
28.3.8 Debug FIFO Low Register (DBG_FL)..........................................................................................................557
28.3.9 Debug Comparator A Extension Register (DBG_CAX)............................................................................... 558
28.3.10 Debug Comparator B Extension Register (DBG_CBX)................................................................................559
28.3.11 Debug Comparator C Extension Register (DBG_CCX)................................................................................560
28.3.12 Debug FIFO Extended Information Register (DBG_FX)..............................................................................561
28.3.13 Debug Control Register (DBG_C).................................................................................................................561
28.3.14 Debug Trigger Register (DBG_T)................................................................................................................. 562
28.3.15 Debug Status Register (DBG_S)....................................................................................................................564
28.3.16 Debug Count Status Register (DBG_CNT)...................................................................................................565
28.4 Functional description...................................................................................................................................................566
28.4.1 Comparator.....................................................................................................................................................566
28.4.1.1 RWA and RWAEN in full modes..............................................................................................566
28.4.1.2 Comparator C in loop1 capture mode........................................................................................566
28.4.2 Breakpoints.................................................................................................................................................... 567
28.4.2.1 Hardware breakpoints................................................................................................................ 567
28.4.3 Trigger selection............................................................................................................................................ 568
28.4.4 Trigger break control (TBC)..........................................................................................................................568
28.4.4.1 Begin- and end-trigger............................................................................................................... 569
28.4.4.2 Arming the DBG module...........................................................................................................569
28.4.4.3 Trigger modes............................................................................................................................ 570
28.4.5 FIFO...............................................................................................................................................................572
28.4.5.1 Storing data in FIFO.................................................................................................................. 573
28.4.5.2 Storing with begin-trigger..........................................................................................................573
28.4.5.3 Storing with end-trigger.............................................................................................................573
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NXP Semiconductors 31
Section number Title Page
28.4.5.4 Reading data from FIFO............................................................................................................ 573
28.4.6 Interrupt priority.............................................................................................................................................574
28.5 Resets............................................................................................................................................................................575
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32 NXP Semiconductors
Chapter 1 About This Document

1.1 Overview

1.1.1 Purpose

This document describes the features, architecture, and programming model of the NXP microcontrollers.
1.1.2

Audience

A reference manual is primarily for system architects and software application developers who are using or considering using an NXP product in a system.
1.2

Conventions

1.2.1 Numbering systems

The following suffixes identify different numbering systems:
This suffix Identifies a
b Binary number. For example, the binary equivalent of the
number 5 is written 101b. In some cases, binary numbers are shown with the prefix 0b.
d Decimal number. Decimal numbers are followed by this suffix
only when the possibility of confusion exists. In general, decimal numbers are shown without a suffix.
h Hexadecimal number. For example, the hexadecimal
equivalent of the number 60 is written 3Ch. In some cases, hexadecimal numbers are shown with the prefix 0x.
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NXP Semiconductors 33
Conventions

1.2.2 Typographic notation

The following typographic notation is used throughout this document:
Example Description
placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for
the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers.
code
SR[SCM] A mnemonic in brackets represents a named field in a register. This example refers to the
REVNO[6:4], XAD[7:0] Numbers in brackets and separated by a colon represent either:
Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type is also used for example code. Instruction mnemonics and directives in text and tables are shown in all caps; for example, BSR.
Scaling Mode (SCM) field in the Status Register (SR).
• A subset of a register's named field For example, REVNO[6:4] refers to bits 6–4 that are part of the COREREV field that
occupies bits 6–0 of the REVNO register.
• A continuous range of individual signals of a bus For example, XAD[7:0] refers to signals 7–0 of the XAD bus.

1.2.3 Special terms

The following terms have special meanings:
Term Meaning
asserted Refers to the state of a signal as follows:
• An active-high signal is asserted when high (1).
• An active-low signal is asserted when low (0).
deasserted Refers to the state of a signal as follows:
• An active-high signal is deasserted when low (0).
• An active-low signal is deasserted when high (1).
In some cases, deasserted signals are described as negated.
reserved Refers to a memory space, register, or field that is either
reserved for future use or for which, when written to, the module or chip behavior is unpredictable.
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34 NXP Semiconductors
Chapter 2 Introduction

2.1 Introduction

This device is a low-cost, high-performance UHV HCS08 8-bit microcontroller units (MCUs). It uses the enhanced S08L central processor unit with MOSFET predrivers.
The features are as follows:
• Core platform clock up to 40 MHz, bus clock up to 20 MHz
• Memory option is up to 16 KB flash with 8 B flash line buffer, 768 B RAM (256 B is unrestricted, 512 B is restricted during flash erasing and programming) and 8 B register file
• Wide operating voltage ranges from 4.5–18 V
• 24-pin QFN package
• Ambient operating temperature ranges from –40 °C to 105 °C
2.2

Module functional categories

The modules on this device are grouped into functional categories. Information found here describes the modules assigned to each category in more detail.
Table 2-1. Module functional categories
Module category Description
HCS08 core • 8-bit MCU core, 40 MHz CPU frequency. System • System integration module
• Power management and mode controllers
• Multiple power modes available based on run, wait, stop, and power­down modes
• Interrupt priority controller (IPC)
• Inter-module crossbar
Memories • Up to 16 KB flash memory for SU16 and up to 8 KB flash memory for SU8
Table continues on the next page...
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NXP Semiconductors 35
Module functional categories
Table 2-1. Module functional categories (continued)
Module category Description
• Up to 768 bytes SRAM, including 256 B of which is unrestricted, and the rest 512 B is restricted during flash erasing and programming.
• Up to 8 bytes system register file
Clocks • Internal clock source
• 31.25 to 39.0625 kHz IRC
• 20 kHz oscillator with functional in all power modes
• Frequency-locked loop
• DC to 40 MHz
Security • Windowed COP watchdog
• One cyclic redundancy check (CRC)
Analog • Two 12-bit analog-to-digital converters (ADC)
• One high speed comparator (CMP) with internal 6-bit digital-to-analog converter (DAC)
• One gate drive unit (GDU)
Timers • One 16-bit PWM
• One 16-bit FTM
• One 16-bit modulo timer (MTIM)
• Two pulse width timers (PWT)
• One programmable delay block (PDB)
Communications • One inter-integrated circuit (I2C) module
• One serial communications interface (SCI)
Human-Machine Interfaces (HMI) • Port control (PORT)
• One keyboard interrupt (KBI)

2.2.1 S08L core modules

The following core modules are available on this device.
Table 2-2. Core modules
Module Description
HCS08 V6 CPU The HCS08 CPU is fully source- and object-code-compatible with the M68HC08
CPU. Several instructions and enhanced addressing modes were added to improve C compiler efficiency and to support a new background debug system which replaces the monitor mode of earlier M68HC08 microcontrollers.
Debug module The DBG module implements an on-chip ICE (in-circuit emulation) system and
allows non-intrusive debug of application software by providing an on-chip trace buffer with flexible triggering capability. The trigger can also provide extended breakpoint capacity. The on-chip ICE system is optimized for the HCS08 8-bit architecture and supports 64 KB of memory space.

2.2.2 System modules

The following system modules are available on this device.
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36 NXP Semiconductors
Chapter 2 Introduction
Table 2-3. System modules
Module Description
System integration module (SIM) The SIM includes integration logic and several module configuration settings. Power management controller (PMC) The PMC provides the user with multiple power options. Multiple modes are
supported that allow the user to optimize power consumption for the level of functionality needed. Includes power-on-reset (POR) and integrated low voltage detect (LVD) with reset (brownout) capability and selectable LVD trip points.
Development support Development supports single-wire background debug mode (BDM), which uses the
on-chip background debug controller (BDC) module, and the independent on-chip realtime in-circuit emulation (ICE) system, which uses the on-chip debug (DBG) module.
Debug module (DBG) The DBG module implements an on-chip ICE (in-circuit emulation) system and
allows non-intrusive debug of application software by providing an on-chip trace buffer with flexible triggering capability.

2.2.3 Memories and memory interfaces

The following memories and memory interfaces are available on this device.
Table 2-4. Memories and memory interfaces
Module Description
Flash memory Program flash memory — up to 16 KB (SU16) or 8 KB (SU8) of the non-volatile
flash memory that can execute program code.
SRAM Up to 768 bytes internal system RAM, including 256 B of which is unrestricted, the
rest 512 B is restricted during flash erasing and programming.
System register file Up to 8 bytes.

2.2.4 Clocks

The following clock modules are available on this device.
Table 2-5. Clock modules
Module Description
Internal Clock Source (ICS) ICS module containing an internal reference clock (ICSIRCLK) and a frequency
locked loop (FLL).
Low-Power Oscillator (LPO) The PMC module contains a 20 kHz low-power oscillator which acts as a
standalone low-frequency clock source in all modes.
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NXP Semiconductors 37
Module functional categories
2.2.5 Security and integrity modules
The following security and integrity modules are available on this device:
Table 2-6. Security and integrity modules
Module Description
Windowed COP watchdog (WCOP) The COP watchdog is used to force a system reset when the application software
fails to execute as expected.
Cyclic Redundancy Check (CRC) The cyclic redundancy check (CRC) module generates 16/32-bit CRC code for
error detection.

2.2.6 Analog modules

The following analog modules are available on this device:
Table 2-7. Analog modules
Module Description
Analog-to-digital converters (ADC) 12-bit successive-approximation ADC module. Comparator (CMP) One comparator that compares two analog input voltages across the full range of
the supply voltage and can trigger an ADC acquisition, TPM update, or CPU interrupt.
6-bit digital-to-analog converters (DAC) 64-tap resistor ladder network which provides a selectable voltage reference for
comparator.
Gate Drive Unit (GDU) • 5 V voltage regulator referenced to VDD for HS pre-drivers
• Supports wide operation voltages from 4.5 V to 18 V
• Overvoltage detection on the system supply VBUS pin
• 1/8 VDD drive to ADC

2.2.7 Timer modules

The following timer modules are available on this device:
Table 2-8. Timer modules
Module Description
FlexTimer Module (FTM) • Selectable FTM source clock, programmable prescaler
• 16-bit counter supporting free-running, and counting is up or up-down
• Input capture, output compare, and edge-aligned and center-aligned PWM modes
• Operation of FTM channels as pairs with equal outputs or independent channels with independent outputs
• Programmable interrupt on input capture, reference compare, overflowed counter
Table continues on the next page...
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38 NXP Semiconductors
Chapter 2 Introduction
Table 2-8. Timer modules (continued)
Module Description
Programmable Delay Block (PDB) • 16-bit resolution with a shared prescaler
• Support software and hardware trigger
• Support continuous count mode or single shot delay mode
• Supply on-fly delay value update
• Selective output mode: logic level or one-shot pulse
Pulse Width Timer (PWT) • Automatic measurement of pulse width with 16-bit resolution
• Separate positive and negative pulse width measurements
• Programmable triggering edge for starting measurement
• Programmable measuring time between successive alternating edges, rising edges or falling edges
• Programmable pre-scaler from clock input as 16-bit counter time base
• Two selectable clock sources
• Four selectable pulse inputs
• Programmable interrupt generation upon pulse width value updated and counter overflow
Pulse width modulator (PWM) • PWM operation clock runs at system clock
• Six PWM signals
• Complementary channel operation
• Edge- or center-aligned PWM signals
• 15 bits of resolution
• Half-cycle reload capability
• Integral reload rates from 1 to 16
• Individual software controlled PWM output
• Programmable fault protection
• PWM compare output polarity control
• PWM output polarity control
• Write-protected registers
16-bit modulo timer (MTIM) • 16-bit up-counter
• Four software selectable clock sources for input to prescaler
• Nine selectable clock prescale values
• Modulo compare matched can be an output

2.2.8 Communication interfaces

The following communication interfaces are available on this device:
Table 2-9. Communication modules
Module Description
Inter-integrated circuit (I2C) Allows communication between a number of devices. Also supports the System
Management Bus (SMBus) Specification, version 2.
Serial communications interface (SCI) SCI is used to connect to the RS232 serial input/output port of a personal computer
or workstation and communicate with other embedded controllers.
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NXP Semiconductors 39
S08L Core
S08L Bus
Flash
Line Buffer
User Flash
16 KB (SU16)
8 KB (SU8)
User RAM 768 Bytes
Interrupt Priority
Controller
IRQ
I2C
Modulo Timer
(MTIM)
PWM
ADC0 12-bit
ADC1 12-bit
CMP
+ 6-bit DAC
Windowed Watchdog (WCOP)
Gate Pre-Driver Unit (GDU)
Predriver + 5 CMP + 2 OPAMP
Inter-Module
Crossbar
GPIO Port A&B&C and Peripheral MUX
Power Management Controller (PMC)
System Integration Module (SIM)
Package Pins
Peripheral Bus
BKGD
CPU
Interrupt
Unit
Memory
Map
Controller
Background
Debg
Controller
Peripheral
Bus Bridge
FTM
Ch0,1
PWT
0,1
PDB
Ch0,1
Analog Signals
Analog Inpus
Pre
Driver
Motor Drive
Package Pins
Cyclic Redundancy Check (CRC)
Inter Module Crossbar Outputs
Inter Module Crossbar Inputs
SCI
Internal
32 kHz
Internal
20 kHz LPO
FLL
Internal Clock Source(ICS)
Low Power Osc (LPO)
Clock Generation

MCU block diagram

2.2.9 Human-machine interfaces
The following human-machine interfaces (HMI) are available on this device:
Table 2-10. HMI modules
Module Description
Port Control (PORT) Some general purpose input or output pins are capable of interrupt request
generation.
Keyboard Interrupts (KBI) • Up to eight keyboard interrupt pins with individual pin enable bits
• Each keyboard interrupt pin is programmable
• One software-enabled keyboard interrupt
• Exit from low-power modes
2.3 MCU block diagram
The block diagram below shows the structure of the MCUs.
40 NXP Semiconductors
Figure 2-1. Block diagram
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Chapter 2 Introduction

2.4 Orderable part numbers

The following table summarizes the part numbers of the devices covered by this document.
Table 2-11. Orderable part numbers summary
Part number CPU
frequency
MC9S08SU16VFK 40 MHz 24 QFN 16 KB 768 bytes -40 to 105 °C
MC9S08SU8VFK 40 MHz 24 QFN 8 KB 768 bytes -40 to 105 °C
Pin count Package Total flash
memory
RAM Temperature range
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NXP Semiconductors 41
Orderable part numbers
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42 NXP Semiconductors
Chapter 3 Memory

3.1 Memory map

In this device, the most frequently used registers are placed in the direct page, memory 0x0000 to 0x00FF. Also a portion of RAM is placed in the direct page to take advantage of the direct addressing mode of the CPU. All other register locations in the extended page are the same in terms of instruction cycle times.The placement of the other peripheral modules is not critical because CPU instructions for all other extended memory have the same timing requirements.
As shown below, on-chip memory in this device consists of RAM and flash program memory for nonvolatile data storage, plus I/O and control/status registers. The registers are divided into three groups: direct-page registers, high-page registers and nonvolatile registers.
The entire memory space are partitioned to:
• Direct-page registers: 0x0000–0x007F
• Random access memory: 0x0080–0x037F
• Unimplemented: 0x0380–0x17FF
• High-page registers: 0x1800–0x18FF
• Unimplemented: 0x1900–0xBFFF (SU16) and 0x1900–0xDFFF (SU8)
• Flash memory (SU16): 0xC000–0xFFFF
• Flash array: 0xC000–0FFBF
• Vector table: 0xFFC0–0xFFFF
• Flash memory (SU8): 0xE000–0xFFFF
• Flash array: 0xE000–0FFBF
• Vector table: 0xFFC0–0xFFFF
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NXP Semiconductors 43
HIGH PAGE REGISTERS
DIRECT PAGE REGISTERS
RAM 768 BYTES
8192 BYTES
0x0000 0x007F
0x0080
0x037F
UNIMPLEMENTED
0x0380
0x17FF 0x1800
0x18FF 0x1900
UNIMPLEMENTED
0xFFFF
0xDFFF 0xE000
HIGH PAGE REGISTERS
DIRECT PAGE REGISTERS
RAM 768 BYTES
16,384 BYTES
0x0000 0x007F
0x0080
0x037F
UNIMPLEMENTED
0x0380
0x17FF
0x1800
0x18FF 0x1900
UNIMPLEMENTED
0xFFFF
0xBFFF 0xC000
SU16
SU8

Reset and interrupt vector assignments

Figure 3-1. Memory map
3.2
The following table summarizes the reset and interrupt sources assignments for this device. The high-order byte of the address for the interrupt service routine is located at the first address in the vector address column, and the low-order byte of the address for the interrupt service routine is located at the next higher address. Higher-priority sources are located toward the bottom of the table. The Interrupt Priority Controller module is integrated on this device and provides the ability to alter the default priority scheme.
The vector names shown in this table are the labels used in the NXP-provided header files for the device.
Reset and interrupt vector assignments
Table 3-1. Reset and interrupt vectors
Vector number
31 0xFFC0:FFC1 NVM Vnvm NVM CCIF 30 0xFFC2:FFC3 I2C Viic I2C Or'ed all flags 29 0xFFC4:FFC5 KBI Vkbi KBI KBF
44 NXP Semiconductors
Address
(high/low)
Vector Vector name Module Source
Table continues on the next page...
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Table 3-1. Reset and interrupt vectors (continued)
Chapter 3 Memory
Vector number
28 0xFFC6:FFC7 MTIM overflag Vmtim MTIM TOF 27 0xFFC8:FFC9 Lose of lock Vics ICS LOLS
26 0xFFCA:FFCB
25 0xFFCC:FFCD SCI transmit Vscitx SCI
24 0xFFCE:FFCF SCI receive Vscirx SCI
23 0xFFD0:FFD1 SCI error Vscierr SCI
22 0xFFD2:FFD3
21 0xFFD4:FFD5
20 0xFFD6:FFD7
19 0xFFD8:FFD9 CMP Vcmp ACMP
18 0xFFDA:FFDB FTM overflow Vtpmovf FTM TOF 17 0xFFDC:FFDD FTM channel 1 Vtpmch1 FTM CH1F 16 0xFFDE:FFDF FTM channel 0 Vtpmch0 FTM CH0F 15 0xFFE0:FFE1 Reserved ― ― ― 14 0xFFE2:FFE3 Reserved ― ― ―
13 0xFFE4:FFE5 GDU_AMP_OC GDU GDU
12 0xFFE6:FFE7
11 0xFFE8:FFE9
10 0xFFEA:FFEB PWT1 overflow Vpwt1ovf PWT1 PWTOV
9 0xFFEC:FFED PWT1 data ready Vpwt1rdy PWT1 PWTRDY 8 0xFFEE:FFEF PWT0 overflow Vpwt0ovf PWT0 PWTOV 7 0xFFF0:FFF1 PWT0 data ready Vpwt0rdy PWT0 PWTRDY 6 0xFFF2:FFF3 PWM reload Vmcpwm mcPWM PWMF
Address
(high/low)
Vector Vector name Module Source
PDB successful
compare
GDU_ACMPU_PH
2
GDU_ACMPV_PH
1
GDU_ACMPW_PH
0
ADC1 conversion
complete
ADC0 conversion
complete
Vpdb PDB
Vgducmp2 GCMP2
Vgducmp1 GCMP1
Vgducmp0 GCMP0
Vadc1 ADC1 COCO
Vadc0 ADC0 COCO
TCF0 TCF1
TDRE
TC
RDRF
IDLE
LBKDIF
RXEDGIF
OR
NF FE
PF CFRU CFFU CFRV CFFV
CFRW CFFW
CFR CFF
AMP_OC0 AMP_OC1
Table continues on the next page...
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NXP Semiconductors 45

Register addresses assignments

Table 3-1. Reset and interrupt vectors (continued)
Vector number
5 0xFFF4:FFF5 PWM fault Vmcpwmf mcPWM
4 0xFFF6:FFF7
3 0xFFF8:FFF9
2 0xFFFA:FFFB Xbar_IRQ Virq Crossbar IRQF 1 0xFFFC:FFFD SWI Vswi Core SWI instruction
0 0xFFFE:FFFF Reset Vreset System Control
Address
(high/low)
Vector Vector name Module Source
Over voltage
warning
Low voltage
warning
PMC high temp
warning
Vovw GDU OVWF
Vlvw PMC
flash illegal access
FFLAG0 FFLAG1 FFLAG2 FFLAG3
LVWF
HTIF
POR
WCOP
LVD LOC
/Reset pin
illegal opcode
illegal address
3.3 Register addresses assignments
The register definitions vary in different memory sizes. The register addresses of unused peripherals are reserved. The following table shows the register availability of the devices.
The registers in the devices are divided into two groups:
• Direct-page registers are located in the first 128 locations in the memory map, so they can be accessed with efficient direct addressing mode instructions.
• High-page registers are used much less often, so they are located above 0x1800 in the memory map. This leaves room in the direct page for more frequently used registers and variables.
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46 NXP Semiconductors
Chapter 3 Memory
Direct-page registers can be accessed with efficient direct addressing mode instructions. which requires only the lower byte of the address. Bit manipulation instructions can be used to access any bit in a direct-page register.
Table 3-2. Peripheral registers availability
Address Bytes Peripheral Peripheral registers Comment
Direct Page Registers
0x0000—0x0000 1 PTA PORT_PTAD
Port data0x0001—0x0001 1 PTB PORT_PTBD 0x0002—0x0002 1 PTC PORT_PTCD 0x0003—0x0003 1 PTA PORT_PTADD
Port data direction0x0004—0x0004 1 PTB PORT_PTBDD 0x0005—0x0005 1 PTC PORT_PTCDD 0x0006—0x0006 1 XBAR XBAR_EXTMUX PWM channel 2-to-1 Mux 0x0007—0x0007 1 ― Reserved ―
MTIM_SC, MTIM_CLK, MTIM_CNTH,
0x0008—0x000D 6 MTIM
0x000E—0x00F 2 IPC IPC_SC, IPC_IPMPS ―
0x0010—0x0017 8 ADC0
0x0018—0x001F 8 ADC1
0x0020—0x002B 12 GDU
0x002C—0x002F 4 ― Reserved ―
0x0030—0x0037 8 PWT0
0x0038—0x003F 8 PWT1
0x0040—0x005F 32 PWM
Table continues on the next page...
MTIM_CNTL, MTIM_MODH,
MTIM_MODL
ADC0_SC1, ADC0_SC2, ADC0_SC3,
ADC0_SC4, ADC0_RH, ADC0_RL,
ADC0_CVH, ADC0_CVL
ADC1_SC1, ADC1_SC2, ADC1_SC3,
ADC1_SC4, ADC1_RH, ADC1_RL,
ADC1_CVH, ADC1_CVL
GDU_PHCMP0CR0, GDU_PHCMP0CR1, GDU_PHCMP0FPR, GDU_PHCMP0SCR, GDU_PHCMP1CR0, GDU_PHCMP1CR1, GDU_PHCMP1FPR, GDU_PHCMP1SCR, GDU_PHCMP2CR0, GDU_PHCMP2CR1, GDU_PHCMP2FPR,
GDU_PHCMP2SCR
PWT0_CS, PWT0_CR, PWT0_PPH,
PWT0_PPL, PWT0_NPH,
PWT0_NPL, PWT0_CNTH,
PWT0_CNTL
PWT1_CS, PWT1_CR, PWT1_PPH,
PWT1_PPL, PWT1_NPH,
PWT1_NPL, PWT1_CNTH,
PWT1_CNTL
PWM_CTRLL, PWM_CTRLH,
PWM_FCTRLL, PWM_FCTRLH,
PWM_FLTACKL, PWM_FLTACKH,
―
―
―
―
―
―
―
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NXP Semiconductors 47
Register addresses assignments
Table 3-2. Peripheral registers availability (continued)
Address Bytes Peripheral Peripheral registers Comment
PWM_OUTL, PWM_OUTH,
PWM_CNTRL, PWM_CNTRH,
PWM_CMODL, PWM_CMODH,
PWM_VAL0L, PWM_VAL0H, PWM_VAL1L, PWM_VAL1H, PWM_VAL2L, PWM_VAL2H, PWM_VAL3L, PWM_VAL3H, PWM_VAL4L, PWM_VAL4H, PWM_VAL5L, PWM_VAL5H,
PWM_DTIM0L, PWM_DTIM0H ,
PWM_DTIM1L, PWM_DTIM1H,
PWM_DMAP1H, PWM_DMAP1L,
PWM_DMAP2H,PWM_DMAP2L
PDB_CTRL0, PDB_CTRL1,
PDB_CMPL0, PDB_CMPH0,
0x0060—0x0067 8 PDB
PDB_CMPL1, PDB_CMPH1,
CMP_CR0, CMP_CR1, CMP_FPR,
0x0068—0x006E 8 CMP
CMP_MUXCR, CMP_MUXPE
0x006F—0x006F 1 ― Reserved ―
FTM0_CNTL, FTM0_MODH,
0x0070—0x007A 11 FTM0
0x007B—0x007B 1 ― Reserved ― 0x007C—0x007E 3 KBI KBI_SC, KBI_PE, KBI_ES Port A KBI 0x007F—0x007F 1 IRQ IRQ_SC IRQ from Xbar
0x1800—0x180F 16 SIM
0x1810—0x1817 8 SIM register filer
0x1818—0x181F 8 ― Reserved ―
0x1820—0x1829 10 PWM
0x182A—0x182F 6 ― Reserved ―
FTM0_MODL, FTM0_C0SC,
FTM0_C0VH, FTM0_C0VL, FTM0_C1SC, FTM0_C1VH,
High Page Registers
SIM_SRS, SIM_SBDFR, SIM_SDIDH,
SIM_SOPT2, SIM_MUXPTAL,
SIM_MUXPTAH, SIM_MUXPTBL,
SIM_MUXPTBH, SIM_MUXPTCL,
SIM_SCGC1, SIM_SCGC2,
SIM_PORREG0, SIM_PORREG1, SIM_PORREG2, SIM_PORREG3, SIM_PORREG4, SIM_PORREG5,
SIM_PORREG6, SIM_PORREG7
PWM_CNFGL, PWM_CNFGH,
PWM_CCTRLL, PWM_CCTRLH,
PDB_CNT0,
PDB_CNT1
CMP_SCR, CMP_DACCR,
FTM0_SC, FTM0_CNTH,
FTM0_C1VL
SIM_SDIDL, SIM_SOPT1,
SIM_SCGC3, SIM_SCDIV
PWM_PECTRLL,
PWM_CINVH
Control bit in PDB_CTRL
decides read counter high or
low
―
―
―
―
―
Table continues on the next page...
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48 NXP Semiconductors
Chapter 3 Memory
Table 3-2. Peripheral registers availability (continued)
Address Bytes Peripheral Peripheral registers Comment
FTMRH_FCLKDIV, FTMRH_FSEC,
FTMRH_FCCOBIX, FTMRH_FCNFG,
0x1830—0x183C 16 FTMRH
0x183D—0x1847 11 ― Reserved ―
0x1848—0x184F 8 ICS
0x1850—0x185F 16 PMC
0x1860—0x1867 8 IPC IPC_ILRS0―IPC_ILRS7 ―
0x1868—0x186F 8 SCI0
0x1868—0x186F 8 ― Reserved ―
0x1870—0x187F 16 GDU
0x1880—0x1881 2 ILLA SIM_ILLAH, SIM_ILLAL ― 0x1882—0x188F 16 ― Reserved ―
0x1890—0x1898 9 CRC
0x1899—0x18AF 23 ― Reserved ―
0x18B0—0x18BC 13 I2C
0x18BD—0x18BF 3 ― Reserved ―
0x18C0—0x18CF 16 DBG
0x18D0—0x18DF 16 XBAR XBAR_SEL0—XBAR_SEL15 ―
FTMRH_FSTAT, FTMRH_FPROT,
FTMRH_FCCOBHI,
FTMRH_FCCOBLO, FTMRH_FOPT
ICS_C1, ICS_C2, ICS_C3, ICS_C4,
ICS_S
PMC_CTRL, PMC_RST,
PMC_TPCTRLSTAT, PMC_TPTM,
PMC_RC20KTRM, PMC_LVCTLSTAT1, PMC_LVCTLSTAT2,
PMC_VREFHCFG,
PMC_VREFHLVW, PMC_STAT
SCI0_BDH, SCI0_BDL,
SCI0_C1, SCI0_C2,
SCI0_S1, SCI0_S2,
SCI0_C3, SCI0_D,
GDU_CLMPCTRL, GDU_IOCTRL,
GDU_PHASECTRL, GDU_CURCTRL,
GDU_LIMIT0CR0, GDU_LIMIT0CR1,
GDU_LIMIT0FPR, GDU_LIMIT0SCR,
GDU_LIMIT0DACCR,
GDU_LIMIT1CR0, GDU_LIMIT1CR1.
GDU_LIMIT1FPR, GDU_LIMIT1SCR,
GDU_LIMIT1DACCR,
GDU_STATREG, GDU_SIGBIAS
CRC_DH1, CRC_DH0, CRC_DL1, CRC_DL0, CRC_PH1, CRC_PH0,
CRC_PL1, CRC_PL0, CRC_CTRL
I2C_A1, I2C_F, I2C_C1, I2C_S1,
I2C_D, I2C_C2, I2C_SCS, I2C_RA,
I2C_SMB, I2C_A2, I2C_SLTH,
I2C_SLTL, I2C_S2
DBG_CAH, DBG_CAL, DBG_CBH, DBG_CBL, DBG_CCH, DBG_CCL,
DBG_FH, DBG_FL, DBG_CAX,
DBG_CBX, DBG_CCX, DBG_FX,
DBG_C, DBG_T, DBG_S, DBG_CNT
―
―
―
―
―
―
―
―
Table continues on the next page...
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NXP Semiconductors 49
Register addresses assignments
Table 3-2. Peripheral registers availability (continued)
Address Bytes Peripheral Peripheral registers Comment
0x18E0—0x18E0 1 PTA PORT_PTAPE 0x18E1—0x18E1 1 PTB PORT_PTBPE 0x18E2—0x18E2 1 PTC PORT_PTCPE 0x18E3—0x18E5 3 ― Reserved ― 0x18E6—0x18E6 1 PTB PORT_PTBHD Port high drive enable
0x18E7—0x18EB 5 ― Reserved ―
0x18EC—0x18EF 4 PTx
0x18F0—0x18F7 8 ― Reserved ― 0x18F8—0x18FF 8 SIM SIM_UUID0—SIM_UUID7 64-bit unique ID
PORT_FCLKDIV, PORT_IOFLT0,
PORT_IOFLT1, PORT_IOFLT2
Port pull-up enable
Port Filter for pins
Several reserved flash memory locations, shown in the following table, are used for storing values used by several registers. These registers include an 8-byte backdoor key, NV_BACKKEY, which can be used to gain access to secure memory resources. During reset events, the contents of NVPROT and NVOPT in the reserved flash memory are transferred into corresponding FPROT and FOPT registers in the high-page registers area to control security and block protection options
Table 3-3. Reserved flash memory addresses
Address Register Name Bit 7 6 5 4 3 2 1 Bit 0
0xFF6E NV_FTRIM 0xFF6F NV_ICSTRM TRIM 0xFF70 NV_BACKKEY0 BACKKEY0 0xFF71 NV_BACKKEY1 BACKKEY1 0xFF72 NV_BACKKEY2 BACKKEY2 0xFF73 NV_BACKKEY3 BACKKEY3 0xFF74 NV_BACKKEY4 BACKKEY4 0xFF75 NV_BACKKEY5 BACKKEY5 0xFF76 NV_BACKKEY6 BACKKEY6 0xFF77 NV_BACKKEY7 BACKKEY7 0xFF78 Reserved — — — — — — — — 0xFF79 Reserved — — — — — — — — 0xFF7A Reserved — — — — — — — — 0xFF7B Reserved — — — — — — — —
0xFF7C NV_FPROT
0xFF7D Reserved — — — — — — — —
0xFF7E NV_FOPT NV 0xFF7F NV_FSEC
— — — — — — — FTRIM
FPOPE
N
KEYEN 1 1 1 1 SEC
— FPHDIS FPH — — —
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50 NXP Semiconductors
Chapter 3 Memory
The 8-byte comparison key can be used to temporarily disengage memory security provided the key enable field, NV_FSEC[KEYEN], is 10b. This key mechanism can be accessed only through user code running in secure memory. A security key cannot be entered directly through background debug commands. This security key can be disabled completely by programming the NV_FSEC[KEYEN] bit to 0b. If the security key is disabled, the only way to disengage security is by mass erasing the flash if needed, normally through the background debug interface and verifying that flash is blank. To avoid returning to secure mode after the next reset, program the security bits, NV_FSEC[SEC], to the unsecured state (10b).

3.4 Random-access memory (RAM)

The locations in RAM below 0x0100 can be accessed using the more efficient direct addressing mode. Any single bit in this area can be accessed with the bit manipulation instructions (BCLR, BSET, BRCLR, and BRSET).
The RAM retains data when the MCU is in low-power wait, or stop mode. At power-on, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention.
For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In this series, re-initialize the stack pointer to the top of the RAM so that the direct-page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the NXP-provided equate file).
LDHX #RamLast+1 ;point one past RAM TXS ;SP<-(H:X-1)
When security is enabled, the RAM is considered a secure memory resource and is not accessible through BDM or code executing from non-secure memory.
3.5

Flash memory

This device includes flash memory. The flash memory is ideal for single-supply applications that allow for field reprogramming without requiring external high voltage sources for program or erase operations. The flash module includes a memory controller that executes commands to modify flash memory contents. The user interface to the memory controller consists of the indexed flash common command object (FCCOB)
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NXP Semiconductors 51

System register file

register, which is written to with the command, global address, data, and any required command parameters. The memory controller must complete the execution of a command before the FCCOB register is written to with a new command.
CAUTION
A flash byte or longword must be in the erased state before being programmed. Cumulative programming of bits within a flash byte or longword is not allowed.
The flash memory is read as two bytes per read. Read access time is one bus cycle for two bytes. For flash memory, an erased bit reads 1 and a programmed bit reads 0.
3.6
System register file
This device includes a 8-byte register file that is powered in all power modes. Also, it retains contents during low-voltage detect (LVD) events and is only reset during
a power-on reset.
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Chapter 4 Interrupt

4.1 Interrupts

Interrupts save the current CPU status and registers, execute an interrupt service routine (ISR), and then restore the CPU status so that processing resumes where it left off before the interrupt. Other than the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events such as an edge on the IRQ pin or a timer­overflow event. The debug module can also generate an SWI under certain circumstances.
If an event occurs in an enabled interrupt source, an associated read-only status flag will be set. The CPU does not respond unless only the local interrupt enable is a logic 1. The
CCR [I] is 0 to allow interrupts. The CCR [I] is initially set after reset that masks
(prevents) all maskable interrupt sources. The user program initializes the stack pointer and performs other system setups before clearing the CCR [I] to allow the CPU to respond to interrupts.
When the CPU receives a qualified interrupt request, it completes the current instruction before responding to the interrupt. The interrupt sequence obeys the same cycle-by-cycle sequence as the SWI instruction and consists of:
• Saving the CPU registers on the stack.
• Setting the CCR [I] to mask further interrupts.
• Fetching the interrupt vector for the highest-priority interrupt that is currently pending.
• Filling the instruction queue with the first three bytes of program information starting from the address fetched from the interrupt vector locations.
While the CPU is responding to the interrupt, the CCR [I] is automatically set to prevent another interrupt from interrupting the ISR itself, which is called nesting of interrupts. Normally, the CCR [I] is restored to 0 when the CCR is restored from the value stacked
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Interrupts
on entry to the ISR. In rare cases, the CCR [I] may be cleared inside an ISR, after clearing the status flag that generated the interrupt, so that other interrupts can be serviced without waiting for the first service routine to finish. This practice is recommended only for the most experienced programmers because it can lead to subtle program errors that are difficult to debug.
The interrupt service routine ends with a return-from-interrupt (RTI) instruction that restores the CCR, A, X, and PC registers to their pre-interrupt values by reading the previously saved information off the stack.
Note
For compatibility with the M68HC08, the H register is not automatically saved and restored. Push H onto the stack at the start of the interrupt service routine (ISR) and restore it immediately before the RTI that is used to return from the ISR.
When two or more interrupts are pending when the CCR [I] is cleared, the highest priority source is serviced first.
4.1.1

Interrupt stack frame

The following figure shows the contents and organization of a stack frame. Before the interrupt, the stack pointer (SP) points at the next available byte location on the stack. The current values of CPU registers are stored on the stack, starting with the low-order byte of the program counter (PC) and ending with the CCR. After stacking, the SP points at the next available location on the stack, which is the address that is one less than the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred.
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54 NXP Semiconductors
* High byte (H) of index register is not automatically stacked.
STACKING
ORDER
7
5
5
4
4
3
3
*
1
1
2
2
0
UNSTACKING
ORDER
PROGRAM COUNTER LOW
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER (LOW BYTE X)
PROGRAM COUNTER HIGH
TOWARD LOWER ADDRESSES
TOWARD HIGHER ADDRESSES
SP BEFORE
SP AFTER
INTERRUPT STACKING
THE INTERRUPT
Chapter 4 Interrupt
Figure 4-1. Interrupt stack frame
When an RTI instruction executes, these values are recovered from the stack in reverse order. As part of the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information, starting from the PC address recovered from the stack.
The status flag causing the interrupt must be acknowledged (cleared) before returning from the ISR. Typically, the flag must be cleared at the beginning of the ISR because if another interrupt is generated by this source it will be registered so that it can be serviced after completion of the current ISR.
4.1.2

Hardware nested interrupt

This device has interrupt priority controller (IPC) module to provide up to four-level nested interrupt capability. IPC includes the following features:
• Four-level programmable interrupt priority for each interrupt source.
• Support for prioritized preemptive interrupt service routines
• Low-priority interrupt requests are blocked when high-priority interrupt service routines are being serviced.
• Higher or equal priority level interrupt requests can preempt lower priority interrupts being serviced.
• Automatic update of interrupt priority mask with being serviced interrupt source priority level when the interrupt vector is being fetched.
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NXP Semiconductors 55
DECODE
VFETCH
INTOUT0
INTIN0
ILR0[1:0]
ILR47
CPU
ILR0
ILR Register Content
IPM
ADDRESS[5:0]
IPMPS
[1 :0]
[1:0]
[1:0]
[1:0]
[1:0]
INTOUT1
INTIN1
ILR1[1:0]
v
v
v
INTOUT47
INTIN47
ILR47[1:0]
IPCE
x
x
x
x x
x x x
x
x x
x x
x x
x x
x x
x x
x x
x xx
x
x x
x
Two bits are pushed during vector fetch
software (PULIPM = 1)
Two bits are pulled by
. .
.
LOGIC
6
AND SHIFT
(Interrupt Priority Mask Pseudo Stack Register)
+
+
+
.
.
. .
.
.
. .
.
.
. .
Inputs
Outputs
(IPC Enable)
00
1
0
Stop
Interrupts
• Interrupt priority mask can be modified during main flow or interrupt service execution.
• Previous interrupt mask level is automatically stored when interrupt vector is fetched (four levels of previous values accommodated)
The IPC works with the existing HCS08 interrupt mechanism to allow nested interrupts with programmable priority levels. This module also allows implementation of preemptive interrupt according to the programmed interrupt priority with minimal software overhead. The IPC consists of three major functional blocks:
Figure 4-2. Interrupt priority controller block diagram
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Chapter 4 Interrupt
• The interrupt priority level registers
• The interrupt priority level comparator set
• The interrupt mask register update and restore mechanism
4.1.2.1 Interrupt priority level register
This set of registers is associated with the interrupt sources to the HCS08 CPU. Each interrupt priority level is a 2-bit value such that a user can program the interrupt priority level of each source to priority 0, 1, 2, or 3. Level 3 has the highest priority while level 0 has the lowest. Software can read or write to these registers at any time. The interrupt priority level comparator set, interrupt mask register update, and restore mechanism use this information.
4.1.2.2 Interrupt priority level comparator set
When the module is enabled, an active interrupt request forces a comparison between the corresponding ILR and the 2-bit interrupt mask IPM[1:0]. In stop mode, the IPM[1:0] is substituted by value 00b. If the ILR value is greater than or equal to the value of the interrupt priority mask (IPM bits in IPCSC), the corresponding interrupt out (INTOUT) signal will be asserted and signals an interrupt request to the HCS08 CPU.
When the module is disabled, the interrupt request signal from the source is directly passed to the CPU.
The interrupt priority level programmed in the interrupt priority register will not affect the inherent interrupt priority arbitration as defined by the HCS08 CPU because the IPC is an external module. Therefore, if two (or more) interrupts are present in the HCS08 CPU at the same time, the inherent priority in HCS08 CPU will perform arbitration by the inherent interrupt priority.
4.1.2.3
Interrupt priority mask update and restore mechanism
The interrupt priority mask (IPM) is two bits located in the least significant end of IPCSC register. These two bits control which interrupt is allowed to be presented to the HCS08 CPU. During vector fetch, the interrupt priority mask is updated automatically with the value of the ILR corresponding to that interrupt source. The original value of the IPM will be saved onto IPMPS for restoration after the interrupt service routine completes execution. When the interrupt service routine completes execution, the user restore the
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NXP Semiconductors 57
Interrupts
original value of IPM by writing 1 to the IPCSC[PULIPM] bit. In both cases, the IPMPS is a shift register functioning as a pseudo stack register for storing the IPM. When the IPM is updated, the original value is shifted into IPMPS. The IPMPS can store four levels of IPM. If the last position of IPMPS is written, the PSF flag indicates that the IPMPS is full. If all the values in the IPMPS were read, the PSE flag indicates that the IPMPS is empty.
4.1.2.4 Integration and application of the IPC
All interrupt inputs that comes from peripheral modules are asynchronous signals. None of the asynchronous signals of the interrupts are routed to IPC. The asynchronous signals of the interrupts are routed directly to SIM module to wake system clocks in stop mode.
Additional care must be exercised when IRQ is reprioritized by IPC. CPU instructions BIL and BIH need input from IRQ pin. If IRQ interrupt is masked, BIL and BIH still work but the IRQ interrupt will not occur.
• The interrupt priority controller must be enabled to function. While inside an interrupt service routine, some work has to be done to enable other higher priority interrupts. The following is a pseudo code example written in assembly language:
INT_SER : BCLR INTFLAG,INTFLAG_R ; clear flag that generate interrupt . ; do the most critical part . ; which it cannot be interrupted . . . CLI ; global interrupt enable and nested interrupt enabled . ; continue the less critical . . . BSET PULIPM, PULIPM_R ; restore the old IPM value before leaving RTI ; then you can return
• A minimum overhead of six bus clock cycles is added inside an interrupt services routine to enable preemptive interrupts.
• As an interrupt of the same priority level is allowed to pass through IPC to HCS08 CPU, the flag generating the interrupt must be cleared before doing CLI to enable preemptive interrupts.
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Chapter 4 Interrupt
• The IPM is automatically updated to the level the interrupt is servicing and the original level is kept in IPMPS. Watch out for the full (PSF) bit if nesting for more than four levels is expected.
• Before leaving the interrupt service routine, the previous levels must be restored manually by setting PULIPM bit. Watch out for the full (PSF) bit and empty (PSE) bit.
4.2

IPC memory map and register descriptions

IPC memory map
Absolute
address
(hex)
E IPC Status and Control Register (IPC_SC) 8 R/W 20h 4.2.1/59
F Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS) 8 R 00h 4.2.2/60 1860 Interrupt Level Setting Registers n (IPC_ILRS0) 8 R/W 00h 4.2.3/61 1861 Interrupt Level Setting Registers n (IPC_ILRS1) 8 R/W 00h 4.2.3/61 1862 Interrupt Level Setting Registers n (IPC_ILRS2) 8 R/W 00h 4.2.3/61 1863 Interrupt Level Setting Registers n (IPC_ILRS3) 8 R/W 00h 4.2.3/61 1864 Interrupt Level Setting Registers n (IPC_ILRS4) 8 R/W 00h 4.2.3/61 1865 Interrupt Level Setting Registers n (IPC_ILRS5) 8 R/W 00h 4.2.3/61 1866 Interrupt Level Setting Registers n (IPC_ILRS6) 8 R/W 00h 4.2.3/61 1867 Interrupt Level Setting Registers n (IPC_ILRS7) 8 R/W 00h 4.2.3/61
Register name
Width
(in bits)
Access Reset value
4.2.1 IPC Status and Control Register (IPC_SC)
Section/
page
This register contains status and control bits for the IPC.
Address:
NXP Semiconductors 59
Eh base + 0h offset = Eh
Bit 7 6 5 4 3 2 1 0
Read
Write PULIPM
Reset
IPCE
0 0 1 0 0 0 0 0
0 PSE PSF 0 0
IPC_SC field descriptions
Field Description
7
IPCE
Interrupt Priority Controller Enable
This bit enables/disables the interrupt priority controller module.
Table continues on the next page...
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IPM
IPC memory map and register descriptions
IPC_SC field descriptions (continued)
Field Description
0 Disables IPCE. Interrupt generated from the interrupt source is passed directly to CPU without
processing (bypass mode). The IPMPS register is not updated when the module is disabled.
1 Enables IPCE and interrupt generated from the interrupt source is processed by IPC before passing to
CPU.
6
Reserved
5
PSE
4
PSF
3
PULIPM
This field is reserved. This read-only field is reserved and always has the value 0.
Pseudo Stack Empty
This bit indicates that the pseudo stack has no valid information. This bit is automatically updated after each IPMPS register push or pull operation.
Pseudo Stack Full
This bit indicates that the pseudo stack register IPMPS register is full. It is automatically updated after each IPMPS register push or pull operation. If additional interrupt is nested after this bit is set, the earliest interrupt mask value(IPM0[1:0]) stacked in IPMPS will be lost.
0 IPMPS register is not full. 1 IPMPS register is full.
Pull IPM from IPMPS
This bit pulls stacked IPM value from IPMPS register to IPM bits of IPCSC. Zeros are shifted into bit positions 1 and 0 of IPMPS.
0 No operation. 1 Writing 1 to this bit causes a 2-bit value from the interrupt priority mask pseudo stack register to be
pulled to the IPM bits of IPCSC to restore the previous IPM value.
2
Reserved
IPM Interrupt Priority Mask
This field is reserved. This read-only field is reserved and always has the value 0.
This field sets the mask for the interrupt priority control. If the interrupt priority controller is enabled, the interrupt source with an interrupt level (ILRxx) value that is greater than or equal to the value of IPM will be presented to the CPU. Writes to this field are allowed, but doing this will not push information to the IPMPS register. Writing IPM with PULIPM setting when IPCE is already set, the IPM will restore the value pulled from the IPMPS register, not the value written to the IPM register.
4.2.2 Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)
This register is used to store the previous interrupt priority mask level temporarily when the currently active interrupt is executed.
Address:
Eh base + 1h offset = Fh
Bit 7 6 5 4 3 2 1 0
Read IPM3 IPM2 IPM1 IPM0
Write
Reset
0 0 0 0 0 0 0 0
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Chapter 4 Interrupt
IPC_IPMPS field descriptions
Field Description
7–6
IPM3
5–4
IPM2
3–2
IPM1
IPM0 Interrupt Priority Mask pseudo stack position 0
Interrupt Priority Mask pseudo stack position 3
This field is the pseudo stack register for IPM3. The most recent information is stored in IPM3. Interrupt Priority Mask pseudo stack position 2
This field is the pseudo stack register for IPM2. The most recent information is stored in IPM2. Interrupt Priority Mask pseudo stack position 1
This field is the pseudo stack register for IPM1. The most recent information is stored in IPM1.
This field is the pseudo stack register for IPM0. The most recent information is stored in IPM0.
4.2.3 Interrupt Level Setting Registers n (IPC_ILRSn)
This set of registers (ILRS0-ILRS7) contains the user specified interrupt level for each interrupt source, and indicates the number of the register (ILRSn is ILRS0 through ILRS7).
Address:
Eh base + 1852h offset + (1d × i), where i=0d to 7d
Bit 7 6 5 4 3 2 1 0
Read
Write
Reset
ILRn3 ILRn2 ILRn1 ILRn0
0 0 0 0 0 0 0 0
IPC_ILRSn field descriptions
Field Description
7–6
ILRn3
5–4
ILRn2
3–2
ILRn1
ILRn0 Interrupt Level Register for Source n*4+0
Interrupt Level Register for Source n*4+3
This field sets the interrupt level for interrupt source n*4+3. Interrupt Level Register for Source n*4+2
This field sets the interrupt level for interrupt source n*4+2. Interrupt Level Register for Source n*4+1
This field sets the interrupt level for interrupt source n*4+1.
This field sets the interrupt level for interrupt source n*4+0.
4.3 IRQ
The IRQ (interrupt request) module provides a maskable interrupt input.
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NXP Semiconductors 61
IRQIE
D
Q
CK
CLR
IRQ INTERRUPT REQUEST
V
DD
IRQMOD
IRQF
TO CPU FOR
INSTRUCTIONS
RESET
BYPASS
STOP
STOP
BUSCLK
IRQPE
IRQ
1
0
S
IRQEDG
SYNCHRO-
SYNCHRO-
NIZER
NIZER
IRQPDD
WAKE-UP
INPUTS
MODULES
TO INTERNAL
IRQACK
BIL/BIH
To pullup enable logic for IRQ
IRQ

4.3.1 Features

Features of the IRQ module include:
• IRQ signal is from Intermodule crossbar Output, XBAR_OUT15
• IRQ Interrupt Control Bits
• Programmable Edge-only or Edge and Level Interrupt Sensitivity
• Automatic Interrupt Acknowledge
A low level applied to the interrupt request (IRQ) can latch a CPU interrupt request. The following figure shows the structure of the IRQ module:
IRQ is managed by the IRQSC status and control register. When the IRQ function is enabled, synchronous logic monitors the Xbar_OUT15 for edge-only or edge-and-level events. When the MCU is in stop mode and system clocks are shut down, a separate asynchronous path is used so that the IRQ, if enabled, can wake the MCU.
62 NXP Semiconductors
Figure 4-3. IRQ module block diagram
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Chapter 4 Interrupt
4.3.1.1 Configuration options
The IRQ input enable control bit (IRQSC[IRQPE]) must be 1 for the IRQ signal to act as the IRQ input. The user can choose the polarity of edges or levels detected (IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD), or whether an event causes an interrupt or only sets the IRQF flag, which can be polled by software.
Since IRQ signal is from XBAR_OUT15, it is recommend XBAR_OUT15 is set to logic high after reset.
BIH and BIL instructions may be used to detect the level on the IRQ signal when IRQ is enabled.
4.3.1.2 Edge and level sensitivity
The IRQSC[IRQMOD] control bit reconfigures the detection logic so that it can detect edge events and levels. In this detection mode, the IRQF status flag is set when an edge is detected, if the IRQ signal changes from the de-asserted to the asserted level, but the flag is continuously set and cannot be cleared as long as the IRQ signal remains at the asserted level.
4.4

IRQ Memory Map and Register Descriptions

IRQ memory map
Absolute
address
(hex)
7F Interrupt Pin Request Status and Control Register (IRQ_SC) 8 R/W 00h 4.4.1/63
Register name
Width
(in bits)
Access Reset value
Section/
page
4.4.1 Interrupt Pin Request Status and Control Register (IRQ_SC)
This direct page register includes status and control bits, which are used to configure the IRQ function, report status, and acknowledge IRQ events.
Address:
7Fh base + 0h offset = 7Fh
Bit 7 6 5 4 3 2 1 0
Read 0
Write IRQACK
Reset
0 0 0 0 0 0 0 0
IRQPDD IRQEDG IRQPE
IRQF 0
IRQIE IRQMOD
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NXP Semiconductors 63
IRQ Memory Map and Register Descriptions
IRQ_SC field descriptions
Field Description
7
Reserved
6
IRQPDD
5
IRQEDG
4
IRQPE
This field is reserved. This read-only field is reserved and always has the value 0.
Interrupt Request (IRQ) Pull Device Disable
This read/write control bit is used to disable the internal pullup device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used.
0 IRQ pull device enabled if IRQPE = 1. 1 IRQ pull device disabled if IRQPE = 1.
Interrupt Request (IRQ) Edge Select
This read/write control bit is used to select the polarity of edges or levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is sensitive to both edges and levels or only edges. When the IRQ pin is enabled as the IRQ input and is configured to detect rising edges, the optional pullup resistor is disabled.
0 IRQ is falling edge or falling edge/low-level sensitive. 1 IRQ is rising edge or rising edge/high-level sensitive.
IRQ Pin Enable
This read/write control bit enables the IRQ pin function. When this bit is set the IRQ pin can be used as an interrupt request.
3
IRQF
2
IRQACK
1
IRQIE
0
IRQMOD
0 IRQ pin function is disabled. 1 IRQ pin function is enabled.
IRQ Flag
This read-only status bit indicates when an interrupt request event has occurred.
0 No IRQ request. 1 IRQ event detected.
IRQ Acknowledge
This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF). Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1), IRQF cannot be cleared while the IRQ pin remains at its asserted level.
IRQ Interrupt Enable
This read/write control bit determines whether IRQ events generate an interrupt request.
0 Interrupt request when IRQF set is disabled (use polling). 1 Interrupt requested whenever IRQF = 1.
IRQ Detection Mode
This read/write control bit selects either edge-only detection or edge-and-level detection.
0 IRQ event on falling/rising edges only. 1 IRQ event on falling/rising edges and low/high levels.
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Chapter 5 Clock management

5.1 Clock module

This device has ICS and LPO clock modules. The internal clock source (ICS) module provides several clock source options for this
device. The module contains a frequency-locked loop (FLL) that is controllable by either an internal or external reference clock. The module can select clock from the FLL or bypass the FLL as a source of the MCU system clock. The selected clock source is passed through a reduced bus divider, which allows a lower output clock frequency to be derived.
An internal trimmed 32 kHz is the main clock source for ICS. It also can be used as reference for windowed COP watchdog (WCOP)
An external clock input is available in this device which can be used as the reference of ICS to generate system bus clock and analog-to-digital (ADC) modules.
The low-power oscillator (LPO) module is an on-chip low-power oscillator providing around 20 kHz reference clock to windowed COP watchdog (WCOP).
5.2
These series contain two on-chip clock sources:
NXP Semiconductors 65

System clock distribution

• Internal clock source (ICS) module — The main clock source generator providing bus clock and other reference clocks to core, memory and peripherals
• Low-power oscillator (LPO) module — The on-chip low-power oscillator in PMC module providing 20 kHz reference clock to windowed COP watchdog (WCOP) to meet IEC60730 safety standard.
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MTIM FTM
I2C
CPU
BDC
KBI
FLASH
ACMP
ICS
32 kHz
IRC
ICSIRCLK
IPCDBG
2
N
CLKOUT
System Control
WDOG
BUSREF
1/2
1
ICSBDCCLK
ADC0 ADC1
GDU
~
ICSFFCLK
LP
OC
LK
RAM
TCLK
DIV3
ICSOUTCLK
DIV2
MSTRCLK
BUSCLK
LPO
CRC
HSCLK
CLKIN
CLKIN
PWT0 PWT1
PDB
20 MHz after reset
DIV1
PMC
SCI
20 kHz
PWM
System clock distribution
NOTE
The system clock is bus clock.
NOTE
For this device, the master clock and system/bus clock are the same clock.
The following figure shows a simplified clock connection diagram.
Figure 5-1. System clock distribution diagram
The clock system supplies:
• ICSOUTCLK — This up to 40 MHz clock source is used as the master clock and bus clock and high speed clock that is the reference to CPU and all peripherals. Control bits in the ICS control registers determine which of two clock sources is connected:
• 32 kHz Internal reference clock
• Frequency-locked loop (FLL) output
There are three clocks that are derived from this clock source:
• MSTRCLK — Master clock is the clock source for CPU and RAM and DBG and system/ bus clock
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Chapter 5 Clock management
• BUSCLK — Bus clock is the clock source for all peripherals and flash module
• HSCLK — High speed clock is up to 40 MHz. It can be set to 1:1 bus clock or 2:1 bus clock. It does not support other clock ratio. it can be selected as the clock source to the PWM and PDB
After reset, ICSOUTCLK clock is around 20 MHz.
• ICSLCLK — This clock source is derived from the digitally controlled oscillator (DCO) of the ICS when the ICS is configured to run off of the internal or external reference clock. Development tools can select this internal self-clocked source (20 MHz) to speed up BDC communications in systems where the bus clock is slow.
• ICSIRCLK — This is the internal reference clock and can be selected as the clock source to the WCOP module.
• ICSFFCLK — This generates the fixed frequency clock (FFCLK) after being synchronized to the bus clock. It can be selected as clock source, after being divided by 2, to the FTM and MTIM modules. The frequency of the ICSFFCLK is determined by the setting of the ICS.
• LPOCLK — This clock is generated from an internal low power oscillator (≈20 kHz) that is completely independent of the ICS module. The LPOCLK can be selected as the clock source to the WCOP module.
• TCLK — This is an optional external clock source for the FTM and MTIM and PWT0 and PWT1 modules. The TCLK must be limited to 1/4th frequency of the bus clock for synchronization.
• CLKOUT — This clock is a buffered bus clock to a package pin.
• CLKIN — This is an external clock input from package pins. This clock input cannot be dynamically switched between its inputs (DC - 40 MHz).
5.3

Internal clock source (ICS)

The internal clock source (ICS) module provides clock source options for the MCU. The module contains a frequency-locked loop (FLL) as a clock source that is controllable by an internal or external reference clock. The module can provide this FLL clock or the internal reference clock as a source for the MCU system clock, ICSCLK.
Whichever clock source is chosen, ICSCLK is the output from a bus clock divider (BDIV), which allows a lower clock frequency to be derived.
Key features of the ICS module are:
• Frequency-locked loop (FLL) is trimmable for accuracy
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NXP Semiconductors 67

20 kHz low-power oscillator (LPO)

• Internal or external reference clocks can be used to control the FLL
• Reference divider is provided for external clock
• Internal reference clock has nine trim bits available
• Internal or external reference clocks can be selected as the clock source for the MCU
• Whichever clock is selected as the source can be divided down by 1, 2, 4, 8, 16, 32, 64 or 128
• FLL Engaged Internal mode is automatically selected out of reset
• A constant divide by 2 of the DCO output that can be select as BDC clock.
• Digitally-controlled oscillator (DCO) optimized for 32 MHz to 40 MHz frequency range
• FLL lock detector and external clock monitor
• FLL lock detector with interrupt capability
• External reference clock monitor with reset capability
5.4
20 kHz low-power oscillator (LPO)
The 20 kHz low-power oscillator acts as a standalone low-frequency clock source in all run, wait, and stop modes.
5.5

Peripheral clock gating

This device includes a clock gating system to manage the bus clock sources to the individual peripherals. Using this system, the user can enable or disable the bus clock to each of the peripherals at the clock source, eliminating unnecessary clocks to peripherals that are not in use, thereby reducing the overall run and wait mode currents.
For lowest possible run wait currents, user software must disable the clock source to any peripheral not in use. The actual clock will be enabled or disabled immediately following the write to the System Clock Gating Control registers (SIM_SCGCx, x=1, 2, 3). Any peripheral with a gated clock cannot be used unless its clock is enabled. Writing to the registers of a peripheral with a disabled clock has no effect.
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Chapter 5 Clock management
Note
User software must disable the peripheral before disabling the clocks to the peripheral. When clocks to a peripheral are re­enabled, the peripheral registers need to be re-initialized by user software.
In stop modes, the bus clock is disabled for all gated peripherals, regardless of the setting in SIM_SCGCx (x=1,2,3) registers.
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Peripheral clock gating
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70 NXP Semiconductors
Chapter 6 Power Management

6.1 Introduction

The operating modes of the device are described in this chapter. Entry into each mode, exit from each mode, and functionality while in each of the modes are described.
6.2
These MCUs feature the following power modes:
6.2.1

Features

• Run mode
• Wait mode
• CPU shuts down to conserve power
• Bus clocks are running
• Full voltage regulation is maintained
• Stop modes
• System clocks stopped; PMC is powered with voltage regulator in standby
• all internal circuits powered for fast recovery

Run mode

This is the normal operating mode. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at 0xFFFE: 0xFFFF after reset. The power supply is fully regulating and all peripherals can be active in run mode.
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Features

6.2.2 Wait mode

Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU enters a low-power state in which it is not clocked. The CCR [I] is cleared when the CPU enters the wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine.
While the MCU is in wait mode, there are some restrictions on which background debug commands can be used. Only the BACKGROUND command and memory-access-with­status commands are available when the MCU is in wait mode. The memory-access-with­status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from wait mode and enter active background mode.
6.2.3

Stop mode

To enter stop, the user must execute a STOP instruction with stop mode enabled (SIM_SOPT1[STOPE] = 1). The ICS enters its standby state, as does the voltage regulator and the ADC. The states of all of the internal registers and logic, as well as the RAM content, are maintained. The I/O pin states are not latched at the pin. Instead they are maintained by virtue of the states of the internal logic driving the pins being maintained.
Exit from stop is done by asserting reset or through an interrupt. The interrupt include the asynchronous interrupt from the IRQ or KBI pins or ADC, CMP, I2C, SCI.
If stop is exited by means of the
RESET pin, then the MCU will be reset and operation will resume after taking the reset vector. Exit by means of an asynchronous interrupt or the real-time interrupt will result in the MCU taking the appropriate interrupt vector.
Both low voltage detection and low reset are disabled in stop mode.
6.2.4

Active BDM enabled in stop mode

Entry into the active background mode from run mode is enabled if the BDC_SCR[ENBDM] bit is set. This register is described in the development support. If BDC_SCR[ENBDM] is set when the CPU executes a STOP instruction, the system
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Chapter 6 Power Management
clocks to the background debug logic remain active when the MCU enters stop mode, so background debug communication is still possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation.
Most background commands are not available in stop mode. The memory-access-with­status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the BDC_SCR[ENBDM] bit is set. After entering background debug mode, all background commands are available.
6.2.5

Power modes behaviors

Executing the WAIT or STOP command puts the MCU in a low power consumption mode for standby situations. The system integration module (SIM) holds the CPU in a non-clocked state. The operation of each of these modes is described in the following subsections. Both STOP and WAIT clear the CCR [I], allowing interrupt to occur. The following table shows the low power mode behaviors.
Table 6-1. Low power mode behavior
Mode Run Wait Stop
PMC Full regulation Full regulation Loose regulation
ICS On On Standby
LPO On On Optional On
CPU On Standby Standby
Flash On On Standby
RAM On Standby Standby ADC On On Optional on CMP On On Optional on
I/O On On States held
SCI / I2C On On Standby
FTM / PWT / PWM / MTIM On On Standby
WCOP On On Optional on
DBG On On Standby
IPC On On Standby
LVD On On Standby
GDU On On Standby
PDB On On Standby
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Bandgap reference

6.3 Bandgap reference
This device includes an on-chip bandgap reference (≈1.2 V) connected to ADC channels. The bandgap reference voltage does not drop under the full operating voltage even when the operating voltage is falling. This reference voltage acts as an ideal reference voltage for accurate measurements.
This device also includes a high accuracy voltage reference VREFH (~4.2 V). This reference provides high accuracy reference to ADC and 6-bit DAC inside CMP.
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Chapter 7 Signal multiplexing and signal descriptions

7.1 Introduction

To optimize functionality in small packages, pins have several functions available via signal multiplexing. Information found here illustrates which of this device's signals are multiplexed on which external pin.
The Port Control block controls which signal is present on the external pin. Refer to that chapter to find which register controls the operation of a specific pin.
7.2
The reset state and read/write characteristics of the fields within the PORTx_PCRn registers is summarized in the table below.
7.3
1. A given peripheral function must be assigned to a maximum of one package pin. Do
2. To ensure the best signal timing for a given peripheral's interface, choose the pins in

Port control and interrupt module features

• 32-pin ports
NOTE
Not all pins are available on the device. See the following section for details.

Signal multiplexing constraints

not program the same function to more than one pin.
closest proximity to each other.
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NXP Semiconductors 75

Pinout

7.4
Pinout

7.4.1 Signal multiplexing and pin assignments

The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin.
24 QFN Pin Name Default/ALT0 ALT1 ALT2 ALT3
1 PTB5 PWM_WL PTB5 2 PWM_UH PWM_UH 3 PWM_VH PWM_VH 4 PWM_WH PWM_WH 5 VCLAMP VCLAMP 6 VDD VDD 7 VDDX VDDX 8 VSS VSS 9 PTB6/
RESET_b
10 PTC0 CMP_REF/
11 PTB7/
BKGD/ MS
12 PTA7 PWT1 TX XB_OUT1 PTA7/
13 PTA6 PWT0 RX XB_IN1 PTA6/
14 PTA5 TX SDA XB_OUT0 PTA5/
15 PTA4 RX SCL XB_IN0 PTA4/
16 PTA3 AMP1_M/
17 PTA2 AMP1_P/
18 PTA1 AMP0_M/
19 PTA0 AMP0_P/
RESET_b TCLK PTB6
PWM_FAULT0 CLK_IN PTC0
VREFH BKGD/
MS
CLKOUT XB_OUT1 PTA3/
ADC1AD1
XB_IN1 XB_OUT0 PTA2/ CMP2/ ADC1AD0
XB_OUT0 XB_IN1 PTA1/ CMP1/ ADC0AD1
CLK_IN XB_IN0 PTA0/ CMP0/ ADC0AD0
CLKOUT PTB7
KBI7
KBI6
KBI5
KBI4
KBI3
KBI2
KBI1
KBI0
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Chapter 7 Signal multiplexing and signal descriptions
24 QFN Pin Name Default/ALT0 ALT1 ALT2 ALT3
20 PTB0 GDU_CMP0/
ADC0AD2/ ADC1AD2
21 PTB1 GDU_CMP1/
ADC0AD3/ ADC1AD3
22 PTB2 GDU_CMP2/
ADC0AD4/ ADC1AD4
23 PTB3 PWM_UL PTB3 24 PTB4 PWM_VL PTB4
PTB0
PTB1
PTB2

7.4.2 Signal description table

Table 7-1. Pin signal description
24
QFN
1 PWM_WL PWM PWM5 0–5 Default O Internally
2 PWM_UH PWM PWM0 0–18 Default O Internally
3 PWM_VH PWM PWM2 0–18 Default O Internally
4 PWM_WH PWM PWM4 0–18 Default O Internally
5 VCALMP GDU V
6 VDD All VDD 4.5–18 Default S Supply Power supplies 4.5–18 V 7 VDDX PMC VDDX 0–5 Default S 5 V
8 VSS All VSS 0 Default S Supply Ground 9 RESET_b All RESET 0–5 Default I Reset,
Chip
signal
name
PTB5 PORT PTB5 ALT3 I/O This GPIO pin can be
Module Module
signal name
o_clamp
Operating
voltage
range (V)
0–13 Default S Floating 5
Table continues on the next page...
Alt
function
Type1State
during
reset
pull to low
Pull to High
Pull to High
Pull to High
V regulator
output
regulator
output
internal
Signal description
PWM output 5 for driving N­MOSFET
individually programmed as an input or output pin.
PWM output 0 for driving P­MOSFET
PWM output 2 for driving P­MOSFET
PWM output 2 for driving P­MOSFET
Floating 5 V regulator for PMOS Vgs clamp. It outputs 5 V below VDD. Recommend to connect 1 µF low ESR ceramic capacitor, such as X7R capacitor between VDD and this pin to stabilize the voltage regulator output required for proper device operation.
Connect a 4.7 µF or greater bypass capacitor between this pin and VSS to stabilize the voltage regulator output required for proper device operation.
A direct hardware reset on the processor. When RESET is
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NXP Semiconductors 77
Pinout
Table 7-1. Pin signal description (continued)
24
QFN
10 CMP_REF/
11 BKGD/MS Core BKGD/MS 0–5 Default I/O BKGD/MS Background / Mode Select
12 PWT1 PWT PWT1IN0 0–5 Default I Tri-State Input 0 of PWT1
Chip
signal
name
TCLK MTIM TCLK ALT2 I An optional external clock
PTB6 PORT PTB6 ALT3 I/O This GPIO pin can be
VREFH
PWM_FAU
LT0
CLK_IN ALT2 I An optional external clock
PTC0 PORT PTC0 ALT3 I/O This GPIO pin can be
CLKOUT SIM CLKOUT ALT2 O A buffered bus clock output
PTB7 PORT PTB7 ALT3 O This GPIO pin is an output pin
TX SCI TxD ALT1 I/O SCI transmit data output
XB_OUT1 XBAR XBAR_OUT1 ALT2 O Crossbar module output 1
PTA7/ KBI7 PORT/KBIPTA7/KBIP7 ALT3 I/O This GPIO pin can be
Module Module
signal name
PWM FAULT0 ALT1 I PWM fault input is used for
Operating
voltage
range (V)
0–5 Default S Input CMP_REF: Common input of
Alt
function
Type1State
during
reset
pullup
enabled
Signal description
asserted low, the device is initialized and placed in the reset state. A Schmitt-trigger input is used for noise immunity.
source for the FTM, MTIM, PWT0 and PWT1 modules. The TCLK must be limited to 1/4th frequency of the bus clock for synchronization.
individually programmed as an input or output pin.
GDU Phase comparator A, B and C; VREFH: On-chip 4.2V Voltage reference output. When this pin is configured as VREFH, Connect a 2.2 µF bypass capacitor between this pin and VSS to stabilize the voltage reference output required for proper device operation.
disabling selected PWM outputs in case where fault conditions originate off-chip
source. This clock input cannot be dynamically switched between its inputs (DC - 40 MHz)
individually programmed as an input or output pin.
only.
individually programmed as an input or output pin with KBI functionality
Table continues on the next page...
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Chapter 7 Signal multiplexing and signal descriptions
Table 7-1. Pin signal description (continued)
24
QFN
Chip
signal
name
Module Module
signal name
Operating
voltage
range (V)
Alt
function
Type1State
during
reset
Signal description
13 PWT0 PWT PWT0IN0 0–5 Default Input Tri-State Input 0 of PWT0
RX SCI RxD ALT1 Input SCI receive data input
XB_IN1 XBAR XBAR_IN1 ALT2 Input Crossbar module input 1
PTA6/ KBI6 PORT/KBIPTA6/KBIP6 ALT3 I/O This GPIO pin can be
individually programmed as an input or output pin with KBI functionality
14 TX SCI TxD 0–5 Default I/O Tri-State SCI transmit data output
SDA I2C SDA ALT1 I/O I2C serial data line
XB_OUT0 XBAR XBAR_OUT 0 ALT2 O Crossbar module output 0
PTA5/KBI5 PORT/KBIPTA5/KBIP5 ALT3 I/O This GPIO pin can be
individually programmed as an input or output pin with KBI functionality
15 RX SCI RxD 0–5 Default I Tri-State SCI receive data input
SCL I2C SCL ALT1 I/O I2C serial clock
XB_IN0 XBAR XBAR_IN 0 ALT2 I Crossbar module input 0
PTA4/ KBI4 PORT/KBIPTA4/KBIP4 ALT3 I/O This GPIO pin can be
individually programmed as an input or output pin with KBI functionality
16 ADC1AD1/
AMP1_M
ADC/
2
GDU
AD1 0–5 Default I Input ADC1AD1: Input to channel 1
of ADC1; AMP0_M: GDU analog
operational amplifier 1 negative input;
CLKOUT ALT1 O A buffered bus clock output
XB_OUT1 XBAR XBAR_OUT 1 ALT2 O Crossbar module output 1
PTA3/ KBI3 PORT/KBIPTA3/KBIP3 ALT3 I/O This GPIO pin can be
individually programmed as an input or output pin with KBI functionality
17 ADC1AD0/
AMP1_P /
CMP2
2
ADC/
GCMP/
CMP
AD0/INP/
Reference
Input 2
0–5 Default I Input ADC1AD0: Input to channel 0
of ADC1; AMP1_P: GDU analog
operational amplifier 1 positive input;
CMP2: Input 2 of comparator;
XB_IN1 XBAR XBAR_IN 1 ALT1 I Crossbar module input 1
XB_OUT0 XBAR XBAR_OUT 0 ALT2 O Crossbar module output 0
PTA2/KBI2 PORT/KBIPTA2/KBIP2 ALT3 I/O This GPIO pin can be
individually programmed as an input or output pin with KBI functionality
Table continues on the next page...
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Pinout
Table 7-1. Pin signal description (continued)
24
QFN
18 ADC0AD1/
Chip
signal
name
AMP0_M /
2
CMP1
Module Module
signal name
ADC/
GCMP/
CMP
AD1/INM/
Reference
input 1
Operating
voltage
range (V)
Alt
function
Type1State
during
reset
Signal description
0–5 Default I Input ADC0AD1: Input to channel 1
of ADC0; AMP0_M: GDU analog
operational amplifier 0 negative input
CMP1: Input 1 of analog comparator;
XB_OUT0 XBAR XBAR_OUT 1 ALT1 O Crossbar module output 0
XB_IN1 XBAR XBAR_IN 1 ALT2 I Crossbar module input 1
PTA1/KB1 PORT/KBIPTA1/KBIP1 ALT3 I/O This GPIO pin can be
individually programmed as an input or output pin with KBI functionality
19 ADC0AD0 /
AMP0_P /
CMP0
2
ADC/
GCMP/
CMP
AD0/INP/
Reference
input 0
0–5 Default I Input ADC0AD0: Input to channel 0
of ADC0; AMP0_P: GDU analog
operational amplifier 0 positive input;
CMP0: Input 0 of analog comparator;
CLK_IN ALT1 I An optional external clock
source. This clock input cannot be dynamically switched between its inputs (DC - 40 MHz)
XB_IN0 XBAR XBAR_IN 0 ALT2 I Crossbar module input 0
PTA0/ KBI0 PORT/KBIPTA0/KBIP0 ALT3 I/O This GPIO pin can be
individually programmed as an input or output pin with KBI functionality
20 ADC0AD2 /
ADC1AD2 /
GDU_CMP
2
0
ADC0/
ADC1/G
DU
AD2/AD2/
CMP0
0–5 Default I Internal pull
down
ADC0AD2: Input to channel 2 of ADC0;
ADC1AD2: Input to channel 2 of ADC1;
GDU_CMP0: GDU phase comparator 0 positive input
PTB0 PORT PTB0 ALT3 I/O This GPIO pin can be
individually programmed as an input or output pin.
21 ADC0AD3 /
ADC1AD3 /
GDU_CMP
2
1
ADC0/
ADC1/G
DU
AD3/AD3/
CMP1
0–5 Default I Internal pull
down
ADC0AD3: Input to channel 3 of ADC0;
ADC1AD3: Input to channel 3 of ADC1;
GDU_CMP1: GDU Phase comparator 1 positive input
Table continues on the next page...
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Chapter 7 Signal multiplexing and signal descriptions
Table 7-1. Pin signal description (continued)
24
QFN
22 ADC0AD4 /
23 PWM_UL PWM PWM1 0–5 Default O Internally
24 PWM_VL PWM PWM3 0–5 Default O Internally
Chip
signal
name
PTB1 PORT PTB1 ALT3 I/O This GPIO pin can be
ADC1AD4 /
GDU_CMP
2
2
PTB2 PORT PTB2 ALT3 I/O This GPIO pin can be
PTB3 PORT PTB3 ALT3 I/O This GPIO pin can be
PTB4 PORT PTB4 ALT3 I/O This GPIO pin can be
Module Module
signal name
ADC0/
ADC1/G
DU
AD4/AD4/
CMP2
Operating
voltage
range (V)
0–5 Default I Internal pull
Alt
function
Type1State
during
Pull to Low
Pull to Low
reset
down
Signal description
individually programmed as an input or output pin.
ADC0AD4: Input to channel 4 of ADC0;
ADC1AD4: Input to channel 4 of ADC1;
GDU_CMP2: GDU Phase comparator 2 positive input
individually programmed as an input or output pin.
PWM output 1 for driving N­MOSFET
individually programmed as an input or output pin.
PWM output 3 for driving N­MOSFET
individually programmed as an input or output pin.
1. S: supply; I: input; O: output; I/O: input/output
2. When used as an analog input, the signal goes to all analog modules, but the glitch during ADC sampling on this pin may interfere with other analog inputs shared on this pin.

7.4.3 Pinout

The following figures show the pinout diagrams for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see Signal multiplexing and pin assignments.
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NXP Semiconductors 81
24
23
22
PTB4
PTB3
PTB2
PTB0
PTA0
21
20
19
PTB1
PTA3
PTA4
16
15
PTA1
PTA2
18
17
PTA5
PTA6
14
13
PTA7
PTB7/BKGD
PTC0
PTB6/RESET_b
12
11
10
9
VSS
8
VDDX
7
VDD
VCLAMP
PWM_WH
PWM_VH
PWM_UH
PTB5
6
5
4
3
2
1
Pinout
Figure 7-1. 24-pin QFN pinout diagram
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Chapter 8
MUXPTA0
PTADD0=0
ALT0 out en ALT1 out en
ALT2 out en
PTADD0=1
ALT0 out data
ALT0 in en ALT1 in en ALT2 in en
ALT1 out data ALT2 out data
PTAD0
Synchronizer & Glitch filter
BUS clock FLTDIV1
FLTDIV2 FLTDIV3
Digital peripheral or CPU read
0 1
0/1/PTAD0
Analog peripheral
PTAPE0 (is ‘0’ when analog or output, ‘1’ when BKGD/RESET)
PTA0
Port Control (PORT)

8.1 Introduction

This device has three sets of I/O ports, which include up to 17 general-purpose I/O pins. To enable the GPIO function, SIM_MUXPTxL/SIM_MUXPTxH (x=A, B, or C)
registers need be adjusted to select ALT3. The pin control register configures the following functions for each pin within the 8-bit
port.
• Out data on selected pins
• In/out direction on selected pins
• Pullup/pulldown enable on selected pins
KBI shares with PTA on ALT3, so PTA function works only when KBI_PE is disabled; The following figure show the structure of normal I/O pin(PTA0 as example).
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Figure 8-1. Normal I/O structure
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Port data and data direction

NOTE
For PTB6/RESET_b pin, output is true open-drain drive.
8.2 Port data and data direction
Reading and writing of parallel I/O is accomplished through the port data registers (PORT_PTxD, x=A, B, or C). The input or output is controlled by the direction registers. Each port pin has an input enable bit and an output enable bit. When PORT_PTxDD[n] = 0 (x=A, B, or C; n=0–7), a read from PORT_PTxD[n] returns the input value of the associated pin; when PORT_PTxDD[n] = 1, a read from PORT_PTxD[n] returns the last value written to the port data register.
NOTE
When a digital peripheral module or system function is selected and enabled on a pin, reads of the port data register still returns the pin value of the associated pin if PORT_PTxDD[n] = 0. When a shared analog function is selected for a pin, all digital pin functions are disabled. A read of the port data register returns a value of 0 for any bits that have shared analog functions enabled.
A write of valid data to a port data register must occur before setting the direction control bit of an associated port pin. This ensures that the pin will not be driven with an incorrect data value.
8.3

Internal pullup/pulldown enable

An internal pullup or pulldown device can be enabled for each port pin by setting the corresponding bit in one of the pullup enable registers (PORT_PTxPE[n], x=A, B, or C, n=0–7). The internal pullup device is disabled if the pin is configured as an output direction, or by selecting any output peripheral functions, or input peripheral function like PWT, regardless of the state of the corresponding pullup enable register bit. The internal pullup device is also disabled if the pin is controlled by an analog function.
If an SDA, SCL, RX, TX, KBI, or TCLK function is selected and enabled on a pin, the pullup configuration for that pin still works. The internal pullup device is enabled when pin select as BKGD/
RESET function.
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1(FLTxxx period) 2(FLTxxx period)
Input high/low width
Pass to
100%
0
Note: FLTxxx is contents in register PORT_IOFLTn (n=0-2).
Chapter 8 Port Control (PORT)
NOTE
When configuring I2C to use "SDA(PTA5) and SCL(PTA4)" pins, and if an application uses internal pullups instead of external pullups, the internal pullups remain present setting when the pins are configured as outputs, but they are automatically disabled to save power when the output values are low.

8.4 Input glitch filter

A filter is implemented for each port pin that is configured as a digital input. It can be used as a simple low-pass filter to filter any glitch that is introduced from the pins of PTx (x=A,B, or C), I2C, PWT, XBI, RESET, and KBI. The glitch width threshold can be adjusted easily by setting registers PORT_IOFLTn (n=0–2) and PORT_FCLKDIV between 1–4096 BUSCLKs (or 1–128 LPOCLKs). This configurable glitch filter can take the place of an on board external analog filter, and greatly improve the EMC performance because any glitch will not be wrongly sampled or ignored.
Setting register PORT_IOFLTn (n=0–2) can configure the filter of the whole port. For example, setting PORT_IOFLT0[FLTA] affects all PTA pins.
Glitches that are shorter than the selected clock period are filtered out; Glitches that are twice more than the selected clock period are filtered out. It passes to internal circuitry.
Figure 8-2. Input glitch filter
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Memory map and register definition

8.5 Memory map and register definition
PORT memory map
Absolute
address
(hex)
0 Port A Data Register (PORT_PTAD) 8 R/W 00h 8.5.1/86 1 Port B Data Register (PORT_PTBD) 8 R/W 00h 8.5.2/87 2 Port C Data Register (PORT_PTCD) 8 R/W 00h 8.5.3/87 3 Port A Direction Register (PORT_PTADD) 8 R/W 00h 8.5.4/88 4 Port B Direction Register (PORT_PTBDD) 8 R/W 00h 8.5.5/89
5 Port C Direction Register (PORT_PTCDD) 8 R/W 00h 8.5.6/89 18E0 Port A Pullup Enable Register (PORT_PTAPE) 8 R/W 00h 8.5.7/90 18E1 Port B Pullup/Pulldown Enable Register (PORT_PTBPE) 8 R/W 00h 8.5.8/91 18E2 Port C Pullup Enable Register (PORT_PTCPE) 8 R/W 00h 8.5.9/91
18E6
18EC Port Clock Division Register (PORT_FCLKDIV) 8 R/W 00h 8.5.11/92 18ED Port Filter Register 0 (PORT_IOFLT0) 8 R/W 00h 8.5.12/93
18EE Port Filter Register 1 (PORT_IOFLT1) 8 R/W 00h 8.5.13/94 18EF Port Filter Register 2 (PORT_IOFLT2) 8 R/W 00h 8.5.14/95
Port B High Drive Strength Selection Register (PORT_PTBHD)
Register name
Width
(in bits)
Access Reset value
8 R/W 00h 8.5.10/92
Section/
page
8.5.1 Port A Data Register (PORT_PTAD)
Reading and writing of parallel I/O is accomplished through this register. When a digital peripheral module or system function is selected and enabled on a pin,
reads of this register still returns the pin value of the associated pin if PORT_PTADD[n] = 0. (n=0-7) When a shared analog function is selected for a pin, all digital pin functions are disabled. A read of this register returns a value of 0 for any bits that have shared analog functions enabled.
A write of valid data to this register must occur before setting the direction control bit of an associated port pin. This ensures that the pin will not be driven with an incorrect data value.
Address:
0h base + 0h offset = 0h
Bit 7 6 5 4 3 2 1 0
Read
Write
Reset
0 0 0 0 0 0 0 0
PTAD
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Chapter 8 Port Control (PORT)
PORT_PTAD field descriptions
Field Description
PTAD Port A Data Register Bits
For port A pins that are configured as inputs, a read returns the logic level on the pin. For port A pins that are configured as outputs, a read returns the last value that was written to this register. Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level
is driven out of the corresponding MCU pin.
8.5.2 Port B Data Register (PORT_PTBD)
Reading and writing of parallel I/O is accomplished through this register. When a digital peripheral module or system function is selected and enabled on a pin,
reads of this register still returns the pin value of the associated pin if PORT_PTBDD[n] = 0 (n=1-7). When a shared analog function is selected for a pin, all digital pin functions are disabled. A read of this register returns a value of 0 for any bits that have shared analog functions enabled.
A write of valid data to this register must occur before setting the direction control bit of an associated port pin. This ensures that the pin will not be driven with an incorrect data value.
Address:
0h base + 1h offset = 1h
Bit 7 6 5 4 3 2 1 0
Read
Write
Reset
0 0 0 0 0 0 0 0
PTBD
PORT_PTBD field descriptions
Field Description
PTBD Port B Data Register Bits
For port B pins that are configured as inputs, a read returns the logic level on the pin. For port B pins that are configured as outputs, a read returns the last value that was written to this register. Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level
is driven out of the corresponding MCU pin.
8.5.3 Port C Data Register (PORT_PTCD)
Reading and writing of parallel I/O is accomplished through this register.
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Memory map and register definition
When a digital peripheral module or system function is selected and enabled on a pin, reads of this register still returns the pin value of the associated pin if PTCDD[0] = 0. When a shared analog function is selected for a pin, all digital pin functions are disabled. A read of this register returns a value of 0 for any bits that have shared analog functions enabled.
A write of valid data to this register must occur before setting the direction control bit of an associated port pin. This ensures that the pin will not be driven with an incorrect data value.
Address: 0h base + 2h offset = 2h
Bit 7 6 5 4 3 2 1 0
Read 0
Write
Reset
0 0 0 0 0 0 0 0
PORT_PTCD field descriptions
Field Description
7–1
Reserved
0
PTCD
This field is reserved. This read-only field is reserved and always has the value 0.
Port C Data Register Bits
For port C pins that are configured as inputs, a read returns the logic level on the pin. For port C pins that are configured as outputs, a read returns the last value that was written to this
register. Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level
is driven out of the corresponding MCU pin.
PTCD
8.5.4 Port A Direction Register (PORT_PTADD)
Address: 0h base + 3h offset = 3h
Bit 7 6 5 4 3 2 1 0
Read
Write
Reset
0 0 0 0 0 0 0 0
PORT_PTADD field descriptions
Field Description
PTADD Port A Direction Register Bits
These bits control the direction of port A pins and what is read for PTAD reads.
0 Pin is configured as general-purpose input, for the GPIO function. 1 Pin is configured as general-purpose output, for the GPIO function.
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PTADD
8.5.5 Port B Direction Register (PORT_PTBDD)
Address: 0h base + 4h offset = 4h
Bit 7 6 5 4 3 2 1 0
Read
Write
Reset
0 0 0 0 0 0 0 0
PORT_PTBDD field descriptions
Field Description
PTBDD Port B Direction Register Bits
These bits control the direction of port B pins and what is read for PTBD reads.
PTBDD
Chapter 8 Port Control (PORT)
NOTE:
0 Pin is configured as general-purpose input, for the GPIO function. 1 Pin is configured as general-purpose output, for the GPIO function.
PTB7 pin is output only.
8.5.6 Port C Direction Register (PORT_PTCDD)
Address: 0h base + 5h offset = 5h
Bit 7 6 5 4 3 2 1 0
Read 0
Write
Reset
Field Description
7–1
Reserved
0
PTCDD
0 0 0 0 0 0 0 0
PORT_PTCDD field descriptions
This field is reserved. This read-only field is reserved and always has the value 0.
Port C Direction Register Bits
These bits control the direction of port C pins and what is read for PTCD reads.
PTCDD
0 Pin is configured as general-purpose input, for the GPIO function. 1 Pin is configured as general-purpose output, for the GPIO function.
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Memory map and register definition
8.5.7 Port A Pullup Enable Register (PORT_PTAPE)
An internal pullup device can be enabled for each port pin by setting the corresponding bit in one of the pullup enable registers (PTAPE[n], n=0-7). The internal pullup device is disabled regardless of the state of the corresponding pullup enable register bit if:
• the pin is configured as an output direction
• by selecting any output peripheral functions
• input peripheral function like PWT
The internal pullup device is also disabled if the pin is controlled by an analog function. If an SDA, SCL, RX, TX, KBI, or TCLK function is selected and enabled on a pin, the
pullup configuration for that pin still works. The internal pullup device is enabled when pin select as BKGD/RESET function.
NOTE
When configuring I2C to use "SDA(PTA5) and SCL(PTA4)" pins, and if an application uses internal pullups instead of external pullups, the internal pullups remain present setting when the pins are configured as outputs, but they are automatically disabled to save power when the output values are low.
Address:
0h base + 18E0h offset = 18E0h
Bit 7 6 5 4 3 2 1 0
Read
Write
Reset
0 0 0 0 0 0 0 0
PORT_PTAPE field descriptions
Field Description
PTAPE Pull Enable for Port A Bit
These bits determines if the internal pullup device is enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and the internal pullup devices are disabled.
0 Internal pullup device disabled for port A bit n. 1 Internal pullup device enabled for port A bit n.
PTAPE
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Chapter 8 Port Control (PORT)
8.5.8 Port B Pullup/Pulldown Enable Register (PORT_PTBPE)
Address: 0h base + 18E1h offset = 18E1h
Bit 7 6 5 4 3 2 1 0
Read
Write
Reset
0 0 0 0 0 0 0 0
PORT_PTBPE field descriptions
Field Description
PTBPE Pull Enable for Port B Bit
These bits determines if the internal pullup/pulldown device is enabled for the associated PTB pin. For port B pins that are configured as outputs, these bits have no effect and the internal pullup/pulldown devices are disabled.
PTBPE
NOTE:
0 Internal pullup//pulldown device disabled for port B bit n. 1 Internal pullup/pulldown device enabled for port B bit n.
PTB0-PTB2 is default pulldown, can not be pullup enabled. PTB3-PTB5 can be pulldown enabled.
8.5.9 Port C Pullup Enable Register (PORT_PTCPE)
Address: 0h base + 18E2h offset = 18E2h
Bit 7 6 5 4 3 2 1 0
Read 0
Write
Reset
Field Description
7–1
Reserved
0
PTCPE
0 0 0 0 0 0 0 0
PORT_PTCPE field descriptions
This field is reserved. This read-only field is reserved and always has the value 0.
Pull Enable for Port C Bit
These bits determines if the internal pullup device is enabled for the associated PTC pin. For port C pins that are configured as outputs, these bits have no effect and the internal pullup devices are disabled.
PTCPE
0 Internal pullup device disabled for port C bit n. 1 Internal pullup device enabled for port C bit n.
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Memory map and register definition
8.5.10 Port B High Drive Strength Selection Register (PORT_PTBHD)
Output extreme high drive strength sink/source current can be enabled by setting the corresponding bit in the PORT_PTBHD register for PTB7. Output extremely high sink/ source current is enabled when they are operated as output. Extreme high drive function is disabled if the pin is configured as an input by the parallel I/O control logic. When configured as any shared peripheral function, extreme high drive function still works on these pins, but only when they are configured as outputs.
Address:
0h base + 18E6h offset = 18E6h
Bit 7 6 5 4 3 2 1 0
Read
Write
Reset
HD7
0 0 0 0 0 0 0 0
0
PORT_PTBHD field descriptions
Field Description
7
HD7
Reserved This field is reserved.
Output High Drive Strength Selection for Port B Bit 7
This bit enables the extreme high drive capability of associated PTB pin.
0 Low output drive enabled for port B bit 7. 1 High output drive enabled for port B bit 7.
This read-only field is reserved and always has the value 0.
8.5.11 Port Clock Division Register (PORT_FCLKDIV)
Configure the high/low level glitch width threshold. Glitches that are shorter than the selected clock width will be filtered out; glitches that are more than twice the selected clock width will not be filtered out (they will pass to the internal circuitry).
Address:
0h base + 18ECh offset = 18ECh
Bit 7 6 5 4 3 2 1 0
Read
Write
Reset
0 0 0 0 0 0 0 0
FLTDIV3 FLTDIV2 FLTDIV1
PORT_FCLKDIV field descriptions
Field Description
7–5
FLTDIV3
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Filter Division Set 3
Table continues on the next page...
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PORT_FCLKDIV field descriptions (continued)
Field Description
Port Filter Division Set 3
000 LPOCLK. 001 LPOCLK/2. 010 LPOCLK/4. 011 LPOCLK/8. 100 LPOCLK/16. 101 LPOCLK/32. 110 LPOCLK/64. 111 LPOCLK/128.
4–2
FLTDIV2
FLTDIV1 Filter Division Set 1
Filter Division Set 2
Port Filter Division Set 2
000 BUSCLK/32. 001 BUSCLK/64. 010 BUSCLK/128. 011 BUSCLK/256. 100 BUSCLK/512. 101 BUSCLK/1024. 110 BUSCLK/2048. 111 BUSCLK/4096.
Chapter 8 Port Control (PORT)
Port Filter Division Set 1
00 BUSCLK/2. 01 BUSCLK/4. 10 BUSCLK/8. 11 BUSCLK/16.
8.5.12 Port Filter Register 0 (PORT_IOFLT0)
This register sets the filters for input from PTA to PTC.
Address:
0h base + 18EDh offset = 18EDh
Bit 7 6 5 4 3 2 1 0
Read 0
Write
Reset
0 0 0 0 0 0 0 0
FLTC FLTB FLTA
PORT_IOFLT0 field descriptions
Field Description
7–6
Reserved
This field is reserved. This read-only field is reserved and always has the value 0.
Table continues on the next page...
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Memory map and register definition
PORT_IOFLT0 field descriptions (continued)
Field Description
5–4
FLTC
3–2
FLTB
FLTA Filter selection for input from PTA
Filter selection for input from PTC
00 BUSCLK 01 FLTDIV1 10 FLTDIV2 11 FLTDIV3
Filter selection for input from PTB
00 BUSCLK 01 FLTDIV1 10 FLTDIV2 11 FLTDIV3
00 BUSCLK 01 FLTDIV1 10 FLTDIV2 11 FLTDIV3
8.5.13 Port Filter Register 1 (PORT_IOFLT1)
This register sets the filters for input.
Address:
0h base + 18EEh offset = 18EEh
Bit 7 6 5 4 3 2 1 0
Read
Write
Reset
FLTKBI FLTRST
0 0 0 0 0 0 0 0
PORT_IOFLT1 field descriptions
Field Description
7–6
FLTKBI
5–4
FLTRST
Reserved This field is reserved.
Filter selection for input from KBI
00 No filter 01 Select FLTDIV1, and will switch to FLTDIV3 in stop mode automatically. 10 Select FLTDIV2, and will switch to FLTDIV3 in stop mode automatically. 11 FLTDIV3
Filter selection for input from RESET
00 No filter. 01 Select FLTDIV1, and will switch to FLTDIV3 in stop mode automatically. 10 Select FLTDIV2, and will switch to FLTDIV3 in stop mode automatically. 11 FLTDIV3
This read-only field is reserved and always has the value 0.
0
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8.5.14 Port Filter Register 2 (PORT_IOFLT2)
This register sets the filters for input from PWT, I2C and XB.
Address: 0h base + 18EFh offset = 18EFh
Bit 7 6 5 4 3 2 1 0
Read
Write
Reset
Field Description
7–6
FLTPWT1
5–4
FLTPWT0
3–2
FLTI2C
FLTXBI Filter Selection For Input from XB_IN0 and XB_IN1
FLTPWT1 FLTPWT0 FLTI2C FLTXBI
0 0 0 0 0 0 0 0
PORT_IOFLT2 field descriptions
Filter Selection For Input from PWT1
00 No filter 01 FLTDIV1 10 FLTDIV2 11 BUSCLK
Filter Selection For Input from PWT0
00 No filter 01 FLTDIV1 10 FLTDIV2 11 BUSCLK
Filter Selection For Input from SDA and SCL.
00 No filter 01 FLTDIV1 10 FLTDIV2 11 BUSCLK
Chapter 8 Port Control (PORT)
00 No filter 01 FLTDIV1 10 FLTDIV2 11 FLTDIV3
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Memory map and register definition
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Chapter 9 System Integration Module (SIM)

9.1 Chip specific windowed COP

The windowed COP (WCOP) module triggers a system reset if it is allowed to time out. The program is expected to periodically reload the COP timer, thereby preventing it from timing out. However, if a fault occurs that causes the program to stop working, the timer will not be reloaded and it will time out. The resulting trigger of a system reset brings the system back from an unresponsive state into a normal state.
After any reset, the WCOP is enabled. If the WCOP is not used in an application, it can be disabled by clearing SIM_SOPT1[COPT].
The WCOP counter is reset by writing 0x55 and 0xAA (in that order) to the address of the SIM_SRS during the selected timeout period. Writes do not affect the data in that field. As soon as the write sequence is complete, the WCOP timeout period is restarted. If the program fails to perform this restart during the timeout period, the microcontroller resets. Also, if any value other than 0x55 or 0xAA is written to the SIM_SRS register, the microcontroller immediately resets.
Windowed watchdog operation is available by setting SIM_SOPT1[COPW], In this mode, writes to service watchdog register SIM_SRS to clear WCOP counter must be in a selected timeout period. A premature write immediately resets the chip.
WCOP has four clock selections: BUSCLK (20 MHz), ICSIRCLK (up to the 32 kHz) and an independent clock source LPOCLK (up to the 20 kHz), CLKIN
Customization:
• Primary clock: BUSCLK (20 MHz)
• Input clock option: BUSCLK (20 MHz); ICSIRCLK (up to the 32 kHz), LPOCLK (up to the 20 kHz), CLKIN (40 MHz)
• WCOP is a part of SIM. Its register set is a subset of SIM registers.
Module Instances:
• One
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System device identification (SDID)

9.2 System device identification (SDID)
This device is hard coded to the value 0x45 in the SIM_SDID registers.

9.3 Universally unique identification (UUID)

This device contains up to 64-bit UUID to identify each device in this family. The intent of UUID is to enable distributed systems to uniquely identify information without significant central coordination.
9.4

Reset and system initialization

Resetting the MCU provides a way to start processing from a set of known initial conditions. During reset, most control and status registers are forced to initial values and the program counter is loaded from the reset vector (0xFFFE:0xFFFF). On-chip peripheral modules are disabled and I/O pins are initially configured as default functions on ALT0. The CCR [I] bit is set to block maskable interrupts so that the user program has a chance to initialize the stack pointer (SP) and system control settings. SP is forced to 0x00FF at reset.
This device has the following sources for reset:
• Power-on reset (POR)
• Low-voltage detect (LVD)
• Windowed COP (COP) timer
• Illegal opcode detect (ILOP)
• Illegal address detect (ILAD)
• Background debug forced reset
• External reset pin (RESET)
• Loss of clock reset (LOC)
• Flash illegal access detect (FILA)
Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status (SRS) register.
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Chapter 9 System Integration Module (SIM)
When the MCU is reset by SIM_SRS[ILAD], the address of illegal address is captured in illegal address register, which is a 16-bit register consisting of SIM_ILLAL and SIM_ILLAH that contains the LSB and MSB 8-bit of the address, respectively.

9.5 Computer operating properly (COP) watchdog

The COP watchdog is used to force a system reset when the application software fails to execute as expected. To prevent a system reset from the COP timer (when it is enabled), application software must reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter before it times out, a system reset is generated to force the system back to an known starting point. After any reset, the COP watchdog is enabled (see System Options Register 1 (SIM_SOPT1) for additional information). If the COP watchdog is not used in an application, it can be disabled by clearing SOPT1[COPT].
The COP counter is reset by writing 0x55 and 0xAA (in this order) to the address of SRS during the selected timeout period. Writes do not affect the data in the read-only SRS. As soon as the write sequence is done, the COP timeout period is restarted. If the program fails to do this during the time-out period, the MCU will reset. Also, if any value other than 0x55 or 0xAA is written to SRS, the MCU is immediately reset. The SOPT1[COPCLKS] selects the clock source used for the COP timer. The clock source options are
• bus clock;
• internal 20 kHz LPO clock source
• 32 kHz ICSIRCLK
• CLK_IN from external pin
With each clock source, there are three associated time-outs controlled by SOPT1[COPT]. The following table summaries the control functions of the SOPT1[COPCLKS] and SOPT1[COPT] bits. The COP watchdog defaults to operation from the 20 kHz LPO clock source and the longest time-out (210 cycles).
When the bus clock source is selected, windowed COP operation is available by setting SOPT1[COPW]. In this mode, writes to the SRS register to clear the COP timer must occur in the last 25% of the selected timeout period. A premature write immediately resets the MCU. When the LPO, ICSIRCLK, or CLK_IN clock source is selected, windowed COP operation is not available. The COP counter is initialized by the first writes to the SOPT1 registers and after any system reset. Subsequent writes to SOPT1 have no effect on COP operation. Even if the application will use the reset default settings of SOPT1[COPT], SOPT1[COPCLKS], and SOPT1[COPW] bits, the user must write to the write-once SOPT1 register during reset initialization to lock in the settings.
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System options

This will prevent accidental changes if the application program gets lost. The write to SRS that services (clears) the COP counter must not be placed in an interrupt service routine (ISR) because the ISR could continue to be executed periodically even if the main application program fails.
If the bus clock source is selected, the COP counter does not increment while the MCU is in background debug mode or while the system is in stop mode. The COP counter resumes when the MCU exits background debug mode or stop mode.
If the 20 kHz LPO, ICSIRCLK, or CLK_IN clock source is selected, the COP counter is re-initialized to zero upon entry to either background debug mode or stop mode and begins from zero upon exit from background debug mode or stop mode.
Table 9-1. Configuration option
Control bits Clock source COP window opens1COP overflow count
SOPT1[COPCLKS] SOPT1[COPT]
N/A 00 N/A N/A COP is disabled
00/10 01 20 kHz LPOCLK /
ICSIRCLK
00/10 10 20 kHz LPOCLK /
ICSIRCLK
00/10 11 20 kHz LPOCLK /
ICSIRCLK 01 01 BUSCLK 6,144 cycles 213 cycles 01 10 BUSCLK 49,152 cycles 216 cycles 01 11 BUSCLK 196,608 cycles 218 cycles 11 01 CLK_IN N/A 213 cycles 11 10 CLK_IN N/A 216 cycles 11 11 CLK_IN N/A 218 cycles
N/A 25 cycles
N/A 28 cycles
N/A 210 cycles
1. Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This column displays the minimum number of clock counts required before the COP timer can be reset when in windowed COP mode (SOPT1[COPW] = 1).
9.6
9.6.1
System options

BKGD pin

After POR, PTB7/CLKOUT/BKGD/MS pin functions as BKGD output. Other functions are selected by SIM_MUXPTBH[MUXPTB7]. This pin is an output only when configured as PTB7.
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100 NXP Semiconductors
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