NXP Semiconductors MC9S08QL8 MCU, MC9S08QL8, MC9S08QL4 Reference Manual
MC9S08QL8 MCU Series Reference Manual
Covers: MC9S08QL8
MC9S08QL4
MC9S08QL8 MCU Series Reference Manual, Rev. 1
MC9S08QL8RM
Rev. 1
07/2018
NXP Semiconductors 1
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://nxp.com
The following revision history table summarizes changes contained in this document.
Revision
Number
0 06/2018 Initial creation.
1 07/2018
Revision
Date
Removed blank pages in the chapters.
Updated PTA and PTC registers.
Description of Changes
© 2018 NXP B.V. All rights reserved.
MC9S08QL8 MCU Series Reference Manual, Rev. 1
2 NXP Semiconductors
List of Chapters
Chapter Number Title Page
Chapter 1 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Chapter 2 Pins and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Chapter 3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Chapter 4 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Chapter 5 Resets, Interrupts, and General System Control . . . . . . . . . . . . . 57
Chapter 6 Parallel Input/Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Chapter 7 Keyboard Interrupt (S08KBIV2) . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Chapter 8 Central Processor Unit (S08CPUV5) . . . . . . . . . . . . . . . . . . . . . . . 95
Chapter 9 Analog Comparator (S08ACMPVLPV1) . . . . . . . . . . . . . . . . . . . . 115
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) . . . . . . . . . . . . . . . 121
Chapter 11 Internal Clock Source (S08ICSV3) . . . . . . . . . . . . . . . . . . . . . . . 149
Chapter 12 Modulo Timer (S08MTIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Chapter 13 Real-Time Counter (S08RTCV1) . . . . . . . . . . . . . . . . . . . . . . . . .173
Chapter 14 Serial Communications Interface (S08SCIV4). . . . . . . . . . . . . . 181
Chapter 15 Timer/Pulse-Width Modulator (S08TPMV3) . . . . . . . . . . . . . . . . 201
Chapter 16 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
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MC9S08QL8 MCU Series Reference Manual, Rev. 1
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Contents
Section Number Title Page
Chapter 1
Device Overview
1.1 Devices in the MC9S08QL8 Series ................................................................................................13
1.2 MCU Block Diagram ......................................................................................................................14
1.3 System Clock Distribution ..............................................................................................................15
Chapter 2
Pins and Connections
2.1 Introduction .....................................................................................................................................17
2.2 Device Pin Assignment ...................................................................................................................17
2.3 Recommended System Connections ...............................................................................................19
2.4 Pin Detail .........................................................................................................................................20
2.4.1 Power Pins ........................................................................................................................20
2.4.2 Oscillator ...........................................................................................................................20
2.4.3 RESET Pin ........................................................................................................................21
2.4.4 Background / Mode Select (BKGD/MS) ..........................................................................21
2.4.5 General-Purpose I/O (GPIO) and Peripheral Ports ...........................................................22
Chapter 3
Modes of Operation
3.1 Introduction .....................................................................................................................................25
3.2 Features ...........................................................................................................................................25
3.3 Run Mode ........................................................................................................................................25
3.3.1 Low Power Run Mode (LPRun) .......................................................................................25
3.4 Active Background Mode ...............................................................................................................26
3.5 Wait Mode .......................................................................................................................................27
3.5.1 Low Power Wait Mode (LPWait) .....................................................................................27
3.6 Stop Modes ......................................................................................................................................28
3.6.1 Stop2 Mode .......................................................................................................................29
3.6.2 Stop3 Mode .......................................................................................................................30
3.6.3 Active BDM Enabled in Stop Mode .................................................................................31
3.6.4 LVD Enabled in Stop Mode ..............................................................................................31
3.6.5 Stop Modes in Low Power Run Mode ..............................................................................31
3.7 Mode Selection ................................................................................................................................31
3.7.1 On-Chip Peripheral Modules in Stop and Low Power Modes .........................................34
Chapter 4
Memory
4.1 MC9S08QL8 Series Memory Map .................................................................................................37
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4.2 Reset and Interrupt Vector Assignments .........................................................................................37
4.3 Register Addresses and Bit Assignments ........................................................................................39
4.4 RAM ................................................................................................................................................43
4.5 Flash ................................................................................................................................................44
4.5.1 Features .............................................................................................................................44
4.5.2 Program and Erase Times .................................................................................................44
4.5.3 Program and Erase Command Execution .........................................................................45
4.5.4 Burst Program Execution ..................................................................................................46
4.5.5 Access Errors ....................................................................................................................48
4.5.6 Flash Block Protection ......................................................................................................48
4.5.7 Vector Redirection ............................................................................................................49
4.6 Security ............................................................................................................................................49
4.7 Flash Registers and Control Bits .....................................................................................................50
4.7.1 Flash Clock Divider Register (FCDIV) ............................................................................51
4.7.2 Flash Options Register (FOPT and NVOPT) ...................................................................52
4.7.3 Flash Configuration Register (FCNFG) ...........................................................................53
4.7.4 Flash Protection Register (FPROT and NVPROT) ..........................................................53
4.7.5 Flash Status Register (FSTAT) ..........................................................................................54
4.7.6 Flash Command Register (FCMD) ...................................................................................55
Chapter 5
Resets, Interrupts, and General System Control
5.1 Introduction .....................................................................................................................................57
5.2 Features ...........................................................................................................................................57
5.3 MCU Reset ......................................................................................................................................57
5.4 Computer Operating Properly (COP) Watchdog .............................................................................58
5.5 Interrupts .........................................................................................................................................59
5.5.1 Interrupt Stack Frame .......................................................................................................60
5.5.2 External Interrupt Request (IRQ) Pin ...............................................................................60
5.5.3 Interrupt Vectors, Sources, and Local Masks ....................................................................61
5.6 Low-Voltage Detect (LVD) System ................................................................................................63
5.6.1 Power-On Reset Operation ...............................................................................................63
5.6.2 Low-Voltage Detection (LVD) Reset Operation ...............................................................63
5.6.3 Low-Voltage Detection (LVD) Interrupt Operation ..........................................................63
5.6.4 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................63
5.7 Peripheral Clock Gating ..................................................................................................................63
5.8 Reset, Interrupt, and System Control Registers and Control Bits ...................................................64
5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................64
5.8.2 System Reset Status Register (SRS) .................................................................................66
5.8.3 System Background Debug Force Reset Register (SBDFR) ............................................67
5.8.4 System Options Register 1 (SOPT1) ................................................................................68
5.8.5 System Options Register 2 (SOPT2) ................................................................................69
5.8.6 System Device Identification Register (SDIDH, SDIDL) ................................................70
5.8.7 System Power Management Status and Control 1 Register (SPMSC1) ...........................71
5.8.8 System Power Management Status and Control 2 Register (SPMSC2) ...........................72
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5.8.9 System Power Management Status and Control 3 Register (SPMSC3) ...........................73
5.8.10 System Clock Gating Control 1 Register (SCGC1) ..........................................................74
5.8.11 System Clock Gating Control 2 Register (SCGC2) ..........................................................75
Chapter 6
Parallel Input/Output Control
6.1 Port Data and Data Direction ..........................................................................................................77
6.2 Pullup, Slew Rate, and Drive Strength ............................................................................................78
6.2.1 Port Internal Pullup Enable ...............................................................................................78
6.2.2 Port Slew Rate Enable ......................................................................................................78
6.2.3 Port Drive Strength Select ................................................................................................78
6.3 Pin Behavior in Stop Modes ............................................................................................................79
6.4 Parallel I/O and Pin Control Registers ............................................................................................79
6.4.1 Port A Registers ................................................................................................................80
6.4.2 Port B Registers ................................................................................................................82
6.4.3 Port C Registers ................................................................................................................85
Chapter 7
Keyboard Interrupt (S08KBIV2)
7.1 Introduction .....................................................................................................................................89
7.1.1 KBI Clock Gating .............................................................................................................89
7.1.2 Features .............................................................................................................................90
7.1.3 Modes of Operation ..........................................................................................................90
7.1.4 Block Diagram ..................................................................................................................90
7.2 External Signal Description ............................................................................................................91
7.3 Register Definition ..........................................................................................................................92
7.3.1 KBI Interrupt Status and Control Register (KBISC) ........................................................92
7.3.2 KBI Interrupt Pin Select Register (KBIPE) ......................................................................93
7.3.3 KBI Interrupt Edge Select Register (KBIES) ...................................................................93
7.4 Functional Description ....................................................................................................................93
7.4.1 Edge Only Sensitivity .......................................................................................................94
7.4.2 Edge and Level Sensitivity ...............................................................................................94
7.4.3 Pullup/Pulldown Resistors ................................................................................................94
7.4.4 Keyboard Interrupt Initialization ......................................................................................94
Chapter 8
Central Processor Unit (S08CPUV5)
8.1 Introduction .....................................................................................................................................95
8.1.1 Features .............................................................................................................................95
8.2 Programmer’s Model and CPU Registers .......................................................................................96
8.2.1 Accumulator (A) ...............................................................................................................96
8.2.2 Index Register (H:X) ........................................................................................................96
8.2.3 Stack Pointer (SP) .............................................................................................................97
8.2.4 Program Counter (PC) ......................................................................................................97
8.2.5 Condition Code Register (CCR) .......................................................................................97
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8.3 Addressing Modes ...........................................................................................................................99
8.3.1 Inherent Addressing Mode (INH) .....................................................................................99
8.3.2 Relative Addressing Mode (REL) .....................................................................................99
8.3.3 Immediate Addressing Mode (IMM) ................................................................................99
8.3.4 Direct Addressing Mode (DIR) .........................................................................................99
8.3.5 Extended Addressing Mode (EXT) .................................................................................100
8.3.6 Indexed Addressing Mode ..............................................................................................100
8.4 Special Operations .........................................................................................................................101
8.4.1 Reset Sequence ...............................................................................................................101
8.4.2 Interrupt Sequence ..........................................................................................................101
8.4.3 Wait Mode Operation ......................................................................................................102
8.4.4 Stop Mode Operation ......................................................................................................102
8.4.5 BGND Instruction ...........................................................................................................103
8.5 HCS08 Instruction Set Summary ..................................................................................................104
Chapter 9
Analog Comparator (S08ACMPVLPV1)
9.1 Introduction ................................................................................................................................... 115
9.1.1 ACMP Configuration Information ..................................................................................115
9.1.2 ACMP/TPM Configuration Information ........................................................................115
9.1.3 ACMP Clock Gating .......................................................................................................115
9.1.4 Stop1 Not Available ........................................................................................................115
9.1.5 Features ...........................................................................................................................116
9.1.6 Modes of Operation ........................................................................................................116
9.1.7 Block Diagram ................................................................................................................116
9.2 External Signal Description ..........................................................................................................117
9.3 Register Definition ........................................................................................................................117
9.3.1 Status and Control Register (ACMPxSC) ......................................................................117
9.4 Functional Description ..................................................................................................................118
9.5 Interrupts .......................................................................................................................................118
Chapter 10
Analog-to-Digital Converter (S08ADC12V1)
10.1 Introduction ...................................................................................................................................121
10.1.1 ADC Clock Gating ..........................................................................................................121
10.1.2 Module Configurations ...................................................................................................121
10.1.3 Features ...........................................................................................................................124
10.1.4 ADC Module Block Diagram .........................................................................................124
10.2 External Signal Description ..........................................................................................................125
10.2.1 Analog Power (V
10.2.2 Analog Ground (V
10.2.3 Voltage Reference High (V
10.2.4 Voltage Reference Low (V
10.2.5 Analog Channel Inputs (ADx) ........................................................................................126
10.3 Register Definition ........................................................................................................................126
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) ....................................................................................................126
DDA
) ...................................................................................................126
SSA
) ...................................................................................126
REFH
) ....................................................................................126
REFL
10.3.1 Status and Control Register 1 (ADCSC1) ......................................................................126
10.3.2 Status and Control Register 2 (ADCSC2) ......................................................................128
10.3.3 Data Result High Register (ADCRH) .............................................................................129
10.3.4 Data Result Low Register (ADCRL) ..............................................................................129
10.3.5 Compare Value High Register (ADCCVH) ....................................................................130
10.3.6 Compare Value Low Register (ADCCVL) .....................................................................130
10.3.7 Configuration Register (ADCCFG) ................................................................................130
10.3.8 Pin Control 1 Register (APCTL1) ..................................................................................132
10.3.9 Pin Control 2 Register (APCTL2) ..................................................................................133
10.3.10Pin Control 3 Register (APCTL3) ..................................................................................134
10.4 Functional Description ..................................................................................................................135
10.4.1 Clock Select and Divide Control ....................................................................................135
10.4.2 Input Select and Pin Control ...........................................................................................136
10.4.3 Hardware Trigger ............................................................................................................136
10.4.4 Conversion Control .........................................................................................................136
10.4.5 Automatic Compare Function .........................................................................................139
10.4.6 MCU Wait Mode Operation ............................................................................................140
10.4.7 MCU Stop3 Mode Operation ..........................................................................................140
10.4.8 MCU Stop2 Mode Operation ..........................................................................................141
10.5 Initialization Information ..............................................................................................................141
10.5.1 ADC Module Initialization Example .............................................................................141
10.6 Application Information ................................................................................................................143
10.6.1 External Pins and Routing ..............................................................................................143
10.6.2 Sources of Error ..............................................................................................................145
Chapter 11
Internal Clock Source (S08ICSV3)
11.1 Introduction ...................................................................................................................................149
11.1.1 DCO Select bits ..............................................................................................................149
11.1.2 Features ...........................................................................................................................150
11.1.3 Block Diagram ................................................................................................................150
11.1.4 Modes of Operation ........................................................................................................151
11.2 External Signal Description ..........................................................................................................152
11.3 Register Definition ........................................................................................................................152
11.3.1 ICS Control Register 1 (ICSC1) .....................................................................................153
11.3.2 ICS Control Register 2 (ICSC2) .....................................................................................154
11.3.3 ICS Trim Register (ICSTRM) .........................................................................................155
11.3.4 ICS Status and Control (ICSSC) .....................................................................................155
11.4 Functional Description ..................................................................................................................157
11.4.1 Operational Modes ..........................................................................................................157
11.4.2 Mode Switching ..............................................................................................................159
11.4.3 Bus Frequency Divider ...................................................................................................160
11.4.4 Low Power Bit Usage .....................................................................................................160
11.4.5 DCO Maximum Frequency with 32.768 kHz Oscillator ................................................160
11.4.6 Internal Reference Clock ................................................................................................160
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11.4.7 External Reference Clock ...............................................................................................161
11.4.8 Fixed Frequency Clock ...................................................................................................161
11.4.9 Local Clock .....................................................................................................................161
Chapter 12
Modulo Timer (S08MTIMV1)
12.1 Introduction ...................................................................................................................................163
12.1.1 MTIM/TPM Configuration Information .........................................................................163
12.1.2 MTIM Clock Gating .......................................................................................................163
12.1.3 Features ...........................................................................................................................164
12.1.4 Modes of Operation ........................................................................................................164
12.1.5 Block Diagram ................................................................................................................165
12.2 External Signal Description ..........................................................................................................165
12.3 Register Definition ........................................................................................................................165
12.3.1 MTIM Status and Control Register (MTIMSC) .............................................................167
12.3.2 MTIM Clock Configuration Register (MTIMCLK) .......................................................168
12.3.3 MTIM Counter Register (MTIMCNT) ...........................................................................169
12.3.4 MTIM Modulo Register (MTIMMOD) ..........................................................................169
12.4 Functional Description ..................................................................................................................170
12.4.1 MTIM Operation Example .............................................................................................171
Chapter 13
Real-Time Counter (S08RTCV1)
13.1 Introduction ...................................................................................................................................173
13.1.1 ADC Hardware Trigger ..................................................................................................173
13.1.2 RTC Clock Sources .........................................................................................................173
13.1.3 RTC Modes of Operation ................................................................................................173
13.1.4 RTC Status after Stop2 Wakeup ......................................................................................173
13.1.5 RTC Clock Gating ..........................................................................................................173
13.1.6 Features ...........................................................................................................................174
13.1.7 Modes of Operation ........................................................................................................174
13.1.8 Block Diagram ................................................................................................................175
13.2 External Signal Description ..........................................................................................................175
13.3 Register Definition ........................................................................................................................175
13.3.1 RTC Status and Control Register (RTCSC) ....................................................................176
13.3.2 RTC Counter Register (RTCCNT) ..................................................................................177
13.3.3 RTC Modulo Register (RTCMOD) ................................................................................177
13.4 Functional Description ..................................................................................................................177
13.4.1 RTC Operation Example .................................................................................................178
13.5 Initialization/Application Information ..........................................................................................179
Chapter 14
Serial Communications Interface (S08SCIV4)
14.1 Introduction ...................................................................................................................................181
14.1.1 SCI Clock Gating ............................................................................................................181
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14.1.2 Features ...........................................................................................................................183
14.1.3 Modes of Operation ........................................................................................................183
14.1.4 Block Diagram ................................................................................................................183
14.2 Register Definition ........................................................................................................................186
14.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL) ..............................................................186
14.2.2 SCI Control Register 1 (SCIC1) .....................................................................................187
14.2.3 SCI Control Register 2 (SCIC2) .....................................................................................188
14.2.4 SCI Status Register 1 (SCIS1) ........................................................................................189
14.2.5 SCI Status Register 2 (SCIS2) ........................................................................................191
14.2.6 SCI Control Register 3 (SCIC3) .....................................................................................192
14.2.7 SCI Data Register (SCID) ...............................................................................................193
14.3 Functional Description ..................................................................................................................193
14.3.1 Baud Rate Generation .....................................................................................................193
14.3.2 Transmitter Functional Description ................................................................................194
14.3.3 Receiver Functional Description ....................................................................................195
14.3.4 Interrupts and Status Flags ..............................................................................................197
14.3.5 Additional SCI Functions ...............................................................................................198
Chapter 15
Timer/Pulse-Width Modulator (S08TPMV3)
15.1 Introduction ...................................................................................................................................201
15.1.1 ACMP/TPM Configuration Information ........................................................................201
15.1.2 TPM External Clock .......................................................................................................201
15.1.3 TPM Pin Repositioning ..................................................................................................201
15.1.4 TPM Clock Gating ..........................................................................................................201
15.1.5 TPMV3 Differences from Previous Versions .................................................................201
15.1.6 Migrating from TPMV1 ..................................................................................................204
15.1.7 Features ...........................................................................................................................205
15.1.8 Modes of Operation ........................................................................................................205
15.1.9 Block Diagram ................................................................................................................206
15.2 Signal Description .........................................................................................................................208
15.2.1 Detailed Signal Descriptions ..........................................................................................208
15.3 Register Definition ........................................................................................................................211
15.3.1 TPM Status and Control Register (TPMxSC) ................................................................211
15.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................212
15.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................213
15.3.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................214
15.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................215
15.4 Functional Description ..................................................................................................................217
15.4.1 Counter ............................................................................................................................217
15.4.2 Channel Mode Selection .................................................................................................218
15.5 Reset Overview .............................................................................................................................221
15.5.1 General ............................................................................................................................221
15.5.2 Description of Reset Operation .......................................................................................222
15.6 Interrupts .......................................................................................................................................222
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15.6.1 General ............................................................................................................................222
15.6.2 Description of Interrupt Operation .................................................................................222
Chapter 16
Development Support
16.1 Introduction ...................................................................................................................................225
16.1.1 Forcing Active Background ............................................................................................225
16.1.2 Module Configuration .....................................................................................................225
16.1.3 Features ...........................................................................................................................226
16.2 Background Debug Controller (BDC) ..........................................................................................226
16.2.1 BKGD Pin Description ...................................................................................................227
16.2.2 Communication Details ..................................................................................................227
16.2.3 BDC Commands .............................................................................................................230
16.2.4 BDC Hardware Breakpoint .............................................................................................233
16.3 Register Definition ........................................................................................................................233
16.3.1 BDC Registers and Control Bits .....................................................................................234
16.3.2 System Background Debug Force Reset Register (SBDFR) ..........................................236
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12 NXP Semiconductors
Chapter 1 Device Overview
The MC9S08QL8 and MC9S08QL4 are members of the cost-effective, low-power, low voltage,
high-performance HCS08 family of 8-bit microcontroller units (MCUs). All MCUs in the family use the
enhanced HCS08 core and are available with a variety of modules, memory sizes, memory types, and
package types.
1.1 Devices in the MC9S08QL8 Series
Table 1-1 summarizes the feature set available in the MC9S08QL8 series of MCUs.
Table 1-1. MC9S08QL8 Series Features by MCU and Package
Feature MC9S08QL8 MC9S08QL4
Flash size (bytes) 8192 4096
RAM size (bytes) 512 256
Pin quantity 20 16 20 16
ACMP yes
ADC channels 8
ADC Resolution 12 12 12 12
ICS yes
MTIM yes
IRQ yes
KBI 8
Port I/O
RTC yes
SCI yes
TPM channels 1
XOSCVLP yes
Package 20-pin TSSOP, 16-pin TSSOP
1
1
Port I/O count includes the output-only PTA4 and the input-only PTA5 pins.
18 14 18 14
t
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NXP Semiconductors 13
Chapter 1 Device Overview
USER FLASH
USER RAM
HCS08 CORE
CPU
BDC
16-BIT TIMER/PWM
MODULE (TPM)
PTB7/EXTAL
PORT B
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
COP
LVD
8-BIT MODULO TIMER
MODULE (MTIM)
PTB6/XTAL
PTB5/TPMCH0
PTB4
PTB3/KBIP7/ADP7
PTB2/KBIP6/ADP6
VOLTAGE REGULATOR
PORT A
PTA1/KBIP1/ADP1/ACMP–
ANALOG COMPARATOR
(ACMP)
LOW-POWER OSCILLATOR
20 MHz INTERNAL CLOCK
SOURCE (ICS)
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSC)
V
SS
V
DD
ANALOG-TO-DIGITAL
CONVERTER (ADC)
12-BIT
PTB1/KBIP5/TxD/ADP5
PTB0/KBIP4/RxD/ADP4
PORT C
REAL-TIME COUNTER
(MC9S08QL8 = 8192 BYTES)
(MC9S08QL4 = 4096 BYTES)
(MC9S08QL8 = 512 BYTES)
(MC9S08QL4 = 256 BYTES)
PTA3/KBIP3/ADP3
PTA2/KBIP2/ADP2
PTA0/KBIP0/TPMCH0/ADP0/ACMP
PTA4/ACMPO/BKGD/MS
PTA5/IRQ/TCLK/RESET
IRQ
pins not available on 16-pin package
(RTC)
PTC3
PTC2
PTC1
PTC0
V
REFL/VSSA
V
REFH/VDDA
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI)
KEYBOARD INTERRUPT
(KBI)
1
V
DDA/VREFH
and V
SSA/VREFL
are double bonded to V
DD
and VSS
1.2 MCU Block Diagram
The block diagram in Figure 1-1 shows the structure of the MC9S08QL8 series MCU.
Figure 1-1. MC9S08QL8 Series Block Diagram
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Chapter 1 Device Overview
TPM MTIM
BDCCPU
ADC
3
FLASH
2
ICS
ICSOUT
2
BUSCLK
ICSLCLK
ICSIRCLK
COP
1
The fixed frequency clock (FFCLK) is internally synchronized to the bus clock and
must not exceed one half of the bus clock frequency. It is XCLK in Chapter 12,
Modulo Timer (S08MTIMV1).
2
Flash has frequency requirements for program and erase operation. See
MC9S08QL8 Series Data Sheet for details.
3
ADC has minimum and maximum frequency requirements. See Chapter 10,
Analog-to-Digital Converter (S08ADC12V1) and MC9S08QL8 Data Sheet for
details.
XOSCVLP
EXTAL
XTAL
FFCLK
1
ICSFFCLK
RTC
1 kHZ
LPO
TCLK
ICSERCLK
2
SYNC*
LPOCLK
OSCOUT
SCI
Table 1-2 provides the functional version of the on-chip modules.
Table 1-2. Module Versions
Module Version
Analog Comparator (ACMPVLP) 1
Analog-to-Digital Converter (ADC12) 1
Central Processor Unit (CPU) 5
Internal Clock Source (ICS) 3
Keyboard Interrupt (KBI) 2
Low Power Oscillator (XOSCVLP) 1
Modulo Timer (MTIM) 1
Real-Time Counter (RTC) 1
Timer Pulse Width Modulator (TPM) 3
Serial Communications Interface (SCI) 4
1.3 System Clock Distribution
Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock
inputs. The clock inputs to the modules indicate the clock(s) that are used to drive the module functions.
All memory mapped registers associated with the modules are clocked with BUSCLK.
Figure 1-2. System Clock Distribution Diagram
NXP Semiconductors 15
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Chapter 1 Device Overview
The ICS supplies the following clock sources:
• ICSOUT — This clock source is used as the CPU clock and is divided by 2 to generate the
peripheral bus clock, BUSCLK. Control bits in the ICS control registers determine which of three
clock sources is connected:
— Internal reference clock
— External reference clock
— Frequency-locked loop (FLL) output
See Chapter 11, Internal Clock Source (S08ICSV3) for details on configuring the ICSOUT clock.
• ICSLCLK — This clock source is derived from the digitally controlled oscillator, DCO, of the ICS
when the ICS is configured to run off of the internal or external reference clock. Development tools
can select this internal self-clocked source (~ 8 MHz) to speed up BDC communications in systems
where the bus clock is slow.
• ICSERCLK — This is the external reference clock and can be selected as the alternate clock for
the ADC module. Section 11.4.7, External Reference Clock explains the ICSERCLK in more
detail. See Chapter 10, Analog-to-Digital Converter (S08ADC12V1) for more information
regarding the use of ICSERCLK with these modules.
• ICSIRCLK — This is the internal reference clock and can be selected as the real-time counter clock
source. Chapter 11, Internal Clock Source (S08ICSV3) explains the ICSIRCLK in more detail. See
Chapter 13, Real-Time Counter (S08RTCV1) for more information regarding the use of
ICSIRCLK.
• ICSFFCLK — This generates the fixed frequency clock (FFCLK) after being synchronized to the
bus clock. It can be selected as clock source for the TPM module and MTIM module. The
frequency of the ICSFFCLK is determined by the settings of the ICS. See Section 11.4.8, Fixed
Frequency Clock in Chapter 11, Internal Clock Source (S08ICSV3) for details.
• LPOCLK — This clock is generated from an internal low power oscillator that is completely
independent of the ICS module. The LPOCLK can be selected as the clock source to the RTC or
COP modules. See Chapter 13, Real-Time Counter (S08RTCV1) and Section 5.4, Computer
Operating Properly (COP) Watchdog for details on using the LPOCLK with these modules.
• OSCOUT — This is the output of the XOSCVLP module and can be selected as the real-time
counter clock source.
• TCLK — TCLK is the optional external clock source for the TPM and MTIM modules. The TCLK
must be limited to 1/4th the frequency of the bus clock for synchronization. See Chapter 15,
Timer/Pulse-Width Modulator (S08TPMV3) and Chapter 12, Modulo Timer (S08MTIMV1) for
more details.
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16 NXP Semiconductors
Chapter 2
1
2
3
4
5
6
7
8
9
10
11
13
14
PTC2
PTB4
PTC3
PTC0
PTB3/KBIP7/ADP7
PTB2/KBIP6/ADP6
PTB1/KBIP5/TxD/ADP5
PTB0/KBIP4/RxD/ADP4
PTA2/KBIP2/ADP2
PTA3/KBIP3/ADP3
PTA1/KBIP1/ADP1/ACMP–
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
PTC1
PTA5/IRQ/TCLK/RESET
PTA4/ACMPO/BKGD/MS
V
DD
V
SS
PTB7/EXTAL
PTB6/XTAL
PTB5/TPMCH0
15
16
17
18
19
20
12
Pins shown in bold type are lost in the next lower pin count package.
Pins and Connections
2.1 Introduction
This chapter describes signals that connect to package pins. It includes pinout diagrams, a signal properties
table, and a detailed signal discussion.
2.2 Device Pin Assignment
Figure 2-1 and Figure 2-2 shows the pin assignments in the packages for the MC9S08QL8 series devices.
Figure 2-1. MC9S08QL8 Series in 20-Pin TSSOP Package
MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 17
Chapter 2 Pins and Connections
1
2
3
4
5
6
7
8
9
10
11
13
14
PTB4
PTB3/KBIP7/ADP7
PTB2/KBIP6/ADP6
PTB1/KBIP5/TxD/ADP5
PTB0/KBIP4/RxD/ADP4
PTA2/KBIP2/ADP2
PTA3/KBIP3/ADP3
PTA1/KBIP1/ADP1/ACMP–
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
PTA5/IRQ/TCLK/RESET
PTA4/ACMPO/BKGD/MS
V
DD
V
SS
PTB7/EXTAL
PTB6/XTAL
PTB5/TPMCH0
15
16
12
Figure 2-2. MC9S08QL8 Series in 16-Pin TSSOP Packages
18 NXP Semiconductors
MC9S08QL8 MCU Series Reference Manual, Rev. 1
Chapter 2 Pins and Connections
BKGD/MS
RESET/IRQ
OPTIONAL
MANUAL
RESET
PORT
A
V
DD
BACKGROUND HEADER
C2
C1
X1
R
F
R
S
SYSTEM
POWER
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
PTA1/KBIP1/ADP1/ACMP–
PTA2/KBIP2/ADP2
PTA3/KBIP3/ADP3
PTA4/ACMPO/BKGD/MS
PTA5/IRQ/TCLK/RESET
PORT
B
PTB0/KBIP4/RxD/ADP4
PTB1/KBIP5/TxD/ADP5
PTB2/KBIP6/ADP6
PTB3/KBIP7/ADP7
PTB4
PTB5/TPMCH0
PTB6/XTAL
PTB7/EXTAL
PORT
C
MC9S08QL8
V
DDA/VREFH
V
SSA/VREFL
C
BY
0.1 F
C
BLK
10 F
+
+
OPTIONAL EXTERNAL OSCILLATOR
OPTIONAL
EMC
PROTECTION
V
DD
4.7 k–10 k
0.1F
XTAL
EXTAL
NOTES:
1
V
DDA/VREFH
and V
SSA/VREFL
are tired with VDD and VSS respectively.
2
RESET pin can only be used to reset into user mode, you can not enter BDM using RESET pin. BDM can be entered
by holding MS low during POR or writing a 1 to BDFR in SBDFR with MS low after issuing BDM command.
3
When PTA5 is configured as IRQ, pin has optional internal pullup device.
4
RC filter on RESET/IRQ pin is recommended for noisy environments.
5
When PTA5 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an
internal pullup device.
6
When PTA4 is configured as BKGD, pin becomes bi-directional
7
When using the XOSCVLP module in low range and low power mode, the external components RF, RS, C1 and C2
are not required.
(NOTE 4)
(NOTE 2)
(NOTE 3,5)
(NOTE 6)
(NOTE 7)
3 V
(NOTE 1)
(NOTE 1)
PTC0
PTC1
PTC2
PTC3
2.3 Recommended System Connections
Figure 2-3 shows pin connections that are common to MC9S08QL8 series application systems.
Figure 2-3. Basic System Connections
MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 19
Chapter 2 Pins and Connections
2.4 Pin Detail
This section provides a detailed description of system connections.
2.4.1 Power Pins
VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all
I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides a regulated
lower-voltage source for the CPU and other internal circuitry of the MCU.
Typically, application systems have two separate capacitors across the power pins. In this case, there must
be a bulk electrolytic capacitor, such as a 10-F tantalum capacitor, to provide bulk charge storage for the
overall system and a 0.1-F ceramic bypass capacitor located as near to the MCU power pins as practical
to suppress high-frequency noise.
V
and V
DDA
ADC and ACMP modules.
are the analog power supply pins for the MCU. This voltage source supplies power to the
SSA
The V
for the ADC module. For this MCU, V
pin. For this MCU, V
REFH
and V
pins are the voltage reference high and voltage reference low inputs, respectively
REFL
shares the V
SSA
shares the V
DDA
pin, and they are double bonded to the VSS pin.
REFL
pin and they are double bonded to the VDD
REFH
2.4.2 Oscillator
Immediately after reset, the MCU uses an internally generated clock provided by the internal clock source
(ICS) module. The oscillator can be configured to run in stop2 or stop3 modes. For more information on
the ICS, see Chapter 11, Internal Clock Source (S08ICSV3).
The oscillator (XOSCVLP) in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic
resonator. An external clock source can optionally be connected to the EXTAL input pin.
Refer to Figure 2-3 for the following discussion. RS (when used) and RF must be low-inductance resistors
such as carbon composition resistors. Wire-wound resistors and some metal film resistors have too much
inductance. C1 and C2 normally must be high-quality ceramic capacitors that are specifically designed for
high-frequency applications.
RF provides a bias path to keep the EXTAL input in its linear range during crystal startup; its value is not
generally critical. Typical systems use 1 M to 10 M. Higher values are sensitive to humidity and lower
values reduce gain and (in extreme cases) could prevent startup.
C1 and C2 are typically in the 5 pF to 25 pF range and are chosen to match the requirements of a specific
crystal or resonator. Be sure to consider printed circuit board (PCB) capacitance and MCU pin capacitance
when selecting C1 and C2. The crystal manufacturer typically specifies a load capacitance which is the
series combination of C1 and C2 (which are usually the same size). As a first-order approximation, use
10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL).
When using the oscillator in low range and low gain mode, the external components RS, RF, C1 and C2 are
not required.
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20 NXP Semiconductors
Chapter 2 Pins and Connections
2.4.3 RESET Pin
After a power-on reset (POR), the PTA5/IRQ/TCLK/RESET pin defaults to a general-purpose input port
pin, PTA5. Setting RSTPE in SOPT1 configures the pin to be the RESET pin with an open-drain drive
containing an internal pullup device. Once PTA5 is configured as RESET, the pin will function as RESET
until the next POR or LVD reset. When enabled, the RESET
external source when the pin is driven low.
Internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary.
This pin is normally connected to the standard 6-pin background debug connector so a development
system can directly reset the MCU system. A manual external reset can be added by supplying a simple
switch to ground (pull reset pin low to force a reset).
Whenever any non-POR reset is initiated (whether from an external signal or from an internal system), the
enabled R
ESET pin is driven low for about 34 bus cycles. The reset circuitry decodes the cause of reset
and records it by setting a corresponding bit in the system reset status register (SRS).
NOTE
This pin does not contain a clamp diode to VDD and must not be driven
above VDD.
NOTE
pin can be used to reset the MCU from an
The voltage on the internally pulled up RESET pin when measured will be
below VDD. The internal gates connected to this pin are pulled to VDD. If
the RESET pin is required to drive to a V
level an external pullup must
DD
be used.
NOTE
In EMC-sensitive applications, an external RC filter is recommended on the
RESET pin, if enabled. See Figure 2-3 for an example.
2.4.4 Background / Mode Select (BKGD/MS)
During a power-on-reset (POR) or a background debug force reset (see Section 5.8.3, System Background
Debug Force Reset Register (SBDFR) for more information), the PTA4/ACMPO/BKGD/MS pin
functions as a mode select pin. Immediately after any reset, the pin functions as the background pin and
can be used for background debug communication. When enabled as the BKGD/MS pin (BKGDPE = 1),
an internal pullup device is automatically enabled.
The background debug communication function is enabled when BKGDPE in SOPT1 is set. BKGDPE is
set following any reset of the MCU and must be cleared to use the PTA4/ACMPO/BKGD/MS pin’s
alternative pin functions.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of the
internal reset after a POR, or force a background debug controller (BDC) reset. If a debug system is
connected to the standard 6-pin background debug header, it can hold BKGD/MS low during a POR or
after issuing a background debug force reset. This will force the MCU into active background mode.
MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 21
Chapter 2 Pins and Connections
NOTE
A resistive or capacitive load on the PTA4/ACMPO/BKGD/MS pin could
cause the MCU to enter active background mode on a POR if the pin voltage
rises slower than VDD.
The BKGD/MS pin is used primarily with BDC communications, and features a custom protocol that uses
16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock can run as fast
as the bus clock, so no significant capacitance must be connected to the BKGD/MS pin that could interfere
with background serial communications.
Although the BKGD/MS pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play a minimal role in determining rise and fall
times on the BKGD/MS pin.
2.4.5 General-Purpose I/O (GPIO) and Peripheral Ports
The MC9S08QL8 series of MCUs support up to 16 general-purpose I/O pins, 1 input-only pin, and 1
output-only pin, which are shared with on-chip peripheral functions (timer, ADC, ACMP, etc.). The GPIO
output-only (PTA4/ACMPO/BKGD/MS) and input-only (PTA5/IRQ/TCLK/RESET) pins are
bi-directional when configured as BKGD and RESET, respectively.
When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output,
software can select one of two drive strengths and enable or disable slew rate control. When a port pin is
configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a
pullup device.
PTA5 is a special I/O pin. When the PTA5/IRQ/TCLK/RESET pin is configured as PTA5 input with the
pullup enabled, the voltage observed on the pin will not be pulled to VDD. However, the internal voltage
on the PTA5 node will be at VDD.
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pin’s output buffer. For information about controlling these pins as general-purpose I/O
pins, see Chapter 6, Parallel Input/Output Control.
NOTE
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program must enable on-chip pullup devices or
change the direction of unused or non-bonded pins to outputs so they do not
float.
When using the 16-pin device, the user must either enable on-chip pullup
devices or change the direction of non-bonded PTC3–PTC0 pins to outputs
so the pins do not float.
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22 NXP Semiconductors
Table 2-1. Pin Availability by Package Pin-Count
Chapter 2 Pins and Connections
Pin
Number
<-- Lowest Priority --> Highest
20 16 Port Pin Alt 1 Alt 2 Alt 3 Alt 4
1 1 PTA5 IRQ TCLK RESET
—
2 2 PTA4 ACMPO BKGD MS —
33—— ——V
44—— ——V
DD
SS
5 5 PTB7 — — — EXTAL
6 6 PTB6 — — — XTAL
1
7 7 PTB5 TPMCH0
———
8 8 PTB4 — — — —
9—PTC3— ———
10—PTC2— ———
11—PTC1— ———
12—PTC0— ———
13 9 PTB3 KBIP7 — ADP7 —
14 10 PTB2 KBIP6 — ADP6 —
15 11 PTB1 KBIP5 TxD ADP5 —
16 12 PTB0 KBIP4 RxD ADP4 —
17 13 PTA3 KBIP3 — ADP3 —
18 14 PTA2 KBIP2 — ADP2 —
2
19 15 PTA1 KBIP1 — ADP1
20 16 PTA0 KBIP0 TPMCH0 ADP0
1
TPMCH0 pin can be repositioned at PTB5 using TPMCH0PS in SOPT2,
ACMP–
2
ACMP+
default reset location is PTA0.
2
If ADC and ACMP are enabled, both modules will have access to the pin.
2
2
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NXP Semiconductors 23
Chapter 2 Pins and Connections
MC9S08QL8 MCU Series Reference Manual, Rev. 1
24 NXP Semiconductors
Chapter 3 Modes of Operation
3.1 Introduction
The operating modes of the MC9S08QL8 series are described in this chapter. Entry into each mode, exit
from each mode, and functionality while in each of the modes are described.
3.2 Features
• Active background mode for code development
• Run mode — CPU clocks can be run at full speed and the internal supply is fully regulated.
• LPRUN mode — CPU and peripheral clocks are restricted to 125 kHz at maximum and the internal
voltage regulator is in standby
• Wait mode — CPU shuts down to conserve power; system clocks are running and full regulation
is maintained
• LPWAIT mode — CPU shuts down to conserve power; peripheral clocks are restricted to 125 kHz
in maximum and the internal voltage regulator is in standby
• Stop modes — System clocks are stopped and voltage regulator is in standby
— Stop3 — All internal circuits are powered for fast recovery
— Stop2 — Partial power down of internal circuits, RAM content is retained, I/O states held
3.3 Run Mode
This is the normal operating mode for the MC9S08QL8 series. In this mode, the CPU executes code from
internal memory with execution beginning at the address fetched from memory at 0xFFFE–0xFFFF after
reset.
3.3.1 Low Power Run Mode (LPRun)
In the low power run mode, the on-chip voltage regulator is put into its standby state. This state uses the
minimum power consumption necessary for CPU functionality. Power consumption is most reduced by
disabling the clocks to all unused peripherals by clearing the corresponding bits in the SCGC1 and SCGC2
registers.
Before entering this mode, the following conditions must be met:
• FBELP is the selected clock mode for the ICS.
• The HGO bit in the ICSC2 register is clear.
• The bus frequency is less than 125 kHz.
MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 25
Chapter 3 Modes of Operation
• If enabled, the ADC must be configured to use the asynchronous clock source, ADACK, to meet
the ADC minimum frequency requirements. The bandgap channel cannot be converted in low
power run mode.
• The LVD and LVW must be disabled by clearing either the LVDE or LVDSE bits in the SPMSC1
register.
• Flash programming/erasing is not allowed.
• ACMP option to compare to internal bandgap reference is not allowed in LPRUN and LPWAIT.
Once these conditions are met, low power run mode can be entered by setting the LPR bit in the SPMSC2
register.
To re-enter standard run mode, clear the LPR bit. The LPRS bit in the SPMSC2 register is a read-only
status bit that can be used to determine if the regulator is in full regulation mode or not. When LPRS is ‘0’,
the regulator is in full regulation mode and the MCU can run at full speed in any clock mode.
3.3.1.1 Interrupts in Low Power Run Mode
Low power run mode provides the option to return to full regulation if any interrupt occurs. This is done
by setting the LPWUI bit in the SPMSC2 register. The ICS can then be set for full speed immediately in
the interrupt service routine.
If the LPWUI bit is clear, interrupts will be serviced in low power run mode.
If the LPWUI bit is set, LPR and LPRS bits will be cleared and interrupts will be serviced with the
regulator in full regulation.
3.3.1.2 Resets in Low Power Run Mode
Any reset will exit low power run mode, clear the LPR and LPRS bits, and return the device to normal run
mode.
3.4 Active Background Mode
The active background mode functions are managed through the BDC in the HCS08 core. The BDC
provides the means for analyzing MCU operation during software development.
Active background mode is entered in any of five ways:
• When the BKGD/MS pin is low during POR
• When the BKGD/MS pin is low immediately after issuing a background debug force reset (see
Section 5.8.3, System Background Debug Force Reset Register (SBDFR)).
• When a BACKGROUND command is received through the BKGD/MS pin
• When a BGND instruction is executed
• When encountering a BDC breakpoint
After entering active background mode, the CPU is held in a suspended state while it waits for serial
background commands instead of executing instructions from the user application program.
Background commands are of two types:
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26 NXP Semiconductors
Chapter 3 Modes of Operation
• Non-intrusive commands, defined as commands that can be issued while the user program is
running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run
mode; non-intrusive commands can also be executed when the MCU is in the active background
mode. Non-intrusive commands include:
— Memory access commands
— Memory-access-with-status commands
— BDC register access commands
— The BACKGROUND command
• Active background commands, which can only be executed while the MCU is in active background
mode. Active background commands include commands to:
— Read or write CPU registers
— Trace one user program instruction at a time
— Leave active background mode to return to the user application program (GO)
The active background mode is used to program a bootloader or user application program into the flash
program memory before the MCU is operated in run mode for the first time. When the MC9S08QL8 series
are shipped from the NXP Semiconductors factory, the flash program memory is erased by default unless
specifically noted. As a result, no program can be executed in run mode until the flash memory is initially
programmed. The active background mode can also be used to erase and reprogram the flash memory after
it has been previously programmed.
For additional information about the active background mode, refer to the Chapter 16, Development
Support.
3.5 Wait Mode
Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU
enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the
wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and
resumes processing, beginning with the stacking operations that lead to the interrupt service routine.
While the MCU is in wait mode, there are some restrictions on which background debug commands can
be used. Only the BACKGROUND command and memory-access-with-status commands are available
when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access,
but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND
command can be used to wake the MCU from wait mode and enter active background mode.
3.5.1 Low Power Wait Mode (LPWait)
Low power wait mode is entered by executing a WAIT instruction while the MCU is in low power run
mode. In the low power wait mode, the on-chip voltage regulator remains in its standby state (as in the low
power run mode). This state uses the minimum power consumption necessary for most modules to
maintain functionality. Power consumption is most reduced by disabling the clocks to all unused
peripherals by clearing the corresponding bits in the SCGC register.
The same restrictions on the low power run mode apply to low power wait mode.
MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 27
Chapter 3 Modes of Operation
3.5.1.1 Interrupts in Low Power Wait Mode
If the LPWUI bit is set when the WAIT instruction is executed, then the voltage regulator will return to
full regulation when wait mode is exited. The ICS can be set for full speed immediately in the interrupt
service routine.
If the LPWUI bit is clear when the WAIT instruction is executed, an interrupt will return the device to low
power run mode.
If the LPWUI bit is set when the WAIT instruction is executed, an interrupt will return the device to normal
run mode with full regulation and the LPR and LPRS bits will be cleared.
3.5.1.2 Resets in Low Power Wait Mode
Any reset will exit low power wait mode, clear the LPR and LPRS bits, and return the device to normal
run mode.
3.6 Stop Modes
One of two stop modes (stop2 or stop3) is entered upon execution of a STOP instruction when the STOPE
bit in the system option 1 register (SOPT1) is set. In both stop modes, the bus and CPU clocks are halted.
In stop3 the voltage regulator is in standby. In stop2 the voltage regulator is in partial powerdown. The ICS
module can be configured to leave the reference clocks running. See Chapter 11, Internal Clock Source
(S08ICSV3) for more information.
If the STOPE bit is not set when the CPU executes a STOP instruction, the MCU will not enter either stop
mode and an illegal opcode reset is forced. The stop modes are selected by setting the appropriate bits in
the System Power Management Status and Control 2 Register (SPMSC2).
Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various
conditions. The selected mode is entered following the execution of a STOP instruction.
Table 3-1. Stop Mode Selection
Register SOPT1 BDCSCR SPMSC1 SPMSC2
1
Bit name STOPE ENBDM
0 x x x Stop modes disabled; illegal opcode reset if STOP
1 1 x x Stop3 with BDM enabled
1 0 Both bits must be 1 x Stop3 with voltage regulator active
1 0 Either bit a 0 0 Stop3
1 0 Either bit a 0 1 Stop2
1
ENBDM is located in the BDCSCR which is accessible only through BDC commands, see Chapter 16, Development
Support.
2
When in stop3 mode with BDM enabled, The S
LVD E LVD SE PP DC
will be near R
IDD
instruction executed
levels because internal clocks are enabled.
IDD
Stop Mode
2
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28 NXP Semiconductors
Chapter 3 Modes of Operation
3.6.1 Stop2 Mode
Stop2 mode is entered by executing a STOP instruction under the conditions as shown in Tabl e 3-1. Most
of the internal circuitry of the MCU is powered off in stop2 with the exception of the RAM and optionally
the RTC and low power oscillator. Upon entering stop2, all I/O pin control signals are latched so that the
pins retain their states during stop2.
Exit from stop2 is performed by asserting the wakeup pin (PTA5/IRQ/TCLK/RESET) on the MCU.
NOTE
PTA5/IRQ/TCLK/RESET is an active low wakeup. To avoid an immediate
exit from stop 2, either the internal pullup must be enabled prior to
executing a STOP instruction or an external pullup must be connected. If
PTA5/IRQ/TCLK/RESET is not to be used as the wakeup pin, configure it
as PTA5 with the pullup enabled.
In addition, the real-time counter (RTC) can wake the MCU from stop2, if enabled.
Upon wakeup from stop2 mode, the MCU starts up as from a power-on reset (POR):
• All module control and status registers are reset, except for SPMSC1-SPMSC3, RTCSC, RTCCNT
and RTCMOD.
• The LVD reset function is enabled and the MCU remains in the reset state if V
trip point
is below the LVD
DD
• The CPU takes the reset vector
In addition to the above, upon waking from stop2, the PPDF bit in SPMSC2 is set. This flag is used to
direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched
until a 1 is written to PPDACK in SPMSC2.
If using the low power oscillator during stop2, the user must reconfigure the ICSC2 register which contains
oscillator control bits before PPDACK is written.
To maintain I/O states for pins that were configured as GPIO before entering stop2, the user must restore
the contents of the I/O port registers, which have been saved in RAM, to the port registers before writing
to the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the
pins will switch to their reset states when PPDACK is written.
For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that
interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.
3.6.1.1 Stop2 Mode Recovery Time
The stop2 recovery time is defined as the interval from the exit trigger to the first opcode fetch. There are
three main components to this wakeup time: the voltage regulator recovery time, the clock source start up
time, and the reset processing time.
MC9S08QL8 MCU Series Reference Manual, Rev. 1
NXP Semiconductors 29
Chapter 3 Modes of Operation
The voltage regulator recovery time (t
) is provided in the data sheet. This time is not influenced by the
VRR
clock source frequency or VDD and is therefore relatively consistent.
Since exiting from stop2 causes the MCU to wake as if a POR occurred, the standard reset processing will
always occur which takes about 150 ICSOUT cycles after the clock source has started. Therefore, the
equation for stop2 recovery time is
Stop2 recovery time = t
+ clock start up time + 150 ICSOUT cycles. Eqn. 3-1
VRR
Since ICSOUT defaults to FLL output running at 8.4 MHz during a reset, and the FLL takes about 1 ms
to start outputting a clock signal (although it won’t be stable initially) Equation 3-5 simplifies to
Stop2 recovery time = t
+ 1 sec + 17.9 s. Eqn. 3-2
VRR
3.6.2 Stop3 Mode
Stop3 mode is entered by executing a STOP instruction under the conditions shown in Table 3-1. The
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.
Stop3 can be exited by asserting RESET, or by an interrupt from one of the following sources: the RTC,
LVD, LVW, ADC, ACMP, IRQ, SCI or the KBI.
If stop3 is exited by means of the RESET pin, then the MCU is reset and operation will resume after taking
the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the
appropriate interrupt vector.
3.6.2.1 Stop3 Mode Recovery Time
The stop3 recovery time is defined as the interval from the exit trigger to the first opcode fetch. There are
three main components to this wakeup time: the voltage regulator recovery time, the clock source start up
time, and the reset or interrupt processing time.
The voltage regulator recovery time (t
clock source frequency or VDD and is therefore relatively consistent.
When an interrupt is used as the exit trigger, the clock must restart and ICSOUT must oscillate six times
before the interrupt processing begins. The interrupt processing requires 11 bus cycles (22 ICSOUT
cycles) for the stacking and vector fetch. Therefore, the first opcode of the interrupt service routine (ISR)
will begin after
Stop3 recovery time = t
The clock source start up time is dependent on the clock mode selected when the MCU enters stop mode.
When the FLL output is selected as the clock source, the FLL starts up within a microsecond at roughly
the same frequency as before stop mode is entered. Typical start up time for the internal reference is given
in the data sheet. Typical start up times for the crystal oscillator are also given in the data sheet.
Assuming the FLL is the selected clock source upon entering stop3 and the FLL is configured for a
20 MHz ICSOUT frequency, then Equation 3-6 simplifies to
) is provided in the data sheet. This time is not influenced by the
VRR
+ clock start up time + 28 ICSOUT cycles. Eqn. 3-3
VRR
MC9S08QL8 MCU Series Reference Manual, Rev. 1
30 NXP Semiconductors
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