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MC9S08PA4
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NXP Semiconductors MC9S08PA4 Reference Manual

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MC9S08PA4 Reference Manual
Supports: MC9S08PA4
Document Number: MC9S08PA4RM
Rev. 5, 08/2017
MC9S08PA4 Reference Manual, Rev. 5, 08/2017
2 NXP Semiconductors
Contents
Section number Title Page
Device Overview
1.1 Introduction.....................................................................................................................................................................23
1.2 MCU block diagram....................................................................................................................................................... 24
1.3 System clock distribution................................................................................................................................................25
Pins and connections
2.1 Device pin assignment.................................................................................................................................................... 29
2.2 Pin functions................................................................................................................................................................... 30
2.2.1 Power (VDD, VSS)..........................................................................................................................................30
2.2.2 Oscillator (XTAL, EXTAL)............................................................................................................................ 31
2.2.3 External reset pin (RESET) and interrupt pin (IRQ)....................................................................................... 32
2.2.4 Background/mode select (BKGD/MS)............................................................................................................ 33
2.2.5 Port A input/output (I/O) pins (PTA5–PTA0)................................................................................................. 34
2.2.6 Port B input/output (I/O) pins (PTB7–PTB0)..................................................................................................34
2.2.7 Port C input/output (I/O) pins (PTC3–PTC0)..................................................................................................34
2.2.8 True open drain pins (PTB0)........................................................................................................................... 34
2.2.9 High current drive pins (PTB4, PTB5)............................................................................................................ 34
2.3 Peripheral pinouts........................................................................................................................................................... 35
Power management
3.1 Introduction.....................................................................................................................................................................37
3.2 Features...........................................................................................................................................................................37
3.2.1 Run mode......................................................................................................................................................... 37
3.2.2 Wait mode........................................................................................................................................................38
3.2.3 Stop3 mode...................................................................................................................................................... 38
3.2.4 Active BDM enabled in stop3 mode................................................................................................................38
3.2.5 LVD enabled in stop mode.............................................................................................................................. 39
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3.2.6 Power modes behaviors................................................................................................................................... 39
3.3 Low voltage detect (LVD) system..................................................................................................................................40
3.3.1 Power-on reset (POR) operation......................................................................................................................41
3.3.2 LVD reset operation.........................................................................................................................................41
3.3.3 Low-voltage warning (LVW).......................................................................................................................... 41
3.4 Bandgap reference.......................................................................................................................................................... 42
3.5 Power management control bits and registers................................................................................................................ 42
3.5.1 System Power Management Status and Control 1 Register (PMC_SPMSC1)................................................42
3.5.2 System Power Management Status and Control 2 Register (PMC_SPMSC2)................................................44
Memory map
4.1 Memory map...................................................................................................................................................................45
4.2 Reset and interrupt vector assignments...........................................................................................................................46
4.3 Register addresses and bit assignments.......................................................................................................................... 47
4.4 Random-access memory (RAM).................................................................................................................................... 55
4.5 Flash and EEPROM........................................................................................................................................................56
4.5.1 Overview..........................................................................................................................................................56
4.5.2 Function descriptions....................................................................................................................................... 58
4.5.2.1 Modes of operation.......................................................................................................................... 58
4.5.2.2 Flash and EEPROM memory map...................................................................................................58
4.5.2.3 Flash and EEPROM initialization after system reset.......................................................................58
4.5.2.4 Flash and EEPROM command operations.......................................................................................59
4.5.2.5 Flash and EEPROM interrupts.........................................................................................................64
4.5.2.6 Protection......................................................................................................................................... 65
4.5.2.7 Security............................................................................................................................................ 68
4.5.2.8 Flash and EEPROM commands.......................................................................................................70
4.5.2.9 Flash and EEPROM command summary........................................................................................ 72
4.6 Flash and EEPROM registers descriptions.....................................................................................................................86
4.6.1 Flash Clock Divider Register (NVM_FCLKDIV)...........................................................................................86
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4.6.2 Flash Security Register (NVM_FSEC)............................................................................................................87
4.6.3 Flash CCOB Index Register (NVM_FCCOBIX)............................................................................................ 88
4.6.4 Flash Configuration Register (NVM_FCNFG)............................................................................................... 88
4.6.5 Flash Error Configuration Register (NVM_FERCNFG).................................................................................89
4.6.6 Flash Status Register (NVM_FSTAT).............................................................................................................90
4.6.7 Flash Error Status Register (NVM_FERSTAT).............................................................................................. 91
4.6.8 Flash Protection Register (NVM_FPROT)......................................................................................................92
4.6.9 EEPROM Protection Register (NVM_EEPROT)............................................................................................93
4.6.10 Flash Common Command Object Register:High (NVM_FCCOBHI)............................................................ 94
4.6.11 Flash Common Command Object Register: Low (NVM_FCCOBLO)...........................................................95
4.6.12 Flash Option Register (NVM_FOPT)..............................................................................................................95
Interrupt
5.1 Interrupts.........................................................................................................................................................................97
5.1.1 Interrupt stack frame........................................................................................................................................ 98
5.1.2 Interrupt vectors, sources, and local masks......................................................................................................99
5.1.3 Hardware nested interrupt................................................................................................................................101
5.1.3.1 Interrupt priority level register.........................................................................................................103
5.1.3.2 Interrupt priority level comparator set............................................................................................. 104
5.1.3.3 Interrupt priority mask update and restore mechanism....................................................................104
5.1.3.4 Integration and application of the IPC............................................................................................. 105
5.2 IRQ..................................................................................................................................................................................105
5.2.1 Features............................................................................................................................................................ 106
5.2.1.1 Pin configuration options.................................................................................................................106
5.2.1.2 Edge and level sensitivity................................................................................................................ 107
5.3 Interrupt pin request register...........................................................................................................................................107
5.3.1 Interrupt Pin Request Status and Control Register (IRQ_SC).........................................................................108
5.4 Interrupt priority control register.................................................................................................................................... 109
5.4.1 IPC Status and Control Register (IPC_SC)......................................................................................................110
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5.4.2 Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)........................................................................ 111
5.4.3
Interrupt Level Setting Registers n (IPC_ILRSn)............................................................................................111
System control
6.1 System device identification (SDID)..............................................................................................................................113
6.2 Universally unique identification (UUID)......................................................................................................................113
6.3 Reset and system initialization........................................................................................................................................113
6.4 System options................................................................................................................................................................114
6.4.1 BKGD pin enable.............................................................................................................................................114
6.4.2 RESET pin enable............................................................................................................................................114
6.4.3 SCI0 pin reassignment..................................................................................................................................... 114
6.4.4 FTM0 channels pin reassignment.................................................................................................................... 115
6.4.5 FTM1 pin reassignment................................................................................................................................... 115
6.5 System interconnection...................................................................................................................................................115
6.5.1 ACMP output selection....................................................................................................................................115
6.5.2 SCI0 TxD modulation......................................................................................................................................116
6.5.3 SCI0 RxD capture............................................................................................................................................ 116
6.5.4 SCI0 RxD filter................................................................................................................................................ 117
6.5.5 RTC capture..................................................................................................................................................... 117
6.5.6 ADC hardware trigger......................................................................................................................................117
6.6 System Control Registers................................................................................................................................................118
6.6.1 System Reset Status Register (SYS_SRS).......................................................................................................119
6.6.2 System Background Debug Force Reset Register (SYS_SBDFR)..................................................................121
6.6.3 System Device Identification Register: High (SYS_SDIDH)......................................................................... 121
6.6.4 System Device Identification Register: Low (SYS_SDIDL).......................................................................... 122
6.6.5 System Options Register 1 (SYS_SOPT1)...................................................................................................... 122
6.6.6 System Options Register 2 (SYS_SOPT2)...................................................................................................... 124
6.6.7 System Options Register 3 (SYS_SOPT3)...................................................................................................... 125
6.6.8 Illegal Address Register: High (SYS_ILLAH)................................................................................................126
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6.6.9 Illegal Address Register: Low (SYS_ILLAL).................................................................................................126
6.6.10 Universally Unique Identifier Register 1 (SYS_UUID1)................................................................................ 127
6.6.11 Universally Unique Identifier Register 2 (SYS_UUID2)................................................................................ 127
6.6.12 Universally Unique Identifier Register 3 (SYS_UUID3)................................................................................ 128
6.6.13 Universally Unique Identifier Register 4 (SYS_UUID4)................................................................................ 128
6.6.14 Universally Unique Identifier Register 5 (SYS_UUID5)................................................................................ 129
6.6.15 Universally Unique Identifier Register 6 (SYS_UUID6)................................................................................ 129
6.6.16 Universally Unique Identifier Register 7 (SYS_UUID7)................................................................................ 130
6.6.17 Universally Unique Identifier Register 8 (SYS_UUID8)................................................................................ 130
Parallel input/output
7.1 Introduction.....................................................................................................................................................................131
7.2 Port data and data direction.............................................................................................................................................133
7.3 Internal pullup enable..................................................................................................................................................... 133
7.4 Input glitch filter setting..................................................................................................................................................134
7.5 High current drive...........................................................................................................................................................134
7.6 Pin behavior in stop mode...............................................................................................................................................134
7.7 Port data registers............................................................................................................................................................134
7.7.1 Port A Data Register (PORT_PTAD)..............................................................................................................135
7.7.2 Port B Data Register (PORT_PTBD).............................................................................................................. 136
7.7.3 Port C Data Register (PORT_PTCD).............................................................................................................. 136
7.7.4 Port High Drive Enable Register (PORT_HDRVE)........................................................................................137
7.7.5 Port A Output Enable Register (PORT_PTAOE)............................................................................................137
7.7.6 Port B Output Enable Register (PORT_PTBOE)............................................................................................ 138
7.7.7 Port C Output Enable Register (PORT_PTCOE)............................................................................................ 139
7.7.8 Port A Input Enable Register (PORT_PTAIE)................................................................................................140
7.7.9 Port B Input Enable Register (PORT_PTBIE)................................................................................................ 141
7.7.10 Port C Input Enable Register (PORT_PTCIE)................................................................................................ 142
7.7.11 Port Filter Register 0 (PORT_IOFLT0)...........................................................................................................143
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7.7.12 Port Filter Register 2 (PORT_IOFLT2)...........................................................................................................144
7.7.13 Port Clock Division Register (PORT_FCLKDIV).......................................................................................... 145
7.7.14 Port A Pullup Enable Register (PORT_PTAPE)............................................................................................. 146
7.7.15 Port B Pullup Enable Register (PORT_PTBPE)..............................................................................................147
7.7.16 Port C Pullup Enable Register (PORT_PTCPE)..............................................................................................148
Clock management
8.1 Clock module..................................................................................................................................................................151
8.2 Internal clock source (ICS)............................................................................................................................................. 152
8.2.1 Function description.........................................................................................................................................153
8.2.1.1 Bus frequency divider...................................................................................................................... 154
8.2.1.2 Low power bit usage........................................................................................................................154
8.2.1.3 Internal reference clock (ICSIRCLK)..............................................................................................154
8.2.1.4 Fixed frequency clock (ICSFFCLK)................................................................................................155
8.2.1.5 BDC clock........................................................................................................................................156
8.2.2 Modes of operation.......................................................................................................................................... 156
8.2.2.1 FLL engaged internal (FEI)............................................................................................................. 157
8.2.2.2 FLL engaged external (FEE)............................................................................................................158
8.2.2.3 FLL bypassed internal (FBI)............................................................................................................158
8.2.2.4 FLL bypassed internal low power (FBILP)..................................................................................... 158
8.2.2.5 FLL bypassed external (FBE)..........................................................................................................159
8.2.2.6 FLL bypassed external low power (FBELP)................................................................................... 159
8.2.2.7 Stop (STOP).....................................................................................................................................160
8.2.3 FLL lock and clock monitor.............................................................................................................................161
8.2.3.1 FLL clock lock.................................................................................................................................161
8.2.3.2 External reference clock monitor.....................................................................................................161
8.3 Initialization / application information........................................................................................................................... 161
8.3.1 Initializing FEI mode....................................................................................................................................... 162
8.3.2 Initializing FBI mode.......................................................................................................................................162
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8.3.3 Initializing FEE mode...................................................................................................................................... 162
8.3.4 Initializing FBE mode......................................................................................................................................163
8.3.5 External oscillator (OSC).................................................................................................................................163
8.3.5.1 Bypass mode.................................................................................................................................... 164
8.3.5.2 Low-power configuration................................................................................................................ 164
8.3.5.3 High-gain configuration...................................................................................................................165
8.3.5.4 Initializing external oscillator for peripherals..................................................................................165
8.4 1 kHz low-power oscillator (LPO)................................................................................................................................. 166
8.5 Peripheral clock gating................................................................................................................................................... 166
8.6 ICS control registers....................................................................................................................................................... 166
8.6.1 ICS Control Register 1 (ICS_C1).................................................................................................................... 167
8.6.2 ICS Control Register 2 (ICS_C2).................................................................................................................... 168
8.6.3 ICS Control Register 3 (ICS_C3).................................................................................................................... 169
8.6.4 ICS Control Register 4 (ICS_C4).................................................................................................................... 169
8.6.5 ICS Status Register (ICS_S)............................................................................................................................ 170
8.6.6 OSC Status and Control Register (ICS_OSCSC)............................................................................................ 171
8.7 System clock gating control registers............................................................................................................................. 172
8.7.1 System Clock Gating Control 1 Register (SCG_C1).......................................................................................173
8.7.2 System Clock Gating Control 2 Register (SCG_C2).......................................................................................174
8.7.3 System Clock Gating Control 3 Register (SCG_C3).......................................................................................175
8.7.4 System Clock Gating Control 4 Register (SCG_C4).......................................................................................175
Chip configurations
9.1 Introduction.....................................................................................................................................................................177
9.2 Core modules.................................................................................................................................................................. 177
9.2.1 Central processor unit (CPU)...........................................................................................................................177
9.2.2 Debug module (DBG)......................................................................................................................................177
9.3 System modules.............................................................................................................................................................. 178
9.3.1 Watchdog (WDOG)......................................................................................................................................... 178
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9.4 Clock module..................................................................................................................................................................178
9.5 Memory...........................................................................................................................................................................180
9.5.1 Random-access-memory (RAM)..................................................................................................................... 180
9.5.2 Non-volatile memory (NVM).......................................................................................................................... 180
9.6 Power modules................................................................................................................................................................180
9.7 Timers............................................................................................................................................................................. 181
9.7.1 FlexTimer module (FTM)................................................................................................................................181
9.7.1.1 FTM0 interconnection......................................................................................................................182
9.7.1.2 FTM1 interconnection......................................................................................................................183
9.7.2 Real-time counter (RTC)................................................................................................................................. 183
9.8 Communication interfaces.............................................................................................................................................. 185
9.8.1 Serial communications interface (SCI)............................................................................................................185
9.8.1.1 SCI0 infrared functions....................................................................................................................186
9.9 Analog.............................................................................................................................................................................187
9.9.1 Analog-to-digital converter (ADC)..................................................................................................................187
9.9.1.1 ADC channel assignments............................................................................................................... 188
9.9.1.2 Alternate clock................................................................................................................................. 189
9.9.1.3 Hardware trigger.............................................................................................................................. 190
9.9.1.4 Temperature sensor..........................................................................................................................190
9.9.2 Analog comparator (ACMP)............................................................................................................................191
9.9.2.1 ACMP configuration information....................................................................................................192
9.9.2.2 ACMP in stop3 mode.......................................................................................................................193
9.9.2.3 ACMP to FTM configuration information.......................................................................................193
9.9.2.4 ACMP for SCI0 RXD filter............................................................................................................. 193
9.10 Human-machine interfaces HMI.....................................................................................................................................194
9.10.1 Keyboard interrupts (KBI)............................................................................................................................... 194
Chapter 10
Central processor unit
10.1 Introduction.....................................................................................................................................................................197
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10.1.1 Features............................................................................................................................................................ 197
10.2 Programmer's Model and CPU Registers....................................................................................................................... 198
10.2.1 Accumulator (A).............................................................................................................................................. 198
10.2.2 Index Register (H:X)........................................................................................................................................199
10.2.3 Stack Pointer (SP)............................................................................................................................................ 199
10.2.4 Program Counter (PC)..................................................................................................................................... 200
10.2.5 Condition Code Register (CCR)...................................................................................................................... 200
10.3 Addressing Modes.......................................................................................................................................................... 201
10.3.1 Inherent Addressing Mode (INH).................................................................................................................... 202
10.3.2 Relative Addressing Mode (REL)....................................................................................................................202
10.3.3 Immediate Addressing Mode (IMM)............................................................................................................... 202
10.3.4 Direct Addressing Mode (DIR)........................................................................................................................203
10.3.5 Extended Addressing Mode (EXT)..................................................................................................................203
10.3.6 Indexed Addressing Mode............................................................................................................................... 204
10.3.6.1 Indexed, No Offset (IX)...................................................................................................................204
10.3.6.2 Indexed, No Offset with Post Increment (IX+)................................................................................204
10.3.6.3 Indexed, 8-Bit Offset (IX1)..............................................................................................................204
10.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+).......................................................................... 205
10.3.6.5 Indexed, 16-Bit Offset (IX2)............................................................................................................205
10.3.6.6 SP-Relative, 8-Bit Offset (SP1)....................................................................................................... 205
10.3.6.7 SP-Relative, 16-Bit Offset (SP2)..................................................................................................... 206
10.3.7 Memory to memory Addressing Mode............................................................................................................ 206
10.3.7.1 Direct to Direct.................................................................................................................................206
10.3.7.2 Immediate to Direct......................................................................................................................... 206
10.3.7.3 Indexed to Direct, Post Increment....................................................................................................206
10.3.7.4 Direct to Indexed, Post-Increment................................................................................................... 207
10.4 Operation modes............................................................................................................................................................. 207
10.4.1 Stop mode........................................................................................................................................................ 207
10.4.2 Wait mode........................................................................................................................................................ 207
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10.4.3 Background mode............................................................................................................................................ 208
10.4.4 Security mode.................................................................................................................................................. 209
10.5 HCS08 V6 Opcodes........................................................................................................................................................211
10.6 Special Operations.......................................................................................................................................................... 211
10.6.1 Reset Sequence................................................................................................................................................ 211
10.6.2 Interrupt Sequence........................................................................................................................................... 211
10.7 Instruction Set Summary.................................................................................................................................................212
Chapter 11
Keyboard Interrupts (KBI)
11.1 Introduction.....................................................................................................................................................................225
11.1.1 Features............................................................................................................................................................ 225
11.1.2 Modes of Operation......................................................................................................................................... 225
11.1.2.1 KBI in Wait mode............................................................................................................................225
11.1.2.2 KBI in Stop modes...........................................................................................................................226
11.1.2.3 KBI in Active Background mode.....................................................................................................226
11.1.3 Block Diagram................................................................................................................................................. 226
11.2 External signals description............................................................................................................................................ 227
11.3 Register definition...........................................................................................................................................................227
11.4 Memory Map and Registers............................................................................................................................................227
11.4.1
11.4.2
11.4.3
11.5 Functional Description....................................................................................................................................................229
11.5.1 Edge-only sensitivity........................................................................................................................................230
11.5.2 Edge and level sensitivity................................................................................................................................ 230
11.5.3 KBI Pullup Resistor......................................................................................................................................... 230
11.5.4 KBI initialization..............................................................................................................................................230
KBI Status and Control Register (KBIx_SC).................................................................................................. 228
KBIx Pin Enable Register (KBIx_PE).............................................................................................................228
KBIx Edge Select Register (KBIx_ES)........................................................................................................... 229
Chapter 12
FlexTimer Module (FTM)
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12.1 Introduction.....................................................................................................................................................................233
12.1.1 FlexTimer philosophy...................................................................................................................................... 233
12.1.2 Features............................................................................................................................................................ 233
12.1.3 Modes of operation.......................................................................................................................................... 234
12.1.4 Block diagram.................................................................................................................................................. 234
12.2 Signal description............................................................................................................................................................235
12.2.1 EXTCLK — FTM external clock.................................................................................................................... 236
12.2.2 CHn — FTM channel (n) I/O pin.................................................................................................................... 236
12.3 Memory map and register definition...............................................................................................................................236
12.3.1 Module memory map....................................................................................................................................... 236
12.3.2 Register descriptions........................................................................................................................................ 236
12.3.3
12.3.4
12.3.5
12.3.6
12.3.7
12.3.8
12.3.9
12.3.10
12.4 Functional Description....................................................................................................................................................244
12.4.1 Clock Source.................................................................................................................................................... 245
12.4.2 Prescaler........................................................................................................................................................... 246
12.4.3 Counter.............................................................................................................................................................246
Status and Control (FTMx_SC)....................................................................................................................... 238
Counter High (FTMx_CNTH)......................................................................................................................... 239
Counter Low (FTMx_CNTL).......................................................................................................................... 240
Modulo High (FTMx_MODH)........................................................................................................................ 240
Modulo Low (FTMx_MODL)......................................................................................................................... 241
Channel Status and Control (FTMx_CnSC).................................................................................................... 241
Channel Value High (FTMx_CnVH)...............................................................................................................243
Channel Value Low (FTMx_CnVL)................................................................................................................244
12.4.1.1 Counter Clock Source...................................................................................................................... 245
12.4.3.1 Up counting......................................................................................................................................246
12.4.3.2 Up-down counting............................................................................................................................247
12.4.3.3 Free running counter........................................................................................................................ 248
12.4.3.4 Counter reset.................................................................................................................................... 248
12.4.4 Input capture mode...........................................................................................................................................248
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12.4.5 Output compare mode...................................................................................................................................... 249
12.4.6 Edge-aligned PWM (EPWM) mode................................................................................................................ 251
12.4.7 Center-aligned PWM (CPWM) mode..............................................................................................................252
12.4.8 Update of the registers with write buffers........................................................................................................254
12.4.8.1 MODH:L registers........................................................................................................................... 254
12.4.8.2 CnVH:L registers............................................................................................................................. 255
12.4.9 BDM mode.......................................................................................................................................................255
12.5 Reset overview................................................................................................................................................................255
12.6 FTM Interrupts................................................................................................................................................................257
12.6.1 Timer overflow interrupt..................................................................................................................................257
12.6.2 Channel (n) interrupt........................................................................................................................................ 257
Chapter 13
Real-time counter (RTC)
13.1 Introduction.....................................................................................................................................................................259
13.2 Features...........................................................................................................................................................................259
13.2.1 Modes of operation.......................................................................................................................................... 259
13.2.1.1 Wait mode........................................................................................................................................259
13.2.1.2 Stop modes.......................................................................................................................................260
13.2.2 Block diagram.................................................................................................................................................. 260
13.3 Register definition...........................................................................................................................................................260
13.3.1 RTC Status and Control Register 1 (RTC_SC1)............................................................................................. 261
13.3.2 RTC Status and Control Register 2 (RTC_SC2)............................................................................................. 262
13.3.3 RTC Modulo Register: High (RTC_MODH).................................................................................................. 263
13.3.4 RTC Modulo Register: Low (RTC_MODL)................................................................................................... 263
13.3.5 RTC Counter Register: High (RTC_CNTH)................................................................................................... 263
13.3.6 RTC Counter Register: Low (RTC_CNTL).................................................................................................... 264
13.4 Functional description.....................................................................................................................................................264
13.4.1 RTC operation example................................................................................................................................... 265
13.5 Initialization/application information............................................................................................................................. 266
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Chapter 14
Serial communications interface (SCI)
14.1 Introduction.....................................................................................................................................................................269
14.1.1 Features............................................................................................................................................................ 269
14.1.2 Modes of operation.......................................................................................................................................... 269
14.1.3 Block diagram.................................................................................................................................................. 270
14.2 SCI signal descriptions................................................................................................................................................... 272
14.2.1 Detailed signal descriptions............................................................................................................................. 272
14.3 Register definition...........................................................................................................................................................272
14.3.1
14.3.2
14.3.3
14.3.4
14.3.5
14.3.6
14.3.7
14.3.8
14.4 Functional description.....................................................................................................................................................282
14.4.1 Baud rate generation........................................................................................................................................ 283
14.4.2 Transmitter functional description................................................................................................................... 283
14.4.3 Receiver functional description....................................................................................................................... 285
SCI Baud Rate Register: High (SCIx_BDH)................................................................................................... 273
SCI Baud Rate Register: Low (SCIx_BDL).................................................................................................... 274
SCI Control Register 1 (SCIx_C1)...................................................................................................................274
SCI Control Register 2 (SCIx_C2)...................................................................................................................276
SCI Status Register 1 (SCIx_S1)..................................................................................................................... 277
SCI Status Register 2 (SCIx_S2)..................................................................................................................... 279
SCI Control Register 3 (SCIx_C3)...................................................................................................................280
SCI Data Register (SCIx_D)............................................................................................................................282
14.4.2.1 Send break and queued idle............................................................................................................. 284
14.4.3.1 Data sampling technique..................................................................................................................286
14.4.3.2 Receiver wake-up operation.............................................................................................................287
14.4.4 Interrupts and status flags................................................................................................................................ 288
14.4.5 Baud rate tolerance...........................................................................................................................................289
14.4.5.1 Slow data tolerance.......................................................................................................................... 289
14.4.5.2 Fast data tolerance............................................................................................................................291
14.4.6 Additional SCI functions................................................................................................................................. 292
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14.4.6.1 8- and 9-bit data modes....................................................................................................................292
14.4.6.2 Stop mode operation........................................................................................................................ 292
14.4.6.3 Loop mode....................................................................................................................................... 292
14.4.6.4 Single-wire operation.......................................................................................................................293
Chapter 15
Analog-to-digital converter (ADC)
15.1 Introduction.....................................................................................................................................................................295
15.1.1 Features............................................................................................................................................................ 295
15.1.2 Block Diagram................................................................................................................................................. 296
15.2 External Signal Description............................................................................................................................................ 296
15.2.1 Analog Power (VDDA)................................................................................................................................... 297
15.2.2 Analog Ground (VSSA)...................................................................................................................................297
15.2.3 Voltage Reference High (VREFH).................................................................................................................. 297
15.2.4 Voltage Reference Low (VREFL)................................................................................................................... 297
15.2.5 Analog Channel Inputs (ADx)......................................................................................................................... 297
15.3 ADC Control Registers...................................................................................................................................................298
15.3.1 Status and Control Register 1 (ADC_SC1)......................................................................................................298
15.3.2 Status and Control Register 2 (ADC_SC2)......................................................................................................300
15.3.3 Status and Control Register 3 (ADC_SC3)......................................................................................................301
15.3.4 Status and Control Register 4 (ADC_SC4)......................................................................................................302
15.3.5 Conversion Result High Register (ADC_RH)................................................................................................. 303
15.3.6 Conversion Result Low Register (ADC_RL).................................................................................................. 304
15.3.7 Compare Value High Register (ADC_CVH)...................................................................................................305
15.3.8 Compare Value Low Register (ADC_CVL)....................................................................................................305
15.3.9 Pin Control 1 Register (ADC_APCTL1)......................................................................................................... 306
15.4 Functional description.....................................................................................................................................................307
15.4.1 Clock select and divide control........................................................................................................................ 307
15.4.2 Input select and pin control.............................................................................................................................. 308
15.4.3 Hardware trigger.............................................................................................................................................. 308
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16 NXP Semiconductors
Section number Title Page
15.4.4 Conversion control........................................................................................................................................... 309
15.4.4.1 Initiating conversions.......................................................................................................................309
15.4.4.2 Completing conversions...................................................................................................................309
15.4.4.3 Aborting conversions....................................................................................................................... 310
15.4.4.4 Power control................................................................................................................................... 311
15.4.4.5 Sample time and total conversion time............................................................................................311
15.4.5 Automatic compare function............................................................................................................................312
15.4.6 FIFO operation................................................................................................................................................. 313
15.4.7 MCU wait mode operation...............................................................................................................................316
15.4.8 MCU Stop3 mode operation............................................................................................................................ 317
15.4.8.1 Stop3 mode with ADACK disabled.................................................................................................317
15.4.8.2 Stop3 mode with ADACK enabled..................................................................................................317
15.5 Initialization information................................................................................................................................................ 318
15.5.1 ADC module initialization example................................................................................................................ 318
15.5.1.1 Initialization sequence......................................................................................................................318
15.5.1.2 Pseudo-code example.......................................................................................................................319
15.5.2 ADC FIFO module initialization example.......................................................................................................319
15.5.2.1 Pseudo-code example.......................................................................................................................320
15.6 Application information..................................................................................................................................................321
15.6.1 External pins and routing................................................................................................................................. 321
15.6.1.1 Analog supply pins...........................................................................................................................321
15.6.1.2 Analog reference pins...................................................................................................................... 321
15.6.1.3 Analog input pins.............................................................................................................................322
15.6.2 Sources of error................................................................................................................................................ 323
15.6.2.1 Sampling error..................................................................................................................................323
15.6.2.2 Pin leakage error.............................................................................................................................. 323
15.6.2.3 Noise-induced errors........................................................................................................................323
15.6.2.4 Code width and quantization error...................................................................................................324
15.6.2.5 Linearity errors.................................................................................................................................325
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NXP Semiconductors 17
Section number Title Page
15.6.2.6 Code jitter, non-monotonicity, and missing codes...........................................................................326
Chapter 16
Analog comparator (ACMP)
16.1 Introduction.....................................................................................................................................................................327
16.1.1 Features............................................................................................................................................................ 327
16.1.2 Modes of operation.......................................................................................................................................... 327
16.1.2.1 Operation in Wait mode...................................................................................................................328
16.1.2.2 Operation in Stop3 mode................................................................................................................. 328
16.1.2.3 Operation in Debug mode................................................................................................................328
16.1.3 Block diagram.................................................................................................................................................. 328
16.2 External signal description..............................................................................................................................................329
16.3 Memory map and register definition...............................................................................................................................329
16.3.1 ACMP Control and Status Register (ACMP_CS)........................................................................................... 330
16.3.2 ACMP Control Register 0 (ACMP_C0).......................................................................................................... 331
16.3.3 ACMP Control Register 1 (ACMP_C1).......................................................................................................... 331
16.3.4 ACMP Control Register 2 (ACMP_C2).......................................................................................................... 332
16.4 Functional description.....................................................................................................................................................332
16.5 Setup and operation of ACMP........................................................................................................................................333
16.6 Resets..............................................................................................................................................................................334
16.7 Interrupts.........................................................................................................................................................................334
Chapter 17
Watchdog (WDOG)
17.1 Introduction.....................................................................................................................................................................335
17.1.1 Features............................................................................................................................................................ 335
17.1.2 Block diagram.................................................................................................................................................. 336
17.2 Memory map and register definition...............................................................................................................................337
17.2.1 Watchdog Control and Status Register 1 (WDOG_CS1)................................................................................ 337
17.2.2 Watchdog Control and Status Register 2 (WDOG_CS2)................................................................................ 339
17.2.3 Watchdog Counter Register: High (WDOG_CNTH)...................................................................................... 340
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Section number Title Page
17.2.4 Watchdog Counter Register: Low (WDOG_CNTL)....................................................................................... 340
17.2.5 Watchdog Timeout Value Register: High (WDOG_TOVALH)..................................................................... 341
17.2.6 Watchdog Timeout Value Register: Low (WDOG_TOVALL)...................................................................... 341
17.2.7 Watchdog Window Register: High (WDOG_WINH)..................................................................................... 342
17.2.8 Watchdog Window Register: Low (WDOG_WINL)...................................................................................... 342
17.3 Functional description.....................................................................................................................................................343
17.3.1 Watchdog refresh mechanism.......................................................................................................................... 343
17.3.1.1 Window mode..................................................................................................................................344
17.3.1.2 Refreshing the Watchdog.................................................................................................................344
17.3.1.3 Example code: Refreshing the Watchdog........................................................................................345
17.3.2 Configuring the Watchdog...............................................................................................................................345
17.3.2.1 Reconfiguring the Watchdog........................................................................................................... 345
17.3.2.2 Unlocking the Watchdog................................................................................................................. 346
17.3.2.3 Example code: Reconfiguring the Watchdog.................................................................................. 346
17.3.3 Clock source.....................................................................................................................................................346
17.3.4 Using interrupts to delay resets........................................................................................................................ 348
17.3.5 Backup reset..................................................................................................................................................... 348
17.3.6 Functionality in debug and low-power modes................................................................................................. 348
17.3.7 Fast testing of the watchdog.............................................................................................................................349
17.3.7.1 Testing each byte of the counter...................................................................................................... 349
17.3.7.2 Entering user mode.......................................................................................................................... 350
Chapter 18
Development support
18.1 Introduction.....................................................................................................................................................................351
18.1.1 Forcing active background...............................................................................................................................351
18.1.2 Features............................................................................................................................................................ 351
18.2 Background debug controller (BDC)..............................................................................................................................352
18.2.1 BKGD pin description..................................................................................................................................... 353
18.2.2 Communication details.................................................................................................................................... 354
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NXP Semiconductors 19
Section number Title Page
18.2.3 BDC commands............................................................................................................................................... 356
18.2.4 BDC hardware breakpoint............................................................................................................................... 359
18.3 On-chip debug system (DBG)........................................................................................................................................ 359
18.3.1 Comparators A and B.......................................................................................................................................360
18.3.2 Bus capture information and FIFO operation.................................................................................................. 360
18.3.3 Change-of-flow information............................................................................................................................ 361
18.3.4 Tag vs. force breakpoints and triggers............................................................................................................. 362
18.3.5 Trigger modes.................................................................................................................................................. 363
18.3.6 Hardware breakpoints...................................................................................................................................... 364
18.4 Memory map and register description............................................................................................................................ 365
18.4.1 BDC Status and Control Register (BDC_SCR)............................................................................................... 365
18.4.2 BDC Breakpoint Match Register: High (BDC_BKPTH)................................................................................ 367
18.4.3 BDC Breakpoint Register: Low (BDC_BKPTL)............................................................................................ 368
18.4.4 System Background Debug Force Reset Register (BDC_SBDFR).................................................................368
Chapter 19
Debug module (DBG)
19.1 Introduction.....................................................................................................................................................................371
19.1.1 Features............................................................................................................................................................ 371
19.1.2 Modes of operation.......................................................................................................................................... 372
19.1.3 Block diagram.................................................................................................................................................. 372
19.2 Signal description............................................................................................................................................................373
19.3 Memory map and registers..............................................................................................................................................373
19.3.1 Debug Comparator A High Register (DBG_CAH)......................................................................................... 374
19.3.2 Debug Comparator A Low Register (DBG_CAL).......................................................................................... 375
19.3.3 Debug Comparator B High Register (DBG_CBH)..........................................................................................376
19.3.4 Debug Comparator B Low Register (DBG_CBL)...........................................................................................376
19.3.5 Debug Comparator C High Register (DBG_CCH)..........................................................................................377
19.3.6 Debug Comparator C Low Register (DBG_CCL)...........................................................................................378
19.3.7 Debug FIFO High Register (DBG_FH)...........................................................................................................378
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Section number Title Page
19.3.8 Debug FIFO Low Register (DBG_FL)............................................................................................................ 379
19.3.9 Debug Comparator A Extension Register (DBG_CAX)................................................................................. 380
19.3.10 Debug Comparator B Extension Register (DBG_CBX)..................................................................................381
19.3.11 Debug Comparator C Extension Register (DBG_CCX)..................................................................................382
19.3.12 Debug FIFO Extended Information Register (DBG_FX)................................................................................383
19.3.13 Debug Control Register (DBG_C)...................................................................................................................383
19.3.14 Debug Trigger Register (DBG_T)................................................................................................................... 384
19.3.15 Debug Status Register (DBG_S)......................................................................................................................386
19.3.16 Debug Count Status Register (DBG_CNT)..................................................................................................... 387
19.4 Functional description.....................................................................................................................................................388
19.4.1 Comparator.......................................................................................................................................................388
19.4.1.1 RWA and RWAEN in full modes....................................................................................................388
19.4.1.2 Comparator C in loop1 capture mode..............................................................................................388
19.4.2 Breakpoints...................................................................................................................................................... 389
19.4.2.1 Hardware breakpoints...................................................................................................................... 389
19.4.3 Trigger selection.............................................................................................................................................. 390
19.4.4 Trigger break control (TBC)............................................................................................................................ 390
19.4.4.1 Begin- and end-trigger..................................................................................................................... 391
19.4.4.2 Arming the DBG module.................................................................................................................391
19.4.4.3 Trigger modes.................................................................................................................................. 392
19.4.5 FIFO................................................................................................................................................................. 394
19.4.5.1 Storing data in FIFO........................................................................................................................ 395
19.4.5.2 Storing with begin-trigger................................................................................................................395
19.4.5.3 Storing with end-trigger...................................................................................................................395
19.4.5.4 Reading data from FIFO.................................................................................................................. 395
19.4.6 Interrupt priority...............................................................................................................................................396
19.5 Resets..............................................................................................................................................................................397
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22 NXP Semiconductors
Chapter 1 Device Overview

1.1 Introduction

These devices are members of the low-cost, high-performance HCS08 family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 central processor unit and are available with a variety of modules, memory sizes and types, and package types. The following table summarizes the peripheral availability per package type for the devices available.
Table 1-1. Memory and package availability
Feature MC9S08PA4
Flash size (bytes) 4,096
EEPROM size (bytes) 128
RAM size (bytes) 512
SOIC-20 Yes
TSSOP-16 Yes
DFN-8 Yes
Table 1-2. Feature availability
Pin number 20-pin 16-pin 8-pin
Bus frequency (MHz) 20 20 20
IRQ Yes
WDOG Yes
DBG Yes
IPC Yes ICS Yes
XOSC Yes No
RTC Yes SCI0 Yes
ACMP Yes
Table continues on the next page...
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NXP Semiconductors 23

MCU block diagram

Table 1-2. Feature availability (continued)
Pin number 20-pin 16-pin 8-pin
FTM0 channels 2-ch 2-ch 2-ch FTM1 channels 2-ch 2-ch 1-ch
FTM2 channels (internal) 2-ch 2-ch 2-ch
ADC 8 8 4
KBI pins 8 8 4
GPIO 18 14 6
1.2 MCU block diagram
The block diagram below shows the structure of the MCUs.
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24 NXP Semiconductors
2. PTB0 operates as true open drain when working as output.
HCS08 CORE
2-CH FLEX TIMER
MODULE (FTM0)
SYSTEM INTEGRATION
MODULE (SIM)
POWER MANAGEMENT
Port A
WDG
1 kHz OSC LVD
V
SS
V
REFH
V
REFL
V
DDA
V
SSA
IRQ
SERIAL COMMUNICATION
INTERFACE (SCI0)
REAL-TIME CLOCK
(RTC)
EXTAL
XTAL
V
DD
20 MHz INTERNAL CLOCK
SOURCE (ICS)
ANALOG-TO-DIGITAL
CONVERTER(
ADC)
8-CH 12-BIT
BDCCPU
INTERRUPT PRIORITY
ON-CHIP ICE AND
DEBUG MODUE (DBG)
EXTERNAL OSCILLATOR
SOURCE (XOSC)
Port BPort C
USER EEPROM
PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1 PTA2/KBI0P2/FTM0CH0/RxD0/ADP2 PTA3/KBI0P3/FTM0CH1/TxD0/ADP3 PTA4/ACMPO/BKGD/MS PTA5/IRQ
/FTM1CH0/RESET
PTB0/KBI0P4/RxD0/TCLK0/ADP4 PTB1/KBI0P5/TxD0/ADP5 PTB2/KBI0P6/ADP6 PTB3/KBI0P7/TCLK1/ADP7 PTB4/FTM1CH0
3
PTB5/FTM1CH1
3
PTB6/XTAL PTB7/EXTAL
PTC0 PTC1 PTC2 PTC3
USER RAM
CONTROLLER (PMC)
MC9S08PA4 = 128 bytes
USER FLASH
MC9S08PA4 = 4,096 bytes
KEYBOARD INTERRUPT
MC9S08PA4 = 512 bytes
MODULE (KBI0)
2-CH FLEX TIMER
MODULE (FTM1)
ANALOG COMPARATOR
(ACMP)
CONTROLLER(IPC)
1. PTA4/ACMPO/BKGD/MS is an output-only pin when used as port pin.
1
2
3. PTB4 and PTB5 can provide high sink/source current drive.
2-CH FLEX TIMER
MODULE (FTM2 )
Chapter 1 Device Overview
Figure 1-1. MCU block diagram
1.3
These series contain three on-chip clock sources:
NXP Semiconductors 25

System clock distribution

• Internal clock source (ICS) module — The main clock source generator providing bus clock and other reference clocks to peripherals
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ICSLCLK
ICSFFCLK
XTAL EXTAL
WDG
RTC
FTM0
FTM1
ADC
SCI0
CPU BDCFLASH
ACMP
RAM
LPOCLK
ICS
OSC
OSCOUT
1-kHz
LPO
ICSIRCLK
IPCDBG
KBI0
TCLK1
TCLK0
ICSCLK (~8 MHz after reset)
1/2
FTM2
System clock distribution
• External oscillator (XOSC) module — The external oscillator providing reference clock to internal clock source (ICS), the real-time clock counter clock module (RTC) and other MCU sub-systems.
• Low-power oscillator (LPO) module — The on-chip low-power oscillator providing 1 kHz reference clock to RTC and watchdog (WDOG).
NOTE
For this device, the system clock is the bus clock.
The following figure shows a simplified clock connection diagram.
Figure 1-2. System clock distribution diagram
The clock system supplies:
• ICSCLK(BUS) — This up to 20 MHz clock source is used as the bus clock that is the reference to CPU and all peripherals. Control bits in the ICS control registers determine which of the clock sources is connected:
• Internal reference clock
• External reference clock
• Frequency-locked loop (FLL) output
• ICSLCLK — This clock source is derived from the digitally controlled oscillator (DCO) of the ICS when the ICS is configured to run off of the internal or external reference clock. Development tools can select this internal self-clocked source (8 MHz) to speed up BDC communications in systems where the bus clock is slow.
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Chapter 1 Device Overview
• ICSIRCLK — This is the internal reference clock and can be selected as the clock source to the WDOG module.
• ICSFFCLK — This generates the fixed frequency clock (FFCLK) after being synchronized to the bus clock. It can be selected as clock source to the FTM modules. The frequency of the ICSFFCLK is determined by the setting of the ICS.
• LPOCLK — This clock is generated from an internal low power oscillator (≈1 kHz) that is completely independent of the ICS module. The LPOCLK can be selected as the clock source to the RTC or WDOG modules.
• OSCOUT — This is the direct output of the external oscillator module and can be selected as the clock source for RTC, WDOG and ADC.
• TCLK0 — This is an optional external clock source for the FTM0 module. The TCLK0 must be limited to 1/4th frequency of the bus clock for synchronization.
• TCLK1 — This is an optional external clock source for the FTM1 module. The TCLK1 must be limited to 1/4th frequency of the bus clock for synchronization.
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NXP Semiconductors 27
System clock distribution
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Chapter 2
20 19 18 17
9
10
11
12
13
14
15
16
1 2 3 4 5 6 7 8
V
DD
V
SS
PTB7/EXTAL
PTB6/XTAL
1
PTB4/FTM1CH0
1
PTC1
PTC0
PTB3/KBI0P7/TCLK1/ADP7
PTB2/KBI0P6/ADP6
PTA2/KBI0P2/FTM0CH0/RxD0/ADP2 PTA3/KBI0P3/FTM0CH1/TxD0/ADP3
PTB0/KBI0P4/RxD0/TCLK0/ADP4 PTB1/KBI0P5/TxD0/ADP5
PTA4/ACMPO/BKGD/MS
PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1
bold are not available on less pin-count packages.
1. High source/sink current pins
Pins in
PTA5/IRQ/FTM1CH0/RESET
PTB5/FTM1CH1
PTC3 PTC2
2
2. True open drain pins
9
10
11
12
13
14
15
16
1 2 3 4 5 6 7 8
V
DD
V
SS
PTB7/EXTAL
PTB6/XTAL
1
PTB4/FTM1CH0
1
PTB3/KBI0P7/TCLK1/ADP7
PTB2/KBI0P6/ADP6
PTA2/KBI0P2/FTM0CH0/RxD0/ADP2 PTA3/KBI0P3/FTM0CH1/TxD0/ADP3 PTB0/KBI0P4/RxD0/TCLK0/ADP4
PTB1/KBI0P5/TxD0/ADP5
PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1
bold are not available on less pin-count packages.
1. High source/sink current pins
Pins in
PTA5/IRQ/FTM1CH0/RESET
PTB5/FTM1CH1
PTA4/ACMPO/BKGD/MS
2
2. True open drain pins
Pins and connections

2.1 Device pin assignment

Figure 2-1. MC9S08PA4 20-pin SOIC package
NXP Semiconductors 29
Figure 2-2. 16-pin TSSOP package
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5
DD
V
SS
PTA2/KBI0P2/FTM0CH0/RxD0/ADP2 PTA3/KBI0P3/FTM0CH1/TxD0/ADP3
PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1
PTA5/IRQ/FTM1CH0/RESET
PTA4/ACMPO/BKGD/MS
8
1 2 3
4
7 6
V
MCU
C1
C2
V
DD
V
ss
V
0.1
F

Pin functions

Figure 2-3. 8-pin DFN package
2.2
Pin functions

2.2.1 Power (VDD, VSS)

VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides a regulated lower-voltage source to the CPU and to the MCU's other internal circuitry.
Typically, application systems have two separate capacitors across the power pins. In this case, there should be a bulk electrolytic capacitor, such as a 10 µF tantalum capacitor, that provides bulk charge storage for the overall system and a 0.1 µF ceramic bypass capacitor located as near to the paired VDD and VSS power pins as practical to suppress high-frequency noise.
30 NXP Semiconductors
Figure 2-4. Power supply bypassing
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MCU
EXTAL
XTAL
R
s
R
F
C1
C2
X1
Chapter 2 Pins and connections

2.2.2 Oscillator (XTAL, EXTAL)

The XTAL and EXTAL pins are used to provide the connections for the on-chip oscillator. The oscillator (XOSC) in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator. Optionally, an external clock source can be connected to the EXTAL input pin. The oscillator can be configured to run in stop3 mode.
Refer to the following figure, RS (when used) and RF must be low-inductance resistors such as carbon composition resistors. Wire-wound resistors, and some metal film resistors, have too much inductance. C1 and C2 normally must be high-quality ceramic capacitors that are specifically designed for high-frequency applications.
Figure 2-5. Typical crystal or resonator circuit
RF is used to provide a bias path to keep the EXTAL input in its linear range during crystal startup; its value is not generally critical. Typical systems use 1 M to 10 M. Higher values are sensitive to humidity and lower values reduce gain and (in extreme cases) could prevent startup.
C1 and C2 are typically in the 5 pF to 25 pF range and are chosen to match the requirements of a specific crystal or resonator. Take into account printed circuit board (PCB) capacitance and MCU pin capacitance when selecting C1 and C2. The crystal manufacturer typically specifies a load capacitance, which is the series combination of C1 and C2 (which are usually the same size). As a first-order approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin (EXTAL and XTAL).
NXP Semiconductors 31
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MCU
V
DD
PTA5/IRQ/FTM1CH0/RESET
V
SS
F
0.1
4.7k
10k
Pin functions

2.2.3 External reset pin (RESET) and interrupt pin (IRQ)

A low on the RESET pin forces the MCU to an known startup state. RESET is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. This pin contains an internal pullup resistor.
RESET shares an I/O pin with PTA5. The RESET pin function is enabled by default after POR reset, because internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background debug connector so that a development system can directly reset the MCU system. If RESET function of PTA5/IRQ/FTM1CH0/RESET pin is enabled, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset). When the RESET pin function is enabled, an internal pullup resistor is connected to this pin and a reset signal can feed into MCU with an input hysteresis. POR reset brings RESET pin into its default configuration, reset other than POR has no effect on the RESET pin function configuration.
When PTA5/IRQ/FTM1CH0/RESET is enabled as IRQ pin, it is the input source for the IRQ interrupt and is also the input for the BIH and BIL instructions. IRQ is asynchronous external interrupt pins.
In EMC-sensitive applications, an external RC filter is recommended on the reset pin. See the following figure for example.
Figure 2-6. PTA5/IRQ/FTM1CH0/RESET external RC filter
32 NXP Semiconductors
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Optional Manual Reset
BKGD/MS
V
DD
V
SS
PTA5/IRQ/FTM1CH0/RESET
Chapter 2 Pins and connections

2.2.4 Background/mode select (BKGD/MS)

During a power-on-reset (POR) or background debug force reset, the PTA4/ACMPO/ BKGD/MS pin functions as a mode select pin. Immediately after internal reset rises the pin functions as the background pin and can be used for background debug communication. While the pin functions as a background/mode selection pin, it includes an internal pullup device and a standard output driver.
The background debug communication function is enabled when SOPT1[BKGDPE] bit is set. SOPT1[BKGDPE] is set following any reset of the MCU and must be cleared to use the PTA4/ACMPO/BKGD/MS pin's alternative pin functions.
If this pin is floating, the MCU will enter normal operating mode at the rising edge of reset. If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low during the POR or immediately after issuing a background debug force reset, which will force the MCU into active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom protocol that uses 16 clock cycles of the target MCU's BDC clock per bit time. The target MCU's BDC clock can run as fast as the bus clock, so there should never be any significant capacitance connected to the BKGD/MS pin that interferes with background serial communications. When the pin performs output only PTA4, it can drive only capacitance-limited MOSFET. Driving a bipolar transistor directly by PTA4 is prohibited because this can cause mode entry fault and BKGD errors.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise time. Small capacitances from cables and the absolute value of the internal pullup device play almost no role in determining rise and fall time on the BKGD pin.
NXP Semiconductors 33
Figure 2-7. Typical debug circuit
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Pin functions

2.2.5 Port A input/output (I/O) pins (PTA5–PTA0)

PTA5–PTA0 except PTA4 are general-purpose, bidirectional I/O port pins. These port pins also have selectable pullup devices when configured for input mode except PTA4. The pullup devices are selectable on an individual port bit basis. The pulling devices are disengaged when configured for output mode.
PTA4 is output only when used as port pin. The pulling device is disabled at this condition.
2.2.6
PTB7–PTB0 are general-purpose, bidirectional I/O port pins. These port pins also have selectable pullup devices when configured for input mode, the pullup devices are selectable on an individual port bit basis. The pulling devices are disengaged when configured for output mode.
PTB0 provide true open drain when operated as output.
2.2.7
PTC3–PTC0 are general-purpose, bidirectional I/O port pins. These port pins also have selectable pullup devices when configured for input mode, and the pullup devices are selectable on an individual port bit basis. The pulling devices are disengaged when configured for output mode.
2.2.8

Port B input/output (I/O) pins (PTB7–PTB0)

Port C input/output (I/O) pins (PTC3–PTC0)

True open drain pins (PTB0)

PTB0 operates in true open drain mode.
2.2.9
When high current function is enabled, PTB4 and PTB5 can drive output current. Each high current drive pin can drive higher sink/source current than the other normal pins, please refer to data sheet for the drive capacity.
34 NXP Semiconductors

High current drive pins (PTB4, PTB5)

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Chapter 2 Pins and connections

2.3 Peripheral pinouts

These MCUs support up to 18 general-purpose I/O pins, which are shared with on-chip peripheral functions (FTM, ACMP, ADC, SCI, KBI, etc.). These 18 general-purpose I/O pins include one output-only pin (PTA4).
When a port pin is configured as general-purpose input, or when a peripheral uses the port pin as an input, the software can enable a pullup device.
When a high current drive port pin is configured as general-purpose output or when a peripheral uses the port pin as an output, software can select alternative drive strengths.
For information about controlling these pins as general-purpose I/O pins, see the Parallel
input/output. For information about how and when on-chip peripheral systems use these
pins, see the appropriate module chapter. Immediately after reset, all pins are configured as high-impedance general-purpose IO
with internal pullup devices disabled.
Table 2-1. Pin availability by package pin-count
Pin Number Lowest Priority <-- --> Highest
20-SOIC 16-TSSOP 8-DFN Port Pin Alt 1 Alt 2 Alt 3 Alt 4
1 1 1 PTA5 IRQ FTM1CH0 — RESET 2 2 2 PTA4 — ACMPO BKGD MS 3 3 3 — — — — V 4 4 4 — — — — V 5 5 — PTB7 — — — EXTAL 6 6 — PTB6 — — — XTAL 7 7 — PTB5 8 8 — PTB4
9 — — PTC3 — — — — 10 — — PTC2 — — — — 11 — — PTC1 — — — — 12 — — PTC0 — — — — 13 9 — PTB3 KBI0P7 — TCLK1 ADP7 14 10 — PTB2 KBI0P6 — — ADP6 15 11 — PTB1 KBI0P5 TxD0 — ADP5 16 12 — PTB0 17 13 5 PTA3 KBI0P3 FTM0CH1 TxD0 ADP3 18 14 6 PTA2 KBI0P2 FTM0CH0 RxD0 ADP2 19 15 7 PTA1 KBI0P1 FTM0CH1 ACMP1 ADP1 20 16 8 PTA0 KBI0P0 FTM0CH0 ACMP0 ADP0
-1
-1
3
— FTM1CH1 — — — FTM1CH0 — —
KBI0P4 RxD0 TCLK0 ADP4
DD
SS
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NXP Semiconductors 35
Peripheral pinouts
1. This is a high current drive pin when operated as output. Please see High current drive for more information.
2. This is a high current drive pin when operated as output. Please see High current drive for more information.
3. This is a true open-drain pin when operated as output.
Note
When an alternative function is first enabled, it is possible to get a spurious edge to the module. User software must clear any associated flags before interrupts are enabled. The table above illustrates the priority if multiple modules are enabled. The highest priority module will have control over the pin. Selecting a higher priority pin function with a lower priority function already enabled can cause spurious edges to the lower priority module. Disable all modules that share a pin before enabling another module.
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36 NXP Semiconductors
Chapter 3 Power management

3.1 Introduction

The operating modes of the device are described in this chapter. Entry into each mode, exit from each mode, and functionality while in each of the modes are described.
3.2
These MCUs feature the following power modes:
3.2.1

Features

• Run mode
• Wait mode
• CPU shuts down to conserve power
• Bus clocks are running
• Full voltage regulation is maintained
• Stop3 modes
• System clocks stopped; voltage regulator in standby
• all internal circuits powered for fast recovery

Run mode

This is the normal operating mode. In this mode, the CPU executes code from internal memory with execution beginning at the address fetched from memory at 0xFFFE: 0xFFFF after reset. The power supply is fully regulating and all peripherals can be active in run mode.
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NXP Semiconductors 37
Features

3.2.2 Wait mode

Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine.
While the MCU is in wait mode, there are some restrictions on which background debug commands can be used. Only the BACKGROUND command and memory-access-with­status commands are available when the MCU is in wait mode. The memory-access-with­status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from wait mode and enter active background mode.
3.2.3

Stop3 mode

To enter stop3, the user must execute a STOP instruction with stop mode enabled (SOPT1[STOPE] = 1). Upon entering the stop3 mode, all of the clocks in the MCU are halted by default, but OSC clock and internal reference clock can be turned on by setting the ICS control registers. The ICS enters its standby state, as does the voltage regulator and the ADC. The states of all of the internal registers and logic, as well as the RAM content, are maintained. The I/O pin states are not latched at the pin. Instead they are maintained by virtue of the states of the internal logic driving the pins being maintained.
Exit from stop3 is done by asserting reset or through an interrupt. The interrupt include the asynchronous interrupt from the IRQ or KBI pins, the SCI receive interrupt, the ADC, ACMP or LVI interrupt and the real-time interrupt.
If stop3 is exited by means of the
RESET pin, then the MCU will be reset and operation will resume after taking the reset vector. Exit by means of an asynchronous interrupt or the real-time interrupt will result in the MCU taking the appropriate interrupt vector.
The LPO (≈1 kHz) for the real-time counter clock allows a wakeup from stop3 mode with no external components. When RTC_SC2[RTCPS] is clear, the real-time counter clock function is disabled.
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Chapter 3 Power management
3.2.4 Active BDM enabled in stop3 mode
Entry into the active background mode from run mode is enabled if the BDC_SCR[ENBDM] bit is set. This register is described in the development support. If BDC_SCR[ENBDM] is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode, so background debug communication is still possible. In addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation.
Most background commands are not available in stop mode. The memory-access-with­status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from stop and enter active background mode if the BDC_SCR[ENBDM] bit is set. After entering background debug mode, all background commands are available.
3.2.5

LVD enabled in stop mode

The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time the CPU executes a STOP instruction, then the voltage regulator remains active during stop3 mode.
3.2.6

Power modes behaviors

Executing the WAIT or STOP command puts the MCU in a low power consumption mode for standby situations. The system integration module (SIM) holds the CPU in a non-clocked state. The operation of each of these modes is described in the following subsections. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupt to occur. The following table shows the low power mode behaviors.
Table 3-1. Low power mode behavior
Mode Run Wait Stop3
PMC Full regulation Full regulation Loose regulation ICS On On Optional on OSC On On Optional on LPO On On On CPU On Standby Standby FLASH On On Standby
Table continues on the next page...
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NXP Semiconductors 39

Low voltage detect (LVD) system

Table 3-1. Low power mode behavior (continued)
Mode Run Wait Stop3
RAM On Standby Standby ADC On On Optional on ACMP On On Optional on I/O On On States held SCI On On Standby FTM On On Standby WDOG On On Standby DBG On On Standby IPC On On Standby RTC On On Optional on LVD On On Optional on
3.3 Low voltage detect (LVD) system
This device includes a system to protect against low voltage conditions in order to protect memory contents and control MCU system states during supply voltage variations. This system consists of a power-on reset (POR) circuit and an LVD circuit with a user selectable trip voltage, either high (V when SPMSC1[LVDE] is set and the trip voltage is selected by SPMSC2[LVDV]. The LVD is disabled upon entering the stop modes unless the SPMSC1[LVDSE] bit is set or active BDM enabled (BDCSCR[ENBDM]=1). If SPMSC1[LVDSE] and SPMSC1[LVDE] are both set, the current consumption in stop3 with the LVD enabled will be greater.
LVDH
) or low (V
). The LVD circuit is enabled
LVDL
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40 NXP Semiconductors
Bandgap
+
vD
D
v
ss
v
BG
R
1
R
7
LVDV:LVDWV
LVD0
LVD1
LVD
+
LVW
LVW0
LVW1
LVW2 LVW3
Chapter 3 Power management
Figure 3-1. Low voltage detect (LVD) block diagram
3.3.1

Power-on reset (POR) operation

When power is initially applied to the MCU, or when the supply voltage drops below the V LVD circuit will hold the chip in reset until the supply has risen above the V
level, the POR circuit will cause a reset condition. As the supply voltage rises, the
POR
LVDL
level.
Both the SRS[POR] and SRS[LVD] are set following a POR.
3.3.2

LVD reset operation

The LVD can be configured to generate a reset upon detection of a low voltage condition by setting SPMSC1[LVDRE] to 1. After an LVD reset has occurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the level determined by LVDV. The SRS[LVD] bit is set following either an LVD reset or POR.
3.3.3

Low-voltage warning (LVW)

The LVD system has a low voltage warning flag to indicate that the supply voltage is approaching the LVD voltage. When a low voltage condition is detected and the LVD circuit is configured for interrupt operation (SPMSC1[LVDE] set, SPMSC1[LVWIE] set), SPMSC1[LVWF] will be set and LVW interrupt will occur. There are four user­selectable trip voltages for the LVW upon each LVDV configuration. The trip voltage is selected by SPMSC2[LVWV].
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NXP Semiconductors 41

Bandgap reference

3.4 Bandgap reference
This device includes an on-chip bandgap reference (≈1.2V) connected to ADC channel and ACMP. The bandgap reference voltage will not drop under the full operating voltage even when the operating voltage is falling. This reference voltage acts as an ideal reference voltage for accurate measurements.

3.5 Power management control bits and registers

PMC memory map
Absolute
address
(hex)
3040
3041
Register name
System Power Management Status and Control 1 Register (PMC_SPMSC1)
System Power Management Status and Control 2 Register (PMC_SPMSC2)
Width
(in bits)
Access Reset value
8 R/W 1Ch 3.5.1/42
8 R/W 00h 3.5.2/44
Section/
page
3.5.1 System Power Management Status and Control 1 Register
(PMC_SPMSC1)
This high page register contains status and control bits to support the low-voltage detection function, and to enable the bandgap voltage reference for use by the ADC module. This register should be written during the user's reset initialization program to set the desired controls, even if the desired settings are the same as the reset settings.
Address:
3040h base + 0h offset = 3040h
Bit 7 6 5 4 3 2 1 0
Read LVWF 0
Write LVWACK
Reset
0 0 0 1 1 1 0 0
LVWIE LVDRE LVDSE LVDE BGBDS BGBE
PMC_SPMSC1 field descriptions
Field Description
7
LVWF
42 NXP Semiconductors
Low-Voltage Warning Flag
The LVWF bit indicates the low-voltage warning status.
Table continues on the next page...
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PMC_SPMSC1 field descriptions (continued)
Field Description
6
LVWACK
5
LVWIE
4
LVDRE
NOTE:
0 Low-voltage warning is not present. 1 Low-voltage warning is present or was present.
Low-Voltage Warning Acknowledge
If LVWF = 1, a low-voltage condition has occurred. To acknowledge this low-voltage warning, write 1 to LVWACK, which automatically clears LVWF to 0 if the low-voltage warning is no longer present.
Low-Voltage Warning Interrupt Enable
This bit enables hardware interrupt requests for LVWF.
0 Hardware interrupt disabled (use polling). 1 Request a hardware interrupt when LVWF = 1.
Low-Voltage Detect Reset Enable
This write-once bit enables LVD events to generate a hardware reset (provided LVDE = 1).
LVWF will be set in the case when V is already below V
. LVWF bit may be 1 after power on reset, therefore, to use LVW interrupt
LVW
transitions below the trip point or after reset and V
Supply
function, before enabling LVWIE, LVWF must be cleared by writing LVWACK first.
Chapter 3 Power management
Supply
3
LVDSE
2
LVDE
1
BGBDS
0
BGBE
NOTE:
This bit can be written only one time after reset. Additional writes are ignored.
0 LVD events do not generate hardware resets. 1 Force an MCU reset when an enabled low-voltage detect event occurs.
Low-Voltage Detect Stop Enable
Provided LVDE = 1, this read/write bit determines whether the low-voltage detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode. 1 Low-voltage detect enabled during stop mode.
Low-Voltage Detect Enable
This write-once bit enables low-voltage detect logic and qualifies the operation of other bits in this register.
NOTE:
This bit can be written only one time after reset. Additional writes are ignored.
0 LVD logic disabled. 1 LVD logic enabled.
Bandgap Buffer Drive Select
This bit is used to select the high drive mode of the bandgap buffer.
0 Bandgap buffer enabled in low drive mode if BGBE = 1. 1 Bandgap buffer enabled in high drive mode if BGBE = 1.
Bandgap Buffer Enable
This bit enables an internal buffer for the bandgap voltage reference for use by the ADC module on one of its internal channels.
0 Bandgap buffer disabled. 1 Bandgap buffer enabled.
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NXP Semiconductors 43
Power management control bits and registers
3.5.2 System Power Management Status and Control 2 Register
(PMC_SPMSC2)
This register is used to report the status of the low-voltage warning function, and to configure the stop mode behavior of the MCU. This register should be written during the user's reset initialization program to set the desired controls, even if the desired settings are the same as the reset settings.
Address: 3040h base + 1h offset = 3041h
Bit 7 6 5 4 3 2 1 0
Read 0 Write
Reset
0 0 0 0 0 0 0 0
LVDV LVWV
PMC_SPMSC2 field descriptions
Field Description
7
Reserved
6
LVDV
This field is reserved. This read-only field is reserved and always has the value 0.
Low-Voltage Detect Voltage Select
This write-once bit selects the low-voltage detect (LVD) trip point setting. See data sheet for details.
0
0 Low trip point selected (V 1 High trip point selected (V
5–4
LVWV
Reserved This field is reserved.
Low-Voltage Warning Voltage Select
This bit selects the low-voltage warning (LVW) trip point voltage. See data sheet for details.
00 Low trip point selected (V 01 Middle 1 trip point selected (V 10 Middle 2 trip point selected (V 11 High trip point selected (V
This read-only field is reserved and always has the value 0.
LVD
LVD
LVW
LVW
= V
= V
= V
= V
LVW
LVW
LVDL
LVDH
LVW1
= V = V
LVW4
).
).
).
LVW2
LVW3
).
). ).
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Chapter 4 Memory map

4.1 Memory map

The HCS08 core processor can address 64 KB of memory space. The memory map, shown in the following figure, includes:
• User flash memory (flash)
• MC9S08PA4: 4,096 bytes; 8 pages of 512 bytes each
• Random-access memory (RAM)
• MC9S08PA4: 512 bytes
• Electrically erasable programmable read-only memory (EEPROM)
• MC9S08PA4: 128 bytes; 64 pages of 2 bytes each
• Direct-page registers (0x0000 through 0x003F)
• High-page registers (0x3000 through 0x30FF)
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NXP Semiconductors 45
128 BYTES EEPROM
HIGH PAGE REGISTERS
DIRECT PAGE REGISTERS
512 BYTES RAM
4,096B FLASH
0x0000 0x0040
0x003F
0x3100
0xFFFF
0x30FF
0x3000
0x023F
0x0240
0x2FFF
UNIMPLEMENTED
VECTOR TABLE
0x317F
0x3180
UNIMPLEMENTED
0xF000
0xFFAF 0xFFB0

Reset and interrupt vector assignments

Figure 4-1. Memory map
4.2
Reset and interrupt vector assignments
The following table shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the header files for the device.
Table 4-1. Reset and interrupt vectors
Address
Vector Vector name
(high/low)
0xFFB0:FFB1 NVM Vnvm 0xFFB2:FFB3 Reserved Reserved 0xFFB4:FFB5 KBI0 Vkbi0 0xFFB6:FFB7 Reserved Reserved
0xFFB8:FFB9 RTC Vrtc 0xFFBA:FFBB Reserved Reserved 0xFFBC:FFBD Reserved Reserved 0xFEBE:FFBF Reserved Reserved
0xFFC0:FFC1 Reserved Reserved
0xFFC2:FFC3 Reserved Reserved
0xFFC4:FFC5 Reserved Reserved
Table continues on the next page...
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46 NXP Semiconductors
Table 4-1. Reset and interrupt vectors (continued)
Chapter 4 Memory map
Address
(high/low)
0xFFC6:FFC7 Reserved Reserved
0xFFC8:FFC9 Reserved Reserved 0xFFCA:FFCB Reserved Reserved 0xFFCC:FFCD SCI0 transmit Vsci0txd 0xFFCE:FFCF SCI0 receive Vsci0rxd
0xFFD0:FFD1 SCI0 error Vsci0err
0xFFD2:FFD3 ADC Vadc
0xFFD4:FFD5 ACMP Vacmp
0xFFD6:FFD7 Reserved Reserved
0xFFD8:FFD9 Reserved Reserved 0xFFDA:FFDB FTM0 overflow Vftm0ovf 0xFFDC:FFDD FTM0 channel 1 Vftm0ch1 0xFFDE:FFDF FTM0 channel 0 Vftm0ch0
0xFFE0:FFE1 FTM1 overflow Vftm1ovf
0xFFE2:FFE3 FTM1 channel 1 Vftm1ch1
0xFFE4:FFE5 FTM1 channel 0 Vftm1ch0
0xFFE6:FFE7 FTM2 overflow Vftm2ovf
0xFFE8:FFE9 Reserved Reserved 0xFFEA:FFEB Reserved Reserved 0xFFEC:FFED Reserved Reserved 0xFFEE:FFEF Reserved Reserved
0xFFF0:FFF1 FTM2 channel 1 Vftm2ch1
0xFFF2:FFF3 FTM2 channel 0 Vftm2ch0
0xFFF4:FFF5 Reserved Reserved
0xFFF6:FFF7 Clock loss of lock Vclk
0xFFF8:FFF9 Low voltage warning Vlvw
0xFFFA:FFFB IRQ or Watchdog Virq or Vwdog 0xFFFC:FFFD SWI Vswi
0xFFFE:FFFF Reset Vreset
Vector Vector name

4.3 Register addresses and bit assignments

The register definitions vary in different memory sizes. The register addresses of unused peripherals are reserved. The following table shows the register availability of the devices.
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Register addresses and bit assignments
Table 4-2. Peripheral registers availability
Address Bytes Peripheral registers
0x0000—0x0002 3 Port data 0x0010—0x0017 8 ADC 0x0020—0x002A 11 FTM0
0x002C—0x002F 4 ACMP
0x0030—0x003A 11 FTM1 0x003B—0x003B 1 IRQ 0x003C—0x003C 1 KBI0
0x003E—0x003F 2 IPC 0x3000—0x300B 12 SIM
0x300C—0x300F 4 SCG
0x3010—0x301F 16 DBG 0x3020—0x302C 13 NVM
0x3030—0x3037 8 WDOG
0x3038—0x303E 7 ICS, XOSC
0x3040—0x3041 2 PMC 0x304A—0x304B 2 SYS
0x3050—0x3059 10 IPC
0x306A—0x306F 6 RTC
0x307C—0x307D 2 KBI0
0x3080—0x3087 8 SCI0
0x30AC—0x30AC 1 ADC
0x30AF—0x30AF 1 Port high drive enable 0x30B0—0x30B2 3 Port output enable 0x30B8—0x30BA 3 Port input enable 0x30C0—0x30CA 11 FTM2 0x30EC—0x30EF 4 Port filter
0x30F0—0x30F2 3 Port pullup 0x30F8—0x30FF 8 SYS
The registers in the devices are divided into two groups:
• Direct-page registers are located in the first 64 locations in the memory map, so they can be accessed with efficient direct addressing mode instructions.
• High-page registers are used much less often, so they are located above 0x3000 in the memory map. This leaves room in the direct page for more frequently used registers and variables.
Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation instructions can be used to access any bit in a direct-page register.
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Chapter 4 Memory map
The direct page registers can use the more efficient direct addressing mode, which requires only the lower byte of the address.
The following tables are summaries of all user-accessible direct-page and high-page registers and control bits. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads as a 0; and a shaded cell with a 1 indicates this unused bit always reads as a 1. Shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s.
Table 4-3. Direct-page register allocation
Address Register name Bit 7 6 5 4 3 2 1 Bit 0
0x0000 PORT_PTAD 0x0001 PORT_PTBD PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0
0x0002 PORT_PTCD — — — — PTCD3 PTCD2 PTCD1 PTCD0 0x0003-0x0007 Reserved — — — — — — — — 0x0008-0x000F Reserved — — — — — — — —
0x0010 ADC_SC1 COCO AIEN ADCO ADCH
0x0011 ADC_SC2 ADACT ADTRG ACFE ACFGT
0x0012 ADC_SC3 ADLPC ADIV
0x0013 ADC_SC4 —
0x0014 ADC_RH Bit 15 14 13 12 11 10 9 Bit 8
0x0015 ADC_RL Bit 7 6 5 4 3 2 1 Bit 0
0x0016 ADC_CVH Bit 15 14 13 12 11 10 9 Bit 8
0x0017 ADC_CVL Bit 7 6 5 4 3 2 1 Bit 0
0x0018-0X001F Reserved — — — — — — — —
0x0020 FTM0_SC TOF TOIE CPWMS CLKS1 CLKS0 PS2 PS1 PS0
0x0021 FTM0_CNTH Bit 15 14 13 12 11 10 9 Bit 8
0x0022 FTM0_CNTL Bit 7 6 5 4 3 2 1 Bit 0
0x0023 FTM0_MODH Bit 15 14 13 12 11 10 9 Bit 8
0x0024 FTM0_MODL Bit 7 6 5 4 3 2 1 Bit 0
0x0025 FTM0_C0SC CHF CHIE MSB MSA ELSB ELSA — —
0x0026 FTM0_C0VH Bit 15 14 13 12 11 10 9 Bit 8
0x0027 FTM0_C0VL Bit 7 6 5 4 3 2 1 Bit 0
0x0028 FTM0_C1SC CHF CHIE MSB MSA ELSB ELSA — —
0x0029 FTM0_C1VH Bit 15 14 13 12 11 10 9 Bit 8
0x002A FTM0_C1VL Bit 7 6 5 4 3 2 1 Bit 0 0x002B Reserved — — — — — — — — 0x002C ACMP_CS ACE HYST ACF ACIE ACO ACOPE ACMOD 0x002D ACMP_C0 — — ACPSEL — — ACNSEL
— — PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
ASCAN
E
FEMPT
ADLSM
P
ACFSEL — — AFDEP
FFULL — —
Y
MODE ADICLK
Table continues on the next page...
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NXP Semiconductors 49
Register addresses and bit assignments
Table 4-3. Direct-page register allocation (continued)
Address Register name Bit 7 6 5 4 3 2 1 Bit 0
0x002E ACMP_C1
0x002F ACMP_C2 — — — — — ACIPE2 ACIPE1 ACIPE0
0x0030 FTM1_SC TOF TOIE CPWMS CLKS1 CLKS0 PS2 PS1 PS0
0x0031 FTM1_CNTH Bit 15 14 13 12 11 10 9 Bit 8
0x0032 FTM1_CNTL Bit 7 6 5 4 3 2 1 Bit 0
0x0033 FTM1_MODH Bit 15 14 13 12 11 10 9 Bit 8
0x0034 FTM1_MODL Bit 7 6 5 4 3 2 1 Bit 0
0x0035 FTM1_C0SC CHF CHIE MSB MSA ELSB ELSA — —
0x0036 FTM1_C0VH Bit 15 14 13 12 11 10 9 Bit 8
0x0037 FTM1_C0VL Bit 7 6 5 4 3 2 1 Bit 0
0x0038 FTM1_C1SC CHF CHIE MSB MSA ELSB ELSA — —
0x0039 FTM1_C1VH Bit 15 14 13 12 11 10 9 Bit 8
0x003A FTM1_C1VL Bit 7 6 5 4 3 2 1 Bit 0
0x003B IRQ_SC — IRQPDD IRQEDG IRQPE IRQF IRQACK IRQIE
0x003C KBI0_SC — — — — KBF KBACK KBIE KBMOD 0x003D Reserved — — — — — — — — 0x003E IPC_SC IPCE — PSE PSF PULIPM — IPM 0x003F IPC_IPMPS
DACEN
DACRE
F
IPM3 IPM2 IPM1 IPM0
DACVAL
IRQMO
D
Table 4-4. High-page register allocation
Address Register name Bit 7 6 5 4 3 2 1 Bit 0
0x3000 SYS_SRS
0x3001 SYS_SBDFR — — — — — — — BDFR
0x3002 SYS_SDIDH — — — — ID11 ID10 ID9 ID8
0x3003 SYS_SDIDL ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
0x3004 SYS_SOPT1 SCI0PS FTM1PS FTM0PS —
0x3005 SYS_SOPT2 TXDME — RXDFE RXDCE ACIC RTCC ADHWTS
0x3006 SYS_SOPT3 — — FTMCHS — — — —
0x3007-0x300B Reserved — — — — — — — —
0x300C SCG_C1 FTM2 FTM1 FTM0 — — — — RTC 0x300D SCG_C2 — — DBG NVM IPC — — — 0x300E SCG_C3 — — — SCI0 — — — — 0x300F SCG_C4 ACMP — ADC — IRQ — — KBI0
0x3010 DBG_CAH Bit 15 14 13 12 11 10 9 Bit 8
0x3011 DBG_CAL Bit 7 6 5 4 3 2 1 Bit 0
0x3012 DBG_CBH Bit 15 14 13 12 11 10 9 Bit 8
POR PIN WDOG ILOP ILAD LOC LVD —
BKGDP
Table continues on the next page...
RSTPE FWAKE STOPE
E
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50 NXP Semiconductors
Chapter 4 Memory map
Table 4-4. High-page register allocation (continued)
Address Register name Bit 7 6 5 4 3 2 1 Bit 0
0x3013 DBG_CBL
0x3014 DBG_CCH Bit 15 14 13 12 11 10 9 Bit 8
0x3015 DBG_CCL Bit 7 6 5 4 3 2 1 Bit 0
0x3016 DBG_FH Bit 15 14 13 12 11 10 9 Bit 8
0x3017 DBG_FL Bit 7 6 5 4 3 2 1 Bit 0
0x3018 DBG_CAX RWAEN RWA — — — — — —
0x3019 DBG_CBX RWBEN RWB — — — — — —
0x301A DBG_CCX RWCEN RWC — — — — — — 0x301B DBG_FX PPACC — — — — — — Bit 16 0x301C DBG_C DBGEN ARM TAG BRKEN — — — LOOP1
0x301D DBG_T
0x301E DBG_S AF BF CF — — — — ARMF 0x301F DBG_CNT — — — — CNT
0x3020 NVM_FCLKDIV FDIVLD
0x3021 NVM_FSEC KEYEN1 KEYEN0 1 1 1 1 SEC1 SEC0
0x3022 NVM_FCCOBIX — — — — —
0x3023 Reserved — — — — — — — —
0x3024 NVM_FCNFG CCIE — — IGNSF — — FDFD FSFD
0x3025 NVM_FERCNFG — — — — — — DFDIE SFDIE
0x3026 NVM_FSTAT CCIF —
0x3027 NVM_FERSTAT — — — — — — DFDIF SFDIF
0x3028 NVM_FPROT FPOEN — FPHDIS FPHS1 FPHS0 — — —
0x3029 NVM_EEPROT
0x302A NVM_FCCOBHI
0x302B NVM_FCCOBLO CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 0x302C NVM_FOPT NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0
0x302D-0x302F Reserved — — — — — — — —
0x3030 WDOG_CS1 EN INT
0x3031 WDOG_CS2 WIN FLG — PRES — — CLK
0x3032 WDOG_CNTH Bit 15 14 13 12 11 10 9 Bit 8
0x3033 WDOG_CNTL Bit 7 6 5 4 3 2 1 Bit 0
0x3034 WDOG_TOVALH Bit 15 14 13 12 11 10 9 Bit 8
0x3035 WDOG_TOVALL Bit 7 6 5 4 3 2 1 Bit 0
0x3036 WDOG_WINH Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 6 5 4 3 2 1 Bit 0
TRGSE
DPOPE
CCOB15CCOB14CCOB13CCOB12CCOB11CCOB1
BEGIN — — TRG
L
FDIVLC
K
N
— — — — — DPS1 DPS0
FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0
ACCER
R
UPDAT
E
FPVIOL
MGBUS
Y
TST DBG WAIT STOP
CCOBIX2CCOBIX1CCOBIX
MGSTAT1MGSTA
—
CCOB9 CCOB8
0
T0
0
Table continues on the next page...
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Register addresses and bit assignments
Table 4-4. High-page register allocation (continued)
Address Register name Bit 7 6 5 4 3 2 1 Bit 0
0x3037 WDOG_WINL
0x3038 ICS_C1 CLKS RDIV IREFS
0x3039 ICS_C2 BDIV LP — — — —
0x303A ICS_C3 SCTRIM
0x303B ICS_C4 LOLIE — CME — — — —
0x303C ICS_S LOLS LOCK — IREFST CLKST — — 0x303D Reserved — — — — — — — —
0x303E ICS_OSCSC OSCEN —
0x303F Reserved — — — — — — — —
0x3040 PMC_SPMSC1 LVWF
0x3041 PMC_SPMSC2 — LVDV LVWV — — — — 0x3042-0x3049 Reserved — — — — — — — —
0x304A SYS_ILLAH Bit 15 14 13 12 11 19 9 Bit 8 0x304B SYS_ILLAL Bit 7 6 5 4 3 2 1 Bit 0
0x304C-0x304F Reserved — — — — — — — —
0x3050 IPC_ILRS0 ILR3 ILR2 ILR1 ILR0
0x3051 IPC_ILRS1 ILR7 ILR6 ILR5 ILR4
0x3052 IPC_ILRS2 ILR11 ILR10 ILR9 ILR8
0x3053 IPC_ILRS3 ILR15 ILR14 ILR13 ILR12
0x3054 IPC_ILRS4 ILR19 ILR18 ILR17 ILR16
0x3055 IPC_ILRS5 ILR23 ILR22 ILR21 ILR20
0x3056 IPC_ILRS6 ILR27 ILR26 ILR25 ILR24
0x3057 IPC_ILRS7 ILR31 ILR30 ILR29 ILR28
0x3058 IPC_ILRS8 ILR35 ILR34 ILR33 ILR32
0x3059 IPC_ILRS9 ILR39 ILR38 ILR37 ILR36
0x305A-0x305F Reserved — — — — — — — —
0x3060-0x3069 Reserved — — — — — — — —
0x306A RTC_SC1 RTIF RTIE — — — — — — 0x306B RTC_SC2 RTCLKS — — — RTCPS 0x306C RTC_MODH MODH 0x306D RTC_MODL MODL 0x306E RTC_CNTH CNTH 0x306F RTC_CNTL CNTL
0x3070-0x307B Reserved — — — — — — — —
0x307C KBI0_PE KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0
0x307D KBI0_ES
Bit 7 6 5 4 3 2 1 Bit 0
IRCLKENIREFST
OSCST
EN
LVWAC
KBEDG7KBEDG6KBEDG5KBEDG4KBEDG3KBEDG2KBEDG1KBEDG
LVWIE LVDRE LVDSE LVDE BGBDS BGBE
K
OSCOS — RANGE HGO
EN
SCFTRI
M
OSCINI
T
0
Table continues on the next page...
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Chapter 4 Memory map
Table 4-4. High-page register allocation (continued)
Address Register name Bit 7 6 5 4 3 2 1 Bit 0
0x307E-0x307F Reserved
0x3080 SCI0_BDH LBKDIE
0x3081 SCI0_BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
0x3082 SCI0_C1 LOOPS
0x3083 SCI0_C2 TIE TCIE RIE ILIE TE RE RWU SBK
0x3084 SCI0_S1 TDRE TC RDRF IDLE OR NF FE PF
0x3085 SCI0_S2 LBKDIF
0x3086 SCI0_C3 R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE
0x3087 SCI0_D D7 D6 D5 D4 D3 D2 D1 D0 0x3088-0x3097 Reserved — — — — — — — —
0x3098-0x30AB Reserved — — — — — — — —
0x30AC ADC_APCTL1 ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0
0x30AD-0x30AE Reserved — — — — — — — —
0x30AF PORT_HDRVE — — — — — — PTB5 PTB4 0x30B0 PORT_PTAOE — — PTAOE5 PTAOE4 PTAOE3 PTAOE2 PTAOE1 PTAOE0 0x30B1 PORT_PTBOE PTBOE7 PTBOE6 PTBOE5 PTBOE4 PTBOE3 PTBOE2 PTBOE1 PTBOE0
0x30B2 PORT_PTCOE — — — —
0x30B3-0x30B7 Reserved — — — — — — — —
0x30B8 PORT_PTAIE — — PTAIE5 — PTAIE3 PTAIE2 PTAIE1 PTAIE0 0x30B9 PORT_PTBIE PTBIE7 PTBIE6 PTBIE5 PTBIE4 PTBIE3 PTBIE2 PTBIE1 PTBIE0 0x30BA PORT_PTCIE — — — — PTCIE3 PTCIE2 PTCIE1 PTCIE0
0x30BB-0x30BF Reserved — — — — — — — —
0x30C0 FTM2_SC TOF TOIE CPWMS CLKS1 CLKS0 PS2 PS1 PS0 0x30C1 FTM2_CNTH Bit 15 14 13 12 11 10 9 Bit 8 0x30C2 FTM2_CNTL Bit 7 6 5 4 3 2 1 Bit 0 0x30C3 FTM2_MODH Bit 15 14 13 12 11 10 9 Bit 8 0x30C4 FTM2_MODL Bit 7 6 5 4 3 2 1 Bit 0 0x30C5 FTM2_C0SC CHF CHIE MSB MSA ELSB ELSA — — 0x30C6 FTM2_C0VH Bit 15 14 13 12 11 10 9 Bit 8 0x30C7 FTM2_C0VL Bit 7 6 5 4 3 2 1 Bit 0 0x30C8 FTM2_C1SC CHF CHIE MSB MSA ELSB ELSA — — 0x30C9 FTM2_C1VH Bit 15 14 13 12 11 10 9 Bit 8
0x30CA FTM2_C1VL Bit 7 6 5 4 3 2 1 Bit 0
0x30CB-0x30EB Reserved — — — — — — — —
0x30EC PORT_IOFLT0 — — FLTC FLTB FLTA 0x30ED Reserved — — — — — — — —
0x30EE PORT_IOFLT2 — — — — FLTKBI0 FLTRST
— — — — — — — —
RXEDGI
E
SCISWA
RXEDGI
F
SBNS SBR12 SBR11 SBR10 SBR9 SBR8
RSRC M WAKE ILT PE PT
I
— RXINV RWUID BRK13 LBKDE RAF
PTCOE3PTCOE2PTCOE1PTCOE
0
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Register addresses and bit assignments
Table 4-4. High-page register allocation (continued)
Address Register name Bit 7 6 5 4 3 2 1 Bit 0
0x30EF PORT_FCLKDIV 0x30F0 PORT_PTAPE — — PTAPE5 — PTAPE3 PTAPE2 PTAPE1 PTAPE0 0x30F1 PORT_PTBPE PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0 0x30F2 PORT_PTCPE — — — — PTCPE3 PTCPE2 PTCPE1 PTCPE0
0x30F3-0x30F7 Reserved — — — — — — — —
0x30F8 SYS_UUID1 ID63 ID62 ID61 ID60 ID59 ID58 ID57 ID56 0x30F9 SYS_UUID2 ID55 ID54 ID53 ID52 ID51 ID50 ID49 ID48 0x30FA SYS_UUID3 ID47 ID46 ID45 ID44 ID43 ID42 ID41 ID40 0x30FB SYS_UUID4 ID39 ID38 ID37 ID36 ID35 ID34 ID33 ID32 0x30FC SYS_UUID5 ID31 ID30 ID29 ID28 ID27 ID26 ID25 ID24 0x30FD SYS_UUID6 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 0x30FE SYS_UUID7 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 0x30FF SYS_UUID8
ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
FLTDIV3 FLTDIV2 FLTDIV1
Several reserved flash memory locations, shown in the following table, are used for storing values used by several registers. These registers include an 8-byte backdoor key, NV_BACKKEY, which can be used to gain access to secure memory resources. During reset events, the contents of NVPROT and NVOPT in the reserved flash memory are transferred into corresponding FPROT and FOPT registers in the high-page registers area to control security and block protection options.
Table 4-5. Reserved flash memory addresses
Address Register Name Bit 7 6 5 4 3 2 1 Bit 0
0xFF70 NV_BACKKEY0 0xFF71 NV_BACKKEY1 BACKKEY1 0xFF72 NV_BACKKEY2 BACKKEY2 0xFF73 NV_BACKKEY3 BACKKEY3 0xFF74 NV_BACKKEY4 BACKKEY4 0xFF75 NV_BACKKEY5 BACKKEY5 0xFF76 NV_BACKKEY6 BACKKEY6 0xFF77 NV_BACKKEY7 BACKKEY7 0xFF78 Reserved — — — — — — — — 0xFF79 Reserved — — — — — — — — 0xFF7A Reserved — — — — — — — — 0xFF7B Reserved — — — — — — — —
0xFF7C NV_FPROT
0xFF7D NV_EEPROT
FPOPE
N
DPOPE
N
Table continues on the next page...
— FPHDIS FPH — — —
BACKKEY0
— DPS
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Table 4-5. Reserved flash memory addresses (continued)
Address Register Name Bit 7 6 5 4 3 2 1 Bit 0
0xFF7E NV_FOPT 0xFF7F NV_FSEC
KEYEN 1 1 1 1 SEC
NV
The 8-byte comparison key can be used to temporarily disengage memory security provided the key enable field, NV_FSEC[KEYEN], is 10b. This key mechanism can be accessed only through user code running in secure memory. A security key cannot be entered directly through background debug commands. This security key can be disabled completely by programming the NV_FSEC[KEYEN] bit to 0. If the security key is disabled, the only way to disengage security is by mass erasing the flash if needed, normally through the background debug interface and verifying that flash is blank. To avoid returning to secure mode after the next reset, program the security bits, NV_FSEC[SEC], to the unsecured state (10b).
4.4

Random-access memory (RAM)

This section describes the 512 bytes of RAM (random-access memory). These devices include static RAM. The locations in RAM below 0x0100 can be accessed
using the more efficient direct addressing mode. Any single bit in this area can be accessed with the bit manipulation instructions (BCLR, BSET, BRCLR, and BRSET).
The RAM retains data when the MCU is in low-power wait, or stop3 mode. At power-on, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention.
For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In this series, re-initialize the stack pointer to the top of the RAM so that the direct-page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the equate file).
LDHX #RamLast+1 ;point one past RAM TXS ;SP<-(H:X-1)
When security is enabled, the RAM is considered a secure memory resource and is not accessible through BDM or code executing from non-secure memory.
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Flash and EEPROM

4.5 Flash and EEPROM

4.5.1 Overview

This device includes various configuration of flash and EEPROM. The controller for flash and EEPROM is ideal for single-supply applications for field programming without external high voltage sources for program or erase operations.
The flash memory is ideal for single-supply applications that allow for field reprogramming without requiring external high voltage sources for program or erase operations. The flash module includes a memory controller that executes commands to modify flash memory contents. The user interface to the memory controller consists of the indexed flash common command object (FCCOB) register, which is written to with the command, global address, data, and any required command parameters. The memory controller must complete the execution of a command before the FCCOB register is written to with a new command.
CAUTION
A flash byte or longword must be in the erased state before being programmed. Cumulative programming of bits within a flash byte or longword is not allowed.
The flash memory is read as bytes. Read access time is one bus cycle for bytes. For flash memory, an erased bit reads 1 and a programmed bit reads 0. It is possible to read from flash memory while commands are being executed on EEPROM memory. It is not possible to read from EEPROM memory while a command (erase/program) is executing on flash memory. Simultaneous EEPROM memory are implemented with error correction codes (ECC) that can resolve single bit faults and detect double bit faults.
The following figure shows the block diagram of the flash and EEPROM module.
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Divider
Clock
Command Interrupt Request
Protection
Registers
Security
Sector 1
Sector 1
Sector 7
Sector 0
Sector 0
FLASH
EEPROM
Interface
NVM controller
Bus Clock
Error Interrupt Request
CPU
1K
x3
2
128x8
Sector 63
Flash
Chapter 4 Memory map
Figure 4-2. Flash and EEPROM block diagram
Flash features:
• 4 KB of flash memory composed of one 4 KB flash block divided into 8 sectors of 512 bytes
• Automated program and erase algorithm with verification
• Fast sector erase and longword program operation
• Ability to read the flash memory while programming a word in the EEPROM memory
• Flexible protection scheme to prevent accidental program or erase of flash memory
EEPROM features:
• 128 bytes of EEPROM memory composed of one 128 byte EEPROM block divided into 64 sectors of 2 bytes
• Single bit fault correction and double bit fault detection within a word during read operations
• Automated program and erase algorithm with verification and generation of ECC parity bits
• Fast sector erase and byte program operation
• Protection scheme to prevent accidental program or erase of EEPROM memory
• Ability to program up to four bytes in a burst sequence
Other features
• No external high-voltage power supply required for flash memory program and erase operations
• Interrupt generation on flash command completion and flash error detection
• Security mechanism to prevent unauthorized access to the flash memory
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Flash and EEPROM

4.5.2 Function descriptions

4.5.2.1 Modes of operation
The flash and EEPROM module provides the normal user mode of operation. The operating mode is determined by module-level inputs and affects the FCLKDIV, FCNFG, and EEPROT registers.
4.5.2.1.1 Wait mode
The flash and EEPROM module is not affected if the MCU enters wait mode. The flash module can recover the MCU from wait via the CCIF interrupt. See Flash and EEPROM
interrupts.
4.5.2.1.2 Stop mode
If a flash and EEPROM command is active, that is, FSTAT[CCIF] = 0, when the MCU requests stop mode, the current NVM operation will be completed before the MCU is allowed to enter stop mode.
4.5.2.2
Flash and EEPROM memory map
The MCU places the flash memory between global address 0x0000 and 0xFFFF as shown in the following table. Not all flash are available to users because some addresses are overlapped with RAM, EEPROM, and registers.
MC9S08PA4 contains a piece of 4 KB flash that is fully available for users. This flash block is divided into 8 sectors of 512 bytes.
Table 4-6. Flash memory addressing
Device Global address Size (Bytes) Description User availability
MC9S08PA4 0xF000 — 0xFFFF 4 KB
Flash block contains flash configuration field
Sector [0:7]: fully available
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Chapter 4 Memory map
4.5.2.3 Flash and EEPROM initialization after system reset
On each system reset, the flash and EEPROM module executes an initialization sequence that establishes initial values for the flash and EEPROM block configuration parameters, the FPROT and EEPROT protection registers, and the FOPT and FSEC registers. The initialization routine reverts to built-in default values that leave the module in a fully protected and secured state if errors are encountered during execution of the reset sequence. If a double bit fault is detected during the reset sequence, both FSTAT[MGSTAT] bits will be set.
FSTAT[CCIF] is cleared throughout the initialization sequence. The NVM module holds off all CPU access for a portion of the initialization sequence. Flash and EEPROM reads are allowed after the hold is removed. Completion of the initialization sequence is marked by setting FSTAT[CCIF] high, which enables user commands.
If a reset occurs while any flash or EEPROM command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed.
4.5.2.4 Flash and EEPROM command operations
Flash and EEPROM command operations are used to modify flash and EEPROM memory contents.
The command operations contain three steps:
1. Configure the clock for flash or EEPROM program and erase command operations.
2. Use command write sequence to set flash and EEPROM command parameters and launch execution.
3. Execute valid flash and EEPROM commands according to MCU functional mode and MCU security state.
The figure below shows a general flowchart of the flash or EEPROM command write sequence.
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Read: FCLKDIV
START
FDIV
Read: FSTAT
Read: FSTAT
CCIF
Write: FCLKDIV
register
NOTE: FCLKDIV must be
set after each reset
Set?
CCIF
ACCERR
Results from previous Command
Write to FCCOBIX register
to identify specific command
parameter to load
Write to FCCOB register
to load required command
parameter
More
Write: FSTAT register
(to launch command)
Read: FSTAT register
CCIF Set?
Bit Polling for
Command Completion Check
Clear CCIF 0x80
Parameters?
Write: FSTAT register
Clear ACCERR
FPVIOL 0x30
or FPVIOL Set?
Access Error and
Protection Violation Check
Set?
No
No
No
Yes
Yes
Yes
No
Yes
END
register
No
No
Yes
Yes
Clock Divider
Value Check
FCCOB
Availability Check
register
Correct?
register
Flash and EEPROM
Figure 4-3. Generic flash and EEPROM command write sequence flowchart
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Chapter 4 Memory map
4.5.2.4.1 Writing the FCLKDIV register
Prior to issuing any flash and EEPROM program or erase command after a reset, the user is required to write the FCLKDIV register to divide BUSCLK down to a target FCLK of 1MHz. The following table shows recommended values for the FDIV field based on BUSCLK frequency.
Table 4-7. FDIV values for various BUSCLK frequencies
BUSCLK frequency
(MHz)
1
MIN
1.0 1.6 0x00
1.6 2.6 0x01
2.6 3.6 0x02
3.6 4.6 0x03
4.6 5.6 0x04
5.6 6.6 0x05
6.6 7.6 0x06
7.6 8.6 0x07
8.6 9.6 0x08
9.6 10.6 0x09
10.6 11.6 0x0A
11.6 12.6 0x0B
12.6 13.6 0x0C
13.6 14.6 0x0D
14.6 15.6 0x0E
15.6 16.6 0x0F
16.6 17.6 0x10
17.6 18.6 0x11
18.6 19.6 0x12
19.6 20.0 0x13
MAX
2
FDIV[5:0]
1. BUSCLK is greater than this value
2. BUSCLK is less than or equal to this value
CAUTION
Programming or erasing the flash and EEPROM memory cannot be performed if the bus clock runs at less than 0.8 MHz. Setting FCLKDIV[FDIV] too high can destroy the flash and EEPROM memory due to overstress. Setting FCLKDIV[FDIV] too low can result in incomplete programming or erasure of the flash and EEPROM memory cells.
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Flash and EEPROM
When the FCLKDIV register is written, the FCLKDIV[FDIVLD] bit is set automatically. If the FCLKDIV[FDIVLD] bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written, any flash and EEPROM program or erase command loaded during a command write sequence will not execute and the FSTAT[ACCERR] bit will be set.
4.5.2.4.2 Command write sequence
The memory controller will launch all valid flash and EEPROM commands entered using a command write sequence.
Before launching a command, the FSTAT[ACCERR] and FSTAT[FPVIOL] bits must be clear and the FSTAT[CCIF] flag will be tested to determine the status of the current command write sequence. If FSTAT[CCIF] is 0, indicating that the previous command write sequence is still active, a new command write sequence cannot be started and all writes to the FCCOB register are ignored.
The FCCOB parameter fields must be loaded with all required parameters for the flash and EEPROM command being executed. Access to the FCCOB parameter fields is controlled via FCCOBIX[CCOBIX] bits.
Flash and EEPROM command mode uses the indexed FCCOB register to provide a command code and its relevant parameters to the memory controller. First, the user must set up all required FCCOB field. Then they can initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This action clears the CCIF command completion flag to 0. When the user clears the FSTAT[CCIF] bit all FCCOB parameter field are locked and cannot be changed by the user until the command completes (evidenced by the memory controller returning FSTAT[CCIF] to1). Some commands return information to the FCCOB register array.
The generic format for the FCCOB parameter fields in flash and EEPROM command mode is shown in the following table. The return values are available for reading after the FSTAT[CCIF] flag has been returned to 1 by the memory controller. Writes to the unimplemented parameter fields, FCCOBIX[CCOBIX] =110b and FCCOBIX[CCOBIX] = 111b, are ignored with read from these fields returning 0x0000.
The table below shows the generic flash command format. The high byte of the first word in the CCOB array contains the command code, followed by the parameters for this specific flash command. For details on the FCCOB settings required by each command, see the flash command descriptions in Flash and EEPROM command summary .
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Chapter 4 Memory map
Table 4-8. FCCOB – flash and EEPROM command mode typical usage
CCOBIX[2:0] Byte FCCOB parameter fields in flash and EEPROM command mode
000
001
010
011
100
101
HI FCMD[7:0] defining flash command
LO Global address [23:16]
HI Global address [15:8]
LO Global address [7:0]
HI Data 0 [15:8]
LO Data 0 [7:0]
HI Data 1 [15:8]
LO Data 1 [7:0]
HI Data 2 [15:8]
LO Data 2 [7:0]
HI Data 3 [15:8]
LO Data 3 [7:0]
The contents of the FCCOB parameter fields are transferred to the memory controller when the user clears the FSTAT[CCIF] command completion flag by writing 1. The CCIF flag will remain clear until the flash and EEPROM command has completed. Upon completion, the memory controller will return FSTAT[CCIF] to 1 and the FCCOB register will be used to communicate any results.
The following table presents the valid flash and EEPROM commands, as enabled by the combination of the functional MCU mode with the MCU security state of unsecured or secured.
MCU secured state is selected by NVM_FSEC[SEC].
Table 4-9. Flash and EEPROM commands by mode and security state
FCMD Command
0x01 Erase verify all blocks * * 0x02 Erase verify block * * 0x03 Erase verify flash section * N/A 0x04 Read once * N/A 0x06 Program flash * N/A 0x07 Program once * N/A 0x08 Erase all block * * 0x09 Erase flash block * * 0x0A Erase flash sector * N/A 0x0B Unsecure NVM N/A *
0x0C Verify backdoor access key * *
Unsecured Secured
1
U
2
U
Table continues on the next page...
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Flash and EEPROM
Table 4-9. Flash and EEPROM commands by mode and security state (continued)
FCMD Command
0x0D Set user margin level * N/A
0x10 Erase verify EEPROM section * * 0x11 Program EEPROM * N/A 0x12 Erase EEPROM sector * N/A
1. Unsecured User mode
2. Secured User mode
Unsecured Secured
1
U
2
U
4.5.2.5 Flash and EEPROM interrupts
The flash and EEPROM module can generate an interrupt when a flash command operation has completed or when a flash and EEPROM command operation has detected an ECC fault.
Table 4-10. Flash interrupt source
Interrupt source Interrupt flag Local enable Global (CCR) mask
Flash and EEPROM command complete
ECC double bit fault on flash and EEPROM read
ECC single bit fault on flash and EEPROM read
CCIF
(FSTAT register)
DFDIF
(FERSTAT register)
SFDIF
(FERSTAT register)
(FERCNFG register)
(FERCNFG register)
CCIE
I Bit
(FCNFG register)
DFDIE
I Bit
SFDIE
I Bit
4.5.2.5.1 Description of flash and EEPROM interrupt operation
The flash module uses the FSTAT[CCIF] flag in combination with the FCNFG[CCIE] interrupt enable bit to generate the flash command interrupt request. The flash module uses the DFDIF and SFDIF flags in combination with the FERSTAT[DFDIE] and FERSTAT[SFDIE] interrupt enable bits to generate the flash error interrupt request.
The logic used for generating the flash module interrupts is shown in the following figure.
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CCIE
CCIF
SFDIF
Flash and EEPROM Command
Flash and EEPROM
Complete Interrupt Request
Error Interrupt Request
CPU Interrupt
Flash Configuration Field 16 bytes (0xFF70
0xFF7F)
Flash Protected/Unprotected Higher Region 1, 2, 3, 4Kbytes
Protection Fixed End
0x0000
Flash START = 0xF000
0xF400
0xFC00
0xFFFF
0xF800
Chapter 4 Memory map
Figure 4-4. Flash and EEPROM module interrupts implementation
4.5.2.6 Protection
The FPROT register can be set to protect regions in the flash memory from accidental programming or erasing. Two separate memory regions, one growing downward from global address 0xFFFF in the flash memory, called the higher region; and the remaining addresses in the flash memory, can be activated for protection. The flash memory addresses covered by these protectable regions are shown in the flash memory map. The higher address region is mainly targeted to hold the boot loader code because it covers the vector space.
Default protection settings as well as security information that allows the MCU to restrict access to the flash module are stored in the flash configuration field as described in the table below.
NXP Semiconductors 65
Figure 4-5. Flash protection memory map
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Flash and EEPROM
Table 4-11. Flash configuration field
Global address Size (Bytes) Description
0xFF70 — 0xFF77
0xFF78 — 0xFF7B 4 Reserved
0xFF7C 0xFF7D 0xFF7E 0xFF7F
1. 0xFF78–0xFF7F for a flash phrase and must be programmed in a single command write sequence. Each byte in the 0xFF78-0xFF7B reserved field must be programmed to 0xFF.
1
1
1
1
1
8
1 Flash protection byte 1 EEPROM protection byte 1 Flash nonvolatile byte 1 Flash security byte
Backdoor comparison key. See Verify backdoor access key command and
Unsecuring the MCU using backdoor key access.
The flash and EEPROM module provides protection to the MCU. During the reset sequence, the FPROT register is loaded with the contents of the flash protection byte in the flash configuration field at global address 0xFF7C in flash memory. The protection functions depend on the configuration of bit settings in FPORT register.
Table 4-12. Flash protection function
FPOPEN FPHDIS Function
1 1 No flash protection 1 0 Protected high range 0 1 Full flash memory protected 0 0 Unprotected high range
1
1. For range size, seeTable 4.
The flash protection scheme can be used by applications requiring reprogramming in single chip mode while providing as much protection as possible if reprogramming is not required.
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FPHDIS = 1
FPHDIS = 0
Protected region not defined by FPHS
Unprotected region
Protected region with size defined by FPHS
FPHS[1:0]
FPOPEN = 1
FPOPEN = 1
Scenario 3
Scenario 2
Scenario 1
Scenario 0
Flash Start Address
0xFFFF
FPOPEN = 0
FPOPEN = 0
FPHDIS = 1
FPHDIS = 0
Figure 4-6. Flash protection scenarios
Chapter 4 Memory map
The general guideline is that flash protection can only be added and not removed. The following table specifies all valid transitions between flash protection scenarios. Any attempt to write an invalid scenario to the FPROT register will be ignored. The contents of the FPROT register reflect the active protection scenario. See the FPROT[FPHS] and FPROT[FPLS] bit descriptions for additional restrictions.
The flash protection address range is listed in the following two tables regarding the scenarios in the table above.
Table 4-13. Flash protection scenario transitions
From protection
scenario
0 × × 1 × 2 × × 3 × × × ×
0 1 2 3
To protection scenario
Table 4-14. Flash protection higher address range
FPHS[1:0] Global address range Protected size
00 0xFC00 – 0xFFFF 1 Kbytes 01 0xF800 – 0xFFFF 2 Kbytes 10 0xF400 – 0xFFFF 3 Kbytes 11 0xF000 – 0xFFFF 4 Kbytes
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During the reset sequence, fields NVM_EEPROT[DPOPEN] and NVM_EEPROT[DPS] are loaded with the contents of the EEPROM protection byte in the flash configuration field at global address 0xFF7D located in flash memory. EEPROM protection address range is specified by the NVM_EEPROT[DPS].
Table 4-15. EEPROM protection address range
DPS[1:0] Global address range Protected size
00 0x3100 – 0x311F 32 bytes 01 0x3100 – 0x313F 64 bytes 10 0x3100 – 0x315F 96 bytes 11 0x3100 – 0x317F 128 bytes
All possible flash protection scenarios are shown in Figure 4-6. Although the protection scheme is loaded from the flash memory at global address 0xFF7C during the reset sequence, it can be changed by the user.
4.5.2.7 Security
The flash and EEPROM module provides security information to the MCU. The flash security state is defined by the NVM_FSEC[SEC] bits. During reset, the flash module initializes the NVM_FSEC register using data read from the security byte of the flash and EEPROM configuration field at global address 0xFF7F. The security state out of reset can be permanently changed by programming the security byte, assuming that the MCU is starting from a mode where the necessary flash and EEPROM erase and program commands are available and that the upper region of the flash is unprotected. If the flash security byte is successfully programmed, its new value will take affect after the next MCU reset.
The following subsections describe these security-related subjects:
• Unsecuring the MCU using backdoor key access
• Unsecuring the MCU using BDM
• Mode and security effects on flash and EEPROM command availability
4.5.2.7.1
Unsecuring the MCU using backdoor key access
The MCU may be unsecured by using the backdoor key access feature which requires knowledge of the contents of the backdoor keys, which are four 16-bit words programmed at addresses 0xFF70–0xFF77. If the KEYEN[1:0] bits are in the enabled
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state, the verify backdoor access key command – see Verify backdoor access key
command, allows the user to present four prospective keys for comparison to the keys
stored in the flash and EEPROM memory via the memory controller. If the keys presented in the verify backdoor access key command match the backdoor keys stored in the flash and EEPROM memory, the FSEC[SEC] bits will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not permitted as backdoor keys. While the Verify Backdoor Access Key command is active, flash memory and EEPROM memory will not be available for read access and will return invalid data.
The user code stored in the flash memory must have a method of receiving the backdoor keys from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports.
If the KEYEN[1:0] bits are in the enabled state, the MCU can be unsecured by the backdoor key access sequence described below:
1. Follow the command sequence for the verify backdoor access key command as explained in Verify backdoor access key command.
2. If the verify backdoor access key command is successful, the MCU is unsecured and the FSEC[SEC] bits are forced to the unsecure state of 10.
The verify backdoor access key command is monitored by the memory controller and an illegal key will prohibit future use of the verify backdoor access key command. A reset of the MCU is the only method to re-enable the verify backdoor access key command. The security as defined in the flash and EEPROM security byte (0xFF7F) is not changed by using the verify backdoor access key command sequence. The backdoor keys stored in addresses 0xFF70–0xFF77 are unaffected by the verify backdoor access key command sequence. The verify backdoor access key command sequence has no effect on the program and erase protections defined in the flash and EEPROM protection register, FPORT.
After the backdoor keys have been correctly matched, the MCU will be unsecured. After the MCU is unsecured, the sector containing the flash and EEPROM security byte can be erased and the flash and EEPROM security byte can be reprogrammed to the unsecure state, if desired. In the unsecure state, the user has full control of the contents of the backdoor keys by programming addresses 0xFF70–0xFF77 in the flash configuration field.
4.5.2.7.2
Unsecuring the MCU using BDM
A secured MCU can be unsecured by using the following method to erase the flash and EEPROM memory:
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1. Reset the MCU.
2. Set FCDIV register as described in Writing the FCLKDIV register.
3. Configure registers NVM_FERSTAT and NVM_FPROT to disable protection in the flash and EEPROM memory.
4. Execute the erase all blocks command write sequence to erase the flash and EEPROM memory. Alternately, the unsecure NVM command can be executed.
If the flash and EEPROM memory are verified as erased, the MCU will be unsecured. All BDM. commands will now be enabled and the flash security byte may be programmed to the unsecure state by continuing with the steps that follow.
5. Execute the program flash command write sequence to program the flash security byte to the unsecured state.
6. Reset the MCU.
4.5.2.7.3 Mode and security effects on flash and EEPROM command availability
The availability of flash and EEPROM module commands depends on the MCU operating mode and security state as shown in Table 4-9.
4.5.2.8
Flash and EEPROM commands
4.5.2.8.1 Flash commands
The following table summarizes the valid flash commands as well as the effects of the commands on the flash block and other resources within the flash and EEPROM module.
Table 4-16. Flash commands
FCMD Command Function on flash memory
0x01 Erase verify all blocks Verify that all flash (and EEPROM) blocks are erased 0x02 Erase verify block Verify that a flash block is erased 0x03 Erase verify flash section Verify that a given number of words starting at the address provided are erased
0x04 Read Once
0x06 Program flash Program up to two longwords in a flash block
0x07 Program once
0x08 Erase all block Erase all flash and EEPROM blocks
Read a dedicated 64 byte field in the nonvolatile information register in flash block that was previously programmed using the program once command
Program a dedicated 64 byte field in the nonvolatile information register in flash block that is allowed to be programmed only once
Table continues on the next page...
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Table 4-16. Flash commands (continued)
FCMD Command Function on flash memory
An erase of all flash blocks is possible only when the FPROT[FPHDIS], and FPROT[FPOEN] bits and the EEPROT[DPOPEN] bit are set prior to launching the command
Erase a flash or EEPROM block
0x09 Erase flash block
0x0A Erase flash sector Erase all bytes in a flash sector
0x0B Unsecure flash
0x0C Verify backdoor access key Supports a method of releasing MCU security by verifying a set of security keys 0x0D Set user margin level Specifies a user margin read level for all flash blocks
An erase of the full flash block is possible only when FPROT[FPHDIS], and FPROT[FPOEN] bits are set prior to launching the command
Supports a method of releasing MCU security by erasing all flash (and EEPROM) blocks and verifying that all flash (and EEPROM) blocks are erased
4.5.2.8.2 EEPROM commands
The following table summarizes the valid EEPROM commands along with the effects of the commands on the EEPROM block.
Table 4-17. EEPROM commands
FCMD Command Function on flash memory
0x01 Erase verify all blocks Verify that all EEPROM (and flash) blocks are erased. 0x02 Erase verify block Verify that an EEPROM block is erased.
Erase all EEPROM and flash blocks
0x08 Erase all block
0x09 Erase EEPROM Block
0x0B Unsecure EEPROM
0x0D Set User Margin Level Specifies a user margin read level for all flash blocks.
0x10
0x11 Program EEPROM Program up to four bytes in the EEPROM block. 0x12 Erase EEPROM Sector Erase all bytes in a sector of the EEPROM block.
Erase Verify EEPROM
Section
An erase of all EEPROM blocks is possible only when the FPROT[FPHDIS], and FPROT[FPOEN] bits and the DPOPEN bit in the EEPORT register are set prior to launching the command.
Erase a EEPROM and flash block An erase of the full flash block is possible only when FPROT[FPHDIS] and
FPROT[FPOPEN] bits are set prior to launching the command. Supports a method of releasing MCU security by erasing all EEPROM and flash
blocks and verifying that all EEPROM and flash blocks are erased.
Verify that a given number of bytes starting at the address provided are erased.
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4.5.2.8.3 Allowed simultaneous flash and EEPROM operations
Only the operations marked 'OK' in the following table are permitted to be run simultaneously on the flash and EEPROM blocks. Some operations cannot be executed simultaneously because certain hardware resources are shared by the two memories. The priority has been placed on permitting flash reads while program and erase operations execute on the EEPROM, providing read (flash) while write (EEPROM) functionality.
Table 4-18. Allowed simultaneous flash and EEPROM operations
Program flash
Read OK OK OK
Margin Read
Program Sector Erase Mass Erase
1. A 'Margin read' is any read after executing the margin setting commands 'Set user margin level' or 'Set field margin level' with anything but the 'normal' level specified. See the Note on margin settings in
2. The 'Mass erase' operations are commands 'Erase all blocks' and 'Erase flash block'
1
2
Read Margin read Program Sector erase Mass erase
EEPROM
OK
4.5.2.9 Flash and EEPROM command summary
This section provides details of all available flash commands launched by a command write sequence. The FSTAT[ACCERR] bit will be set during the command write sequence if any of the following illegal steps are performed, causing the command not to be processed by the memory controller:
• Starting any command write sequence that programs or erases flash memory before initializing the FLCKDIV register.
• Writing an invalid command as part of the command write sequence.
• For additional possible errors, refer to the error handling table provided for each command.
If a flash block is read during the execution of an algorithm (FSTAT[CCIF] = 0) on that same block, the read operation will return invalid data if both flags FERSTAT[SFDIF] and FERSTAT[DFDIF] are set. If the FERSTAT[SFDIF] or FERSTAT[DFDIF] flags were not previously set when the invalid read operation occurred, both the FERSTAT[SFDIF] and FERSTAT[DFDIF] flags will be set.
If the FSTAT[ACCERR] or FSTAT[FPVIOL] bits are set, the user must clear these bits before starting any command write sequence.
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CAUTION
An EEPROM byte or flash longword must be in the erased state before being programmed. Cumulative programming of bits within an EEPROM byte or flash longword is not allowed.
4.5.2.9.1 Erase verify all blocks command
The erase verify all blocks command will verify that all flash and EEPROM blocks have been erased.
Table 4-19. Erase verify all blocks command FCCOB requirements
CCOBIX[2:0] NVM_FCCOBHI parameters NVM_FCCOBLO parameters
000 0x01 Not required
Upon clearing NVM_FSTAT[CCIF] to launch the erase verify all blocks command, the memory controller will verify that the entire flash memory space is erased. The NVM_FSTAT[CCIF] flag will set after the erase verify all blocks operation has completed. If all blocks are not erased, it means blank check failed and both NVM_FSTAT[MGSTAT] bits will be set.
Table 4-20. Erase verify all blocks command error handling
Register Error bit Error condition
ACCERR Set if CCOBIX[2:0] != 000 at command launch
FPVIOL None
NVM_FSTAT
1. As found in the memory map for NVM
MGSTAT1
MGSTAT0
Set if any errors have been encountered during the read1 or if blank check failed
Set if any non-correctable errors have been encountered during the read or if blank check failed
4.5.2.9.2 Erase verify block command
The erase verify block command allows the user to verify that an entire flash or EEPROM block has been erased. The FCCOB global address [23:0] bits determine which block must be verified.
Table 4-21. Erase verify block command FCCOB requirements
CCOBIX[2:0] NVM_FCCOBHI parameters NVM_FCCOBLO parameters
000 0x02 Global address [23:16] to identify Flash block 001 Global address [15:0] in flash block to be verified
1
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1. Global address [23] selects between flash (0) or EEPROM (1) block, that can otherwise eventually share the same address on the MCU global memory map.
Upon clearing NVM_FSTAT[CCIF] to launch the erase verify block command, the memory controller will verify that the selected flash or EEPROM block is erased. The NVM_FSTAT[CCIF] flag will set after the erase verify block operation has completed. If the block is not erased, it means blank check failed and both NVM_FSTAT[MGSTAT] bits will be set.
Table 4-22. Erase verify block command error handling
Register Error bit Error condition
ACCERR
FPVIOL None
FSTAT
MGSTAT1
MGSTAT0
Set if CCOBIX[2:0] != 000 at command launch Set if an invalid global address [23:0] is supplied
Set if any errors have been encountered during the read or if blank check failed
Set if any non-correctable errors have been encountered during the read or if blank check failed
1
1. As found in the memory map for NVM
4.5.2.9.3 Erase verify flash section command
The erase verify flash section command will verify that a section of code in the flash memory is erased. The erase verify flash section command defines the starting point of the code to be verified and the number of longwords.
Table 4-23. Erase verify flash section command FCCOB requirements
CCOBIX[2:0] NVM_FCCOBHI parameters NVM_FCCOBLO parameters
000 0x03 Global address [23:16] of flash block 001 Global address [15:0] of the first longwords to be verified 010 Number of long words to be verified
Upon clearing NVM_FSTAT[CCIF] to launch the erase verify flash section command, the memory controller will verify that the selected section of flash memory is erased. The NVM_FSTAT[CCIF] flag will set after the erase verify flash section operation has completed. If the section is not erased, it means blank check failed and both FSTAT[MGSTAT] bits will be set.
Table 4-24. Erase verify flash section command error handling
Register Error bit Error condition
FSTAT ACCERR Set if CCOBIX[2:0] != 010 at command launch
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Table 4-24. Erase verify flash section command error handling (continued)
Register Error bit Error condition
Set if command not available in current mode (see Table 4-9)
1
2
FPVIOL None
MGSTAT1
MGSTAT0
1. As defined by the memory map for NVM
2. As found in the memory map for NVM
Set if an invalid global address [23:0] is supplied (see Table 4-6) Set if a misaligned long words address is supplied (global address[1:0] !=
00) Set if the requested section crosses flash address boundary
Set if any errors have been encountered during the read2 or if blank check failed
Set if any non-correctable errors have been encountered during the read or if blank check failed
4.5.2.9.4 Read once command
The read once command provides read access to a reserved 64 byte field (8 phrase) located in the nonvolatile information register of flash. The read once field can only be programmed once and can not be erased. It can be used to store the product ID or any other information that can be written only once. It is programmed using the program once command described in Program once command. To avoid code runaway, the read once command must not be executed from the flash block containing the program once reserved field.
Table 4-25. Read once command FCCOB requirements
CCOBIX[2:0] FCCOB parameters
000 0x04 Not required 001 Read once phrase index (0x0000 – 0x0007) 010 Read once word 0 value 011 Read once word 1 value 100 Read once word 2 value 101 Read once word 3 value
Upon clearing FSTAT[CCIF] to launch the read once command, a read once phrase is fetched and stored in the FCCOB indexed register. The FSTAT[CCIF] flag will set after the read once operation has completed. Valid phrase index values for the read once command range from 0x0000 to 0x0007. During execution of the read once command, any attempt to read addresses within flash block will return invalid data.
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Table 4-26. Read once command error handling
Register Error bit Error condition
Set if CCOBIX[2:0] != 001 at command launch
FSTAT
ACCERR
FPVIOL None MGSTAT1 Set if any errors have been encountered during the read MGSTAT0 Set if any non-correctable errors have been encountered during the read
Set if command is not available in current mode (see Table 4-9) Set if an invalid phrase index is supplied
4.5.2.9.5 Program flash command
The program flash operation will program up to two previously erased longwords in the flash memory using an embedded algorithm.
Note
A flash phrase must be in the erased state before being programmed. Cumulative programming of bits within a flash phrase is not allowed.
Table 4-27. Program flash command FCCOB requirements
CCOBIX[2:0] NVM_FCCOBHI parameters NVM_FCCOBLO parameters
000 0x06 Global address [23:16] to identify flash block 001 Global address [15:0] of longwords location to be programmed 010 Word 0 (longword 0) program value 011 Word 1 (longword 0) program value 100 Word 2 (longword 1) program value 101 Word 3 (longword 1) program value
1. Global address [1:0] must be 00.
1
Upon clearing NVM_FSTAT[CCIF] to launch the program flash command, the memory controller will program the data words to the supplied global address and will then proceed to verify the data words read back as expected. The NVM_FSTAT[CCIF] flag will set after the program flash operation has completed.
Table 4-28. Program flash command error handling
Register Error bit Error condition
Set if CCOBIX[2:0] ≠ 011 or 101 at command launch
NVM_FSTAT ACCERR
Set if command not available in current mode (see Table 4-9) Set if an invalid global address [23:0] is supplied (see Table 4-6)
1
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Table 4-28. Program flash command error handling (continued)
Register Error bit Error condition
Set if a misaligned longword address is supplied (global address [1:0] !=
00) Set if the requested group of words breaches the end of the flash block.
FPVIOL Set if the global address [23:0] points to a protected data MGSTAT1 Set if any errors have been encountered during the verify operation
MGSTAT0
1. As defined by the memory map of NVM
Set if any non-correctable errors have been encountered during the verify operation
4.5.2.9.6 Program once command
The program once command restricts programming to a reserved 64 byte field (8 phrases) in the nonvolatile information register located in flash. The program once reserved field can be read using the read once command as described in Read once command. The program once command must be issued only because the nonvolatile information register in flash cannot be erased. To avoid code runaway, the read once command must not be executed from the flash block containing the program once reserved field.
Table 4-29. Program once command FCCOB requirements
CCOBIX[2:0] FCCOB parameters
000 0x07 Not required 001 Program Once phrase index (0x000 – 0x0007) 010 Program once Word 0 value 011 Program once Word 1value 100 Program once Word 2 value 101 Program once Word 3 value
Upon clearing FSTAT[CCIF] to launch the program once command, the memory controller first verifies that the selected phrase is erased. If erased, then the selected phrase will be programmed and then verified with read back. The FSTAT[CCIF] flag will remain clear, setting only after the program once operation has completed.
The reserved nonvolatile information register accessed by the program once command cannot be erased, and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index values for the program once command range from 0x0000 to 0x0007. During execution of the program once command, any attempt to read addresses within flash will return invalid data.
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Table 4-30. Program once command error handling
Register Error bit Error condition
Set if CCOBIX[2:0] != 101 at command launch
ACCERR
FSTAT
FPVIOL None MGSTAT1 Set if any errors have been encountered during the verify operation
MGSTAT0
1. If a program once phrase is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the program once command will be allowed to execute again on that same phrase.
Set if command not available in current mode (see Table 4-9) Set if an invalid phrase index is supplied Set if the requested phrase has already been programmed
Set if any non-correctable errors have been encountered during the verify operation
1
4.5.2.9.7 Erase all blocks command
The erase all blocks operation will erase the entire flash and EEPROM memory space.
Table 4-31. Erase all blocks command FCCOB requirements
CCOBIX[2:0] NVM_FCCOBHI parameters NVM_FCCOBLO parameters
000 0x08 Not required
Upon clearing NVM_FSTAT[CCIF] to launch the erase all blocks command, the memory controller will erase the entire NVM memory space and verify that it is erased. If the memory controller verifies that the entire NVM memory space was properly erased, security will be released. Therefore, the device is in unsecured state. During the execution of this command (NVM_FSTAT[CCIF] = 0) the user must not write to any NVM module register. The NVM_FSTAT[CCIF] flag will set after the erase all blocks operation has completed.
Table 4-32. Erase all blocks command error handling
Register Error bit Error condition
Set if CCOBIX[2:0] ≠ 000 at command launch Set if command not available in current mode (see Table 4-9)
1
Set if any non-correctable errors have been encountered during the verify operation
1
NVM_FSTAT
ACCERR
FPVIOL Set if any area of the flash or EEPROM memory is protected
MGSTAT1 Set if any errors have been encountered during the verify operation
MGSTAT0
1. As found in the memory map for NVM
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4.5.2.9.8 Erase flash block command
The erase flash block operation will erase all addresses in a flash or EEPROM block.
Table 4-33. Erase flash block command FCCOB requirements
CCOBIX[2:0] FCCOB parameters
000 0x09 Global address [23:16] to identify flash block 001 Global address[15:0] in flash block to be erased
1. Global address [23] selects between flash (0) or EEPROM (1) block, that can otherwise eventually share the same address on the MCU global memory map.
1
Upon clearing FSTAT[CCIF] to launch the erase flash block command, the memory controller will erase the selected flash block and verify that it is erased. The FSTAT[CCIF] flag will set after the erase flash block operation has completed.
Table 4-34. Erase flash block command error handling
Register Error Bit Error Condition
Set if CCOBIX[2:0] != 001 at command launch
FSTAT
ACCERR
FPVIOL Set if an area of the selected flash block is protected
MGSTAT1 Set if any errors have been encountered during the verify operation
MGSTAT0
Set if command not available in current mode (see Table 4-9) Set if an invalid global address [23:16] is supplied
Set if any non-correctable errors have been encountered during the verify operation
2
1
2
1. As defined by the memory map for NVM
2. As found in the memory map for NVM
4.5.2.9.9 Erase flash sector command
The erase flash sector operation will erase all addresses in a flash sector.
Table 4-35. Erase flash sector command FCCOB requirements
CCOBIX[2:0] FCCOB parameters
000 0x0A Global address [23:16] to identify flash block to be erased
001
Global address [15:0] anywhere within the sector to be erased. Refer to Overview for the flash
sector size
Upon clearing FSTAT[CCIF] to launch the erase flash sector command, the memory controller will erase the selected flash sector and then verify that it is erased. The FSTAT[CCIF] flag will be set after the erase flash sector operation has completed.
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Table 4-36. Erase flash sector command error handling
Register Error bit Error condition
Set if CCOBIX[2:0] != 001 at command launch Set if command not available in current mode (see Table 4-9)
ACCERR
FSTAT
FPVIOL Set if the selected flash sector is protected
MGSTAT1 Set if any errors have been encountered during the verify operation
MGSTAT0
1. As defined by the memory map for NVM
Set if an invalid global address [23:16] is supplied.1 (see Table 4-6) Set if a misaligned longword address is supplied (global address [1:0] !=
00)
Set if any non-correctable errors have been encountered during the verify operation
4.5.2.9.10 Unsecure flash command
The unsecure flash command will erase the entire flash and EEPROM memory space, and if the erase is successful, will release security.
Table 4-37. Unsecure flash command FCCOB requirements
CCOBIX[2:0] FCCOB parameters
000 0x0B Not required
Upon clearing FSTAT[CCIF] to launch the unsecure flash command, the memory controller will erase the entire flash and EEPROM memory space and verify that it is erased. If the memory controller verifies that the entire flash and EEPROM memory space was properly erased, security will be released. If the erase verify is not successful, the unsecure flash operation sets FSTAT[MGSTAT1] and terminates without changing the security state. During the execution of this command (FSTAT[CCIF] = 0), the user must not write to any flash and EEPROM module register. The FSTAT[CCIF] flag is set after the unsecure flash operation has completed.
Table 4-38. Unsecure flash command error handling
Register Error bit Error condition
Set if CCOBIX[2:0] != 000 at command launch Set if command is not available in current mode (see Table 4-9)
1
Set if any non-correctable errors have been encountered during the verify operation
1
FSTAT
ACCERR
FPVIOL Set if any area of the flash or EEPROM memory is protected
MGSTAT1 Set if any errors have been encountered during the verify operation
MGSTAT0
1. As found in the memory map for NVM
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4.5.2.9.11 Verify backdoor access key command
The verify backdoor access key command will execute only if it is enabled by the NVM_FSEC[KEYEN] bits. The verify backdoor access key command releases security if user-supplied keys match those stored in the flash security bytes of the flash configuration field. See Table 4-6 for details. The code that performs verifying backdoor access command must be running from RAM or EEPROM.
Table 4-39. Verify backdoor access key command FCCOB requirements
CCOBIX[2:0] NVM_FCCOBHI parameters NVM_FCCOBLO parameters
000 0x0C Not required 001 Key 0 010 Key 1 011 Key 2 100 Key 3
Upon clearing NVM_FSTAT[CCIF] to launch the verify backdoor access key command, the memory controller will check the NVM_FSEC[KEYEN] bits to verify that this command is enabled. If not enabled, the memory controller sets the NVM_FSTAT[ACCERR] bit. If the command is enabled, the memory controller compares the key provided in FCCOB to the backdoor comparison key in the flash configuration field with Key 0 compared to 0xFF70, and so on. If the backdoor keys match, security will be released. If the backdoor keys do not match, security is not released and all future attempts to execute the verify backdoor access key command are aborted (set NVM_FSTAT[ACCERR]) until a reset occurs. The NVM_FSTAT[CCIF] flag is set after the verify backdoor access key operation has completed.
Table 4-40. Verify backdoor access key command error handling
Register Error bit Error condition
Set if CCOBIX[2:0] ≠ 100 at command launch
ACCERR
NVM_FSTAT
FPVIOL None MGSTAT1 None MGSTAT0 None
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Set if an incorrect backdoor key is supplied Set if backdoor key access has not been enabled (KEYEN[1:0] ≠ 10 Set if the backdoor key has mismatched since the last reset
Flash and EEPROM
4.5.2.9.12 Set user margin level command
The user margin is a small delta to the normal read reference level and, in effect, is a minimum safety margin. That is, if the reads pass at the tighter tolerances of the user margins, the normal reads have at least that much safety margin before users experience data loss.
The set user margin level command causes the memory controller to set the margin level for future read operations of the flash or EEPROM block.
Table 4-41. Set user margin level command FCCOB requirements
CCOBIX[2:0] NVM_FCCOBHI parameters NVM_FCCOBLO parameters
000 0x0D Global address [23:16] to identify flash block 001 Global address [15:0] to identify flash block 010 Margin level setting
1. Global Address [23] selects between flash (0) or EEPROM (1) block, that can otherwise eventually share the same address on the MCU global memory map.
1
Upon clearing NVM_FSTAT[CCIF] to launch the set user margin level command, the memory controller will set the user margin level for the targeted block and then set the NVM_FSTAT[CCIF] flag.
Note
When the EEPROM block is targeted, the EEPROM user margin levels are applied only to the EEPROM reads. However, when the Flash block is targeted, the flash user margin levels are applied to both Flash and EEPROM reads. It is not possible to apply user margin levels to the flash block only.
Valid margin level settings for the set user margin level command are defined in the following tables.
Table 4-42. Valid set user margin level settings
CCOB
(CCOBIX = 010)
0x0000 Return to normal level 0x0001 User margin-1 level 0x0002 User margin-0 level
1. Read margin to the erased state
2. Read margin to the programmed state
Level description
1
2
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Table 4-43. Set user margin level command error handling
Register Error bit Error condition
Set if CCOBIX[2:0] != 010 at command launch
ACCERR
NVM_FSTAT
FPVIOL None MGSTAT1 None MGSTAT0 None
Set if command is not available in current mode (see Table 4-9) Set if an invalid global address [23:0] is supplied Set if an invalid margin level setting is supplied
Note
User margin levels can be used to check that NVM memory contents have adequate margin for normal level read operations. If unexpected results are encountered when checking NVM memory contents at user margin levels, a potential loss of information has been detected.
Chapter 4 Memory map
4.5.2.9.13
Erase verify EEPROM section command
The erase verify EEPROM section command will verify that a section of code in the EEPROM is erased. The erase verify EEPROM section command defines the starting point of the data to be verified and the number of bytes.
Table 4-44. Erase verify EEPROM section command FCCOB requirements
CCOBIX[2:0] NVM_FCCOBHI parameters NVM_FCCOBLO parameters
000 0x10 Global address [23:16] to identify the EEPROM block 001 Global address [15:0] of the first byte to be verified 010 Number of bytes to be verified
Upon clearing NVM_FSTAT[CCIF] to launch the erase verify that EEPROM section command, the memory controller will verify the selected section of EEPROM memory is erased. The NVM_FSTAT[CCIF] flag will set after the erase verify EEPROM section operation has completed. If the section is not erased, which means that blank check failed, both NVM_FSTAT[MGSTAT] bits will be set.
Table 4-45. Erase verify EEPROM section command error handling
Register Error bit Error condition
FSTAT ACCERR
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Set if CCOBIX[2:0] ≠ 010 at command launch Set if command is not available in current mode (see Table 4-9)
Table continues on the next page...
Flash and EEPROM
Table 4-45. Erase verify EEPROM section command error handling (continued)
Register Error bit Error condition
Set if an invalid global address [23:0] is supplied Set if the requested section breaches the end of the EEPROM block
FPVIOL None
MGSTAT1
MGSTAT0
Set if any errors have been encountered during the read or if blank check failed
Set if any non-correctable errors have been encountered during the read or it blank check failed.
4.5.2.9.14 Program EEPROM command
The program EEPROM operation programs one to four previously erased bytes in the EEPROM block. The program EEPROM operation will confirm that the targeted location(s) were successfully programmed upon completion.
Note
A EEPROM byte must be in the erased state before being programmed. Cumulative programming of bits within a EEPROM byte is not allowed.
Table 4-46. Program EEPROM command FCCOB requirements
CCOBIX[2:0] NVM_FCCOBHI parameters NVM_FCCOBLO parameters
000 0x11 Global address [23:16] to identify the EEPROM block 001 Global address [15:0] of the first word to be verified 010 Byte 0 program value 011 Byte 1 program value, if desired 100 Byte 2 program value, if desired 101 Byte 3 program value, if desired
Upon clearing NVM_FSTAT[CCIF] to launch the program EEPROM command, the user-supplied words will be transferred to the memory controller and be programmed if the area is unprotected. The CCOBIX index value at program EEPROM command launch determines how many bytes will be programmed in the EEPROM block. The NVM_FSTAT[CCIF] flag is set when the operation has completed.
Table 4-47. Program EEPROM command error handling
Register Error Bit Error condition
NVM_FSTAT ACCERR
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Set if CCOBIX[2:0] < 010 at command launch Set if CCOBIX[2:0] >101 at command launch
Table continues on the next page...
Chapter 4 Memory map
Table 4-47. Program EEPROM command error handling (continued)
Register Error Bit Error condition
Set if command is not available in current mode (see Table 4-9) Set if an invalid global address [23:0] is supplied Set if the requested group of words breaches the end of the EEPROM
block
FPVIOL Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation
MGSTAT0
Set if any non-correctable errors have been encountered during the verify operation
4.5.2.9.15 Erase EEPROM sector command
The erase EEPROM sector operation will erase all addresses in a sector of the EEPROM block.
Table 4-48. Erase EEPROM sector command FCCOB requirements
CCOBIX[2:0] NVM_FCCOBHI parameters NVM_FCCOBLO parameters
000 0x12 Global address [23:16] to identify EEPROM block
001
Global address [15:0] anywhere within the sector to be erased. See Overview for EEPROM sector
size
Upon clearing NVM_FSTAT[CCIF] to launch the erase EEPROM sector command, the memory controller will erase the selected EEPROM sector and verify that it is erased. The NVM_FSTAT[CCIF] flag will set after the erase EEPROM sector operation has completed.
Table 4-49. Erase EEPROM sector command error handling
Register Error bit Error condition
Set if CCOBIX[2:0] ≠ 001 at command launch
NVM_FSTAT
ACCERR
FPVIOL Set if the selected area of the EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation
MGSTAT0
Set if command is not available in current mode (see Table 4-9) Set if an invalid global address [23:0] is supplied (see Table 4-6)
Set if any non-correctable errors have been encountered during the verify operation
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Flash and EEPROM registers descriptions

4.6 Flash and EEPROM registers descriptions
The flash module contains a set of 16 user control and status registers located between 0x3020 and 0x302F. In the case of the writable registers, the write accesses are forbidden during flash command execution. For more details, see Caution note in Flash and
EEPROM memory map. A summary of the flash module registers is given in the
following table with detailed descriptions in the following subsections.
NVM memory map
Absolute
address
(hex)
3020 Flash Clock Divider Register (NVM_FCLKDIV) 8 R/W 00h 4.6.1/86 3021 Flash Security Register (NVM_FSEC) 8 R Undefined 4.6.2/87 3022 Flash CCOB Index Register (NVM_FCCOBIX) 8 R/W 00h 4.6.3/88 3024 Flash Configuration Register (NVM_FCNFG) 8 R/W 00h 4.6.4/88 3025 Flash Error Configuration Register (NVM_FERCNFG) 8 R/W 00h 4.6.5/89 3026 Flash Status Register (NVM_FSTAT) 8 R/W 80h 4.6.6/90 3027 Flash Error Status Register (NVM_FERSTAT) 8 R/W 00h 4.6.7/91 3028 Flash Protection Register (NVM_FPROT) 8 R Undefined 4.6.8/92 3029 EEPROM Protection Register (NVM_EEPROT) 8 R/W Undefined 4.6.9/93
302A
302B
302C Flash Option Register (NVM_FOPT) 8 R Undefined 4.6.12/95
Flash Common Command Object Register:High (NVM_FCCOBHI)
Flash Common Command Object Register: Low (NVM_FCCOBLO)
Register name
Width
(in bits)
Access Reset value
8 R/W 00h 4.6.10/94
8 R/W 00h 4.6.11/95
4.6.1 Flash Clock Divider Register (NVM_FCLKDIV)
Section/
page
The FCLKDIV register is used to control timed events in program and erase algorithms.
NOTE
The FCLKDIV register must not be written while a flash command is executing (NVM_FSTAT[CCIF] = 0)
Address:
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3020h base + 0h offset = 3020h
Bit 7 6 5 4 3 2 1 0
Read FDIVLD
Write
Reset
0 0 0 0 0 0 0 0
FDIVLCK FDIV
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NVM_FCLKDIV field descriptions
Field Description
7
FDIVLD
6
FDIVLCK
FDIV Clock Divider Bits
Clock Divider Loaded
0 FCLKDIV register has not been written since the last reset. 1 FCLKDIV register has been written since the last reset.
Clock Divider Locked
0 FDIV field is open for writing. 1 FDIV value is locked and cannot be changed. After the lock bit is set high, only reset can clear this bit
and restore writability to the FDIV field in user mode.
FDIV[5:0] must be set to effectively divide BUSCLK down to 1MHz to control timed events during flash program and erase algorithms. Refer to the table in the Writing the FCLKDIV register for the recommended values of FDIV based on the BUSCLK frequency.
4.6.2 Flash Security Register (NVM_FSEC)
Chapter 4 Memory map
The FSEC register holds all bits associated with the security of the MCU and NVM module. All bits in the FSEC register are readable but not writable. During the reset sequence, the FSEC register is loaded with the contents of the flash security byte in the flash configuration field at global address 0xFF7F located in flash memory.
See Security for security function.
Address:
* Notes:
3020h base + 1h offset = 3021h
Bit 7 6 5 4 3 2 1 0
Read KEYEN Reserved SEC
Write
Reset
x = Undefined at reset.•
x* x* x* x* x* x* x* x*
NVM_FSEC field descriptions
Field Description
7–6
KEYEN
Backdoor Key Security Enable Bits
The KEYEN[1:0] bits define the enabling of backdoor key access to the flash module.
NOTE:
00 Disabled 01 Disabled 10 Enabled 11 Disabled
01 is the preferred KEYEN state to disable backdoor key access.
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Flash and EEPROM registers descriptions
NVM_FSEC field descriptions (continued)
Field Description
5–2
Reserved
SEC Flash Security Bits
This field is reserved.
The SEC[1:0] bits define the security state of the MCU. If the flash module is unsecured using backdoor key access, the SEC bits are forced to 10.
NOTE:
00 Secured 01 Secured 10 Unsecured 11 Secured
01 is the preferred SEC state to set MCU to secured state.
4.6.3 Flash CCOB Index Register (NVM_FCCOBIX)
The FCCOBIX register is used to index the FCCOB register for NVM memory operations.
Address:
3020h base + 2h offset = 3022h
Bit 7 6 5 4 3 2 1 0
Read 0 Write
Reset
0 0 0 0 0 0 0 0
CCOBIX
NVM_FCCOBIX field descriptions
Field Description
7–3
Reserved
CCOBIX Common Command Register Index
This field is reserved. This read-only field is reserved and always has the value 0.
The CCOBIX bits are used to select which word of the FCCOB register array is being read or written to.
4.6.4 Flash Configuration Register (NVM_FCNFG)
The FCNFG register enables the flash command complete interrupt and forces ECC faults on flash array read access from the CPU.
Address:
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3020h base + 4h offset = 3024h
Bit 7 6 5 4 3 2 1 0
Read Write
Reset
CCIE
0 0 0 0 0 0 0 0
0
IGNSF
0
FDFD FSFD
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NVM_FCNFG field descriptions
Field Description
7
CCIE
6–5
Reserved
4
IGNSF
3–2
Reserved
1
FDFD
Command Complete Interrupt Enable
The CCIE bit controls interrupt generation when a flash command has completed.
0 Command complete interrupt disabled. 1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set.
This field is reserved. This read-only field is reserved and always has the value 0.
Ignore Single Bit Fault
The IGNSF controls single bit fault reporting in the FERSTAT register.
0 All single bit faults detected during array reads are reported. 1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not
be generated.
This field is reserved. This read-only field is reserved and always has the value 0.
Force Double Bit Fault Detect
The FDFD bit allows the user to simulate a double bit fault during flash array read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD.
Chapter 4 Memory map
0 Flash array read operations will set the FERSTAT[DFDIF] flag only if a double bit fault is detected. 1 Any flash array read operation will force the FERSTAT[DFDIF] flag to be set and an interrupt will be
generated as long as the DFDIE interrupt enable in the FERCNFG register is set.
0
FSFD
Force Single Bit Fault Detect
The FSFD bit allows the user to simulate a single bit fault during flash array read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD.
0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is
detected.
1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set and an interrupt
will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set.
4.6.5 Flash Error Configuration Register (NVM_FERCNFG)
The FERCNFG register enables the flash error interrupts for the FERSTAT flags.
Address:
3020h base + 5h offset = 3025h
Bit 7 6 5 4 3 2 1 0
Read 0 Write
Reset
0 0 0 0 0 0 0 0
DFDIE SFDIE
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Flash and EEPROM registers descriptions
NVM_FERCNFG field descriptions
Field Description
7–2
Reserved
1
DFDIE
0
SFDIE
This field is reserved. This read-only field is reserved and always has the value 0.
Double Bit Fault Detect Interrupt Enable
The DFDIE bit controls interrupt generation when a double bit fault is detected during a flash block read operation.
0 DFDIF interrupt disabled. 1 An interrupt will be requested whenever the DFDIF flag is set.
Single Bit Fault Detect Interrupt Enable
The SFDIE bit controls interrupt generation when a single bit fault is detected during a flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set. 1 An interrupt will be requested whenever the SFDIF flag is set.
4.6.6 Flash Status Register (NVM_FSTAT)
The FSTAT register reports the operational status of the flash and EEPROM module.
Address:
3020h base + 6h offset = 3026h
Bit 7 6 5 4 3 2 1 0
Read
Write
Reset
CCIF
1 0 0 0 0 0 0 0
0
ACCERR FPVIOL
MGBUSY 0 MGSTAT
NVM_FSTAT field descriptions
Field Description
7
CCIF
6
Reserved
5
ACCERR
Command Complete Interrupt Flag
The CCIF flag indicates that a flash command has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command completion or command violation.
0 Flash command in progress. 1 Flash command has completed.
This field is reserved. This read-only field is reserved and always has the value 0.
Flash Access Error Flag
The ACCERR bit indicates an illegal access has occurred to the flash memory caused by either a violation of the command write sequence or issuing an illegal flash command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR.
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NVM_FSTAT field descriptions (continued)
Field Description
0 No access error detected. 1 Access error detected.
4
FPVIOL
3
MGBUSY
2
Reserved MGSTAT Memory Controller Command Completion Status Flag
Flash Protection Violation Flag
The FPVIOL bit indicates an attempt was made to program or erase an address in a protected area of flash or EEPROM memory during a command write sequence. The FPVIOL bit is cleared by writing a 1 to FPVIOL. Writing a 0 to the FPIOL bit has no effect on FPIOL. While FPIOL is set, it is not possible to launch a command or start a command write sequence.
0 No protection violation detected. 1 Protection violation detected.
Memory Controller Busy Flag
The MGBUSY flag reflects the active state of the memory controller.
0 Memory controller is idle. 1 Memory controller is busy executing a flash command (CCIF = 0).
This field is reserved. This read-only field is reserved and always has the value 0.
Chapter 4 Memory map
One or more MGSTAT flag bits are set if an error is detected during execution of a flash command or during the flash reset sequence.
NOTE:
Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence.
4.6.7 Flash Error Status Register (NVM_FERSTAT)
The FERSTAT register reflects the error status of internal flash and EEPROM operations.
Address:
3020h base + 7h offset = 3027h
Bit 7 6 5 4 3 2 1 0
Read 0 Write
Reset
0 0 0 0 0 0 0 0
DFDIF SFDIF
NVM_FERSTAT field descriptions
Field Description
7–2
Reserved
1
DFDIF
This field is reserved. This read-only field is reserved and always has the value 0.
Double Bit Fault Detect Interrupt Flag
The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a flash array read operation or that a flash array read operation returning invalid data was
Table continues on the next page...
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Flash and EEPROM registers descriptions
NVM_FERSTAT field descriptions (continued)
Field Description
attempted on a flash block that was under a flash command operation. The DFDIF flag is cleared by writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.
0
SFDIF
NOTE:
NOTE:
0 No double bit fault detected. 1 Double bit fault detected or a flash array read operation returning invalid data was attempted while
Single Bit Fault Detect Interrupt Flag
With the IGNSF bit in the FCNFG register clear, the SFDIF flag indicates that a single bit fault was detected in the stored parity and data bits during a flash array read operation or that a flash array read operation returning invalid data was attempted on a flash block that was under a flash command operation. The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on SRFDIF.
0 No single bit fault detected. 1 Single bit fault detected and corrected or a flash array read operation returning invalid data was
The single bit fault and double bit fault flags are mutually exclusive for parity errors, meaning that an ECC fault occurrence can be either single fault or double fault but never both. A simultaneous access collision, when the flash array read operation is returning invalid data attempted while a command is running, is indicated when both SFDIF and DFDIF flags are high.
There is a one cycle delay in storing the ECC DFDIF and SFDIF fault flags in the register. At least one NOP is required after a flash memory read before checking FERSTAT for the occurrence of EEC errors.
command running.
attempted while command running.
4.6.8 Flash Protection Register (NVM_FPROT)
The FPROT register defines which flash sectors are protected against program and erase operations.
The unreserved bits of the FPROT register are writable with the restriction that the size of the protected region can only be increased (see Protection).
During the reset sequence, the FPROT register is loaded with the contents of the flash protection byte in the flash configuration field at global address 0xFF7C located in flash memory. To change the flash protection that will be loaded during the reset sequence, the upper sector of the flash memory must be unprotected, then the flash protection byte must be reprogrammed.
Trying to alter data in any protected area in the flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. The block erase of a flash block is not possible if any of the flash sectors contained in the same flash block are protected.
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Address: 3020h base + 8h offset = 3028h
Bit 7 6 5 4 3 2 1 0
* Notes:
x = Undefined at reset.•
Read Write
Reset
FPOPEN
x* x* x* x* x* x* x* x*
1
FPHDIS FPHS
NVM_FPROT field descriptions
Field Description
7
FPOPEN
6
Reserved
5
FPHDIS
Flash Protection Operation Enable
The FPOPEN bit determines the protection function for program or erase operations.
0 When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified
by the corresponding FPHS and FPLS bits.
1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified
by the corresponding FPHS and FPLS bits.
This field is reserved. This read-only field is reserved and always has the value 1.
Flash Protection Higher Address Range Disable
The FPHDIS bit determines whether there is a protected/unprotected area in a specific region of the flash memory ending with global address 0xFFFF.
Chapter 4 Memory map
0
0 Protection/Unprotection enabled. 1 Protection/Unprotection disabled.
4–3
FPHS
Reserved This field is reserved.
Flash Protection Higher Address Size
The FPHS bits determine the size of the protected/unprotected area in flash memory. The FPHS bits can be written to only while the FPHDIS bit is set.
This read-only field is reserved and always has the value 0.
4.6.9 EEPROM Protection Register (NVM_EEPROT)
The EEPROT register defines which EEPROM sectors are protected against program and erase operations.
The unreserved bits of the EEPROT register are writable with the restriction that protection can be added but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1, protection disabled, to 0, protection enabled. If the DPOPEN bit is set, the state of the DPS bits is irrelevant.
During the reset sequence, fields DPOPEN and DPS of the EEPROT register are loaded with the contents of the EEPROM protection byte in the flash configuration field at global address 0xFF7D located in flash memory. To change the EEPROM protection that
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Flash and EEPROM registers descriptions
will be loaded during the reset sequence, the flash sector containing the EEPROM protection byte must be unprotected. Then the EEPROM protection byte must be programmed.
Trying to alter data in any protected area in the EEPROM memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. Block erase of the EEPROM memory is not possible if any of the EEPROM sectors are protected.
Address: 3020h base + 9h offset = 3029h
Bit 7 6 5 4 3 2 1 0
* Notes:
x = Undefined at reset.•
Read Write
Reset
DPOPEN
x* x* x* x* x* x* x* x*
NVM_EEPROT field descriptions
0
DPS
Field Description
7
DPOPEN
6–2
Reserved
DPS EEPROM Protection Size
EEPROM Protection Control
0 Enables EEPROM memory protection from program and erase with protected address range defined
by DPS bits.
1 Disables EEPROM memory protection from program and erase. This field is reserved.
This read-only field is reserved and always has the value 0.
These bits determine the size of the protected area in the EEPROM memory.
4.6.10 Flash Common Command Object Register:High (NVM_FCCOBHI)
The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte-wide reads and writes are allowed to the FCCOB register.
Address:
3020h base + Ah offset = 302Ah
Bit 7 6 5 4 3 2 1 0
Read Write
Reset
0 0 0 0 0 0 0 0
CCOB
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Chapter 4 Memory map
NVM_FCCOBHI field descriptions
Field Description
CCOB Common Command Object Bit 15:8
High 8 bits of common command object register
4.6.11 Flash Common Command Object Register: Low (NVM_FCCOBLO)
The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte-wide reads and writes are allowed to the FCCOB register.
Address:
3020h base + Bh offset = 302Bh
Bit 7 6 5 4 3 2 1 0
Read Write
Reset
0 0 0 0 0 0 0 0
CCOB
NVM_FCCOBLO field descriptions
Field Description
CCOB Common Command Object Bit 7:0
Low 8 bits of common command object register
4.6.12 Flash Option Register (NVM_FOPT)
The FOPT register is the flash option register. During the reset sequence, the FOPT register is loaded from the flash nonvolatile byte in
the flash configuration field at global address 0xFF7E located in flash memory as indicated by reset condition.
Address:
* Notes:
NXP Semiconductors 95
3020h base + Ch offset = 302Ch
Bit 7 6 5 4 3 2 1 0
Read NV
Write
Reset
x = Undefined at reset.•
x* x* x* x* x* x* x* x*
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Flash and EEPROM registers descriptions
NVM_FOPT field descriptions
Field Description
NV Nonvolatile Bits
The NV[7:0] bits are available as nonvolatile bits. During the reset sequence, the FOPT register is loaded from the flash nonvolatile byte in the flash configuration field at global address 0xFF7E located in flash memory.
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Chapter 5 Interrupt

5.1 Interrupts

Interrupts save the current CPU status and registers, execute an interrupt service routine (ISR), and then restore the CPU status so that processing resumes where it left off before the interrupt. Other than the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events such as an edge on the IRQ pin or a timer­overflow event. The debug module can also generate an SWI under certain circumstances.
If an event occurs in an enabled interrupt source, an associated read-only status flag will be set. The CPU will not respond unless only the local interrupt enable is a logic 1. The I bit in the CCR is 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset that masks (prevents) all maskable interrupt sources. The user program initializes the stack pointer and performs other system setups before clearing the I bit to allow the CPU to respond to interrupts.
When the CPU receives a qualified interrupt request, it completes the current instruction before responding to the interrupt. The interrupt sequence obeys the same cycle-by-cycle sequence as the SWI instruction and consists of:
• Saving the CPU registers on the stack.
• Setting the I bit in the CCR to mask further interrupts.
• Fetching the interrupt vector for the highest-priority interrupt that is currently pending.
• Filling the instruction queue with the first three bytes of program information starting from the address fetched from the interrupt vector locations.
While the CPU is responding to the interrupt, the I bit is automatically set to prevent another interrupt from interrupting the ISR itself, which is called nesting of interrupts. Normally, the I bit is restored to 0 when the CCR is restored from the value stacked on
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Interrupts
entry to the ISR. In rare cases, the I bit may be cleared inside an ISR, after clearing the status flag that generated the interrupt, so that other interrupts can be serviced without waiting for the first service routine to finish. This practice is recommended only for the most experienced programmers because it can lead to subtle program errors that are difficult to debug.
The interrupt service routine ends with a return-from-interrupt (RTI) instruction that restores the CCR, A, X, and PC registers to their pre-interrupt values by reading the previously saved information off the stack.
Note
For compatibility with the M68HC08, the H register is not automatically saved and restored. Push H onto the stack at the start of the interrupt service routine (ISR) and restore it immediately before the RTI that is used to return from the ISR.
When two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced first.
5.1.1

Interrupt stack frame

The following figure shows the contents and organization of a stack frame. Before the interrupt, the stack pointer (SP) points at the next available byte location on the stack. The current values of CPU registers are stored on the stack, starting with the low-order byte of the program counter (PC) and ending with the CCR. After stacking, the SP points at the next available location on the stack, which is the address that is one less than the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred.
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* High byte (H) of index register is not automatically stacked.
ORDER
7
5
5
4
4
3
3
*
1
1
2
2
0
UNSTACKING
ORDER
PROGRAM COUNTER LOW
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER (LOW BYTE X)
PROGRAM COUNTER HIGH
TOWARD LOWER ADDRESSES
TOWARD HIGHER ADDRESSES
SP BEFORE
SP AFTER
INTERRUPT STACKING
THE INTERRUPT
Chapter 5 Interrupt
Figure 5-1. Interrupt stack frame
When an RTI instruction executes, these values are recovered from the stack in reverse order. As part of the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information, starting from the PC address recovered from the stack.
The status flag causing the interrupt must be acknowledged (cleared) before returning from the ISR. Typically, the flag must be cleared at the beginning of the ISR because if another interrupt is generated by this source it will be registered so that it can be serviced after completion of the current ISR.
5.1.2

Interrupt vectors, sources, and local masks

The following table provides a summary of all interrupt sources. High-priority sources are located toward the bottom of the table. The high-order byte of the address for the interrupt service routine is located at the first address in the vector address column, and the low-order byte of the address for the interrupt service routine is located at the next higher address.
When an interrupt condition occurs, an associated flag bit is set. If the associated local interrupt enable is 1, an interrupt request is sent to the CPU. If the global interrupt mask (I bit in the CCR) is 0, the CPU finishes the current instruction, stacks the PCL, PCH, X, A, and CCR CPU registers, sets the I bit, and then fetches the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine.
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NXP Semiconductors 99
Interrupts
Table 5-1. Vector summary (from lowest to highest priority)
Vector number
39 0xFFB0:FFB1 Vnvm NVM
38 0xFFB2:FFB3 Unused Unused Unused Unused Unused
37 0xFFB4:FFB5 Vkeyboard0 KBI0 KBF KBIE
36 0xFFB6:FFB7 Unused Unused Unused Unused Unused 35 0xFFB8:FFB9 Vrtc RTC RTIF RTIE RTC overflow 34 0xFFBA:FFBB Unused Unused Unused Unused Unused 33 0xFFBC:FFBD Unused Unused Unused Unused Unused 32 0xFFBE:FFBF Unused Unused Unused Unused Unused 31 0xFFC0:FFC1 Unused Unused Unused Unused Unused 30 0xFFC2:FFC3 Unused Unused Unused Unused Unused 29 0xFFC4:FFC5 Unused Unused Unused Unused Unused 28 0xFFC6:FFC7 Unused Unused Unused Unused Unused 27 0xFFC8:FFC9 Unused Unused Unused Unused Unused 26 0xFFCA:FFCB Unused Unused Unused Unused Unused
25 0xFFCC:FFCD Vsci0tx SCI0
24 0xFFCE:FFCF Vsci0rx SCI0
23 0xFFD0:FFD1 Vsci0err SCI0
22 0xFFD2:FFD3 Vadc ADC COCO AIEN
21 0xFFD4:FFD5 Vacmp ACMP ACF ACIE
20 0xFFD6:FFD7 Unused Unused Unused Unused Unused 19 0xFFD8:FFD9 Unused Unused Unused Unused Unused 18 0xFFDA:FFDB Vftm0ovf FTM0 TOF TOIE FTM0 overflow 17 0xFFDC:FFDD Vftm0ch1 FTM0CH1 CH1F CH1IE FTM0 channel 1 16 0xFFDE:FFDF Vftm0ch0 FTM0CH0 CH0F CH0IE FTM0 channel 0 15 0xFFE0:FFE1 Vftm1ovf FTM1 TOF TOIE FTM1 overflow 14 0xFFE2:FFE3 Vftm1ch1 FTM1CH1 CH1F CH1IE FTM1 channel 1
Address (high/
low)
Vector name Module Source Local enable Description
CCIF DFDIF SFDIF
TRDE TC IDLE RDRF LBKDIF RXEDGIF OR NF FE PF
CCIE
TIE TCIE ILIE RIE LBKDIE RXEDGIE ORIE NEIE FEIE PEIE
NVM command complete interrupt
Keyboard interrupt 0
SCI0 transmit
SCI0 receive
SCI0 error
ADC conversion complete interrupt
Analog comparator interrupt
Table continues on the next page...
MC9S08PA4 Reference Manual, Rev. 5, 08/2017
100 NXP Semiconductors
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