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HCS08
Microcontrollers
freescale.com
MC9S08LG32
MC9S08LG16
Reference Manual
THIS DOCUMENT CONTAINS INFORMATION ON A NEW PRODUCT UNDER DEVELOPMENT. FREESCALE RESERVES THE RIGHT TO CHANGE OR
DISCONTINUE THIS PRODUCT WITHOUT NOTICE.
MC9S08LG32RM
Rev. 5
8/2009
Page 2
Page 3
MC9S08LG32 Series Features
8-Bit HCS08 Central Processor Unit (CPU)
• Up to 40 MHz CPU at 5.5 V to 2.7 V across temperature
range of –40 °C to 85 °C and –40 °C to 105 °C
• HCS08 instruction set with added BGND instruction
• Support for up to 32 interrupt/reset sources
On-Chip Memory
• 32 KB or 18 KB dual array flash; read/program/erase
over full operating voltage and temperature
• 1984 byte random access memory (RAM)
• Security circuitry to prevent unauthorized access to
RAM and flash contents
Power-Saving Modes
• Two low-power stop modes (stop2 and stop3)
• Reduced-power wait mode
• Peripheral clock gating register can disable clocks to
unused modules, thereby reducing currents
• Low power on-chip crystal oscillator (XOSC) that can be
used in low-power modes to provide accurate clock
source to real time counter and LCD controller
• 100 μs typical wakeup time from stop3 mode
Clock Source Options
• Oscillator (XOSC) — Loop-control Pierce oscillator;
crystal or ceramic resonator range of 31.25 kHz to
38.4 kHz or 1 MHz to 16 MHz
• Internal Clock Source (ICS) — Internal clock source
module containing a frequency-locked-loop (FLL)
controlled by internal or external reference; precision
trimming of internal reference allows 0.2% resolution
and 2% deviation over temperature and voltage; supports
bus frequencies from 1 MHz to 20 MHz
System Protection
• On-chip in-circuit emulator (ICE) debug module
containing three comparators and nine trigger modes;
eight deep FIFO for storing change-of-flow addresses
and event-only data; debug module supports both tag and
force breakpoints
Peripherals
• LCD — Up to 4 x 41 or 8 x 37 LCD driver with internal
charge pump
• ADC — Up to 16-channel, 12-bit resolution; 2.5 μs
conversion time; automatic compare function;
temperature sensor; internal bandgap reference channel;
runs in stop3 and can wake up the system; fully
functional from 5.5 V to 2.7 V
• SCI — Full duplex non-return to zero (NRZ); LIN
master extended break generation; LIN slave extended
break detection; wakeup on active edge
• SPI— Full-duplex or single-wire bidirectional;
double-buffered transmit and receive; master or slave
mode; MSB-first or LSB-first shifting
• IIC — With up to 100 kbps with maximum bus loading;
multi-master operation; programmable slave address;
interrupt driven byte-by-byte data transfer; supports
broadcast mode and 10-bit addressing
• TPMx — One 6 channel and one 2 channel; selectable
input capture, output compare, or buffered edge or
center-aligned PWM on each channel
• MTIM — 8-bit counter with match register; four clock
sources with prescaler dividers; can be used for periodic
wakeup
• RTC — 8-bit modulus counter with binary or decimal
based prescaler; three clock sources including one
external source; can be used for time base, calendar, or
task scheduling functions
• KBI — One keyboard control module capable of
supporting 8x8 keyboard matrix
• IRQ — External pin for wakeup from low-power modes
• COP reset with option to run from dedicated 1 kHz
internal clock or bus clock
• Low-voltage warning with interrupt
• Low-voltage detection with reset
• Illegal opcode detection with reset
• Illegal address detection with reset
• Flash and RAM protection
Development Support
• Single-wire background debug interface
• Breakpoint capability to allow single breakpoint setting
during in-circuit debugging (plus two more breakpoints
in on-chip debug module)
Input/Output
• 39, 53, or 69 GPIOs
• 8 KBI and 1 IRQ interrupt with selectable polarity
• Hysteresis and configurable pullup device on all input
pins; configurable slew rate and drive strength on all
output pins
Package Options
• 48-pin LQFP, 64-pin LQFP, and 80-pin LQFP
Page 4
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MC9S08LG32 Reference Manual
Covers MC9S08LG32
MC9S08LG16
HIS DOCUMENT CONTAINS INFORMATION ON A NEW PRODUCT UNDER DEVELOPMENT. FREESCALE RESERVES THE RIGHT TO CHANGE OR
T
DISCONTINUE THIS PRODUCT WITHOUT NOTICE.
Related Documentation:
• MC9S08LG32PB (Product Brief)
Contains descriptive feature set, example application
information, and developer environment details
• MC9S08LG32 Data Sheet
Contains package information, pinouts,
electricals/characterization data, and mechanical
drawings
Find the most current versions of all documents at:
http://www.freescale.com
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
MC9S08LG32RM
Rev. 5
8/2009
Page 6
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://www.freescale.com
The following revision history table summarizes changes contained in this document.
Revision
Number
Rev. 1 9/2008 First Initial Release.
Rev. 2 9/2008 Second Initial Release.
Rev. 3 11/2008 Alpha Customer Release.
Rev. 4 2/2009 Launch Release.
Rev. 5 8/2009
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
Revision
Date
Description of Changes
•In Chapter 3, “Modes of Operation,” added On-Chip Peripheral Modules in
Stop Modes section in Chapter 3.
•In Ta bl e 5 -2 , corrected addresses for vector number from 23 to 18.
•In Ta bl e 7 -1 , updated KBI pins order as per PINPS1 register.
• Changed TCLK, T1CH0, T1CH1, T2CH0, T2CH1, T2CH2, T2CH3, T2CH4,
T2CH5 to TPMCLK, TPM1CH0, TPM1CH1, TPM2CH0, TPM2CH1,
TPM2CH2, TPM2CH3, TPM2CH4, TPM2CH5.
• Changed ‘LCDCPEN” to “LCDPEN” and “LCDFWF” to “LCDWF.”
•In Chapter 12, “Inter-Integrated Circuit (S08IICV2),” a note is added in the
introduction mentioning that MC9S08LG32 series of MCUs include only one
IIC module.
MC9S08LG32 MCU Series, Rev. 5
6 Freescale Semiconductor
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List of Chapters
Chapter Title Page
Chapter 1 Device Overview ....................................................................................... 21
Chapter 2 Pins and Connections .............................................................................. 27
Chapter 3 Modes of Operation .................................................................................. 41
Chapter 4 Memory ...................................................................................................... 49
Chapter 5 Resets, Interrupts, and General System Control ................................... 73
Chapter 6 Parallel Input/Output Control ...................................................................97
Chapter 7 Keyboard Interrupt (S08KBIV2) ............................................................. 128
Chapter 8 Central Processor Unit (S08CPUV5) ..................................................... 135
Chapter 9 LCD Module (S08LCDLPV1)................................................................... 158
Chapter 10 Analog-to-Digital Converter (S08ADC12V1) ....................................... 200
Chapter 11 Internal Clock Source (S08ICSV3)....................................................... 226
Chapter 12 Inter-Integrated Circuit (S08IICV2) ...................................................... 241
Chapter 13 Serial Communications Interface (S08SCIV4).................................... 259
Chapter 14 Serial Peripheral Interface (S08SPIV4)................................................ 278
Chapter 15 Real-Time Counter (S08RTCV1) .......................................................... 297
Chapter 16 Timer/Pulse-Width Modulator (S08TPMV3) ........................................ 306
Chapter 17 Modulo Timer (S08MTIMV1) ................................................................. 327
Chapter 18 Development Support........................................................................... 337
Chapter 19 Debug Module (DBG) (64K).................................................................. 350
MC9S08LG32 MCU Series, Rev. 5
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Contents
Section Number Title Page
Chapter 1
Device Overview
1.1 Devices in the MC9S08LG32 Series ...............................................................................................21
1.2 MCU Block Diagram .......................................................................................................................22
1.3 System Clock Distribution ...............................................................................................................24
Chapter 2
Pins and Connections
2.1 Introduction ......................................................................................................................................27
2.2 Device Pin Assignment ....................................................................................................................27
2.3 Recommended System Connections ................................................................................................31
2.3.1 Power ................................................................................................................................33
2.3.2 Oscillator ...........................................................................................................................33
2.3.3 RESET ..............................................................................................................................34
2.3.4 Background / Mode Select (BKGD/MS) ..........................................................................34
2.3.5 IRQ ....................................................................................................................................35
2.3.6 LCD Pins ...........................................................................................................................35
2.3.7 General-Purpose I/O (GPIO) and Peripheral Ports ...........................................................36
Chapter 3
Modes of Operation
3.1 Introduction ......................................................................................................................................41
3.2 Features ............................................................................................................................................41
3.3 Run Mode.........................................................................................................................................41
3.4 Active Background Mode ................................................................................................................41
3.5 Wait Mode ........................................................................................................................................42
3.6 Stop Modes.......................................................................................................................................43
3.6.1 Stop2 Mode .......................................................................................................................43
3.6.2 Stop3 Mode .......................................................................................................................44
3.6.3 Active BDM Enabled in Stop Mode .................................................................................45
3.6.4 LVD Enabled in Stop Mode ..............................................................................................45
3.7 Mode Selection.................................................................................................................................45
3.7.1 On-Chip Peripheral Modules in Stop Modes ....................................................................48
Chapter 4
Memory
4.1 Introduction ......................................................................................................................................49
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Section Number Title Page
4.2 MC9S08LG32 Series Memory Map ................................................................................................49
4.3 Reset and Interrupt Vector Assignments ..........................................................................................50
4.4 Register Addresses and Bit Assignments.........................................................................................52
4.4.1 Reserved Flash Locations .................................................................................................59
4.5 RAM.................................................................................................................................................60
4.6 Flash .................................................................................................................................................60
4.6.1 Features .............................................................................................................................61
4.6.2 Program and Erase Times .................................................................................................61
4.6.3 Program and Erase Command Execution .........................................................................62
4.6.4 Burst Program Execution ..................................................................................................63
4.6.5 Access Errors ....................................................................................................................65
4.6.6 Flash Block Protection ......................................................................................................65
4.6.7 Vector Redirection ............................................................................................................66
4.7 Security.............................................................................................................................................66
4.8 Flash Registers and Control Bits......................................................................................................67
4.8.1 Flash Clock Divider Register (FCDIV) ............................................................................68
4.8.2 Flash Options Register (FOPT and NVOPT) ....................................................................69
4.8.3 Flash Configuration Register (FCNFG) ...........................................................................70
4.8.4 Flash Protection Register (FPROT and NVPROT) ..........................................................70
4.8.5 Flash Status Register (FSTAT) ..........................................................................................71
4.8.6 Flash Command Register (FCMD) ...................................................................................72
Chapter 5
Resets, Interrupts, and General System Control
5.1 Introduction ......................................................................................................................................73
5.2 Features ............................................................................................................................................73
5.3 MCU Reset.......................................................................................................................................73
5.4 Computer Operating Properly (COP) Watchdog..............................................................................74
5.5 Interrupts ..........................................................................................................................................75
5.5.1 Interrupt Stack Frame .......................................................................................................76
5.5.2 External Interrupt Request (IRQ) Pin ...............................................................................76
5.5.3 Interrupt Vectors, Sources, and Local Masks ...................................................................77
5.6 Low-Voltage Detect (LVD) System .................................................................................................79
5.6.1 Power-On Reset Operation ...............................................................................................79
5.6.2 Low-Voltage Detection (LVD) Reset Operation ...............................................................79
5.6.3 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................79
5.7 Peripheral Clock Gating ...................................................................................................................79
5.8 Reset, Interrupt, and System Control Registers and Control Bits....................................................80
5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................80
5.8.2 System Reset Status Register (SRS) .................................................................................82
5.8.3 System Background Debug Force Reset Register (SBDFR) ............................................83
5.8.4 System Options Register 1 (SOPT1) ................................................................................84
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Section Number Title Page
5.8.5 System Options Register 2 (SOPT2) ................................................................................85
5.8.6 System Device Identification Register (SDIDH, SDIDL) ................................................86
5.8.7 System Power Management Status and Control 1 Register (SPMSC1) ...........................87
5.8.8 System Power Management Status and Control 2 Register (SPMSC2) ...........................88
5.8.9 System Clock Gating Control 1Register (SCGC1) ...........................................................90
5.8.10 System Clock Gating Control 2 Register (SCGC2) ..........................................................91
5.8.11 Pin Position Control Register (PINPS1) ...........................................................................92
5.8.12 Pin Position Control Register (PINPS2) ...........................................................................93
5.8.13 Pin Position Control Register (PINPS3) ...........................................................................94
5.8.14 Pin Position Control Register (PINPS4) ...........................................................................95
Chapter 6
Parallel Input/Output Control
6.1 Introduction ......................................................................................................................................97
6.2 Pins Shared with LCD......................................................................................................................97
6.3 Port Data and Data Direction ...........................................................................................................97
6.4 Pullup, Slew Rate, and Drive Strength.............................................................................................98
6.4.1 Port Internal Pullup Enable ...............................................................................................98
6.4.2 Port Slew Rate Enable ......................................................................................................99
6.4.3 Port Drive Strength Select ................................................................................................99
6.5 Open Drain Operation ......................................................................................................................99
6.6 Pin Behavior in Stop Modes.............................................................................................................99
6.7 Parallel I/O and Pin Control Registers ...........................................................................................100
6.7.1 Port A Registers ..............................................................................................................100
6.7.2 Port B Registers ..............................................................................................................104
6.7.3 Port C Registers ..............................................................................................................107
6.7.4 Port D Registers ..............................................................................................................110
6.7.5 Port E Registers ..............................................................................................................113
6.7.6 Port F Registers ............................................................................................................... 116
6.7.7 Port G Registers ..............................................................................................................119
6.7.8 Port H Registers ..............................................................................................................122
6.7.9 Port I Registers ................................................................................................................125
Chapter 7
Keyboard Interrupt (S08KBIV2)
7.1 Introduction ....................................................................................................................................128
7.1.1 Module Configuration .....................................................................................................128
7.1.2 KBI Clock Gating ...........................................................................................................128
7.1.3 Features ...........................................................................................................................130
7.1.4 Modes of Operation ........................................................................................................130
7.1.5 Block Diagram ................................................................................................................130
7.2 External Signal Description ...........................................................................................................131
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Section Number Title Page
7.3 Register Definition .........................................................................................................................131
7.3.1 KBI Status and Control Register (KBISC) .....................................................................131
7.3.2 KBI Pin Enable Register (KBIPE) ..................................................................................132
7.3.3 KBI Edge Select Register (KBIES) ................................................................................132
7.4 Functional Description ...................................................................................................................133
7.4.1 Edge Only Sensitivity .....................................................................................................133
7.4.2 Edge and Level Sensitivity .............................................................................................133
7.4.3 KBI Pullup/Pulldown Resistors ......................................................................................134
7.4.4 KBI Initialization ............................................................................................................134
Chapter 8
Central Processor Unit (S08CPUV5)
8.1 Introduction ....................................................................................................................................135
8.1.1 Features ...........................................................................................................................135
8.2 Programmer’s Model and CPU Registers ......................................................................................136
8.2.1 Accumulator (A) .............................................................................................................136
8.2.2 Index Register (H:X) ......................................................................................................136
8.2.3 Stack Pointer (SP) ...........................................................................................................137
8.2.4 Program Counter (PC) ....................................................................................................137
8.2.5 Condition Code Register (CCR) .....................................................................................137
8.3 Addressing Modes..........................................................................................................................139
8.3.1 Inherent Addressing Mode (INH) ...................................................................................139
8.3.2 Relative Addressing Mode (REL) ..................................................................................139
8.3.3 Immediate Addressing Mode (IMM) ..............................................................................139
8.3.4 Direct Addressing Mode (DIR) ......................................................................................139
8.3.5 Extended Addressing Mode (EXT) ................................................................................140
8.3.6 Indexed Addressing Mode ..............................................................................................140
8.4 Special Operations..........................................................................................................................141
8.4.1 Reset Sequence ...............................................................................................................141
8.4.2 Interrupt Sequence ..........................................................................................................141
8.4.3 Wait Mode Operation ......................................................................................................142
8.4.4 Stop Mode Operation ......................................................................................................142
8.4.5 BGND Instruction ...........................................................................................................143
8.5 HCS08 Instruction Set Summary ...................................................................................................144
Chapter 9
LCD Module (S08LCDLPV1)
9.1 Introduction ....................................................................................................................................158
9.1.1 LCD Clock Sources ........................................................................................................158
9.1.2 LCD Modes of Operation ...............................................................................................158
9.1.3 LCD Status after Stop2 Wakeup .....................................................................................158
9.1.4 LCD Clock Gating ..........................................................................................................158
MC9S08LG32 MCU Series, Rev. 5
12 Freescale Semiconductor
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Section Number Title Page
9.1.5 Features ...........................................................................................................................160
9.1.6 Modes of Operation ........................................................................................................161
9.1.7 Block Diagram ................................................................................................................161
9.2 External Signal Description ...........................................................................................................162
9.2.1 LCD[44:0] .......................................................................................................................163
9.2.2 V
9.2.3 V
9.3 Register Definition .........................................................................................................................163
9.3.1 LCD Control Register 0 (LCDC0) ..................................................................................163
9.3.2 LCD Control Register 1 (LCDC1) ..................................................................................164
9.3.3 LCD Voltage Supply Register (LCDSUPPLY) ...............................................................165
9.3.4 LCD Regulated Voltage Control Register (LCDRVC) ...................................................166
9.3.5 LCD Blink Control Register (LCDBCTL) .....................................................................167
9.3.6 LCD Status Register (LCDS) ..........................................................................................168
9.3.7 LCD Pin Enable Registers 0–5 (LCDPEN0–LCDPEN5) ..............................................168
9.3.8 Backplane Enable Registers 0–5 (BPEN0–BPEN5) ......................................................169
9.3.9 LCD Waveform Registers (LCDWF[44:0]) ...................................................................170
9.4 Functional Description ...................................................................................................................174
9.4.1 LCD Driver Description .................................................................................................175
9.4.2 LCDWF Registers ...........................................................................................................183
9.4.3 LCD Display Modes .......................................................................................................183
9.4.4 LCD Charge Pump, Voltage Divider, and Power Supply Operation ..............................185
9.4.5 Resets ..............................................................................................................................188
9.4.6 Interrupts .........................................................................................................................189
9.5 Initialization Section ......................................................................................................................189
9.5.1 Initialization Sequence ....................................................................................................189
9.5.2 Initialization Examples ...................................................................................................190
9.6 Application Information.................................................................................................................194
9.6.1 LCD Seven Segment Example Description ....................................................................195
9.6.2 LCD Contrast Control .....................................................................................................198
9.6.3 Stop Mode Recovery .......................................................................................................199
LL1
cap1
, V
, V
LL2
cap2
, V
...........................................................................................................163
LL3
.....................................................................................................................163
Chapter 10
Analog-to-Digital Converter (S08ADC12V1)
10.1 Introduction ....................................................................................................................................200
10.1.1 ADC shared with LCD ...................................................................................................200
10.1.2 ADC Reference and Supply Voltage ...............................................................................200
10.1.3 ADC Clock Gating ..........................................................................................................200
10.1.4 Module Configurations ...................................................................................................201
10.1.5 Features ...........................................................................................................................204
10.1.6 ADC Module Block Diagram .........................................................................................204
10.2 External Signal Description ...........................................................................................................205
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Section Number Title Page
10.2.1 Analog Power (V
10.2.2 Analog Ground (V
10.2.3 Voltage Reference High (V
10.2.4 Voltage Reference Low (V
) ....................................................................................................206
DDA
) ...................................................................................................206
SSA
) ...................................................................................206
REFH
) ....................................................................................206
REFL
10.2.5 Analog Channel Inputs (ADx) ........................................................................................206
10.3 Register Definition .........................................................................................................................206
10.3.1 Status and Control Register 1 (ADCSC1) ......................................................................206
10.3.2 Status and Control Register 2 (ADCSC2) ......................................................................208
10.3.3 Data Result High Register (ADCRH) .............................................................................208
10.3.4 Data Result Low Register (ADCRL) ..............................................................................209
10.3.5 Compare Value High Register (ADCCVH) ....................................................................209
10.3.6 Compare Value Low Register (ADCCVL) .....................................................................210
10.3.7 Configuration Register (ADCCFG) ................................................................................210
10.3.8 Pin Control 1 Register (APCTL1) ..................................................................................211
10.3.9 Pin Control 2 Register (APCTL2) ..................................................................................212
10.3.10Pin Control 3 Register (APCTL3) ..................................................................................213
10.4 Functional Description ...................................................................................................................214
10.4.1 Clock Select and Divide Control ....................................................................................215
10.4.2 Input Select and Pin Control ...........................................................................................215
10.4.3 Hardware Trigger ............................................................................................................215
10.4.4 Conversion Control .........................................................................................................215
10.4.5 Automatic Compare Function .........................................................................................218
10.4.6 MCU Wait Mode Operation ............................................................................................218
10.4.7 MCU Stop3 Mode Operation ..........................................................................................219
10.4.8 MCU Stop2 Mode Operation ..........................................................................................219
10.5 Initialization Information ...............................................................................................................220
10.5.1 ADC Module Initialization Example ..............................................................................220
10.6 Application Information .................................................................................................................222
10.6.1 External Pins and Routing ..............................................................................................222
10.6.2 Sources of Error ..............................................................................................................223
Chapter 11
Internal Clock Source (S08ICSV3)
11.1 Introduction ....................................................................................................................................226
11.1.1 Features ...........................................................................................................................228
11.1.2 Block Diagram ................................................................................................................228
11.1.3 Modes of Operation ........................................................................................................229
11.2 External Signal Description ...........................................................................................................230
11.3 Register Definition .........................................................................................................................230
11.3.1 ICS Control Register 1 (ICSC1) .....................................................................................231
11.3.2 ICS Control Register 2 (ICSC2) .....................................................................................233
11.3.3 ICS Trim Register (ICSTRM) .........................................................................................233
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11.3.4 ICS Status and Control (ICSSC) .....................................................................................234
11.4 Functional Description ...................................................................................................................236
11.4.1 Operational Modes ..........................................................................................................236
11.4.2 Mode Switching ..............................................................................................................238
11.4.3 Bus Frequency Divider ...................................................................................................239
11.4.4 Low Power Bit Usage .....................................................................................................239
11.4.5 DCO Maximum Frequency with 32.768 kHz Oscillator ................................................239
11.4.6 Internal Reference Clock ................................................................................................239
11.4.7 External Reference Clock ...............................................................................................240
11.4.8 Fixed Frequency Clock ...................................................................................................240
11.4.9 Local Clock .....................................................................................................................240
Chapter 12
Inter-Integrated Circuit (S08IICV2)
12.1 Introduction ....................................................................................................................................241
12.1.1 Module Configuration .....................................................................................................241
12.1.2 IIC Clock Gating .............................................................................................................241
12.1.3 Features ...........................................................................................................................243
12.1.4 Modes of Operation ........................................................................................................243
12.1.5 Block Diagram ................................................................................................................243
12.2 External Signal Description ...........................................................................................................244
12.2.1 SCL — Serial Clock Line ...............................................................................................244
12.2.2 SDA — Serial Data Line ................................................................................................244
12.3 Register Definition .........................................................................................................................244
12.3.1 IIC Address Register (IICxA) .........................................................................................245
12.3.2 IIC Frequency Divider Register (IICxF) ........................................................................245
12.3.3 IIC Control Register (IICxC1) ........................................................................................248
12.3.4 IIC Status Register (IICxS) .............................................................................................248
12.3.5 IIC Data I/O Register (IICxD) ........................................................................................249
12.3.6 IIC Control Register 2 (IICxC2) .....................................................................................250
12.4 Functional Description ...................................................................................................................251
12.4.1 IIC Protocol .....................................................................................................................251
12.4.2 10-bit Address .................................................................................................................254
12.4.3 General Call Address ......................................................................................................255
12.5 Resets .............................................................................................................................................255
12.6 Interrupts ........................................................................................................................................255
12.6.1 Byte Transfer Interrupt ....................................................................................................255
12.6.2 Address Detect Interrupt .................................................................................................256
12.6.3 Arbitration Lost Interrupt ................................................................................................256
12.7 Initialization/Application Information ...........................................................................................257
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Section Number Title Page
Chapter 13
Serial Communications Interface (S08SCIV4)
13.1 Introduction ....................................................................................................................................259
13.1.1 Module Instances ............................................................................................................259
13.1.2 Module Configuration .....................................................................................................259
13.1.3 SCI Clock Gating ............................................................................................................259
13.1.4 Features ...........................................................................................................................261
13.1.5 Modes of Operation ........................................................................................................261
13.1.6 Block Diagram ................................................................................................................262
13.2 Register Definition .........................................................................................................................264
13.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL) ..........................................................264
13.2.2 SCI Control Register 1 (SCIxC1) ...................................................................................265
13.2.3 SCI Control Register 2 (SCIxC2) ...................................................................................266
13.2.4 SCI Status Register 1 (SCIxS1) ......................................................................................267
13.2.5 SCI Status Register 2 (SCIxS2) ......................................................................................269
13.2.6 SCI Control Register 3 (SCIxC3) ...................................................................................270
13.2.7 SCI Data Register (SCIxD) .............................................................................................271
13.3 Functional Description ...................................................................................................................271
13.3.1 Baud Rate Generation .....................................................................................................271
13.3.2 Transmitter Functional Description ................................................................................272
13.3.3 Receiver Functional Description ....................................................................................273
13.3.4 Interrupts and Status Flags ..............................................................................................275
13.3.5 Additional SCI Functions ...............................................................................................276
Chapter 14
Serial Peripheral Interface (S08SPIV4)
14.1 Introduction ....................................................................................................................................278
14.1.1 Module Configuration .....................................................................................................278
14.1.2 SPI Clock Gating ............................................................................................................278
14.1.3 Features ...........................................................................................................................280
14.1.4 Block Diagrams ..............................................................................................................280
14.1.5 SPI Baud Rate Generation ..............................................................................................282
14.2 External Signal Description ...........................................................................................................283
14.2.1 SPSCK — SPI Serial Clock ............................................................................................283
14.2.2 MOSI — Master Data Out, Slave Data In ......................................................................283
14.2.3 MISO — Master Data In, Slave Data Out ......................................................................283
14.2.4 SS
14.3 Modes of Operation........................................................................................................................284
14.3.1 SPI in Stop Modes ..........................................................................................................284
14.4 Register Definition .........................................................................................................................284
14.4.1 SPI Control Register 1 (SPIxC1) ....................................................................................284
14.4.2 SPI Control Register 2 (SPIxC2) ....................................................................................285
— Slave Select ..........................................................................................................283
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Page 17
Section Number Title Page
14.4.3 SPI Baud Rate Register (SPIxBR) ..................................................................................286
14.4.4 SPI Status Register (SPIxS) ............................................................................................287
14.4.5 SPI Data Register (SPIxD) .............................................................................................288
14.5 Functional Description ...................................................................................................................289
14.5.1 Master Mode ...................................................................................................................289
14.5.2 Slave Mode .....................................................................................................................290
14.5.3 SPI Clock Formats ..........................................................................................................291
14.5.4 Special Features ..............................................................................................................293
14.5.5 SPI Interrupts ..................................................................................................................295
14.5.6 Mode Fault Detection .....................................................................................................295
Chapter 15
Real-Time Counter (S08RTCV1)
15.1 Introduction ....................................................................................................................................297
15.1.1 RTC Clock Gating ..........................................................................................................297
15.1.2 Features ...........................................................................................................................299
15.1.3 Modes of Operation ........................................................................................................299
15.1.4 Block Diagram ................................................................................................................300
15.2 External Signal Description ...........................................................................................................300
15.3 Register Definition .........................................................................................................................300
15.3.1 RTC Status and Control Register (RTCSC) ....................................................................301
15.3.2 RTC Counter Register (RTCCNT) ..................................................................................302
15.3.3 RTC Modulo Register (RTCMOD) ................................................................................302
15.4 Functional Description ...................................................................................................................302
15.4.1 RTC Operation Example .................................................................................................303
15.5 Initialization/Application Information ...........................................................................................304
Chapter 16
Timer/Pulse-Width Modulator (S08TPMV3)
16.1 Introduction ....................................................................................................................................306
16.1.1 TPM External Clock .......................................................................................................306
16.1.2 Module Instances ............................................................................................................306
16.1.3 Module Configuration .....................................................................................................306
16.1.4 TPM Clock Gating ..........................................................................................................307
16.1.5 Features ...........................................................................................................................308
16.1.6 Modes of Operation ........................................................................................................308
16.1.7 Block Diagram ................................................................................................................309
16.2 Signal Description ..........................................................................................................................311
16.2.1 Detailed Signal Descriptions ..........................................................................................311
16.3 Register Definition .........................................................................................................................314
16.3.1 TPM Status and Control Register (TPMxSC) ................................................................314
16.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................315
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 17
Page 18
Section Number Title Page
16.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................316
16.3.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................317
16.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................318
16.4 Functional Description ...................................................................................................................319
16.4.1 Counter ............................................................................................................................320
16.4.2 Channel Mode Selection .................................................................................................321
16.5 Reset Overview ..............................................................................................................................324
16.5.1 General ............................................................................................................................324
16.5.2 Description of Reset Operation .......................................................................................324
16.6 Interrupts ........................................................................................................................................324
16.6.1 General ............................................................................................................................324
16.6.2 Description of Interrupt Operation .................................................................................325
Chapter 17
Modulo Timer (S08MTIMV1)
17.1 Introduction ....................................................................................................................................327
17.1.1 MTIM Clock Gating .......................................................................................................327
17.1.2 Features ...........................................................................................................................329
17.1.3 Modes of Operation ........................................................................................................329
17.1.4 Block Diagram ................................................................................................................330
17.2 External Signal Description ...........................................................................................................330
17.3 Memory Map and Register Definition ...........................................................................................331
17.3.1 Memory Map (Register Summary) .................................................................................331
17.3.2 Register Descriptions ......................................................................................................331
17.4 Functional Description ...................................................................................................................335
17.4.1 MTIM Operation Example .............................................................................................336
Chapter 18
Development Support
18.1 Introduction ....................................................................................................................................337
18.1.1 Forcing Active Background ............................................................................................337
18.1.2 Module Configuration .....................................................................................................337
18.1.3 Features ...........................................................................................................................338
18.2 Background Debug Controller (BDC) ...........................................................................................338
18.2.1 BKGD Pin Description ...................................................................................................339
18.2.2 Communication Details ..................................................................................................339
18.2.3 BDC Commands .............................................................................................................343
18.2.4 BDC Hardware Breakpoint .............................................................................................345
18.3 Register Definition .........................................................................................................................345
18.3.1 BDC Registers and Control Bits .....................................................................................346
18.3.2 System Background Debug Force Reset Register (SBDFR) ..........................................348
MC9S08LG32 MCU Series, Rev. 5
18 Freescale Semiconductor
Page 19
Section Number Title Page
Chapter 19
Debug Module (DBG) (64K)
19.1 Introduction ....................................................................................................................................350
19.1.1 Features ...........................................................................................................................350
19.1.2 Modes of Operation ........................................................................................................351
19.1.3 Block Diagram ................................................................................................................351
19.2 Signal Description ..........................................................................................................................352
19.3 Memory Map and Registers ...........................................................................................................352
19.3.1 Module Memory Map .....................................................................................................352
19.3.2 Register Descriptions ......................................................................................................354
19.4 Functional Description ...................................................................................................................365
19.4.1 Comparator .....................................................................................................................365
19.4.2 Breakpoints .....................................................................................................................365
19.4.3 Trigger Selection .............................................................................................................366
19.4.4 Trigger Break Control (TBC) .........................................................................................366
19.4.5 FIFO ................................................................................................................................370
19.4.6 Interrupt Priority .............................................................................................................371
19.5 Resets .............................................................................................................................................371
19.6 Interrupts ........................................................................................................................................371
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 19
Page 20
Page 21
Chapter 1 Device Overview
The MC9S08LG32 and MC9S08LG16 are the members of the low-cost, low-power, and
high-performance HCS08 family of 8-bit microcontroller units (MCUs). All MCUs in the family use the
enhanced HCS08 core and are available with a variety of memory sizes and package types.
The MC9S08LG32 series MCUs are targeted to serve automotive, consumer and industrial markets.
Please check the ordering part numbers for different qualification tier products in Ordering Information
section of MC9S08LG32 Data Sheet.
1.1 Devices in the MC9S08LG32 Series
Table 1-1 summarizes the feature set available in the MC9S08LG32 series of MCUs.
Table 1-1. MC9S08LG32 series Features by MCU and Package
Feature MC9S08LG32 MC9S08LG16
Flash size (bytes) 32,768 18,432
RAM size (bytes) 1984
Pin quantity 80 64 48 64 48
ADC 16 ch 12 ch 9 ch 12 ch 9 ch
LCD 8 x 37
4 x 41
ICE + DBG yes
ICS yes
IIC yes
IRQ yes
KBI 8 pin
GPIOs 695339 53 39
RTC yes
MTIM yes
SCI1 yes
SCI2 yes
SPI yes
TPM1 channels 2
TPM2 channels 6
XOSC yes
8 x 29
4 x 33
8 x 21
4 x 25
8 x 29
4 x 33
8 x 21
4 x 25
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 21
Page 22
Chapter 1 Device Overview
8-BIT KEYBOARD
INTERRUPT (
KBI
)
IIC MODULE (
IIC
)
SERIAL PERIPHERAL
INTERFACE (
SPI
)
USER FLASH B
USER RAM
ON-CHIP ICE (
ICE
) and
DEBUG MODULE (
DBG
)
(LG32 = 16K BYTES)
HCS08 CORE
CPU
BKGD
INT
BKP
2-CHANNEL TIMER/PWM
(
TPM1
)
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
IRQ LVD
LOW-POWER OSCILLATOR
INTERNAL CLOCK
Source (
ICS
)
SERIAL COMMUNICATIONS
6-CHANNEL TIMER/PWM
(
TPM2
)
V
LL1
(LCD)
V
LL2
V
LL3
V
CAP1
V
CAP2
LCD[44:0]
V
SS
V
DD
VO LTAGE
REGULATOR
USER FLASH A
(LG16 = 2K BYTES)
LCD28/ADC5/TPMCLK
/PTA7
LCD27/ADC4/TPM2CH1/KBI7/
PTA6
LCD25/ADC2/RX2/KBI5/
PTA4
INTERFACE (
SCI1
)
TxD1
RxD1
SS
SPSCK
SCL
SDA
MOSI
MISO
V
SSA/VREFL
V
DDA/VREFH
XTAL
EXTAL
IRQ
KBI[7:0]
PORT A
RESET
LIQUID CRYSTAL
DISPLAY DRIVER
ANALOG-TO-DIGITAL
CONVERTER (
ADC
)
12-BIT
AD[15:0]
TPM2CH[5:0]
TPMCLK
TPMCLK
LCD24/ADC1/TX2/KBI4/
PTA3
LCD23/ADC0/SDA/
PTA2
LCD22/SCL/
PTA1
LCD21/
PTA0
(LG32 = 16K BYTES)
(LG16 = 16K BYTES)
LCD26/ADC3/TPM2CH0/KBI6/
PTA5
BKGD/MS
TPM1CH[1:0]
COP
Real Time Counter
(
RTC
)
TMRCLK
SERIAL COMMUNICATIONS
INTERFACE (
SCI2
)
TxD2
RxD2
PORT C
EXTAL/
PTF7
XTAL/
PTF6
TPM2CH4/KBI1/MISO
/
PTF4
PORT F
TPM2CH5/KBI0/SS/
PTF3
ADC14/IRQ/TPM1CH1/SPSCK/
PTF2
ADC13/TPM1CH0/RX1/
PTF1
ADC12/TPM2CH2/KBI3/TX1/
PTF0
TPM2CH3/KBI2/MOSI/
PTF5
SPSCK/SDA/TPM2CH1/
PTI4
PORT I
MOSI/TPM2CH2/
PTI3
MISO/TPM2CH3/
PTI2
TX2/TMRCLK/
PTI1
RX2
/PTI0
SS/SCL/TPM2CH0/
PTI5
PORT D
PORT E
LCD[40:37]
/PTB[7:4]
LCD[32:29]
/PTB[3:0]
LCD[7:0]
/PTD[7:0]
PORT B
LCD[15:8]/
PTE[7:0]
LCD[44:41]/
PTG[7:4]
LCD[36:33]
/PTG[3:0]
PORT G
ADC11/TPM1CH0/KBI3/TX1/
PTH5
ADC10/TPM1CH1/KBI2/RX1/
PTH4
ADC[9:6]/KBI[7:4]/
PTH[3:0]
TPM2CH4/KBI1/
PTH7
ADC15/KBI0/TPM2CH5/
PTH6
PORT H
V
SS2
V
LL3_2
Available only on 80-pin package
Available only on 64-pin and 80-pin package
*/
Default function out of reset
/*
BKGD/MS
/PTC5
RESET
/PTC6
Modulo Timer
(
MTIM
)
1984 BYTES
LCD[20:16]/
PTC[4:0]
1.2 MCU Block Diagram
The block diagram in Figure 1-1 shows the structure of the MC9S08LG32 series MCU.
22 Freescale Semiconductor
Figure 1-1. MC9S08LG32 Series Block Diagram
MC9S08LG32 MCU Series, Rev. 5
Page 23
Table 1-2 provides the functional version of the on-chip modules.
Table 1-2. Module Versions
Module Version
Analog-to-Digital Converter (ADC12) 1
Central Processor Unit (CPU) 5
Inter-Integrated Circuit (IIC) 2
Internal Clock Source (ICS) 3
Keyboard Interrupt (KBI) 2
Liquid Crystal Display Module (LCD) 1
Low Power Oscillator (XOSC) 1
Modulo Timer (MTIM) 1
On-Chip In-Circuit Debug/Emulator (DBG) 3
Real Time Counter (RTC) 1
Serial Communications Interface (SCI) 4
Serial Peripheral Interface (SPI) 4
Timer Pulse Width Modulator (TPM) 3
Chapter 1 Device Overview
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 23
Page 24
Chapter 1 Device Overview
1.3 System Clock Distribution
Figure 1-2 shows a simplified clock connection diagram of the ICS. Some modules in the MCU have
selectable clock inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to
drive the module function. All memory-mapped registers associated with the modules are clocked with
BUSCLK. The ICS supplies the following clock sources:
• ICSOUT — This clock source is used as the CPU clock and is divided by 2 to generate the
peripheral bus clock, BUSCLK. Control bits in the ICS control registers determine which of the
three clock sources is connected:
— Internal reference clock
— External reference clock
— Frequency-locked loop (FLL) output
For more information on configuring the ICSOUT clock, see Chapter 11, “Internal Clock Source
(S08ICSV3).”
• ICSLCLK — This clock source is derived from the digitally controlled oscillator (DCO) of the ICS
when the ICS is configured to run off the internal or external reference clock. The development
tools can select this internal self-clocked source (~ 8 MHz) to speed up the BDC communications
in systems where the bus clock is slow.
• ICSERCLK — This is an external reference clock and can be selected as the alternate clock for
ADC. The “Optional External Reference Clock” section in Chapter 11, “Internal Clock Source
(S08ICSV3),” explains the ICSERCLK in more detail. For more information regarding the use of
ICSERCLK with this module, see Chapter 10, “Analog-to-Digital Converter (S08ADC12V1).”
• ICSIRCLK — This is an internal reference clock and can be selected as the RTC clock source, or
as ALTCLK source for the LCD. Chapter 11, “Internal Clock Source (S08ICSV3)” explains the
ICSIRCLK in more detail. For more information regarding use of ICSIRCLK with these modules,
see Chapter 15, “Real-Time Counter (S08RTCV1),” and Chapter 9, “LCD Module
(S08LCDLPV1).”
• ICSFFCLK — This fixed frequency clock (FFCLK) is generated after it is synchronized with the
bus clock. The frequency of the ICSFFCLK is determined by the settings of the ICS. For more
information, see the “Fixed Frequency Clock” section in Chapter 11, “Internal Clock Source
(S08ICSV3).” It can be selected as a clock source for the MTIM and TPM modules. For
information regarding use of ICSFFCLK with these modules, see Chapter 16, “Timer/Pulse-Width
Modulator (S08TPMV3),” and Chapter 17, “Modulo Timer (S08MTIMV1).”
• LPOCLK — This clock is generated from an internal low power oscillator (LPO) that is
completely independent of the ICS module. The LPOCLK can be selected as the clock source to
the COP and RTC module. See Section 5.4, “Computer Operating Properly (COP) Watchdog,” and
Chapter 15, “Real-Time Counter (S08RTCV1),” for details on using the LPOCLK with these
modules.
• OSCOUT — This is the output of the XOSC module and can be selected as the LCD and RTC
clock source. This clock source can be used for LCD and RTC in stop2 mode. For more information
regarding use of OSCOUT with these modules, see Chapter 15, “Real-Time Counter
(S08RTCV1),” and Chapter 9, “LCD Module (S08LCDLPV1).”
MC9S08LG32 MCU Series, Rev. 5
24 Freescale Semiconductor
Page 25
Chapter 1 Device Overview
TPM1 TPM2
SCI1 SCI2
BDC
CPU
ADC
FLASH
ICS
ICSOUT
÷2
BUSCLK
ICSLCLK
ICSIRCLK
COP
* The fixed frequency clock (FFCLK) is internally
synchronized to the bus clock and must not
exceed one half of the bus clock frequency.
Flash has frequency
requirements for program
and erase operation. See the
electricals appendix for
details.
ADC has min and max
frequency requirements.
See the ADC chapter and
electricals appendix for
details.
XOSC
EXTAL XTAL
FFCLK*
ICSFFCLK
1 kHz
LPO
ICSERCLK
÷2
IIC
DBG
SYNC*
LPOCLK
OSCOUT
LCD
TPMCLK
MTIM
TMRCLK
SPI
KBI
RTC
• TPMCLK — The TPMCLK is an optional external clock source for the TPM modules. The
TPMCLK must be limited to 1/4th of the frequency of the bus clock for synchronization. For more
information, see the “External TPM Clock Sources” section in Chapter 16, “Timer/Pulse-Width
Modulator (S08TPMV3).”
• TMRCLK — The TMRCLK is an optional external clock source for the MTIM module. For more
information, see Chapter 17, “Modulo Timer (S08MTIMV1).”
NOTE
ICSERCLK is a gated version of OSCOUT. ICSERCLK is not available in
STOP modes while OSCOUT is available if ERCLKEN and EREFSTEN
are set.
Figure 1-2. System Clock Distribution Diagram
Freescale Semiconductor 25
MC9S08LG32 MCU Series, Rev. 5
Page 26
Chapter 1 Device Overview
MC9S08LG32 MCU Series, Rev. 5
26 Freescale Semiconductor
Page 27
Chapter 2 Pins and Connections
2.1 Introduction
This section describes signals that connect to the package pins. It includes pinout diagrams, recommended
system connections, and detailed discussions of signals.
2.2 Device Pin Assignment
This section shows the pin assignments for MC9S08LG32 series. The priority of functions on a pin is in
ascending order from left to right and bottom to top. Another view of pinouts and function priority is given
in Table 2-1.
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 27
Page 28
Chapter 2 Pins and Connections
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21222324252627282930313233343536373839
40
80-Pin LQFP
PTE0/LCD8
PTE1/LCD9
PTE2/LCD10
PTE3/LCD11
PTE4/LCD12
PTE5/LCD13
PTG0/LCD33
PTG1/LCD34
PTG4/LCD41
PTG5/LCD42
PTG6/LCD43
PTG7/LCD44
V
LL3_2VSS2
PTE6/LCD14
PTE7/LCD15
PTC0/LCD16
PTC1/LCD17
PTC2/LCD18
PTC3/LCD19
PTD7/LCD7
PTD6/LCD6
PTD5/LCD5
PTD4/LCD4
PTD3/LCD3
PTD2/LCD2
PTB3/LCD32
PTB2/LCD31
PTB7/LCD40
PTB6/LCD39
PTB5/LCD38
PTB4/LCD37
PTB1/LCD30
PTB0/LCD29
PTD1/LCD1
PTD0/LCD0
V
CAP1
V
CAP2
V
LL1
V
LL2
V
LL3
PTF5/MOSI/KBI2/TPM2CH3
PTF4/MISO/KBI1/TPM2CH4
PTI5/TPM2CH0/SCL/SS
PTI4/TPM2CH1/SDA/SPSCK
PTI3/TPM2CH2/MOSI
PTI2/TPM2CH3/MISO
PTI1/TMRCLK/TX2
PTI0/RX2
PTH7/KBI1/TPM2CH4
V
SS
V
DD
PTF7/EXTAL
PTF6/XTAL
V
DDA
/V
REFH
V
SSA
/V
REFL
PTH6/TPM2CH5/KBI0/ADC15
PTF2/SPSCK/TPM1CH1/IRQ/ADC14
PTF1/RX1/TPM1CH0/ADC13
PTF0/TX1/KBI3/TPM2CH2/ADC12
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PTC4/LCD20
PTA0/LCD21
PTG2/LCD35
PTG3/LCD36
PTA1/SCL/LCD22
PTA2/SDA/ADC0/LCD23
PTA3/KBI4/TX2/ADC1/LCD24
PTA4/KBI5/RX2/ADC2/LCD25
PTA5/KBI6/TPM2CH0/ADC3/LCD26
PTA6/KBI7/TPM2CH1/ADC4/LCD27
PTA7/TPMCLK/ADC5/LCD28
PTC5/BKGD/MS
PTC6/RESET
PTH0/KBI4/ADC6
PTH1/KBI5/ADC7
PTH2KBI6/ADC8
PTH3/KBI7/ADC9
PTH4/RX1/KBI2/TPM1CH1/ADC10
PTH5/TX1/KBI3/TPM1CH0/ADC11
PTF3/SS
/KBI0/TPM2CH5
80797877767574737271706968676665646362
61
V
REFH/VREFL
are internally connected to V
Figure 2-1. 80-Pin LDFP
NOTE
DDA/VSSA
.
28 Freescale Semiconductor
MC9S08LG32 MCU Series, Rev. 5
Page 29
Chapter 2 Pins and Connections
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
171819202122232425262728293031
32
64-Pin LQFP
PTE0/LCD8
PTE1/LCD9
PTE2/LCD10
PTE3/LCD11
PTE4/LCD12
PTE5/LCD13
PTG0/LCD33
PTG1/LCD34
V
LL3_2VSS2
PTE6/LCD14
PTE7/LCD15
PTC0/LCD16
PTC1/LCD17
PTC2/LCD18
PTC3/LCD19
PTD7/LCD7
PTD6/LCD6
PTD5/LCD5
PTD4/LCD4
PTD3/LCD3
PTD2/LCD2
PTB3/LCD32
PTB2/LCD31
PTB1/LCD30
PTB0/LCD29
PTD1/LCD1
PTD0/LCD0
V
CAP1
V
CAP2
V
LL1
V
LL2
V
LL3
PTF5/MOSI/KBI2/TPM2CH3
PTF4/MISO/KBI1/TPM2CH4
PTI5/TPM2CH0/SCL/SS
PTI4/TPM2CH1/SDA/SPSCK
PTH7/KBI1/TPM2CH4
V
SS
V
DD
PTF7/EXTAL
PTF6/XTAL
V
DDA
/V
REFH
V
SSA
/V
REFL
PTH6/TPM2CH5/KBI0/ADC15
PTF2/SPSCK/TPM1CH1/IRQ/ADC14
PTF1/RX1/TPM1CH0/ADC13
PTF0/TX1/KBI3/TPM2CH2/ADC12
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
646362616059585756555453525150
49
PTC4/LCD20
PTA0/LCD21
PTG2/LCD35
PTG3/LCD36
PTA1/SCL/LCD22
PTA2/SDA/ADC0/LCD23
PTA3/KBI4/TX2/ADC1/LCD24
PTA4/KBI5/RX2/ADC2/LCD25
PTA5/KBI6/TPM2CH0/ADC3/LCD26
PTA6/KBI7/TPM2CH1/ADC4/LCD27
PTA7/TPMCLK/ADC5/LCD28
PTC5/BKGD/MS
PTC6/RESET
PTH4/RX1/KBI2/TPM1CH1/ADC10
PTH5/TX1/KBI3/TPM1CH0/ADC11
PTF3/SS
/KBI0/TPM2CH5
V
Freescale Semiconductor 29
REFH/VREFL
are internally connected to V
Figure 2-2. 64-Pin LQFP
NOTE
MC9S08LG32 MCU Series, Rev. 5
DDA/VSSA
.
Page 30
Chapter 2 Pins and Connections
PTD0/LCD0
1
2
3
4
5
6
7
8
PTD3/LCD3
V
DDA
/V
REFH
PTF6/XTAL
V
DD
V
SS
PTF4/MISO/KBI1/TPM2CH4
PTF5/MOSI/KBI2/TPM2CH3
PTA7/TPMCLK/ADC5/LCD28
PTC6/RESET
PTC2/LCD18
PTE7/LCD15
PTC0/LCD16
PTC1/LCD17
31
30
29
28
27
26
14
15
17 18
19
37
3839
13
24
25
36
48
9
10
11
V
CAP1
12
V
LL2
V
SSA
/V
REFL
20
PTF2/SPSCKS/TPM1CH1/IRQ/ADC14
21
PTF1/RX1/TPM1CH0/ADC13
22
23
PTC5/BKGD/MS
PTE6/LCD14
40
PTE5/LCD13
41
PTE4/LCD12
42
PTE3/LCD11
43
PTD2/LCD2
V
CAP2
V
LL1
32
33
34
35
PTE1/LCD9
47 46 45
PTE2/LCD10
44
PTD5/LCD5
PTD4/LCD4
V
LL3
PTF3/SS/KBI0/TPM2CH5
PTC3/LCD19
48-Pin LQFP
PTD1/LCD1
PTD7/LCD7
PTD6/LCD6
PTA1/SCL/LCD22
PTA2/SDA/ADC0/LCD23
PTA3/KBI4/TX2/ADC1/LCD24
PTA4/KBI5/RX2/ADC2/LCD25
PTA6/KBI7/TPM2CH1/ADC4/LCD27
PTA5/KBI6/TPM2CH0/ADC3/LCD26
PTC4/LCD20
PTA0/LCD21
PTE0/LCD8
PTF0/TX1/KBI3/TPM2CH2/ADC12
16
PTF7/EXTAL
V
REFH/VREFL
are internally connected to V
Figure 2-3. 48-Pin LQFP
NOTE
DDA/VSSA
.
MC9S08LG32 MCU Series, Rev. 5
30 Freescale Semiconductor
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Chapter 2 Pins and Connections
2.3 Recommended System Connections
Figure 2-4 shows pin connections that are common to MC9S08LG32 series application systems.
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 31
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Chapter 2 Pins and Connections
BKGD/MS
RESET
OPTIONAL
MANUAL
RESET
V
DD
BACKGROUND HEADER
C
2
C
1
X1
R
F
R
S
SYSTEM
POWER
MC9S08LG32
V
DDA/VREFH
V
SSA/VREFL
C
BYAD
0.1
μ
F
V
DD
V
SS
C
BY
0.1
μ
F
C
BLK
10
μ
F
+
5 V
+
XTAL
EXTAL
NOTES:
1
RESET pin can only be used to reset into user mode, you can not enter BDM using RESET pin. To enter BDM, hold MS low
during POR or write a 1 to BDFR in SBDFR with MS low after issuing BDM command.
2
RC filter on RESET pin recommended for noisy environments.
3
When PTC6 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal
pullup device.
4
When PTC5 is configured as BKGD, pin becomes bi-directional.
5
LCD mode shown is for Charge pump enabled, other configurations are necessary for different LCD modes.
(NOTE 3)
(NOTE 4)
LCD Glass
V
LL1
V
LL2
V
CAP2
0.1
μ
F
0.1
μ
F
0.1
μ
F
V
CAP1
0.1μF
V
LL3
LCD[44:0]
LCD
Module
LCD28/ADC5/TPMCLK/
PTA7
LCD25/ADC2/RX2/KBI5/
PTA4
PORT A
LCD24/ADC1/TX2/KBI4/
PTA3
LCD23/ADC0/SDA/
PTA2
LCD22/SCL/
PTA1
LCD21/
PTA0
PORT C
EXTAL/
PTF7
XTAL/
PTF6
TPM2CH4/KBI1/MISO
/
PTF4
PORT F
TPM2CH5/KBI0/
SS/
PTF3
ADC14/IRQ/TPM1CH1/SPSCK/
PTF2
ADC13/TPM1CH0/RX1/
PTF1
ADC12/TPM2CH2/KBI3/TX1/
PTF0
TPM2CH3/KBI2/MOSI/
PTF5
SPSCK/SDA/TPM2CH1/
PTI4
PORT I
MOSI/TPM2CH2/
PTI3
MISO/TPM2CH3/
PTI2
TX2/TMRCLK/
PTI1
RX2/
PTI0
SS
/SCL/TPM2CH0/
PTI5
PORT D
PORT E
LCD[40:37]/
PTB[7:4]
LCD[32:29]/
PTB[3:0]
LCD[20:16]/
PTC[4:0]
LCD[7:0]/
PTD[7:0]
PORT B
LCD[15:8]/
PTE[7:0]
LCD[44:41]/
PTG[7:4]
LCD[36:33]/
PTG[3:0]
PORT G
ADC11/TPM1CH0/KBI3/TX1/
PTH5
ADC10/TPM1CH1/KBI2/RX1/
PTH4
ADC[9:6]/KBI[7:4]/
PTH[3:0]
TPM2CH4/KBI1/
PTH7
ADC15/KBI0/TPM2CH5/
PTH6
PORT H
BKGD/MS
/PTC5
RESET_B
/PTC6
LCD27/ADC4/TPM2CH1/KBI7/
PTA6
LCD26/ADC3/TPM2CH0/KBI6/
PTA5
Available only on 80-pin package
Available only on 64-pin and 80-pin package
*/Default function out of reset/*
Figure 2-4. Basic System Connections
32 Freescale Semiconductor
MC9S08LG32 MCU Series, Rev. 5
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Chapter 2 Pins and Connections
2.3.1 Power
VDD and VSS are primary power supply pins for the MCU. This voltage source supplies power to all I/O
buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides a regulated
lower-voltage source for the CPU and other internal circuitry of the MCU.
The LCD/GPIO can be powered differently. For additional information, see Chapter 6, “Parallel
Input/Output Control.”
Typically, application systems have two separate capacitors across the power pins. In this case, there must
be a bulk electrolytic capacitor, such as a 10-μF tantalum capacitor, to provide bulk charge storage for the
overall system, and a 0.1-μF ceramic bypass capacitor located as near to the MCU power pins as practical
to suppress high-frequency noise.
V
and V
DDA
ADC modules.
are the analog power supply pins for the MCU. This voltage source supplies power to the
SSA
V
for the ADC module. For this MCU, V
REFH
and V
pins are the voltage reference high and the voltage reference low inputs, respectively,
REFL
shares the V
DDA
REFH
pin and V
shares the V
SSA
REFL
pin.
2.3.2 Oscillator
Immediately after reset, the MCU uses an internally generated clock provided by the internal clock source
(ICS) module. The ICS can be configured to run off the on-chip oscillator (ICSERCLK). The output of the
oscillator (OSCOUT) is used to run the RTC and LCD bypassing the ICS. The oscillator can be configured
to run in stop2 or stop3 modes. For more information, see Section 1.3, “System Clock Distribution,” and
Chapter 11, “Internal Clock Source (S08ICSV3).”
The oscillator (XOSC) in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic
resonator. An external clock source can optionally be connected to the EXTAL input pin.
Refer to Figure 2-4 for the following discussion. RS (when used) and RF must be low-inductance resistors,
such as carbon composition resistors. Wire-wound resistors and some metal film resistors have too much
inductance. C1 and C2 normally must be high-quality ceramic capacitors that are specifically designed for
high-frequency applications.
provides a bias path to keep the EXTAL input in its linear range during crystal startup; its value is not
R
F
generally critical. Typical systems use 1 MΩ to 10 MΩ. Higher values are sensitive to humidity and lower
values reduce gain and (in extreme cases) could prevent startup.
C1 and C2 are typically in the 5 pF to 25 pF range and are chosen to match the requirements of a specific
crystal or resonator. Be sure to consider the printed circuit board (PCB) capacitance and the MCU pin
capacitance when selecting C1 and C2. The crystal manufacturer typically specifies a load capacitance,
which is the series combination of C
and C2 (which are usually of the same size). As a first-order
1
approximation, use 10 pF as an estimate of combined pin and PCB capacitance for each oscillator pin
(EXTAL and XTAL).
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Chapter 2 Pins and Connections
2.3.3 RESET
After a power-on reset (POR), the PTC6/RESET pin defaults to RESET. Clearing RSTPE in SOPT1
configures the pin to be an output-only pin with an open-drain drive and an internal pullup device. RSTPE
is a write-once bit; so once written, it becomes read-only until the next reset. This bit is sticky and is reset
only at POR or LVD; it retains its value across other resets. When enabled, the RESET
reset the MCU from an external source when the pin is driven low.
Internal POR and low-voltage reset circuitry typically make external reset circuitry unnecessary. This pin
is normally connected to the standard 6-pin background debug connector, so a development system can
directly reset the MCU system. A manual external reset can be added by supplying a simple switch to
ground (pull reset pin low to force a reset).
Whenever any non-POR reset is initiated (whether from an external signal or from an internal system), the
enabled RESET
pin is driven low for about 34 bus cycles. The reset circuitry decodes the cause of reset
and records it by setting a corresponding bit in the system reset status register (SRS).
NOTE
This pin does not contain a clamp diode to VDD and must not be driven
above VDD.
The voltage on the internally pulled up RESET pin, when measured, is
below VDD. The internal gates connected to this pin are pulled to VDD. If
the RESET pin is required to drive to a V
level, an external pullup must
DD
be used.
pin can be used to
In EMC-sensitive applications, an external RC filter is recommended on the
RESET pin, if enabled.
2.3.4 Background / Mode Select (BKGD/MS)
During POR or background debug force reset (for more information, see Section 5.8.3, “System
Background Debug Force Reset Register (SBDFR)”), the PTC5/BKGD/MS pin functions as a mode select
pin. Immediately after any reset, the pin functions as the background pin and can be used for background
debug communication. When BKGD/MS function is enabled with BKGDPE = 1, an internal pullup device
automatically becomes active. Clearing BKGDPE in SOPT1 configures the pin to be an output-only pin.
The background debug communication function is enabled when BKGDPE in SOPT1 is set. BKGDPE is
set following any reset of the MCU and must be cleared to use the PTC5/BKGD/MS pin’s alternative pin
functions.
After any reset, if nothing is connected to this pin, the MCU enters normal operating mode. If a debug
system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low. It can do
this during a POR or after issuing a background debug force reset. This forces the MCU to active
background mode.
The BKGD/MS pin is used primarily with BDC communications, and features a custom protocol that uses
16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC clock can run as fast
MC9S08LG32 MCU Series, Rev. 5
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Chapter 2 Pins and Connections
as the bus clock, so no significant capacitance must be connected to the BKGD/MS pin that could interfere
with background serial communications.
Although the BKGD/MS pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play a minimal role in determining rise and fall
times on the BKGD/MS pin.
NOTE
Ensure this pin is not low when the part is coming out of POR or BDFR
reset. Exit from stop2 causes POR, therefore POR includes the exit from
stop2. Because the pin defaults to BKGD/MS function out of reset, a low
value on this pin while coming out of POR or BDFR causes the part to boot
into BDM mode. If this pin is not being used at all, it must be tied high. A
pullup is recommended when using this pin as GPIO.
2.3.5 IRQ
The PTF2/IRQ pin can be used as a wakeup source for the MCU. For stop2 wakeup, this pin has an analog
path which is enabled based on the input buffer enable for this pin, irrespective of whether or not this pin
is configured as IRQ.
NOTE
Care needs to be taken that if this pin is configured as input, it is not low
during stop2 mode, otherwise the part exits stop2 mode irrespective of
whether this pin is configured as IRQ or not. This pin can be disabled as a
wakeup source if it is configured as an output.
2.3.6 LCD Pins
2.3.6.1 LCD Power Pins
The V
64-pin and 80-pin packages the V
LCD pins, see Chapter 9, “LCD Module (S08LCDLPV1).”
2.3.6.2 LCD Driver Pins
The MC9S08LG32 series of MCUs provide 45 LCD driver pins for the 80-pin packages, 37 pins for the
64-pin packages, and 29 pins for the 48-pin packages. Each LCD pin has pin enable control, so you can
choose to use any LCD pin as either LCD driver or GPIO. If the LCD module is disabled, the LCD driver
pins become high-impedance and the LCD/GPIO pins are configured as GPIO. The LCD pins are
open-drain after resets except for stop2 wakeup. For more information about LCD driver pins, see
Chapter 9, “LCD Module (S08LCDLPV1).”
LL1
, V
LL2
, V
LL3
, V
cap1
, and V
LL3_2
pins are dedicated to providing power to the LCD module. On
cap2
pin must be tied to V
on board. For more information about
LL3
Pins that have shared function with the LCD have special behavior based on the state of the VSUPPLY
bits in the LCDSUPPLY register. These pins can operate as full complementary drive or open drain drive
MC9S08LG32 MCU Series, Rev. 5
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Chapter 2 Pins and Connections
depending on the VSUPPLY bits. When V
is connected to VDD externally, VSUPPLY = 11,
LL3
FCDEN = 1, and RVEN = 0, the pins operate as full complementary drive. For all other VSUPPLY modes,
the LCD/GPIO operates as open drain.
NOTE
For GPIO muxed with LCD pins, full complimentary or open drain drive is
controlled by the LCD controller. When LCD pins are configured as open
drain GPIOs, then the internal pullup is not disabled in output mode and is
controlled by the GPIO pull control register. This can cause some leakage
from the pads if a pullup is enabled and a zero is being driven.
2.3.7 General-Purpose I/O (GPIO) and Peripheral Ports
The MC9S08LG32 series of MCUs support up to 69 GPIO pins including 2 output-only pins that are
shared with on-chip peripheral functions (timers, serial I/O, LCD, ADC, etc.). The GPIO output-only pins
(PTC5/BKGD/MS and PTC6/RESET) are bi-directional when configured as BKGD and RESET,
respectively.
GPIO that is muxed with LCD pins can be configured to reference VDD or V
“LCD Driver Pins,” for more details.
When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output,
the software can select one of the two drive strengths and can enable or disable the slew rate control. When
a port pin is configured as a general-purpose input or a peripheral uses the port pin as an input, the software
can enable a pullup device.
. See Section 2.3.6.2,
LL3
When an on-chip peripheral system is controlling a pin, the data direction control bits still determine what
is read from port data registers even though the peripheral module controls the pin direction by controlling
an enable for the pin’s output buffer. For information about controlling these pins as general-purpose I/O
pins, see Chapter 6, “Parallel Input/Output Control.”
NOTE
• To avoid extra current drain from floating input pins, the reset
initialization routine in the application program must either enable
on-chip pullup devices or change the direction of unused or non-bonded
pins to outputs so they do not float.
• When using RESET
pin as bi-directional reset and LCD pins as
open-drain GPIO, the internal pullups are not disabled when these pins
are used in output mode. This can cause some current leakage through
the pads if zero is driven. This is also true for stop2 mode.
Table 2-1. Pin Availability by Package Pin-Count
Packages <-- Lowest Priority --> Highest
80 64 48 Port Pin Alt 1 Alt 2 Alt 3 Alt 4
1 1 1 PTD7 LCD7 — — —
2 2 2 PTD6 LCD6 — — —
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Chapter 2 Pins and Connections
Table 2-1. Pin Availability by Package Pin-Count (continued)
Packages <-- Lowest Priority --> Highest
80 64 48 Port Pin Alt 1 Alt 2 Alt 3 Alt 4
3 3 3 PTD5 LCD5 — — —
4 4 4 PTD4 LCD4 — — —
5 5 5 PTD3 LCD3 — — —
6 6 6 PTD2 LCD2 — — —
77—PTB3 LCD32 — — —
88—PTB2 LCD31 — — —
9—— PTB7 LCD40 — — —
10 — — PTB6 LCD39 — — —
11 — — PTB5 LCD38 — — —
12 — — PTB4 LCD37 — — —
13 9 — PTB1 LCD30 — — —
14 10 — PTB0 LCD29 — — —
15 11 7 PTD1 LCD1 — — —
16 12 8 PTD0 LCD0 — — —
17 13 9 V
18 14 10 V
19 15 11 V
20 16 12 V
21 17 13 V
CAP1
CAP2
LL1
LL2
LL3
22 18 14 PTF5 MOSI KBI2 TPM2CH3 —
23 19 15 PTF4 MISO KBI1 TPM2CH4 —
24 20 — PTI5 TPM2CH0 SCL SS
25 21 — PTI4 TPM2CH1 SDA SPSCK —
26 — — PTI3 TPM2CH2 MOSI — —
27 — — PTI2 TPM2CH3 MISO — —
28 — — PTI1 TMRCLK TX2 — —
29 — — PTI0 RX2 — — —
30 22 — PTH7 KBI1 TPM2CH4 — —
31 23 16 V
32 24 17 V
SS
DD
33 25 18 PTF7 EXTAL — — —
34 26 19 PTF6 XTAL — — —
35 27 20 V
36 28 21 V
DDA
SSA
37 29 — PTH6 TPM2CH5 KBI0 ADC15 —
38 30 22 PTF2 SPSCK TPM1CH1 IRQ ADC14
39 31 23 PTF1 RX1 TPM1CH0 ADC13 —
40 32 24 PTF0 TX1 KBI3 TPM2CH2 ADC12
—— — —
—— — —
—— — —
—— — —
—— — —
—
—— — —
—— — —
V
V
REFH
REFL
———
———
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 37
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Chapter 2 Pins and Connections
Table 2-1. Pin Availability by Package Pin-Count (continued)
Packages <-- Lowest Priority --> Highest
80 64 48 Port Pin Alt 1 Alt 2 Alt 3 Alt 4
41 33 25 PTF3 SS
KBI0 TPM2CH5 —
42 34 — PTH5 TX1 KBI3 TPM1CH0 ADC11
43 35 — PTH4 RX1 KBI2 TPM1CH1 ADC10
44 — — PTH3 KBI7 ADC9 — —
45 — — PTH2 KBI6 ADC8 — —
46 — — PTH1 KBI5 ADC7 — —
47 — — PTH0 KBI4 ADC6 — —
48 36 26 PTC6 RESET
———
49 37 27 PTC5 BKGD/MS — — —
50 38 28 PTA7 TPMCLK ADC5 LCD28 —
51 39 29 PTA6 KBI7 TPM2CH1 ADC4 LCD27
52 40 30 PTA5 KBI6 TPM2CH0 ADC3 LCD26
53 41 31 PTA4 KBI5 RX2 ADC2 LCD25
54 42 32 PTA3 KBI4 TX2 ADC1 LCD24
55 43 33 PTA2 SDA ADC0 LCD23 —
56 44 34 PTA1 SCL LCD22 — —
57 45 — PTG3 LCD36 — — —
58 46 — PTG2 LCD35 — — —
59 47 35 PTA0 LCD21 — — —
60 48 36 PTC4 LCD20 — — —
61 49 37 PTC3 LCD19 — — —
62 50 38 PTC2 LCD18 — — —
63 51 39 PTC1 LCD17 — — —
64 52 40 PTC0 LCD16 — — —
65 53 41 PTE7 LCD15 — — —
66 54 42 PTE6 LCD14 — — —
67 55 — V
68 56 — V
SS2
LL3_2
—— — —
—— — —
69 — — PTG7 LCD44 — — —
70 — — PTG6 LCD43 — — —
71 — — PTG5 LCD42 — — —
72 — — PTG4 LCD41 — — —
73 57 — PTG1 LCD34 — — —
74 58 — PTG0 LCD33 — — —
75 59 43 PTE5 LCD13 — — —
76 60 44 PTE4 LCD12 — — —
77 61 45 PTE3 LCD11 — — —
78 62 46 PTE2 LCD10 — — —
MC9S08LG32 MCU Series, Rev. 5
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Chapter 2 Pins and Connections
Table 2-1. Pin Availability by Package Pin-Count (continued)
Packages <-- Lowest Priority --> Highest
80 64 48 Port Pin Alt 1 Alt 2 Alt 3 Alt 4
79 63 47 PTE1 LCD9 — — —
80 64 48 PTE0 LCD8 — — —
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Chapter 2 Pins and Connections
MC9S08LG32 MCU Series, Rev. 5
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Chapter 3 Modes of Operation
3.1 Introduction
This chapter describes the operating modes of the MC9S08LG32 series. It also describes entry, exit, and
the functionality of each mode.
3.2 Features
• Active background mode for code development.
• Run mode — CPU clocks can be run at full speed and the internal supply is fully regulated.
• Wait mode — CPU shuts down to conserve power; system clocks are running and full regulation
is maintained.
• Stop modes — System clocks are stopped and voltage regulator is in standby.
— Stop3 — All internal circuits are powered for fast recovery.
— Stop2 — Partial power down of internal circuits, RAM content is retained, and the I/O states
are held.
3.3 Run Mode
This is the normal operating mode for the MC9S08LG32 series. In this mode, the CPU executes code from
internal memory with execution beginning at the address fetched from memory at 0xFFFE–0xFFFF after
reset.
3.4 Active Background Mode
The active background mode functions are managed through the BDC in the HCS08 core. The BDC and
the on-chip debug module (DBG), provide the means for analyzing MCU operation during software
development.
Active background mode is entered by any of six methods:
• When the BKGD/MS pin is low during POR
• When the BKGD/MS pin is low immediately after issuing a background debug force reset (for
more information, see Section 5.8.3, “System Background Debug Force Reset Register (SBDFR)”)
• When a BACKGROUND command is received through the BKGD/MS pin
• When a BGND instruction is executed
• When encountering a BDC breakpoint
MC9S08LG32 MCU Series, Rev. 5
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Chapter 3 Modes of Operation
• When encountering a DBG breakpoint
NOTE
The MCU needs to be unsecure for the last four methods.
After entering active background mode, the CPU is held in a suspended state while it waits for serial
background commands instead of executing instructions from the user application program.
The background commands are of two types:
• Non-intrusive commands — These commands are defined as commands that can be issued while
the user program is running. Non-intrusive commands can be issued through the BKGD pin while
the MCU is in run mode. Non-intrusive commands can also be executed when the MCU is in active
background mode. Non-intrusive commands include:
— Memory access commands
— Memory-access-with-status commands
— BDC register access commands
— The BACKGROUND command
• Active background commands— These commands can only be executed while the MCU is in
active background mode. Active background commands include commands to:
— Read or write CPU registers
— Trace one user program instruction at a time
— Leave active background mode to return to the user application program (GO)
Active background mode is used to program a bootloader or user application program into the flash
program memory before the MCU is operated in run mode for the first time. When the MC9S08LG32
series is shipped from the Freescale Semiconductor factory, the flash program memory is erased by default,
unless specifically noted. As a result, no program can be executed in run mode until the flash memory is
initially programmed. Active background mode can also be used to erase and reprogram the flash memory
after it has been previously programmed.
For additional information about the active background mode, refer to the Chapter 18, “Development
Support.”
3.5 Wait Mode
Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU
enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters wait
mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and resumes
processing beginning with the stacking operations that lead to the interrupt service routine.
While the MCU is in wait mode, there are some restrictions on which background debug commands can
be used. Only the BACKGROUND command and memory-access-with-status commands are available
when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access,
but they report an error indicating that the MCU is either in stop or wait mode. The BACKGROUND
command can be used to wake the MCU from the wait mode and enter active background mode.
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Chapter 3 Modes of Operation
The clocks to the peripherals are controlled by SCGC registers in this mode. For lowest possible current
in WAIT mode, all peripherals which are not required must be clock gated before entering in this mode.
3.6 Stop Modes
One of the two stop modes (stop2 or stop3) is entered upon execution of a STOP instruction when the
STOPE bit in the system option 1 register (SOPT1) is set. In both the stop modes, the bus and the CPU
clocks are halted.
• In stop3, the voltage regulator is in standby and ICS module can be configured to leave the
reference clocks running.
• In stop2, the voltage regulator is in partial powerdown.
See Chapter 11, “Internal Clock Source (S08ICSV3),” for more information.
If the STOPE bit is not set when the CPU executes a STOP instruction, the MCU does not enter either of
the stop modes and an illegal opcode reset is forced. Stop modes are selected by setting the appropriate
bits in the System Power Management Status and Control Registers, SPMSC1 and SPMSC2.
Table 3-1 shows all control bits that affect the stop mode selection and the modes selected under various
conditions. The selected mode is entered following the execution of a STOP instruction.
Table 3-1. Stop Mode Selection
Register SOPT1 BDCSCR SPMSC1 SPMSC2
Bit name STOPE ENBDM
0 x x x Stop modes disabled; illegal opcode reset if STOP
1 1 x x Stop3 with BDM enabled
1 0 Both bits must be 1 x Stop3 with voltage regulator active
1 0 Either bit a 0 0 Stop3 (with Voltage regulator in Standby)
1 0 Either bit a 0 1 Stop2
1
ENBDM is located in the BDCSCR that is only accessible through BDC commands, see Chapter 18, “Development
Support.”
2
When in stop3 mode with BDM enabled, the S
1
LV DE LV D SE P PD C
is near the R
IDD
instruction executed
levels because internal clocks are enabled.
IDD
Stop Mode
2
3.6.1 Stop2 Mode
To enter stop2, execute a STOP instruction under the conditions as shown in Tab le 3-1 . Most of an internal
circuitry of the MCU is powered off in stop2 mode with an exception of the RAM, the low power
oscillator, RTC and the LCD module. Upon entering stop2 mode, all I/O pin control signals are latched so
that the pins retain their states during stop2. The LCD driver pins continue to drive the signals necessary
to display the LCD data.
To exit from stop2 mode, assert the wakeup pins (PTC6/RESET
or PTF2/IRQ) or through RTC interrupt
or POR.
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Chapter 3 Modes of Operation
NOTE
When PTC6/RESET or PTF2/IRQ is used as an active low wakeup source
it must be configured as an input prior to executing a STOP instruction.
PTC6/RESET and PTF2/IRQ can be disabled as a wakeup if it is configured
as output port. For lowest power consumption in stop2, these pins must not
be left open if configured as input (enable the internal pullup or tie an
external pullup device).
Upon wakeup from stop2 mode, the MCU starts up as from a POR with the following sequence:
• All module control and status registers are reset, except for SPMSC1-SPMSC2, RTCSC,
RTCCNT, RTCMOD, LCDPENx, LCDBPENx, and LCDWFRx.
• The LVD reset function is enabled and the MCU remains in the reset state if V
is below the LVD
DD
trip point.
• The CPU takes the reset vector
In addition to the above, upon waking up from stop2 mode, the PPDF bit in SPMSC2 is set. This flag is
used to direct user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain
latched until a 1 is written to PPDACK in SPMSC2.
If using the low-power oscillator during stop2 mode, you reconfigure the ICSC2 register that contains
oscillator control bits before PPDACK is written.
To maintain I/O states for pins that were configured as GPIO before entering stop2, you restore the
contents of the I/O port registers to the port registers before writing to the PPDACK bit. If the port registers
are not restored from RAM before writing to PPDACK, then the pins are switched to their reset states when
PPDACK is written.
For pins that were configured as peripheral I/O, you reconfigure the peripheral module that interfaces to
the pin before writing to the PPDACK bit. If the peripheral module is not enabled before writing to
PPDACK, the pins are controlled by their associated port control registers when the I/O latches are opened.
If enabled, LCD functionality continues in stop2 mode and upon stop2 recovery the LCD control registers
(LCDC0, LCDC1, LCDSUPPLY, LCDRVC, LCDBCTL, and LCDS) must be re-initialized before writing
the PPDACK.
3.6.2 Stop3 Mode
To enter stop3 mode, execute a STOP instruction under the conditions shown in Tabl e 3-1 . The states of
all the internal registers and logic, RAM contents, and I/O pin states are maintained.
Stop3 mode can be exited by asserting RESET, or by an interrupt from one of the following sources: LVW,
RTC, ADC, IRQ, SCI1, SCI2, LCD, or KBI.
If stop3 is exited by means of the RESET
reset vector. Using an internal interrupt sources to exit, results in the MCU taking an appropriate interrupt
vector.
pin, the MCU is reset and operation resumes after taking the
MC9S08LG32 MCU Series, Rev. 5
44 Freescale Semiconductor
Page 45
Chapter 3 Modes of Operation
3.6.3 Active BDM Enabled in Stop Mode
Entry into active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set. This
register is described in Chapter 18, “Development Support.” If ENBDM is set when the CPU executes a
STOP instruction, the system clocks to the background debug logic remain active when the MCU enters
the stop mode. Because of this, background debug communication remains possible. In addition, the
voltage regulator does not enter its low-power standby state, but maintains full internal regulation. If you
attempt to enter the stop2 mode with ENBDM set, the MCU enters the stop3 mode instead.
Most background commands are not available in the stop mode. The memory-access-with-status
commands do not allow memory access, but they report an error indicating that the MCU is in either stop
or wait mode. The BACKGROUND command can be used to wake the MCU from the stop mode and enter
the active background mode if the ENBDM bit is set. After entering the background debug mode, all
background commands are available.
3.6.4 LVD Enabled in Stop Mode
The LVD system can generate a reset or an interrupt when the supply voltage drops below the LVD or
LVW threshold respectively. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set),
the voltage regulator remains active during stop mode. If you attempt to enter the stop2 mode with LVD
enabled for stop, the MCU enters the stop3 mode instead.
3.7 Mode Selection
Several control signals are used to determine the current operating mode of the device. Table 3-2 shows
the conditions for each of the device’s operating modes.
Table 3-2. Power Mode Selections
Mode of Operation
RUN mode 0 x x x On. ICS in any mode. off on
WAIT mode—(Assumes
WAIT instruction executed.)
Stop3—(Assumes STOPE
bit is set and STOP
instruction executed.) Note
that stop3 is used in place of
stop2 if the BDM or LVD is
enabled.
BDCSCR
BDM
ENBDM
1on
0 x x x CPU clock is off;
1on
0 0 x 0 ICS in STOP. OSCOUT
010 0 off
0 1 1 x off on—stop
1 x x x ICSLCLK still active. on
SPMSC1
PMC
1
LV DE LVD SE P PD C
SPMSC2
PMC
CPU & Periph CLKs
peripheral clocks on. ICS
state is same as RUN
mode.
optionally on.
2
Affects on
Sub-System
BDM
Clock
off on
off standby
Volt ag e
Regulator
currents
increased.
are
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 45
Page 46
Chapter 3 Modes of Operation
Mode Regulator State
Run Full on
Wait Full on
Stop3 Standby
Stop2 Partial powerdown
Run
Stop3
Stop2
Wait
3
1
2
Table 3-2. Power Mode Selections (continued)
Mode of Operation
Stop2—(Assumes STOPE
bit is set and STOP
instruction executed.) If BDM
BDCSCR
BDM
ENBDM
0 0 x 1 OSCOUT optionally on.
SPMSC1
SPMSC2
PMC
1
LV DE LVD SE P PD C
10
PMC
CPU & Periph CLKs
2,3
Affects on
Sub-System
BDM
Clock
off partial
or LVD is enabled, stop3 is
invoked rather than stop2.
1
ENBDM is located in the BDC status and control register (BDCSCR) which is write-accessible only through BDC
commands.
2
Configured within the ICS module based on the settings of IREFSTEN, EREFSTEN, IRCLKEN and ERCLKEN.
3
In stop2, the CPU, flash, ICS and all peripheral modules are powered down except for the RTC and LCD.
Volt ag e
Regulator
powerdown
Figure 3-1. Allowable Power Mode Transitions for the MC9S08LG32 Series
Figure 3-1 illustrates mode state transitions allowed between the legal states shown in Tab le 3- 1.
Table 3-3 defines triggers for the various state transitions shown in Figure 3-1.
Table 3 - 3 . Tr i gg ers fo r Tr a n si ti o ns Shown in Figure 3-1.
Transition # From To Trigger
1 Run Wait WAIT instruction
Wait Run Interrupt or reset
2 Run Stop3 Pre-configure settings shown in Ta b le 3 - 1 , issue
46 Freescale Semiconductor
STOP instruction
Stop3 Run Interrupt or reset
MC9S08LG32 MCU Series, Rev. 5
Page 47
Chapter 3 Modes of Operation
Table 3-3. Triggers for Transitions Shown in Figure 3-1. (continued)
Transition # From To Trigger
3 Run Stop2 Pre-configure settings shown in Ta b le 3 - 1 , issue
STOP instruction
Stop2 Run assert zero on wakup pins (PTC6/RESET or
PTF2/IRQ)
1
An analog connection from these pins to the on-chip regulator wakes up the regulator, which initiates a power-on-reset
1
or RTC interrupt or POR
sequence.
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 47
Page 48
Chapter 3 Modes of Operation
3.7.1 On-Chip Peripheral Modules in Stop Modes
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.1, “Stop2
Mode,” and Section 3.6.2, “Stop3 Mode,” for specific information on system behavior in stop modes.
Table 3-4. Stop and Low Power Mode Behavior
Peripheral
Mode
Stop2 Stop3
CPU Off Standby
RAM Standby Standby
FLASH Off Standby
Port I/O Registers Off Standby
ADC Off Optionally On
BDM Off
2
Optionally On
COP Off Off
ICS Off Optionally On
IIC Off Standby
IRQ Wake Up Optionally On
KBI Off Optionally On
LV D/ LV W O ff
4
Optionally On
LCD Optionally On Optionally On
MTIM Off Optionally On
SCIx Off Standby
SPI Off Standby
RTC Optionally On Optionally On
TPMx Off Standby
Voltage Regulator Partial Powerdown Optionally On
XOSC Optionally On
6
Optionally On
I/O Pins States Held Peripheral Control
1
Requires the asynchronous ADC clock. For stop3, LVD must be enabled to
run in stop if converting the bandgap channel.
2
If ENBDM is set when entering stop2, the MCU will actually enter stop3.
3
IRCLKEN and IREFSTEN set in ICSC1, else in standby.
4
If LVDSE is set when entering stop2, the MCU will actually enter stop3.
5
Requires the LVD to be enabled, else in standby. See Section 3.6.4, “LVD
Enabled in Stop Mode”.
6
ERCLKEN and EREFSTEN set in ICSC2, else in standby.
1
3
5
6
MC9S08LG32 MCU Series, Rev. 5
48 Freescale Semiconductor
Page 49
Chapter 4 Memory
4.1 Introduction
This chapter describes the on-chip memory in the MC9S08LG32 series of MCUs. It details the memory
map, vector and bit assignments, registers and control bits, and other RAM and flash features.
4.2 MC9S08LG32 Series Memory Map
As shown in Figure 4-1, on-chip memory in the MC9S08LG32 series of MCUs consists of RAM, flash
memory for nonvolatile data storage, and I/O and control/status registers. The registers are divided into
four groups:
• Direct-page registers (0x0000 through 0x005F)
• LCD data registers (0x0820 through 0x085C)
• High-page registers (0x1800 through 0x187A)
• Nonvolatile registers (0xFFB0 through 0xFFBF)
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 49
Page 50
Chapter 4 Memory
MC9S08LG32
DIRECT PAGE REGISTERS
RAM
HIGH PAGE REGISTERS
1984 BYTES
0x1800
0x17FF
0xFFFF
16,384 BYTES
UNIMPLEMENTED
0x7FFF
0x8000
0x005F
0x0060
0x187A
0x187B
0x081F
0x0820
MC9S08LG16
0xFFFF
2048 BYTES
16,384 BYTES
FLASH A
FLASH A
0xC000
0xB7FF
FLASHB
Flash B
LCD Registers
0x085C
0x0860
UNIMPLEMENTED
4000 BYTES
DIRECT PAGE REGISTERS
RAM
HIGH PAGE REGISTERS
1984 BYTES
0x1800
0x17FF
UNIMPLEMENTED
0x005F
0x0060
0x187A
0x187B
0x081F
0x0820
LCD Registers
0x085C
0x0860
4000 BYTES
0xC000
0x0000
0x0000
UNIMPLEMENTED
16,384 BYTES
Note:
0x085C-0x085F is reserved. Unlike un-implemented spaces, access to these locations would not cause illegal address
reset.
0xB800
Figure 4-1. MC9S08LG32 Series Memory Maps
4.3 Reset and Interrupt Vector Assignments
Table 4-1 shows the address assignments for reset and interrupt vectors. The vector names shown in this
table are labels used in the Freescale Semiconductor equate file for the MC9S08LG32 series.
Address
(High/Low)
0xFF80:FF81
0xFFC8:FFC9
Table 4-1. Reset and Interrupt Vectors (Sheet 1 of 2)
Vector Vector Name
Unused Vector Space
(available for user program)
50 Freescale Semiconductor
MC9S08LG32 MCU Series, Rev. 5
Page 51
Table 4-1. Reset and Interrupt Vectors (Sheet 2 of 2) (continued)
Chapter 4 Memory
Address
(High/Low)
Vector Vector Name
0xFFCA:0xFFCB RTC Vrtc
0xFFCC:0xFFCD Modulo Timer Vmtim
0xFFCE:0xFFCF TPM2 Overflow Vtpm2ovf
0xFFD0:0xFFD1 TPM2 Channel 5 Vtpm2ch5
0xFFD2:0xFFD3 TPM2 Channel 4 Vtpm2ch4
0xFFD4:0xFFD5 TPM2 Channel 3 Vtpm2ch3
0xFFD6:0xFFD7 TPM2 Channel 2 Vtpm2ch2
0xFFD8:0xFFD9 TPM2 Channel 1 Vtpm2ch1
0xFFDA:0xFFDB TPM2 Channel 0 Vtpm2ch0
0xFFDC:0xFFDD ADC Conversion Vadc
0xFFDE:0xFFDF KBI Interrupt Vkeyboard
0xFFE0:0xFFE1 IIC Viic
0xFFE2:0xFFE3 SCI2 Transmit Vsci2tx
0xFFE4:0xFFE5 SCI2 Receive Vsci2rx
0xFFE6:0xFFE7 SCI2 Error Vsci2err
0xFFE8:0xFFE9 SPI Vspi
0xFFEA:0xFFEB LCD Frame Vlcd
0xFFEC:0xFFED SCI1 Transmit Vsci1tx
0xFFEE:0xFFEF SCI1 Receive Vsci1rx
0xFFF0:0xFFF1 SCI1 Error Vsci1err
0xFFF2:0xFFF3 TPM1 Overflow Vtpm1ovf
0xFFF4:0xFFF5 TPM1 Channel 1 Vtpm1ch1
0xFFF6:0xFFF7 TPM1 Channel 0 Vtpm1ch0
0xFFF8:0xFFF9 Low Voltage Warning Vlvw
0xFFFA:0xFFFB IRQ Virq
0xFFFC:0xFFFD SWI Vswi
0xFFFE:0xFFFF Reset Vreset
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 51
Page 52
Chapter 4 Memory
4.4 Register Addresses and Bit Assignments
The register groups in the MC9S08LG32 series consist of the following locations in the memory map:
• Direct-page registers are located at the first 96 locations. Access these locations with efficient
direct addressing mode instructions.
• LCD Registers, LCDPENx, LCDBPENx, LCDWFx are located at the end of the RAM module.
• High-page registers are used much less often, so they are located above 0x1800 in the memory
map. This leaves more room in the direct page registers for more frequently used registers and
RAM.
• The nonvolatile register area consists of a block of 16 locations in flash memory at
0xFFB0–0xFFBF. Nonvolatile register locations include:
— NVPROT and NVOPT are loaded into working registers at reset
— An 8-byte backdoor comparison key that optionally allows controlled access to secure memory
Because the nonvolatile register locations are flash memory, they must be erased and programmed
like other flash memory locations.
Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation
instructions can be used to access any bit in any direct-page register. Table 4- 2 is a summary of all
user-accessible direct-page registers and control bits.
The direct page registers in Table 4-2 can use the more efficient direct addressing mode, which requires
only the lower byte of the address. Because of this, the lower byte of the address in column one is shown
in bold text. In Table 4-4 and Tab le 4-5, the whole address in column one is shown in bold. In Tabl e 4-2,
Table 4-4, and Tab le 4- 5, the register names in column two are shown in bold to set them apart from the
bit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0
indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit
locations that could read as 1s or 0s. When writing to these bits, write a 0 unless otherwise specified.
MC9S08LG32 MCU Series, Rev. 5
52 Freescale Semiconductor
Page 53
Table 4-2. Direct-Page Register Summary (Sheet 1 of 3)
Chapter 4 Memory
Address
0x0000 PTAD PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
0x0001 PTADD PTADD7 PTADD6 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0
0x0002 PTBD PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD0
0x0003 PTBDD PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0
0x0004 PTCD
0x0005 PTCDD 0 PTCDD6 PTCDD5 PTCDD4 PTCDD3 PTCDD2 PTCDD1 PTCDD0
0x0006 PTDD PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0
0x0007 PTDDD PTDDD7 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0
0x0008 IICA AD7 AD6 AD5 AD4 AD3 AD2 AD1
0x0009 IICF MULT ICR
0x000A IICC1
0x000B IICS TCF IAAS BUSY ARBL 0SRWIICIFRXAK
0x000C IICD DATA
0x000D IICC2 GCAEN ADEXT
0x000E PTED PTED7 PTED6 PTED5 PTED4 PTED3 PTED2 PTED1 PTED0
0x000F PTEDD PTEDD7 PTEDD6 PTEDD5 PTEDD4 PTEDD3 PTEDD2 PTEDD1 PTEDD0
0x0010 SCI1BDH LBKDIE RXEDGIE
0x0011 SCI1BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
0x0012 SCI1C1 LOOPS SCISWAI RSRC M WAKE ILT PE PT
0x0013 SCI1C2 TIE TCIE RIE ILIE TE RE RWU SBK
0x0014 SCI1S1 TDRE TC RDRF IDLE OR NF FE PF
0x0015 SCI1S2 LBKDIF RXEDGIF
0x0016 SCI1C3 R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE
0x0017 SCI1D Bit 7 6 5 4 3 2 1 Bit 0
0x0018 SCI2BDH LBKDIE RXEDGIE
0x0019 SCI2BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
0x001A SCI2C1 LOOPS SCISWAI RSRC M WAKE ILT PE PT
0x001B SCI2C2 TIE TCIE RIE ILIE TE RE RWU SBK
0x001C SCI2S1 TDRE TC RDRF IDLE OR NF FE PF
0x001D SCI2S2 LBKDIF RXEDGIF
0x001E SCI2C3 R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE
0x001F SCI2D Bit 7 6 5 4 3 2 1 Bit 0
0x0020 TPM2SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
0x0021 TPM2CNTH Bit 15 14 13 12 11 10 9 Bit 8
0x0022 TPM2CNTL Bit 7 6 5 4 3 2 1 Bit 0
0x0023 TPM2MODH Bit 15 14 13 12 11 10 9 Bit 8
0x0024 TPM2MODL Bit 7 6 5 4 3 2 1 Bit 0
0x0025 TPM2C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A
0x0026 TPM2C0VH Bit 15 14 13 12 11 10 9 Bit 8
0x0027 TPM2C0VL Bit 7 6 5 4 3 2 1 Bit 0
0x0028 TPM2C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A
0x0029 TPM2C1VH Bit 15 14 13 12 11 10 9 Bit 8
Register
Name
Bit 7 6 5 4 3 2 1 Bit 0
0 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0
IICEN IICIE MST TX TXAK RSTA 0 0
0 0 0 AD10 AD9 AD8
0 SBR12 SBR11 SBR10 SBR9 SBR8
0 RXINV RWUID BRK13 LBKDE RAF
0 SBR12 SBR11 SBR10 SBR9 SBR8
0 RXINV RWUID BRK13 LBKDE RAF
0
0 0
0 0
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 53
Page 54
Chapter 4 Memory
Table 4-2. Direct-Page Register Summary (Sheet 2 of 3)
Address
Register
Name
Bit 7 6 5 4 3 2 1 Bit 0
0x002A TPM2C1VL Bit 7 6 5 4 3 2 1 Bit 0
0x002B TPM2C2SC CH2F CH2IE MS2B MS2A ELS2B ELS2A 0 0
0x002C TPM2C2VH Bit 15 14 13 12 11 10 9 Bit 8
0x002D TPM2C2VL Bit 7 6 5 4 3 2 1 Bit 0
0x002E TPM2C3SC CH3F CH3IE MS3B MS3A ELS3B ELS3A
0 0
0x002F TPM2C3VH Bit 15 14 13 12 11 10 9 Bit 8
0x0030 TPM2C3VL Bit 7 6 5 4 3 2 1 Bit 0
0x0031 TPM2C4SC CH4F CH4IE MS4B MS4A ELS4B ELS4A
0 0
0x0032 TPM2C4VH Bit 15 14 13 12 11 10 9 Bit 8
0x0033 TPM2C4VL Bit 7 6 5 4 3 2 1 Bit 0
0x0034 TPM2C5SC CH5F CH5IE MS5B MS5A ELS5B ELS5A
0 0
0x0035 TPM2C5VH Bit 15 14 13 12 11 10 9 Bit 8
0x0036 TPM2C5VL Bit 7 6 5 4 3 2 1 Bit 0
0x0037 IRQSC
0 IRQPDD IRQEDG IRQPE IRQF IRQACK IRQIE IRQMOD
0x0038 LCDC0 LCDEN SOURCE LCLK2 LCLK1 LCLK0 DUTY2 DUTY1 DUTY0
0x0039 LCDC1 LCDIEN
0x003A LCDSUPPLY CPSEL HREFSEL LADJ1 LADJ0
0 0 0 0 FCDEN LCDWAI LCDSTP
0 BBYPASS VSUPPLY1 VSUPPLY0
0x003B LCDRVC RVEN 0 0 0 RVTRIM3 RVTRIM2 RVTRIM1 RVTRIM0
0x003C LCDBCTL BLINK ALT BLANK
0x003D LCDS LCDIF
0 0 0 0 0 0 0
0 BMODE BRATE2 BRATE1 BRATE0
0x003E PTFD PTFD7 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0
0x003F PTFDD PTFDD7 PTFDD6 PTFDD5 PTFDD4 PTFDD3 PTFDD2 PTFDD1 PTFDD0
0x0040 TPM1SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
0x0041 TPM1CNTH Bit 15 14 13 12 11 10 9 Bit 8
0x0042 TPM1CNTL Bit 7 6 5 4 3 2 1 Bit 0
0x0043 TPM1MODH Bit 15 14 13 12 11 10 9 Bit 8
0x0044 TPM1MODL Bit 7 6 5 4 3 2 1 Bit 0
0x0045 TPM1C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A
0 0
0x0046 TPM1C0VH Bit 15 14 13 12 11 10 9 Bit 8
0x0047 TPM1C0VL Bit 7 6 5 4 3 2 1 Bit 0
0x0048 TPM1C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A
0 0
0x0049 TPM1C1VH Bit 15 14 13 12 11 10 9 Bit 8
0x004A TPM1C1VL Bit 7 6 5 4 3 2 1 Bit 0
0x004B ADCSC1 COCO AIEN ADCO ADCH
0x004C ADCSC2 ADACT ADTRG ACFE ACFGT
0x004D ADCRH
0 0 0 0 ADR11 ADR10 ADR9 ADR8
0 0 — —
0x004E ADCRL ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
0x004F ADCCVH
0 0 0 0 ADCV11 ADCV10 ADCV9 ADCV8
0x0050 ADCCVL ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0
0x0051 ADCCFG ADLPC ADIV ADLSMP MODE ADICLK
0x0052 APCTL1 ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0
0x0053 APCTL2 ADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8
MC9S08LG32 MCU Series, Rev. 5
54 Freescale Semiconductor
Page 55
Table 4-2. Direct-Page Register Summary (Sheet 3 of 3)
Chapter 4 Memory
Address
0x0054 PTGD PTGD7 PTGD6 PTGD5 PTGD4 PTGD3 PTGD2 PTGD1 PTGD0
0x0055 PTGDD PTGDD7 PTGDD6 PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0
0x0056 PTHD PTHD7 PTHD6 PTHD5 PTHD4 PTHD3 PTHD2 PTHD1 PTHD0
0x0057 PTHDD PTHDD7 PTHDD6 PTHDD5 PTHDD4 PTHDD3 PTHDD2 PTHDD1 PTHDD0
0x0058 SPIC1 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
0x0059 SPIC2
0x005A SPIBR
0x005B SPIS SPRF
0x005C Reserved 0 0 0 0 0 0 0 0
0x005D SPID Bit 7 6 5 4 3 2 1 Bit 0
0x005E PTID
0x005F PTIDD 0 0 PTIDD5 PTIDD4 PTIDD3 PTIDD2 PTIDD1 PTIDD0
Register
Name
Bit 7 6 5 4 3 2 1 Bit 0
0 0 0 MODFEN BIDIROE 0 SPISWAI SPC0
0 SPPR2 SPPR1 SPPR0 SPR3 SPR2 SPR1 SPR0
0 SPTEF MODF 0 0 0 0
0 0 PTID5 PTID4 PTID3 PTID2 PTID1 PTID0
Use the LCD registers shown in table below to enable LCD functionality and display the LCD data.
Table 4-3. LCD Registers (Sheet 1 of 2)
Address
0x0820 LCDPEN0 PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0
0x0821 LCDPEN1 PEN15 PEN14 PEN13 PEN12 PEN11 PEN10 PEN9 PEN8
0x0822 LCDPEN2 PEN23 PEN22 PEN21 PEN20 PEN19 PEN18 PEN17 PEN16
0x0823 LCDPEN3 PEN31 PEN30 PEN29 PEN28 PEN27 PEN26 PEN25 PEN24
0x0824 LCDPEN4 PEN39 PEN38 PEN37 PEN36 PEN35 PEN34 PEN33 PEN32
0x0825 LCDPEN5
0x0826
0x0827
0x0828 LCDBPEN0 BPEN7 BPEN6 BPEN5 BPEN4 BPEN3 BPEN2 BPEN1 BPEN0
0x0829 LCDBPEN1 BPEN15 BPEN14 BPEN13 BPEN12 BPEN11 BPEN10 BPEN9 BPEN8
0x082A LCDBPEN2 BPEN23 BPEN22 BPEN21 BPEN20 BPEN19 BPEN18 BPEN17 BPEN16
0x082B LCDBPEN3 BPEN31 BPEN30 BPEN29 BPEN28 BPEN27 BPEN26 BPEN25 BPEN24
0x082C LCDBPEN4 BPEN39 BPEN38 BPEN37 BPEN36 BPEN35 BPEN34 BPEN33 BPEN32
0x082D LCDBPEN5
0x082E
0x082F
0x0830 LCDWF0 BPHLCD0 BPGLCD0 BPFLCD0 BPELCD0 BPDLCD0 BPCLCD0 BPBLCD0 BPALCD0
0x0831 LCDWF1 BPHLCD1 BPGLCD1 BPFLCD1 BPELCD1 BPDLCD1 BPCLCD1 BPBLCD1 BPALCD1
0x0832 LCDWF2 BPHLCD2 BPGLCD2 BPFLCD2 BPELCD2 BPDLCD2 BPCLCD2 BPBLCD2 BPALCD2
0x0833 LCDWF3 BPHLCD3 BPGLCD3 BPFLCD3 BPELCD3 BPDLCD3 BPCLCD3 BPBLCD3 BPALCD3
0x0834 LCDWF4 BPHLCD4 BPGLCD4 BPFLCD4 BPELCD4 BPDLCD4 BPCLCD4 BPBLCD4 BPALCD4
0x0835 LCDWF5 BPHLCD5 BPGLCD5 BPFLCD5 BPELCD5 BPDLCD5 BPCLCD5 BPBLCD5 BPALCD5
0x0836 LCDWF6 BPHLCD6 BPGLCD6 BPFLCD6 BPELCD6 BPDLCD6 BPCLCD6 BPBLCD6 BPALCD6
0x0837 LCDWF7 BPHLCD7 BPGLCD7 BPFLCD7 BPELCD7 BPDLCD7 BPCLCD7 BPBLCD7 BPALCD7
0x0838 LCDWF8 BPHLCD8 BPGLCD8 BPFLCD8 BPELCD8 BPDLCD8 BPCLCD8 BPBLCD8 BPALCD8
Register
Name
Reserved
Reserved —
Bit 7 6 5 4 3 2 1 Bit 0
— — — PEN44 PEN43 PEN42 PEN41 PEN40
—
—
— — — BPEN44 BPEN43 BPEN42 BPEN41 BPEN40
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 55
Page 56
Chapter 4 Memory
Table 4-3. LCD Registers (Sheet 2 of 2)
Address
0x0839 LCDWF9 BPHLCD9 BPGLCD9 BPFLCD9 BPELCD9 BPDLCD9 BPCLCD9 BPBLCD9 BPALCD9
0x083A LCDWF10 BPHLCD10 BPGLCD10 BPFLCD10 BPELCD10 BPDLCD10 BPCLCD10 BPBLCD10 BPALCD10
0x083B LCDWF11 BPHLCD11 BPGLCD11 BPFLCD11 BPELCD11 BPDLCD11 BPCLCD11 BPBLCD11 BPALCD11
0x083C LCDWF12 BPHLCD12 BPGLCD12 BPFLCD12 BPELCD12 BPDLCD12 BPCLCD12 BPBLCD12 BPALCD12
0x083D LCDWF13 BPHLCD13 BPGLCD13 BPFLCD13 BPELCD13 BPDLCD13 BPCLCD13 BPBLCD13 BPALCD13
0x083E LCDWF14 BPHLCD14 BPGLCD14 BPFLCD14 BPELCD14 BPDLCD14 BPCLCD14 BPBLCD14 BPALCD14
0x083F LCDWF15 BPHLCD15 BPGLCD15 BPFLCD15 BPELCD15 BPDLCD15 BPCLCD15 BPBLCD15 BPALCD15
0x0840 LCDWF16 BPHLCD16 BPGLCD16 BPFLCD16 BPELCD16 BPDLCD16 BPCLCD16 BPBLCD16 BPALCD16
0x0841 LCDWF17 BPHLCD17 BPGLCD17 BPFLCD17 BPELCD17 BPDLCD17 BPCLCD17 BPBLCD17 BPALCD17
0x0842 LCDWF18 BPHLCD18 BPGLCD18 BPFLCD18 BPELCD18 BPDLCD18 BPCLCD18 BPBLCD18 BPALCD18
0x0843 LCDWF19 BPHLCD19 BPGLCD19 BPFLCD19 BPELCD19 BPDLCD19 BPCLCD19 BPBLCD19 BPALCD19
0x0844 LCDWF20 BPHLCD20 BPGLCD20 BPFLCD20 BPELCD20 BPDLCD20 BPCLCD20 BPBLCD20 BPALCD20
0x0845 LCDWF21 BPHLCD21 BPGLCD21 BPFLCD21 BPELCD21 BPDLCD21 BPCLCD21 BPBLCD21 BPALCD21
0x0846 LCDWF22 BPHLCD22 BPGLCD22 BPFLCD22 BPELCD22 BPDLCD22 BPCLCD22 BPBLCD22 BPALCD22
0x0847 LCDWF23 BPHLCD23 BPGLCD23 BPFLCD23 BPELCD23 BPDLCD23 BPCLCD23 BPBLCD23 BPALCD23
0x0848 LCDWF24 BPHLCD24 BPGLCD24 BPFLCD24 BPELCD24 BPDLCD24 BPCLCD24 BPBLCD24 BPALCD24
0x0849 LCDWF25 BPHLCD25 BPGLCD25 BPFLCD25 BPELCD25 BPDLCD25 BPCLCD25 BPBLCD25 BPALCD25
0x084A LCDWF26 BPHLCD26 BPGLCD26 BPFLCD26 BPELCD26 BPDLCD26 BPCLCD26 BPBLCD26 BPALCD26
0x084B LCDWF27 BPHLCD27 BPGLCD27 BPFLCD27 BPELCD27 BPDLCD27 BPCLCD27 BPBLCD27 BPALCD27
0x084C LCDWF28 BPHLCD28 BPGLCD28 BPFLCD28 BPELCD28 BPDLCD28 BPCLCD28 BPBLCD28 BPALCD28
0x084D LCDWF29 BPHLCD29 BPGLCD29 BPFLCD29 BPELCD29 BPDLCD29 BPCLCD29 BPBLCD29 BPALCD29
0x084E LCDWF30 BPHLCD30 BPGLCD30 BPFLCD30 BPELCD30 BPDLCD30 BPCLCD30 BPBLCD30 BPALCD30
0x084F LCDWF31 BPHLCD31 BPGLCD31 BPFLCD31 BPELCD31 BPDLCD31 BPCLCD31 BPBLCD31 BPALCD31
0x0850 LCDWF32 BPHLCD32 BPGLCD32 BPFLCD32 BPELCD32 BPDLCD32 BPCLCD32 BPBLCD32 BPALCD32
0x0851 LCDWF33 BPHLCD33 BPGLCD33 BPFLCD33 BPELCD33 BPDLCD33 BPCLCD33 BPBLCD33 BPALCD33
0x0852 LCDWF34 BPHLCD34 BPGLCD34 BPFLCD34 BPELCD34 BPDLCD34 BPCLCD34 BPBLCD34 BPALCD34
0x0853 LCDWF35 BPHLCD35 BPGLCD35 BPFLCD35 BPELCD35 BPDLCD35 BPCLCD35 BPBLCD35 BPALCD35
0x0854 LCDWF36 BPHLCD36 BPGLCD36 BPFLCD36 BPELCD36 BPDLCD36 BPCLCD36 BPBLCD36 BPALCD36
0x0855 LCDWF37 BPHLCD37 BPGLCD37 BPFLCD37 BPELCD37 BPDLCD37 BPCLCD37 BPBLCD37 BPALCD37
0x0856 LCDWF38 BPHLCD38 BPGLCD38 BPFLCD38 BPELCD38 BPDLCD38 BPCLCD38 BPBLCD38 BPALCD38
0x0857 LCDWF39 BPHLCD39 BPGLCD39 BPFLCD39 BPELCD39 BPDLCD39 BPCLCD39 BPBLCD39 BPALCD39
0x0858 LCDWF40 BPHLCD40 BPGLCD40 BPFLCD40 BPELCD40 BPDLCD40 BPCLCD40 BPBLCD40 BPALCD40
0x0859 LCDWF41 BPHLCD41 BPGLCD41 BPFLCD41 BPELCD41 BPDLCD41 BPCLCD41 BPBLCD41 BPALCD41
0x085A LCDWF42 BPHLCD42 BPGLCD42 BPFLCD42 BPELCD42 BPDLCD42 BPCLCD42 BPBLCD42 BPALCD42
0x085B LCDWF43 BPHLCD43 BPGLCD43 BPFLCD43 BPELCD43 BPDLCD43 BPCLCD43 BPBLCD43 BPALCD43
0x085C LCDWF44 BPHLCD44 BPGLCD44 BPFLCD44 BPELCD44 BPDLCD44 BPCLCD44 BPBLCD44 BPALCD44
Register
Name
Bit 7 6 5 4 3 2 1 Bit 0
High-page registers, shown in Table 4-4 , are accessed much less often than other I/O and control registers
so they have been located outside the direct addressable memory space, starting at 0x1800.
MC9S08LG32 MCU Series, Rev. 5
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Chapter 4 Memory
Table 4-4. High-Page Register Summary (Sheet 1 of 3)
AddressRegister NameBit 7654321Bit 0
0x1800 SRS POR PIN COP ILOP ILAD 0LVD 0
0x1801 SBDFR
0x1802 SOPT1 COPE COPT STOPE
0x1803 SOPT2 COPCLKS
0x1804 -
Reserved
0x1805
0x1806 SDIDH — — — — ID11 ID10 ID9 ID8
0x1807 SDIDL ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
0x1808 Reserved
0x1809 SPMSC1 LVWF LVWACK LVWIE LVDRE LVDSE LVDE
0x180A SPMSC2
0x180B -
Reserved —
0x180D
0x180E SCGC1 RTC TPM2 TPM1 ADC MTIM IIC SCI2 SCI1
0x180F SCGC2 DBG FLS IRQ KBI
0x1810 DBGCAH Bit 15 14 13 12 11 10 9 Bit 8
0x1811 DBGCAL Bit 7654321Bit 0
0x1812 DBGCBH Bit 15 14 13 12 11 10 9 Bit 8
0x1813 DBGCBL Bit 7654321Bit 0
0x1814 DBGCCH Bit 15 14 13 12 11 10 9 Bit 8
0x1815 DBGCCL Bit 7654321Bit 0
0x1816 DBGFH Bit 15 14 13 12 11 10 9 Bit 8
0x1817 DBGFL Bit 7654321Bit 0
0x1818 DBGCAX RWAEN RWA
0x1819 DBGCBX RWBEN RWB
0x181A DBGCCX RWCEN RWC
0x181B Reserved — — — — — — — —
0x181C DBGC DBGEN ARM TAG BRKEN
0x181D DBGT TRGSEL BEGIN
0x181E DBGS AF BF CF
0x181F DBGCNT
0x1820 FCDIV DIVLD PRDIV8 DIV
0x1821 FOPT KEYEN FNORED
0x1822 Reserved
0x1823 FCNFG
0x1824 FPROT FPS FPDIS
0x1825 FSTAT FCBEF FCCF FPVIOL FACCERR
0x1826 FCMD FCMD
0x1827 -
Reserved
0x182F
0x1830 PINPS1 KBI7 KBI6 KBI5 KBI4 KBI3 KBI2 KBI1 KBI0
0x1831 PINPS2 TPM2[5] TPM2[4] TPM2[3] TPM2[2] TPM2[1] TPM2[0] TPM1[1] TPM1[0]
0x1832 PINPS3 TX2 RX2 SCL SDA MISO MOSI SCK SS
0 0 0 0 0 0 0BDFR
0 0 0 BKGDPE RSTPE
0 0 0 0 0 0 SPIFE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— — — — — — — —
—BGBE
— — LVDV LVWV PPDF PPDACK — PPDC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0 0 LCD SPI
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0LOOP1
0 0TRG
0 0 0 0ARMF
0 0 0 0 CNT
0 0 0 0SEC
— — — — — — — —
0 0 KEYACC 0 0 0 0 0
0 FBLANK 0 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
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Table 4-4. High-Page Register Summary (Sheet 2 of 3)
AddressRegister NameBit 7654321Bit 0
0x1833 PINPS4 000000TX1RX1
0x1834 -
0x183B
0x183C RTCSC RTIF RTCLKS RTIE RTCPS
0x183D RTCCNT RTCCNT
0x183E RTCMOD RTCMOD
0x183F Reserved
0x1840 PTAPE PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0
0x1841 PTASE PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0
0x1842 PTADS PTADS7 PTADS6 PTADS5 PTADS4 PTADS3 PTADS2 PTADS1 PTADS0
0x1843 Reserved
0x1844 PTBPE PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0
0x1845 PTBSE PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0
0x1846 PTBDS PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0
0x1847 Reserved
0x1848 PTCPE — PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0
0x1849 PTCSE
0x184A PTCDS
0x184B Reserved — — — — — — — —
0x184C PTDPE PTDPE7 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDPE2 PTDPE1 PTDPE0
0x184D PTDSE PTDSE7 PTDSE6 PTDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0
0x184E PTDDS PTDDS7 PTDDS6 PTDDS5 PTDDS4 PTDDS3 PTDDS2 PTDDS1 PTDDS0
0x184F Reserved
0x1850 PTEPE PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0
0x1851 PTESE PTESE7 PTESE6 PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0
0x1852 PTEDS PTEDS7 PTEDS6 PTEDS5 PTEDS4 PTEDS3 PTEDS2 PTEDS1 PTEDS0
0x1853 Reserved
0x1854 PTFPE PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0
0x1855 PTFSE PTFSE7 PTFSE6 PTFSE5 PTFSE4 PTFSE3 PTFSE2 PTFSE1 PTFSE0
0x1856 PTFDS PTFDS7 PTFDS6 PTFDS5 PTFDS4 PTFDS3 PTFDS2 PTFDS1 PTFDS0
0x1857 -
0x185F
0x1860 ICSC1 CLKS RDIV IREFS IRCLKEN IREFSTEN
0x1861 ICSC2 BDIV RANGE HGO LP EREFS ERCLKEN EREFSTEN
0x1862 ICSTRM TRIM
0x1863 ICSSC DRST DMX32 IREFST CLKST OSCINIT FTRIM
0x1864 -
0x1867
0x1868 PTGPE PTGPE7 PTGPE6 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0
0x1869 PTGSE PTGSE7 PTGSE6 PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSE0
0x186A PTGDS PTGDS7 PTGDS6 PTGDS5 PTGDS4 PTGDS3 PTGDS2 PTGDS1 PTGDS0
0x186B Reserved
0x186C PTHPE PTHPE7 PTHPE6 PTHPE5 PTHPE4 PTHPE3 PTHPE2 PTHPE1 PTHPE0
Reserved —
—
— — — — — — — —
— — — — — — — —
— — — — — — — —
— PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0
— PTCDS6 PTCDS5 PTCDS4 PTCDS3 PTCDS2 PTCDS1 PTCDS0
— — — — — — — —
— — — — — — — —
Reserved
—
—
Reserved
Reserved
— — — — — — — —
— — — — — — — —
— — — — — — — —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
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Chapter 4 Memory
Table 4-4. High-Page Register Summary (Sheet 3 of 3)
AddressRegister NameBit 7654321Bit 0
0x186D PTHSE PTHSE7 PTHSE6 PTHSE5 PTHSE4 PTHSE3 PTHSE2 PTHSE1 PTHSE0
0x186E PTHDS PTHDS7 PTHDS6 PTHDS5 PTHDS4 PTHDS3 PTHDS2 PTHDS1 PTHDS0
0x186F Reserved
0x1870 MTIMSC TOF TOIE TRST TSTP 0 0 0 0
0x1871 MTIMCLK
0x1872 MTIMCNT COUNT
0x1873 MTIMMOD MOD
0x1874 PTIPE
0x1875 PTISE
0x1876 PTIDS — — PTIDS5 PTIDS4 PTIDS3 PTIDS2 PTIDS1 PTIDS0
0x1877 Reserved
0x1878 KBISC
0x1879 KBIPE KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0
0x187A KBIES KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBEDG3 KBEDG2 KBEDG1 KBEDG0
— — — — — — — —
0 0CLKS PS
— — PTIPE5 PTIPE4 PTIPE3 PTIPE2 PTIPE1 PTIPE0
— — PTISE5 PTISE4 PTISE3 PTISE2 PTISE1 PTISE0
— — — — — — — —
0 0 0 0 KBF KBACK KBIE KBMOD
4.4.1 Reserved Flash Locations
Several reserved flash memory locations, shown in Tab le 4-5, are used for storing values used by several
registers. These registers include an 8-byte backdoor key, NVBACKKEY, which can be used to gain
access to secure memory resources. During reset events, the contents of NVPROT and NVOPT in the
reserved flash memory are transferred into corresponding FPROT and FOPT registers in the high-page
registers area to control security and block protection options.
Locations 0xFFAE and 0xFFAF are reserved for ICS FTRIM and ICS TRIM values respectively. These
locations are left blank at the factory. Third party tools can program these locations with the trim values.
User can copy these values to corresponding ICS registers to get ICS trimmed clock frequency
Table 4-5. Reserved Flash Memory Addresses
AddressRegister NameBit 7654321Bit 0
0xFFB0 –
0xFFB7
0xFFB8 –
0xFFBC
0xFFBD NVPROT
0xFFBE
0xFFBF NVOPT
NVBACKKEY
Reserved
Reserved
8-Byte Comparison Key
—
—
— — — — — — — —
KEYEN FNORED 0 0 0 0 SEC
—
—
—
—
—
—
FPS FPDIS
—
—
—
—
—
—
—
—
Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily
disengage memory security. This key mechanism can be accessed only through user code running in secure
memory. (A security key cannot be entered directly through background debug commands.) This security
key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the
only way to disengage security is by mass erasing the flash if needed (normally through the background
MC9S08LG32 MCU Series, Rev. 5
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Chapter 4 Memory
debug interface) and verifying that flash is blank. To avoid returning to secure mode after the next reset,
program the security bits (SEC) to the unsecured state (1:0).
4.5 RAM
The MC9S08LG32 series includes static RAM. The locations in RAM below 0x0100 can be accessed
using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit
manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed
program variables in this area of RAM is preferred.
At power-on, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that
the supply voltage does not drop below the minimum value for RAM retention (V
For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the
MC9S08LG32 series, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct
page RAM can be used for frequently accessed RAM variables and bit-addressable program variables.
Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated
to the highest address of the RAM in the Freescale Semiconductor-provided equate file).
LDHX #RamLast+1 ;point one past RAM
TXS ;SP<-(H:X-1)
RAM
).
When security is enabled, the RAM is considered a secure memory resource and is not accessible through
background debug mode (BDM) or through code executing from non-secure memory. See Section 4.7,
“Security,” for a detailed description of the security feature.
4.6 Flash
The flash memory is intended primarily for program storage. In-circuit programming allows the operating
program to be loaded into the flash memory after final assembly of the application product. It is possible
to program the entire array through the single-wire background debug interface. Because no special
voltages are needed for flash erase and programming operations, in-application programming is also
possible through other software-controlled communication paths. For a more detailed discussion of
in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I,
Freescale Semiconductor document order number HCS08RMv1/D.
Because the MC9S08LG32 series contains two flash arrays, program and erase operations can be
conducted on one array while executing code from the other. The security and protection features treat the
two arrays as a single memory entity. Programming and erasing of each flash array is conducted through
the same command interface detailed in the following sections.
It is not possible to page erase or program both arrays at the same time. The mass erase command erases
both arrays, and the blank check command checks both arrays.
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4.6.1 Features
Features of the flash memory include:
• Flash size
— MC9S08LG32: 32,768 bytes (16,384 bytes in Flash A, 16,384 bytes in Flash B)
— MC9S08LG16: 18,432 bytes (2,048 bytes in Flash A, 16,384 in Flash B)
• Single power supply program and erase
• Command interface for fast program and erase operation
• Up to 100,000 program/erase cycles at typical voltage and temperature
• Flexible block protection
• Security feature for flash and RAM
• Auto power-down for low-frequency read accesses
4.6.2 Program and Erase Times
Before any program or erase command can be accepted, the flash clock divider register (FCDIV) must be
written to set the internal clock for the flash module to a frequency (f
(see Section 4.8.1, “Flash Clock Divider Register (FCDIV)”). This register can be written only once, so
normally this write is performed during reset initialization. FCDIV cannot be written if the access error
flag, FACCERR in FSTAT, is set. Ensure that FACCERR is not set before writing to the FCDIV register.
The command processor uses one period of the resulting clock (1/f
FCLK
An integer number of these timing pulses is used by the command processor to complete a program or
erase command.
) between 150 kHz and 200 kHz
FCLK
) to time program and erase pulses.
Table 4-6 shows program and erase times. The bus clock frequency and FCDIV determine the frequency
of FCLK (f
of cycles of FCLK and as an absolute time for the case where t
). The time for one cycle of FCLK is t
FCLK
FCLK
=1/f
FCLK
. The times are shown as a number
FCLK
=5μs. Program and erase times
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
Table 4-6. Program and Erase Times
Parameter Cycles of FCLK Time if FCLK = 200 kHz
Byte program 9 45 μs
Byte program (burst) 4 20 μs
Page erase 4000 20 ms
Mass erase 20,000 100 ms
1
Excluding start/end overhead
1
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4.6.3 Program and Erase Command Execution
The FCDIV register must be initialized and any error flag is cleared before beginning command execution.
The command execution steps are:
1. Write a data value to an address in the flash array. The address and data information from this write
is latched into the flash interface. This write is a required first step in any command sequence. For
erase and blank check commands, the value of the data is not important. For page erase commands,
the address may be any address in the 512-byte page of flash to be erased. For mass erase and blank
check commands, the address can be any address in the flash memory. Whole pages of 512 bytes
are the smallest block of flash that may be erased.
NOTE
Do not program any byte in the flash more than once after a successful erase
operation. Reprogramming bits to a byte that is already programmed is not
allowed without first erasing the page in which the byte resides or mass
erasing the entire flash memory. Programming without first erasing may
disturb data stored in the flash.
2. Write the command code for the desired command to FCMD. The five valid commands are blank
check (0x05), byte program (0x20), burst program (0x25), page erase (0x40), and mass erase
(0x41). The command code is latched into the command buffer.
3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its
address and data information).
A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the
write to the memory array and before writing the 1 that clears FCBEF and launches the complete
command. Aborting a command in this way sets the FACCERR access error flag, which must be
cleared before starting a new command.
A strictly monitored procedure must be obeyed or the command will not be accepted. This
minimizes the possibility of any unintended changes to the flash memory contents. The command
complete flag (FCCF) indicates when a command is complete. The command sequence must be
completed by clearing FCBEF to launch the command. Figure 4-2 is a flowchart for executing all
of the commands except for burst programming. The FCDIV register must be initialized before
using any flash commands. This must be done only once following a reset.
4. Wait until the FCCF bit in FSTAT is set. As soon as FCCF= 1, the operation has completed
successfully.
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Chapter 4 Memory
START
WRITE TO FLASH
TO BUFFER ADDRESS AND DATA
WRITE COMMAND TO FCMD
NO
YES
FPVIOL OR
WRITE 1 TO FCBEF
TO LAUNCH COMMAND
AND CLEAR FCBEF
(2)
1
0
FCCF?
ERROR EXIT
DONE
(2)
Wait at least four bus cycles
0
FACCERR?
CLEAR ERROR
FACCERR?
WRITE TO FCDIV
(1)
(1)
Required only once after reset.
1
before checking FCBEF or FCCF.
FLASH PROGRAM AND
ERASE FLOW
Figure 4-2. Flash Program and Erase Flowchart
4.6.4 Burst Program Execution
The burst program command is used to program sequential bytes of data in less time than would be
required using the standard program command. This is possible because the high voltage to the flash array
does not need to be disabled between program operations. Ordinarily, when a program or erase command
is issued, an internal charge pump associated with the flash memory must be enabled to supply high
voltage to the array. Upon completion of the command, the charge pump is turned off. When a burst
program command is issued, the charge pump is enabled and then remains enabled after completion of the
burst program operation if these two conditions are met:
• The next burst program command has been queued before the current program operation has
completed.
• The next sequential address selects a byte on the same physical row as the current byte being
programmed. A row of flash memory consists of 64 bytes. A byte within a row is selected by
addresses A5 through A0. A new row begins when addresses A5 through A0 are all zero.
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Chapter 4 Memory
1
0
FCBEF?
START
WRITE TO FLASH
TO BUFFER ADDRESS AND DATA
WRITE COMMAND (0x25) TO FCMD
NO
YES
FPVIO OR
WRITE 1 TO FCBEF
TO LAUNCH COMMAND
AND CLEAR FCBEF
(2)
NO
YES
NEW BURST COMMAND?
1
0
FCCF?
ERROR EXIT
DONE
(2)
Wait at least four bus cycles before
1
0
FACCERR?
CLEAR ERROR
FACCERR?
(1)
Required only once after reset.
WRITE TO FCDIV
(1)
checking FCBEF or FCCF.
FLASH BURST
PROGRAM FLOW
The first byte of a series of sequential bytes being programmed in burst mode takes the same amount of
time to program as a byte programmed in standard mode. The subsequent bytes program in the burst
program time provided that the conditions above are met. In the case where the next sequential address is
the beginning of a new row, the program time for that byte is the standard time instead of the burst time.
This is because the high voltage to the array must be disabled and then enabled again. If a new burst
command has not been queued before the current command completes, then the charge pump is disabled
and the high voltage removed from the array.
Figure 4-3. Flash Burst Program Flowchart
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Chapter 4 Memory
4.6.5 Access Errors
An access error occurs whenever the command execution protocol is violated.
Any of the following actions causes the access error flag (FACCERR) in FSTAT to be set. Before any
command can be processed, FACERR must be cleared. To clear FACCERR, write a 1 to FACCERR in
FSTAT.
• Writing to a flash address before the internal flash clock frequency has been set by writing to the
FCDIV register
• Writing to a flash address while FCBEF is not set (A new command cannot start until the command
buffer is empty.)
• Writing a second time to a flash address before launching the previous command (There is only
one write to flash for every command.)
• Writing a second time to FCMD before launching the previous command (There is only one write
to FCMD for every command.)
• Writing to any flash control register other than FCMD after writing to a flash address
• Writing any command code to FCMD other than the five allowed codes (0x05, 0x20, 0x25, 0x40,
or 0x41)
• Writing any flash control register other than the write to FSTAT (to clear FCBEF and launch the
command) after writing the command to FCMD
• The MCU enters stop mode while a program or erase command is in progress (The command is
aborted.)
• Writing the byte program, burst program, or page erase command code (0x20, 0x25, or 0x40) with
a background debug command while the MCU is secured (The background debug controller can
only do blank check and mass erase commands when the MCU is secure.)
• Writing 0 to FCBEF to cancel a partial command
4.6.6 Flash Block Protection
The block protection feature prevents the protected region of flash from program or erase changes. Block
protection is controlled through the flash protection register (FPROT). When enabled, block protection
begins at any 512 byte boundary below the last address of flash, 0xFFFF. (See Section 4.8.4, “Flash
Protection Register (FPROT and NVPROT)”).
After exit from reset, FPROT is loaded with the contents of the NVPROT location, which is in the
nonvolatile register block of the flash memory. FPROT cannot be changed directly from application
software to prevent runaway programs from altering the block protection settings. Because NVPROT is
within the last 512 bytes of flash, if any amount of memory is protected, NVPROT is itself protected and
cannot be altered (intentionally or unintentionally) by the application software. FPROT can be written
through background debug commands, which allows a protected flash memory to be erased and
reprogrammed.
The block protection mechanism is illustrated in Figure 4-4. The FPS bits are used as the upper bits of the
last address of unprotected memory. This address is formed by concatenating FPS7:FPS1 with logic 1 bits
as shown. For example, to protect the last 1536 bytes of memory (addresses 0xFA00 through 0xFFFF), the
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FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1
A15 A14 A13 A12 A11 A10 A9 A81A7 A6 A5 A4 A3 A2 A1 A0
11111111
FPS bits must be set to 1111 100, which results in the value 0xF9FF as the last address of unprotected
memory. In addition to programming the FPS bits to the appropriate value, FPDIS (bit 0 of NVPROT)
must be programmed to logic 0 to enable block protection. Therefore the value 0xF8 must be programmed
into NVPROT to protect addresses 0xFA00 through 0xFFFF.
Figure 4-4. Block Protection Mechanism
One use of block protection is to block protect an area of flash memory for a bootloader program. This
bootloader program then can be used to erase the rest of the flash memory and reprogram it. Because the
bootloader is protected, it remains intact even if MCU power is lost in the middle of an erase and
reprogram operation.
4.6.7 Vector Redirection
Whenever any block protection is enabled, the reset and interrupt vectors are protected. Vector redirection
allows users to modify interrupt vector information without unprotecting bootloader and reset vector
space. Vector redirection is enabled by programming the FNORED bit in the NVOPT register located at
address 0xFFBF to zero. For redirection to occur, at least some portion but not all of the flash memory
must be block protected by programming the NVPROT register located at address 0xFFBD. All of the
interrupt vectors (memory locations 0xFFC0–0xFFFD) are redirected, though the reset vector
(0xFFFE:FFFF) is not.
For example, if 512 bytes of flash are protected, the protected address region is from 0xFE00 through
0xFFFF. The interrupt vectors (0xFFC0–0xFFFD) are redirected to the locations 0xFDC0–0xFDFD. For
instance, if an SPI interrupt is taken, the values in the locations 0xFDE8:FDE9 are used for the vector
instead of the values in the locations 0xFFE8:FFE9. This allows you to reprogram the unprotected portion
of the flash with new program code including new interrupt vector values while leaving the protected area,
which includes the default vector locations, unchanged.
4.7 Security
The MC9S08LG32 series includes circuitry to prevent unauthorized access to the contents of flash and
RAM memory. When security is engaged, flash and RAM are considered secure resources. Direct-page
registers, high-page registers, and the background debug controller are considered unsecured resources.
Programs executing within secure memory have normal access to any MCU memory locations and
resources. Attempts to access a secure memory location with a program executing from an unsecured
memory space or through the background debug interface are blocked (writes are ignored and reads return
all 0s).
Security is engaged or disengaged based on the state of two nonvolatile register bits (SEC01:SEC00) in
the FOPT register. During reset, the contents of the nonvolatile location NVOPT are copied from flash into
the working FOPT register in high-page register space. To engage security, program the NVOPT location.
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You can do this at the same time the flash memory is programmed. The 1:0 state disengages security and
the other three combinations engage security. Notice the erased state (1:1) makes the MCU secure. During
development, whenever the flash is erased, you must immediately program the SEC00 bit to 0 in NVOPT
so SEC01:SEC00 = 1:0. This allows the MCU to remain unsecured after a subsequent reset.
The on-chip debug module cannot be enabled while the MCU is secure. The separate background debug
controller can still be used for background memory access commands of unsecured resources.
You can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor security
key. If the nonvolatile KEYEN bit in NVOPT/FOPT is 0, the backdoor key is disabled and there is no way
to disengage security without completely erasing all flash locations. If KEYEN is 1, a secure user program
can temporarily disengage security by:
1. Writing 1 to KEYACC in the FCNFG register. This makes the flash module interpret writes to the
backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to be
compared against the key rather than as the first step in a flash program or erase command.
2. Writing the user-entered key values to the NVBACKKEY through NVBACKKEY+7 locations.
These writes must be done in order starting with the value for NVBACKKEY and ending with
NVBACKKEY+7. STHX must not be used for these writes because these writes cannot be done
on adjacent bus cycles. User software normally would get the key codes from outside the MCU
system through a communication interface such as a serial I/O.
3. Writing 0 to KEYACC in the FCNFG register. If the 8-byte key that was just written matches the
key stored in the flash locations, SEC01:SEC00 are automatically changed to 1:0 and security
disengages until the next reset.
The security key can be written only from secure memory (either RAM or flash), so it cannot be entered
through background commands without the cooperation of a secure user program.
The backdoor comparison key (NVBACKKEY through NVBACKKEY+7) is located in flash memory
locations in the nonvolatile register space so users can program these locations exactly as they would
program any other flash memory location. The nonvolatile registers are in the same 512-byte block of flash
as the reset and interrupt vectors, so block protecting that space also block protects the backdoor
comparison key. Block protects cannot be changed from user application programs, so if the vector space
is block protected, the backdoor security key mechanism cannot permanently change the block protect,
security settings, or the backdoor key.
Security can always be disengaged through the background debug interface by taking these steps:
1. Disable any block protections by writing FPROT. FPROT can be written only with background
debug commands, not from application software.
2. Mass erase flash if necessary.
3. Blank check flash. Provided flash is completely erased, security is disengaged until the next reset.
To avoid returning to secure mode after the next reset, program NVOPT so SEC01:SEC00 = 1:0.
4.8 Flash Registers and Control Bits
The flash module has six 8-bit registers in the high-page register space. Two locations (NVOPT,
NVPROT) in the nonvolatile register space in flash memory are copied into corresponding high-page
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Chapter 4 Memory
control registers (FOPT, FPROT) at reset. There is also an 8-byte comparison key in flash memory. Refer
to Table 4-4 and Ta ble 4-5 for the absolute address assignments for all flash registers. This section refers
to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header
file is normally used to translate these names into the appropriate absolute addresses.
4.8.1 Flash Clock Divider Register (FCDIV)
Bit 7 of this register is a read-only flag. DIV Bits 6:0 may be read at any time, but can be written only one
time. Before any erase or programming operations are possible, write to this register to set the frequency
of the clock for the nonvolatile memory system within acceptable limits.Table 4-8 shows the appropriate
values for PRDIV8 and DIV for selected bus frequencies.
76543210
RDIVLD
W
Reset00000000
PRDIV8 DIV
= Unimplemented or Reserved
Figure 4-5. Flash Clock Divider Register (FCDIV)
Table 4-7. FCDIV Register Field Descriptions
Field Description
7
DIVLD
6
PRDIV8
5:0
DIV
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for flash.
1 FCDIV has been written since reset; erase and program operations enabled for flash.
Prescale (Divide) Flash Clock by 8
0 Clock input to the flash clock divider is the bus rate clock.
1 Clock input to the flash clock divider is the bus rate clock divided by 8.
Divisor for Flash Clock Divider — The flash clock divider divides the bus rate clock (or the bus rate clock
divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV field plus one. The resulting frequency of the internal
flash clock must fall within the range of 200 kHz to 150 kHz for proper flash operations. Program/Erase timing
pulses are one cycle of this internal flash clock which corresponds to a range of 5 μs to 6.7 μs. The automated
programming logic uses an integer number of these pulses to complete an erase or program operation. See
Equation 4-1 and Equation 4-2.
if PRDIV8 = 0 — f
if PRDIV8 = 1 — f
FCLK
FCLK
= f
= f
÷ (DIV + 1) Eqn. 4-1
Bus
÷ (8 × (DIV + 1)) Eqn. 4-2
Bus
Table 4-8 shows the appropriate values for PRDIV8 and DIV for selected bus frequencies.
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Table 4-8. Flash Clock Divider Settings
Chapter 4 Memory
f
Bus
20 MHz 1 12 192.3 kHz 5.2 μs
10 MHz 0 49 200 kHz 5 μs
8 MHz 0 39 200 kHz 5 μs
4 MHz 0 19 200 kHz 5 μs
2 MHz 0 9 200 kHz 5 μs
1 MHz 0 4 200 kHz 5 μs
200 kHz 0 0 200 kHz 5 μs
150 kHz 0 0 150 kHz 6.7 μs
PRDIV8
(Binary)
DIV
(Decimal)
f
FCLK
Program/Erase Timing Pulse
(5 μs Min, 6.7 μs Max)
4.8.2 Flash Options Register (FOPT and NVOPT)
During reset, the contents of the nonvolatile location NVOPT are copied from flash into FOPT. To change
the value in this register, erase and reprogram the NVOPT location in flash memory as usual and then issue
a new MCU reset.
76543210
R KEYEN FNORED 0 0 0 0 SEC01 SEC00
W
Reset This register is loaded from nonvolatile location NVOPT during reset.
= Unimplemented or Reserved
Figure 4-6. Flash Options Register (FOPT)
Table 4-9. FOPT Register Field Descriptions
Field Description
7
KEYEN
6
FNORED
1:0
SEC0[1:0]
Backdoor Key Mechanism Enable — When this bit is 0, the backdoor key mechanism cannot be used to
disengage security. The backdoor key mechanism is accessible only from the user (secured) firmware. BDM
commands cannot be used to write key comparison values that would unlock the backdoor key. For more detailed
information about the backdoor key mechanism, refer to Section 4.7, “Security.”
0 No backdoor key access allowed.
1 If user firmware writes an 8-byte value that matches the nonvolatile backdoor key (NVBACKKEY through
NVBACKKEY+7 in that order), security is temporarily disengaged until the next MCU reset.
Vector Redirection Disable — When this bit is 1, then vector redirection is disabled.
0 Vector redirection enabled.
1 Vector redirection disabled.
Security State Code — This 2-bit field determines the security state of the MCU as shown in Ta b le 4 - 10 . When
the MCU is secure, the contents of RAM and flash memory cannot be accessed by instructions from any
unsecured source including the background debug interface. SEC01:SEC00 changes to 1:0 after successful
backdoor key entry or a successful blank check of flash.
For more detailed information about security, refer to Section 4.7, “Security.”
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Table 4-10. Security States
SEC01:SEC00 Description
0:0 secure
0:1 secure
1:0 unsecured
1:1 secure
1
SEC01:SEC00 changes to 1:0 after successful backdoor
key entry or a successful blank check of flash.
1
4.8.3 Flash Configuration Register (FCNFG)
76543210
R0 0
KEYACC
W
Reset00000000
= Unimplemented or Reserved
Figure 4-7. Flash Configuration Register (FCNFG)
00000
Table 4-11. FCNFG Register Field Descriptions
Field Description
5
KEYACC
Enable Writing of Access Key — This bit enables writing of the backdoor comparison key. For more detailed
information about the backdoor key mechanism, refer to Section 4.7, “Security.”
0 Writes to flash are interpreted as the start of a flash programming or erase command.
1 Writes to NVBACKKEY (0xFFB0–0xFFB7) are interpreted as comparison key writes while writes to rest of the
flash are ignored.
4.8.4 Flash Protection Register (FPROT and NVPROT)
During reset, the contents of the nonvolatile location NVPROT is copied from flash into FPROT. FPROT
can be read at any time. With FPDIS set, all bits are writable, but with FPDIS clear the FPS bits are writable
as long as the size of the protected region is being increased. Any FPROT write that attempts to decrease
the size of the protected region is ignored.
76543210
R
W
Reset This register is loaded from nonvolatile location NVPROT during reset.
1
Background commands can be used to change the contents of these bits in FPROT.
FPS
(1)
FPDIS
(1)
Figure 4-8. Flash Protection Register (FPROT)
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Table 4-12. FPROT Register Field Descriptions
Field Description
Chapter 4 Memory
7:1
FPS
0
FPDIS
Flash Protect Select Bits — When FPDIS = 0, this 7-bit field determines the ending address of unprotected
flash locations at the high address end of the flash. Protected flash locations cannot be erased or programmed.
Flash Protection Disable
0 Flash block specified by FPS7:FPS1 is block protected (program and erase not allowed).
1 No flash block is protected.
4.8.5 Flash Status Register (FSTAT)
76543210
R
FCBEF
W
Reset11000000
Field Description
7
FCBEF
Flash Command Buffer Empty Flag — The FCBEF bit is used to launch commands. It also indicates that the
command buffer is empty so that a new command sequence can be executed when performing burst
programming. The FCBEF bit is cleared by writing a 1 to it or when a burst program command is transferred to
the array for programming. Only burst program commands can be buffered.
0 Command buffer is full (not ready for additional commands).
1 A new burst program command can be written to the command buffer.
FCCF
FPVIOL FACCERR
= Unimplemented or Reserved
Figure 4-9. Flash Status Register (FSTAT)
Table 4-13. FSTAT Register Field Descriptions
0FBLANK0 0
6
FCCF
5
FPVIOL
Freescale Semiconductor 71
Flash Command Complete Flag — FCCF is set automatically when the command buffer is empty and no
command is being processed. FCCF is cleared automatically when a new command is started (by writing 1 to
FCBEF to register a command). Writing to FCCF has no meaning or effect.
0 Command in progress
1 All commands complete
Protection Violation Flag — FPVIOL is set automatically when a command is written that attempts to erase or
program a location in a protected block (the erroneous command is ignored). FPVIOL is cleared by writing a 1 to
FPVIOL.
0 No protection violation.
1 An attempt was made to erase or program a protected location.
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Table 4-13. FSTAT Register Field Descriptions (continued)
Field Description
4
FACCERR
2
FBLANK
Access Error Flag — FACCERR is set automatically when the proper command sequence is not obeyed exactly
(the erroneous command is ignored), if a program or erase operation is attempted before the FCDIV register has
been initialized, or if the MCU enters stop while a command was in progress. For a more detailed discussion of
the exact actions that are considered access errors, see Section 4.6.5, “Access Errors.” FACCERR is cleared by
writing a 1 to FACCERR. Writing a 0 to FACCERR has no meaning or effect.
0 No access error.
1 An access error has occurred.
Flash Verified as All Blank (erased) Flag — FBLANK is set automatically at the conclusion of a blank check
command if the entire flash array was verified to be erased. FBLANK is cleared by clearing FCBEF to write a new
valid command. Writing to FBLANK has no meaning or effect.
0 After a blank check command is completed and FCCF = 1, FBLANK = 0 indicates the flash array is not
completely erased.
1 After a blank check command is completed and FCCF = 1, FBLANK = 1 indicates the flash array is completely
erased (all 0xFF).
4.8.6 Flash Command Register (FCMD)
Only five command codes are recognized in normal user modes as shown in Table 4-14. Refer to Section
4.6.3, “Program and Erase Command Execution,” for a detailed discussion of flash programming and erase
operations.
76543210
R00000000
WFCMD
Reset00000000
Figure 4-10. Flash Command Register (FCMD)
Table 4-14. Flash Commands
Command FCMD Equate File Label
Blank check 0x05 mBlank
Byte program 0x20 mByteProg
Byte program — burst mode 0x25 mBurstProg
Page erase (512 bytes/page) 0x40 mPageErase
Mass erase (all flash) 0x41 mMassErase
All other command codes are illegal and generate an access error.
It is not necessary to perform a blank check command after a mass erase operation. Only blank check is
required as part of the security unlocking mechanism.
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5.1 Introduction
This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupt
in the MC9S08LG32 series. Some interrupt sources from peripheral modules are discussed in greater
detail in other sections of this document. This section gathers basic information about all reset and interrupt
sources in one place for easy reference.
5.2 Features
Reset and interrupt features include:
• Multiple sources of reset for flexible system configuration and reliable operation
• Reset status register (SRS) to indicate source of most recent reset
• Separate interrupt vector for all modules (reduces polling overhead) (see Table 5-2)
5.3 MCU Reset
Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset,
most control and status registers are forced to initial values and the program counter is loaded from the
reset vector (0xFFFE:0xFFFF). On-chip peripheral modules are disabled and I/O pins are initially
configured as general-purpose high-impedance inputs with pullup devices disabled. The I bit in the
condition code register (CCR) is set to block maskable interrupts so the user program has a chance to
initialize the stack pointer (SP) and system control settings. SP is forced to 0x00FF at reset.
The MC9S08LG32 series has the following sources for reset:
• Power-on reset (POR)
• External pin reset (PIN)
• Computer operating properly (COP) timer
• Illegal opcode detect (ILOP)
• Illegal address detect (ILAD)
• Low-voltage detect (LVD)
• Background debug forced reset
Each of these sources, with the exception of the background debug forced reset, has an associated bit in
the system reset status register (SRS). The background debug forced reset causes all the bits in the SRS
register to clear, and can be detected by all zeros in SRS.
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5.4 Computer Operating Properly (COP) Watchdog
The COP watchdog is intended to force a system reset when the application software fails to execute as
expected. To prevent a system reset from the COP timer (when it is enabled), application software must
reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter
before it times out, a system reset is generated to force the system back to a known starting point.
After any reset, the COPE becomes set in SOPT1 enabling the COP watchdog (see Section 5.8.4, “System
Options Register 1 (SOPT1),” for additional information). If the COP watchdog is not used in an
application, it can be disabled by clearing COPE. The COP counter is reset by writing any value to the
address of SRS. This write does not affect the data in the read-only SRS. Instead, the act of writing to this
address is decoded and sends a reset signal to the COP counter.
The COPCLKS bit in SOPT2 (see Section 5.8.5, “System Options Register 2 (SOPT2),” for additional
information) selects the clock source used for the COP timer. The clock source options are either the bus
clock or an internal 1 kHz clock source. With each clock source, there is an associated short and long
time-out controlled by COPT in SOPT1. Ta ble 5-1 summaries the control functions of the COPCLKS and
COPT bits. The COP watchdog defaults to operation from the 1 kHz clock source and the associated long
time-out (28 cycles).
Table 5-1. COP Configuration Options
Control Bits
Clock Source COP Overflow Count
COPCLKS COPT
00~1 kHz2
01~1 kHz2
10Bus 2
11Bus 2
1
Values are shown in this column based on t
tolerance of this value.
=1ms. See t
LPO
5
cycles (32 ms)
8
cycles (256 ms)
13
cycles
18
cycles
in the data sheet for the
LPO
1
1
Even if your application uses the reset default settings of COPE, COPCLKS, and COPT; you must write
to the write-once SOPT1 and SOPT2 registers, during reset initialization, to lock in the settings. That way,
the settings cannot be changed accidentally if the application program gets lost. The initial writes to SOPT1
and SOPT2 reset the COP counter.
The write to SRS that services (clears) the COP counter must not be placed in an interrupt service routine
(ISR) because the ISR could continue to be executed periodically even if the main application program
fails.
In background debug mode, the COP counter does not increment.
When the bus clock source is selected, the COP counter does not increment while the system is in stop
mode. The COP counter resumes as soon as the MCU exits stop mode.
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When the 1 kHz clock source is selected, the COP counter is re-initialized to zero upon entry to stop mode.
The COP counter begins from zero after the MCU exits stop mode.
5.5 Interrupts
Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine
(ISR), and then restore the CPU status so processing can resume where it left off before the interrupt. Other
than the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events
such as an edge on the IRQ pin or a timer-overflow event. The debug module can also generate an SWI
under certain circumstances.
If an event occurs in an enabled interrupt source, an associated read-only status flag is set. The CPU does
not respond unless the local interrupt enable is a 1 (enabled) and the I bit in the CCR is 0 to allow interrupts.
The global interrupt mask (I bit) in the CCR is initially set after reset which prevents all maskable interrupt
sources. The user program initializes the stack pointer and performs other system setup before clearing the
I bit to allow the CPU to respond to interrupts.
When the CPU receives a qualified interrupt request, it completes the current instruction before responding
to the interrupt. The interrupt sequence obeys the same cycle-by-cycle sequence as the SWI instruction
and consists of:
• Saving the CPU registers on the stack
• Setting the I bit in the CCR to mask further interrupts
• Fetching the interrupt vector for the highest-priority interrupt that is currently pending
• Filling the instruction queue with the first three bytes of program information starting from the
address fetched from the interrupt vector locations
While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of
another interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is
restored to 0 when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit
can be cleared inside an ISR (after clearing the status flag that generated the interrupt) so that other
interrupts can be serviced without waiting for the first service routine to finish. This practice is not
recommended for anyone other than the most experienced programmers because it can lead to subtle
program errors that are difficult to debug.
The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR,
A, X, and PC registers to their pre-interrupt values by reading the previously saved information from the
stack.
NOTE
For compatibility with M68HC08 devices, the H register is not
automatically saved and restored. It is good programming practice to push
H onto the stack at the start of the interrupt service routine (ISR) and restore
it immediately before the RTI that is used to return from the ISR.
If more than one interrupt is pending when the I bit is cleared, the highest priority source is serviced first
(see Table 5-2).
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CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER (LOW BYTE X)
PROGRAM COUNTER HIGH
* High byte (H) of index register is not automatically stacked.
*
PROGRAM COUNTER LOW
²
²
²
²
70
UNSTACKING
ORDER
STACKING
ORDER
5
4
3
2
1
1
2
3
4
5
TOWARD LOWER ADDRESSES
TOWARD HIGHER ADDRESSES
SP BEFORE
SP AFTER
INTERRUPT STACKING
THE INTERRUPT
5.5.1 Interrupt Stack Frame
Figure 5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer
(SP) points at the next available byte location on the stack. The current values of CPU registers are stored
on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR. After
stacking, the SP points at the next available location on the stack. This address is one less than the address
where the CCR was saved. The PC value that is stacked is the address of the instruction in the main
program that would have executed next if the interrupt had not occurred.
Figure 5-1. Interrupt Stack Frame
When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part
of the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information,
starting from the PC address recovered from the stack.
The status flag corresponding to the interrupt source must be acknowledged (cleared) before returning
from the ISR. Typically, the flag is cleared at the beginning of the ISR so that if another interrupt is
generated by this same source it is registered so it can be serviced after completion of the current ISR.
5.5.2 External Interrupt Request (IRQ) Pin
External interrupts are managed by the IRQ status and control register (IRQSC). When the IRQ function
is enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is
in stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ pin can
wake the MCU.
5.5.2.1 Pin Configuration Options
The IRQ pin enable (IRQPE) control bit in IRQSC must be 1 in order for the IRQ pin to act as the interrupt
request (IRQ) input. As an IRQ input, you can choose the polarity of edges or levels detected (IRQEDG),
whether the pin detects edges-only or edges and levels (IRQMOD) and whether an event causes an
interrupt or only sets the IRQF flag which can be polled by software (IRQIE).
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The IRQ pin, when enabled, defaults to use an internal pull device (IRQPDD = 0), configured as a pullup
or pulldown depending on the polarity chosen. If the user desires to use an external pullup or pulldown,
the IRQPDD can be written to a 1 to turn off the internal device.
BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is configured to act
as the IRQ input.
5.5.2.2 Edge and Level Sensitivity
The IRQMOD control bit reconfigures the detection logic so it detects edge events and pin levels. In the
edge and level detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ
pin changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be
cleared) as long as the IRQ pin remains at the asserted level.
5.5.2.3 IRQ Initialization
When IRQ is first enabled it is possible to get a false IRQ interrupt flag. To prevent a false interrupt request
during IRQ initialization, you must do the following:
1. Mask IRQ interrupt by clearing IRQIE in IRQSC.
2. Select the IRQ mode by writing to the IRQEDG, IRQMOD and IRQPDD bits in IRQSC.
3. Enable the IRQ pin by setting the IRQPE bit in IRQSC.
4. Write to IRQACK in IRQSC to clear any false interrupts.
5. Set IRQIE in IRQSC to enable interrupts.
5.5.3 Interrupt Vectors, Sources, and Local Masks
Table 5-2 provides a summary of all interrupt sources. Higher-priority sources are located toward the
bottom of the table. The high-order byte of the address for the interrupt service routine is located at the
first address in the vector address column, and the low-order byte of the address for the interrupt service
routine is located at the next higher address.
When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt
enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in
the CCR) is 0, the CPU finishes the current instruction; stack the PCL, PCH, X, A, and CCR CPU registers;
set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt. Processing then
continues in the interrupt service routine.
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Table 5-2. Vector Summary
Vector
Priority
Lowest
Highest
Vector
Number
31
through
27
Address
(High/Low)
0xFFC0:FFC1
through
0xFFC8:FFC9
Vector
Name
Module Source Enable Description
Unused Vector Space
(available for user program)
26 0xFFCA:0xFFCB Vrtc RTC RTIF RTIE Counter Match
25 0xFFCC:0xFFCD Vmtim MTIM TOF TOIE Counter Match
24 0xFFCE:0xFFCF Vtpm2ovf TPM2 TOF TO2E TPM2 overflow
23 0xFFD0/0xFFD1 Vtpm2ch5 TPM2 CH5F CH5IE TPM2 channel 5
22 0xFFD2/0xFFD3 Vtpm2ch4 TPM2 CH4F CH4IE TPM2 channel 4
21 0xFFD4/0xFFD5 Vtpm2ch3 TPM2 CH3F CH3IE TPM2 channel 3
20 0xFFD6/0xFFD7 Vtpm2ch2 TPM2 CH2F CH2IE TPM2 channel 2
19 0xFFD8/0xFFD9 Vtpm2ch1 TPM2 CH1F CH1IE TPM2 channel 1
18 0xFFDA/0xFFDB Vtpm2ch0 TPM2 CH0F CH0IE TPM2 channel 0
17 0xFFDC/0xFFDD Vadc ADC COCO AIEN ADC
16 0xFFDE/0xFFDF Vkeyboard KBI KBF KBIE Keyboard pins
15 0xFFE0/0xFFE1 Viic IIC IICIS IICIE IIC control
14 0xFFE2/0xFFE3 Vsci2tx SCI2 TDRE, TC TIE, TCIE SCI transmit
13 0xFFE4/0xFFE5 Vsci2rx SCI2 IDLE, RDRF,
LBKDIF,
RXEDGIF
12 0xFFE6/0xFFE7 Vsci2err SCI2 OR, NF,
FE, PF
11 0xFFE8/0xFFE9 Vspi SPI SPIF, MODF,
ILIE, RIE,
SCI receive
LBKDIE,
RXEDGIE
ORIE, NFIE,
SCI error
FEIE, PFIE
SPIE, SPIE, SPTIE SPI
SPTEF
10 0xFFEA/0xFFEB Vlcd LCD LCDF LCDIE LCD Frame Interrupt
9 0xFFEC/0xFFED Vsci1tx SCI1 TDRE, TC TIE, TCIE SCI transmit
8 0xFFEE/0xFFEF Vsci1rx SCI1 IDLE, RDRF,
LBKDIF,
RXEDGIF
7 0xFFF0/0xFFF1 Vsci1err SCI1 OR, NF,
FE, PF
ILIE, RIE,
LBKDIE,
RXEDGIE
ORIE, NFIE,
FEIE, PFIE
SCI receive
SCI error
6 0xFFF2/0xFFF3 Vtpm1ovf TPM1 TOF TOIE TPM1 overflow
5 0xFFF4/0xFFF5 Vtpm1ch1 TPM1 CH1F CH1IE TPM1 channel 1
4 0xFFF6/0xFFF7 Vtpm1ch0 TPM1 CH0F CH0IE TPM1 channel 0
3 0xFFF8/0xFFF9 Vlvw System
LVW F LV W IE Lo w- v o l t ag e wa r ni ng
control
2 0xFFFA/0xFFFB Virq IRQ IRQF IRQIE IRQ pin
1 0xFFFC/0xFFFD Vswi Core SWI Instruction — Software interrupt
0 0xFFFE/0xFFFF Vreset System
control
COP
LV D
RESET
pin
Illegal opcode
Illegal address
COPE
LV DR E
RSTPE
—
—
Watchdog timer
Low-voltage detect
External pin
Illegal opcode
Illegal address
POR
MC9S08LG32 MCU Series, Rev. 5
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Chapter 5 Resets, Interrupts, and General System Control
5.6 Low-Voltage Detect (LVD) System
The MC9S08LG32 series includes a system to protect against low voltage conditions to protect memory
contents and control MCU system states during supply voltage variations. The system is comprised of a
power-on reset (POR) circuit and a LVD circuit. The LVD circuit is enabled when LVDE in SPMSC1. The
LVD is disabled upon entering either of the stop modes unless LVDSE is set in SPMSC1. If LVDSE and
LVDE are both set, then the MCU enters stop3 instead of stop2, and the current consumption in stop3 with
the LVD enabled is greater.
5.6.1 Power-On Reset Operation
When power is initially applied to the MCU, or when the supply voltage drops below the power-on reset
rearm voltage level, V
circuit holds the MCU in reset until the supply has risen above the low voltage detection low threshold,
V
. Both the POR bit and the LVD bit in SRS are set following a POR.
LV DL
5.6.2 Low-Voltage Detection (LVD) Reset Operation
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE to 1. After an LVD reset has occurred, the LVD system holds the MCU in reset until the supply
voltage has risen above the low voltage detection threshold. The LVD bit in the SRS register is set
following either an LVD reset or POR.
, the POR circuit causes a reset condition. As the supply voltage rises, the LVD
POR
5.6.3 Low-Voltage Warning (LVW) Interrupt Operation
The LVD system has a low voltage warning flag (LVWF) to indicate to you that the supply voltage is
approaching, but remains above, the LVD voltage. The LVW has an interrupt associated with it, enabled
by setting the LVWIE bit in the SPMSC1 register. If enabled, an LVW interrupt request occurs when the
LVWF is set. LVWF is cleared by writing a 1 to the LVWACK bit in SPMSC1 provided the LVW condition
no longer exists.
5.7 Peripheral Clock Gating
The MC9S08LG32 series includes a clock gating system to manage the bus clock sources to the individual
peripherals. Using this system, you can enable or disable the bus clock to each of the peripherals at the
clock source, eliminating unnecessary clocks to peripherals which are not in use and thereby reducing the
overall run and wait mode currents.
Out of reset, all peripheral clocks are disabled. For lowest possible run or wait currents, user software must
disable the clock source to any peripheral not in use. The actual clock is enabled or disabled immediately
following the write to the Clock Gating Control registers (SCGC1 and SCGC2). Any peripheral with a
gated clock cannot be used unless its clock is enabled. Writing to the registers of a peripheral with a
disabled clock has no effect.
MC9S08LG32 MCU Series, Rev. 5
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Chapter 5 Resets, Interrupts, and General System Control
NOTE
User software must disable the peripheral before disabling the clocks to the
peripheral. When clocks are re-enabled to a peripheral, the peripheral
registers need to be re-initialized by user software.
In stop modes, the bus clock is disabled for all gated peripherals, regardless of the settings in SCGC1 and
SCGC2.
5.8 Reset, Interrupt, and System Control Registers and Control Bits
One 8-bit register in the direct page register space and fourteen 8-bit registers in the high-page register
space are related to reset and interrupt systems.
Refer to Table 4-2 and Table 4-4 in Chapter 4, “Memory,” for the absolute address assignments for all
registers. This section refers to registers and control bits only by their names. A Freescale-provided equate
or header file is used to translate these names into the appropriate absolute addresses.
Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief
descriptions of these bits are provided here, the related functions are discussed in greater detail in
Chapter 3, “Modes of Operation.”
5.8.1 Interrupt Pin Request Status and Control Register (IRQSC)
This direct page register includes status and control bits which are used to configure the IRQ function,
report status, and acknowledge IRQ events.
76543210
R0
W IRQACK
Reset00000000
Field Description
6
IRQPDD
5
IRQEDG
Interrupt Request (IRQ) Pull Device Disable — This read/write control bit is used to disable the internal
pullup/pulldown device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used.
0 IRQ pull device enabled if IRQPE = 1.
1 IRQ pull device disabled if IRQPE = 1.
Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or
levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is
sensitive to both edges and levels or only edges. When IRQEDG = 1 and the internal pull device is enabled, the
pullup device is reconfigured as an optional pulldown device.
0 IRQ is falling edge or falling edge/low-level sensitive.
1 IRQ is rising edge or rising edge/high-level sensitive.
IRQPDD IRQEDG IRQPE
= Unimplemented or Reserved
Figure 5-2. Interrupt Request Status and Control Register (IRQSC)
Table 5-3. IRQSC Register Field Descriptions
IRQF 0
IRQIE IRQMOD
MC9S08LG32 MCU Series, Rev. 5
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Chapter 5 Resets, Interrupts, and General System Control
Table 5-3. IRQSC Register Field Descriptions (continued)
Field Description
4
IRQPE
3
IRQF
2
IRQACK
1
IRQIE
0
IRQMOD
IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set the IRQ pin can
be used as an interrupt request.
0 IRQ pin function is disabled.
1 IRQ pin function is enabled.
IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred.
0 No IRQ request.
1 IRQ event detected.
IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).
Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1),
IRQF cannot be cleared while the IRQ pin remains at its asserted level.
IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate an interrupt
request.
0 Interrupt request when IRQF set is disabled (use polling).
1 Interrupt requested whenever IRQF = 1.
IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level
detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt
request events. See Section 5.5.2.2, “Edge and Level Sensitivity,” for more details.
0 IRQ event on falling edges or rising edges only.
1 IRQ event on falling edges and low levels or on rising edges and high levels.
MC9S08LG32 MCU Series, Rev. 5
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Chapter 5 Resets, Interrupts, and General System Control
5.8.2 System Reset Status Register (SRS)
This high-page register includes read-only status flags to indicate the source of the most recent reset. When
a debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS is
set. Writing any value to this register address clears the COP watchdog timer without affecting the contents
of this register. The reset state of these bits depends on what caused the MCU to reset.
76543210
R POR PIN COP ILOP ILAD 0 LVD 0
W Writing any value to SRS address clears COP watchdog timer.
POR:
LV D:
Any other
reset:
1
u = unaffected
2
Any of these reset sources that are active at the time of reset entry causes the corresponding bit(s) to be set; bits corresponding
to sources that are not active at the time of reset entry are cleared.
10000010
(1)
u
0Note
0000010
(2)
Note
(2)
Note
(2)
Note
(2)
000
Figure 5-3. System Reset Status (SRS)
Table 5-4. SRS Register Field Descriptions
Field Description
7
POR
6
PIN
5
COP
Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVD threshold.
0 Reset not caused by POR.
1 POR caused reset.
External Reset Pin — Reset was caused by an active-low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source can be blocked by COPE = 0.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
4
ILOP
82 Freescale Semiconductor
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
MC9S08LG32 MCU Series, Rev. 5
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Chapter 5 Resets, Interrupts, and General System Control
Table 5-4. SRS Register Field Descriptions (continued)
Field Description
3
ILAD
1
LV D
Illegal Address — Reset was caused by an attempt to access either data or an instruction at an unimplemented
memory address.
0 Reset not caused by an illegal address
1 Reset caused by an illegal address
Low Voltage Detect — If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset
occurs. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
5.8.3 System Background Debug Force Reset Register (SBDFR)
This high-page register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
76543210
R00000000
W BDFR
Reset:00000000
= Unimplemented or Reserved
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
1
BDFR is writable only through serial background debug commands, not from user programs.
1
Table 5-5. SBDFR Register Field Descriptions
Field Description
0
BDFR
Background Debug Force Reset — A serial background command such as WRITE_BYTE can be used to allow
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program.To enter user mode, PTC5/BKGD/MS must be high immediately after issuing
WRITE_BYTE command. To enter BDM, PTC5/BKGD/MS must be low immediately after issuing WRITE_BYTE
command. See the data sheet for more information.
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Chapter 5 Resets, Interrupts, and General System Control
5.8.4 System Options Register 1 (SOPT1)
This high-page register is a write-once register, so only the first write after reset is honored. It can be read
at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to
avoid accidental changes to these sensitive settings. SOPT1 must be written during the user’s reset
initialization program to set the desired controls even if the desired settings are the same as the reset
settings.
76543210
R
COPE COPT STOPE
W
Reset:1100001u
000
BKGDPE RSTPE
(1)
POR and
LV R:
11000011
= Unimplemented or Reserved
Figure 5-5. System Options Register 1 (SOPT1)
1
u = unaffected
Table 5-6. SOPT1 Register Field Descriptions
Field Description
7
COPE
6
COPT
5
STOPE
1
BKGDPE
COP Watchdog Enable — This write-once bit selects whether the COP watchdog is enabled.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
COP Watchdog Timeout — This write-once bit selects the timeout period of the COP. COPT along with
COPCLKS in SOPT2 defines the COP timeout period.
0 Short timeout period selected.
1 Long timeout period selected.
Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user
program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
Background Debug Mode Pin Enable — This write-once bit when set enables the PTC5/BKGD/MS pin to
function as BKGD/MS. When clear, the pin functions as output only GPIO. This pin defaults to the BKGD/MS
function following any MCU reset.
0 PTC5/BKGD/MS pin functions as PTC5.
1 PTC5/BKGD/MS pin functions as BKGD/MS.
0
RSTPE
84 Freescale Semiconductor
RESET
clear, the pin functions as open drain output only GPIO. This pin defaults to its RESET
POR or LVD. When RSTPE is set, an internal pullup device is enabled on RESET
0 PTC6/RESET
1 PTC6/RESET
Pin Enable — This write-once bit when set enables the PTC6/RESET pin to function as RESET. When
function following an MCU
.
pin functions as PTC6.
pin functions as RESET.
MC9S08LG32 MCU Series, Rev. 5
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Chapter 5 Resets, Interrupts, and General System Control
5.8.5 System Options Register 2 (SOPT2)
This high-page register contains bits to configure MCU specific features on the MC9S08LG32 series
devices.
76543210
R
COPCLKS
W
Reset:00000001
1
This bit can be written only one time after reset. Additional writes are ignored.
Field Description
1
000000
SPIFE
= Unimplemented or Reserved
Figure 5-6. System Options Register 2 (SOPT2)
Table 5-7. SOPT2 Register Field Descriptions
7
COPCLKS
0
SPIFE
COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog.
0 Internal 1 kHz clock is source to COP.
1 Bus clock is source to COP.
SPI Filter Enable— This bit selects the IFE control of the SPI pins.
0IFE disabled
1 IFE enabled
MC9S08LG32 MCU Series, Rev. 5
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Chapter 5 Resets, Interrupts, and General System Control
5.8.6 System Device Identification Register (SDIDH, SDIDL)
These high-page read-only registers are included so host development systems can identify the HCS08
derivative. This allows the development software to recognize where specific memory blocks, registers,
and control bits are located in a target MCU.
76543210
R ID11 ID10 ID9 ID8
W
Reset:———— 0 0 0 0
= Unimplemented or Reserved
Figure 5-7. System Device Identification Register — High (SDIDH)
Table 5-8. SDIDH Register Field Descriptions
Field Description
7:4
Reserved
3:0
ID[11:8]
76543210
R ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
W
Reset:00101010
Bits 7:4 are reserved. Reading these bits result in an indeterminate value; writes have no effect.
Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The
MC9S08LG32 is hard coded to the value 0x02A. See also ID bits in Ta bl e 5 -9 .
= Unimplemented or Reserved
Figure 5-8. System Device Identification Register — Low (SDIDL)
Table 5-9. SDIDL Register Field Descriptions
Field Description
7:0
ID[7:0]
Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The
MC9S08LG32 is hard coded to the value 0x02A. See also ID bits in Ta bl e 5 -8 .
MC9S08LG32 MCU Series, Rev. 5
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Chapter 5 Resets, Interrupts, and General System Control
5.8.7 System Power Management Status and Control 1 Register (SPMSC1)
This high-page register contains status and control bits to support the low voltage detect function, and to
enable the bandgap voltage reference for use by the ADC module. To configure the low voltage detect trip
voltage, see Table for the LVDV bit description in SPMSC2.
76543210
RLVWF
W LVWACK
RESET: 00011100
POR and LVD:00011100
1
0
LVWIE LVDRE
= Unimplemented or Reserved
2
LVDSE LVDE
2
Figure 5-9. System Power Management Status and Control 1 Register (SPMSC1)
1
LVWF is set in the case when V
2
Write-once only after any system reset
3
Bit 1 is a reserved bit that must always be written to 0.
transitions below the trip point or after reset and V
Supply
Supply
3
0
is already below V
BGBE
LV W
.
Table 5-10. SPMSC1 Register Field Descriptions
Field Description
7
LVWF
6
LV WAC K
5
LV WI E
4
VDRE
3
LV DS E
Low-Voltage Warning Flag - The LVWF bit indicates the Low-Voltage Warning status.
0 Low voltage warning not present.
1 Low voltage warning is present or was present.
Low-Voltage Warning Acknowledge
The LVWACK bit indicates the Low-Voltage Warning Acknowledge status. Writing a logic 1 to LVWACK clears
LVWF to a logic 0 if a low voltage warning is not present.
Low-Voltage Warning Interrupt Enable
This bit enables hardware interrupt requests for LVWF..
0 Hardware interrupt disabled(use polling).
1 Request a hardware interrupt when LVWF=1.
Low-Voltage Detect Reset Enable
This write-once bit enables LVD events to generate a hardware reset(provided LVDE=1). This bit has no effect if
the LVDE bit is a logic 0.
0 LVD events do not generate hardware resets.
1 Force an MCU reset when an enabled low-voltage detect event occurs.
Low-Voltage Detect Stop Enable
Provided LVDE = 1, this read/write bit determines whether the low-voltage detect function operates when the
MCU is in stop mode. This bit has no effect if the LVDE bit is a logic 0.
0 Low-Voltage detect disabled during stop mode.
1 Low-Voltage detect enabled during stop mode.
MC9S08LG32 MCU Series, Rev. 5
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Chapter 5 Resets, Interrupts, and General System Control
Table 5-10. SPMSC1 Register Field Descriptions (continued)
Field Description
2
LV DE
0
BGBE
Low-Voltage Detect Enable
This write-once bit enables low-voltage detect logic and qualifies the operation of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
Bandgap Buffer Enable
This bit enables an internal buffer for the bandgap voltage reference for use by the ADC module on one of its
internal channels.
0 Bandgap buffer disabled.
1 Bandgap buffer enabled.
5.8.8 System Power Management Status and Control 2 Register (SPMSC2)
This register is used to report the status of the low voltage warning function, and to configure the stop
mode behavior of the MCU.
76543210
R0 0
W PPDACK
POR:00000000
LVD:00UU0000
LVDV
1
LV WV
PPDF 0 0
PPDC
2
Any other Re-
set:
00UU0000
= Unimplemented or Reserved U = Unaffected by MCU Reset
Figure 5-10. System Power Management Status and Control 2 Register (SPMSC2)
1 This bit can be written only one time after power-on reset. Additional writes are ignored.
2 This bit can be written only one time after reset. Additional writes are ignore.
Table 5-11. SPMSC2 Register Field Descriptions
Field Description
5
LV DV
5
LV WV
3
PPDF
Low-Voltage Detect Voltage Select
This write-once bit selects the low voltage detect(LVD) trip point setting. It also selects warning voltage
range.See Table 5-12 for definition of these voltages.
Low-Voltage Warning Voltage Select
The bit selects the low voltage warning(LVW) trip point voltage. See Table 5-12 for definition of these voltages.
Partial Power Down Flag
This read-only status bit indicates that the MCU has recovered from stop2 mode.
0 MCU has not recovered from stop2 mode.
1 MCU recovered from stop2 mode.
MC9S08LG32 MCU Series, Rev. 5
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Chapter 5 Resets, Interrupts, and General System Control
Table 5-11. SPMSC2 Register Field Descriptions (continued)
Field Description
2
PPDACK
0
PPDC
Partial Power Down Acknowledge
Writing a logic 1 to PPDACK clears the PPDF bit.
Partial Power Down Control
This write-once bit controls whether stop2 or stop3 mode is selected.
0 Stop3 mode enabled.
1 Stop2, partial power down mode enabled.
Table 5-12. LVD and LVW Trip Points
Num Characteristic Symbol Min Max Unit
1 High LVD trip point (V
2 High LVD trip point (V
3 Low LVD trip point (V
4 Low LVD trip point (V
5 High LVW trip point (V
6 High LVW trip point (V
7 Low LVW trip point (V
8 Low LVW trip point (V
9 High LVW trip point (V
10 High LVW trip point (V
11 Low LVW trip point (V
12 Low LVW trip point (V
1
All values measured with respect to V
2
All values with factory trim
SUPPLY
SUPPLY
SUPPLY
SUPPLY
SUPPLY
SUPPLY
SUPPLY
SUPPLY
SUPPLY
SUPPLY
SUPPLY
SUPPLY
falling, LVDV = 1)
1
V
LV DX H
rising, LVDV = 1) 4.00 4.20 V
falling, LVDV = 0) V
LV DX L
rising, LVDV = 0) 2.54 2.70 V
falling, {LVDV,LVWV} = 00) V
LV WX L L
rising, {LVDV,LVWV} = 00) 2.72 2.88 V
falling, {LVDV,LVWV} = 01) V
LV WX L H
rising, {LVDV,LVWV} = 01) 2.90 3.06 V
falling, {LVDV,LVWV} = 10) V
LV WX H L
rising, {LVDV,LVWV} = 10) 4.30 4.50 V
falling, {LVDV,LVWV} = 11) V
LV WX H H
rising, {LVDV,LVWV} = 11) 4.60 4.80 V
SUPPLY
2
3.90
4.10 V
2.48 2.64 V
2.66 2.82 V
2.84 3.00 V
4.20 4.40 V
4.50 4.70 V
MC9S08LG32 MCU Series, Rev. 5
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Chapter 5 Resets, Interrupts, and General System Control
5.8.9 System Clock Gating Control 1Register (SCGC1)
This high-page register contains control bits to enable or disable the bus clock to the TPMx, ADC, IIC,
MTIM, RTC, and SCIx modules. Gating off the clocks to unused peripherals is used to reduce the MCU’s
run and wait currents. See Section 5.7, “Peripheral Clock Gating,” for more information.
NOTE
User software must disable the peripheral before disabling the clocks to the
peripheral. When clocks are re-enabled to a peripheral, the peripheral
registers need to be re-initialized by user software.
76543210
R
W
Reset:00000000
RTC TPM2 TPM1 ADC MTIM IIC SCI2 SCI1
Figure 5-11. System Clock Gating Control 1Register (SCGC1)
Table 5-13. SCGC1 Register Field Descriptions
Field Description
7
RTC
6
TPM2
5
TPM1
4
ADC
3
MTIM
2
IIC
1
SCI2
RTC Clock Gate Control — This bit controls the clock gate to the RTC module.
0 Bus clock to the RTC module is disabled.
1 Bus clock to the RTC module is enabled.
TPM2 Clock Gate Control — This bit controls the clock gate to the TPM2 module.
0 Bus clock to the TPM2 module is disabled.
1 Bus clock to the TPM2 module is enabled.
TPM1 Clock Gate Control — This bit controls the clock gate to the TPM1 module.
0 Bus clock to the TPM1 module is disabled.
1 Bus clock to the TPM1 module is enabled.
ADC Clock Gate Control — This bit controls the clock gate to the ADC module.
0 Bus clock to the ADC module is disabled.
1 Bus clock to the ADC module is enabled.
MTIM Clock Gate Control — This bit controls the clock gate to the MTIM module.
0 Bus clock to the MTIM module is disabled.
1 Bus clock to the MTIM module is enabled.
IIC Clock Gate Control — This bit controls the clock gate to the IIC module.
0 Bus clock to the IIC module is disabled.
1 Bus clock to the IIC module is enabled.
SCI2 Clock Gate Control — This bit controls the clock gate to the SCI2 module.
0 Bus clock to the SCI2 module is disabled.
1 Bus clock to the SCI2 module is enabled.
0
SCI1
90 Freescale Semiconductor
SCI1 Clock Gate Control — This bit controls the clock gate to the SCI1 module.
0 Bus clock to the SCI1 module is disabled.
1 Bus clock to the SCI1 module is enabled.
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Chapter 5 Resets, Interrupts, and General System Control
5.8.10 System Clock Gating Control 2 Register (SCGC2)
This high-page register contains control bits to enable or disable the bus clock to the IRQ, KBI, LCD, and
SPI modules. Gating off the clocks to unused peripherals is used to reduce the MCU’s run and wait
currents. See Section 5.7, “Peripheral Clock Gating,” for more information.
NOTE
User software must disable the peripheral before disabling the clocks to the
peripheral. When clocks are re-enabled to a peripheral, the peripheral
registers need to be re-initialized by user software.
76543210
R
DBG FLS IRQ KBI
W — —
Reset:01000000
= Unimplemented or Reserved
Figure 5-12. System Clock Gating Control 2 Register (SCGC2)
00
LCD SPI
Table 5-14. SCGC2 Register Field Descriptions
Field Description
7
DBG
6
FLS
5
IRQ
4
KBI
1
LCD
0
SPI
DBG Register Clock Gate Control — This bit controls the bus clock gate to the DBG module.
0 Bus clock to the DBG module is disabled.
1 Bus clock to the DBG module is enabled.
Flash Clock Gate Control — This bit controls the bus clock gate to the Flash module.
0 Bus clock to the Flash module is disabled.
1 Bus clock to the Flash module is enabled.
IRQ Clock Gate Control — This bit controls the bus clock gate to the IRQ module.
0 Bus clock to the IRQ module is disabled.
1 Bus clock to the IRQ module is enabled.
KBI Clock Gate Control — This bit controls the clock gate to the KBI module.
0 Bus clock to the KBI module is disabled.
1 Bus clock to the KBI module is enabled.
LCD Clock Gate Control — This bit controls the bus clock gate to the LCD module. Only the bus clock is gated,
the OSCOUT, TODCLK and LPOCLK are still available to the LCD.
0 Bus clock to the LCD module is disabled.
1 Bus clock to the LCD module is enabled.
SPI Clock Gate Control — This bit controls the clock gate to the SPI module.
0 Bus clock to the SPI module is disabled.
1 Bus clock to the SPI module is enabled.
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Chapter 5 Resets, Interrupts, and General System Control
5.8.11 Pin Position Control Register (PINPS1)
This high-page register contains the control bits that determine which of the two possible pins is used as
the source for the indicated KBIx pin function. The default source is the pin available on the 48-pin
package.
76543210
R
W
Reset:00000000
Field Description
KBI7 KBI6 KBI5 KBI4 KBI3 KBI2 KBI1 KBI0
Figure 5-13. Pin Position Control Register (PINPS1)
Table 5-15. PINPS1 Register Field Descriptions
8
KBI7
7
KBI6
6
KBI5
5
KBI4
4
KBI3
3
KBI2
2
KBI1
1
KBI0
KBI7 Pin Position — This bit controls the pin position of KBI7.
0 KBI7 sourced from PTA6
1 KBI7 sourced from PTH3
KBI6 Pin Position — This bit controls the pin position of KBI6.
0 KBI6 sourced from PTA5
1 KBI6 sourced from PTH2
KBI5 Pin Position — This bit controls the pin position of KBI5.
0 KBI5 sourced from PTA4
1 KBI5 sourced from PTH1
KBI4 Pin Position — This bit controls the pin position of KBI4.
0 KBI4 sourced from PTA3
1 KBI4 sourced from PTH0
KBI3 Pin Position — This bit controls the pin position of KBI3.
0 KBI3 sourced from PTF0
1 KBI3 sourced from PTH5
KBI2 Pin Position — This bit controls the pin position of KBI2.
0 KBI2 sourced from PTF5
1 KBI2 sourced from PTH4
KBI1 Pin Position — This bit controls the pin position of KBI1.
0 KBI1 sourced from PTF4
1 KBI1 sourced from PTH7
KBI0 Pin Position — This bit controls the pin position of KBI0.
0 KBI0 sourced from PTF3
1 KBI0 sourced from PTH6
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Chapter 5 Resets, Interrupts, and General System Control
5.8.12 Pin Position Control Register (PINPS2)
This high-page register contains the control bits that determine which of the two potential pins is used as
the source for the TPMx pin function. The default source is the pin available on the 48-pin package.
76543210
R
TPM2[5] TPM2[4] TPM2[3] TPM2[2] TPM2[1] TPM2[0] TPM1[1] TPM1[0]
W
Reset:00000000
Figure 5-14. Pin Position Control Register (PINPS2)
Table 5-16. PINPS2 Register Field Descriptions
Field Description
7
TPM2[5]
6
TPM2[4]
5
TPM2[3]
4
TPM2[2]
3
TPM2[1]
2
TPM2[0]
1
TPM1[1]
0
TPM1[0]
TPM2[5] Pin Position — This bit controls the pin position of TPM2[5].
0 TPM2[5] sourced from PTF3
1 TPM2[5] sourced from PTH6
TPM2[4] Pin Position — This bit controls the pin position of TPM2[4].
0 TPM2[4] sourced from PTF4
1 TPM2[4] sourced from PTH7
TPM2[3] Pin Position — This bit controls the pin position of TPM2[3].
0 TPM2[3] sourced from PTF5
1 TPM2[3] sourced from PTI2
TPM2[2] Pin Position — This bit controls the pin position of TPM2[2].
0 TPM2[2] sourced from PTF0
1 TPM2[2] sourced from PTI3
TPM2[1] Pin Position — This bit controls the pin position of TPM2[1].
0 TPM2[1] sourced from PTA6
1 TPM2[1] sourced from PTI4
TPM2[0] Pin Position — This bit controls the pin position of TPM2[0].
0 TPM2[0] sourced from PTA5
1 TPM2[0] sourced from PTI5
TPM1[1] Pin Position — This bit controls the pin position of TPM1[1].
0 TPM1[1] sourced from PTF2
1 TPM1[1] sourced from PTH4
TPM1[0] Pin Position — This bit controls the pin position of TPM1[0].
0 TPM1[0] sourced from PTF1
1 TPM1[0] sourced from PTH5
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Chapter 5 Resets, Interrupts, and General System Control
5.8.13 Pin Position Control Register (PINPS3)
This high-page register contains control bits that determine which of the two potential pins is used as the
source for the function. The default source is the pin available on the 48-pin package.
76543210
R
W
Reset:00000000
Field Description
TX2 RX2 SCL SDA MISO MOSI SCK SS
Figure 5-15. Pin Position Control Register (PINPS3)
Table 5-17. PINPS3 Register Field Descriptions
7
TX2
6
RX2
5
SCL
4
SDA
3
MISO
2
MOSI
1
SCK
0
SS
TX2 Pin Position — This bit controls the pin position of TX2.
0 TX2 sourced from PTA3.
1 TX2 sourced from PTI1.
RX2 Pin Position — This bit controls the pin position of RX2.
0 RX2 sourced from PTA4.
1 RX2 sourced from PTI0.
SCL Pin Position — This bit controls the pin position of SCL.
0 SCL sourced from PTA1.
1 SCL sourced from PTI5.
SDA Pin Position — This bit controls the pin position of SDA.
0 SDA sourced from PTA2.
1 SDA sourced from PTI4.
MISO Pin Position — This bit controls the pin position of MISO.
0 MISO sourced from PTF4.
1 MISO sourced from PTI2.
MOSI Pin Position — This bit controls the pin position of MOSI.
0 MOSI sourced from PTF5.
1 MOSI sourced from PTI3.
SCK Pin Position — This bit controls the pin position of SCK.
0 SCK sourced from PTF2.
1 SCK sourced from PTI4.
SS Pin Position — This bit controls the pin position of SS.
0 SS sourced from PTF3.
1 SS sourced from PTI5.
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5.8.14 Pin Position Control Register (PINPS4)
This high-page register contains control bits that determine which of the two potential pins is used as the
source for the function. The default source is the pin available on 48-pin package.
76543210
R
W
Reset:00000000
Field Description
000000TX1RX1
Figure 5-16. Pin Position Control Register (PINPS4)
Table 5-18. PINPS4 Register Field Descriptions
1
TX1
0
RX1
TX1 Pin Position — This bit controls the pin position of TX1.
0 TX1 sourced from PTF0.
1 TX1 sourced from PTH5.
RX1 Pin Position — This bit controls the pin position of RX1.
0 RX1 sourced from PTF1.
1 RX1 sourced from PTH4.
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Chapter 6 Parallel Input/Output Control
6.1 Introduction
This section explains software controls related to parallel input/output (I/O) and pin control. The
MC9S08LG32 has nine parallel I/O ports (PTA-PTI) which include a total of 69 I/O pins, including two
output-only pins. See Chapter 2, “Pins and Connections,” for more information about pin assignments and
external hardware considerations of these pins.
Many of these pins are shared with on-chip peripherals such as timer systems, communication systems, or
keyboard interrupts, as shown in Table 2-1. The peripheral modules have priority over the general-purpose
I/O functions so that when a peripheral is enabled, the I/O functions associated with the shared pins may
be disabled.
After reset, the shared peripheral functions are disabled and the pins are configured as inputs
(PTxDDn = 0). The pin control functions for each pin are configured as follows: slew rate control enabled
(PTxSEn = 1), low drive strength selected (PTxDSn = 0), and internal pullups disabled (PTxPEn = 0).
NOTE
All general-purpose I/O pins are not available on all packages. To avoid
extra current drain from floating input pins, your reset initialization routine
in the application program must either enable on-chip pullup devices or
change the direction of unconnected pins to outputs so the pins do not float.
6.2 Pins Shared with LCD
Pins that have shared function with the LCD have special behavior based on the state of the VSUPPLY
bits in the LCDSUPPLY register. These pins (PTA, PTB, PTC[4:0], PTD, PTE and PTG) can operate as
full complementary drive or open drain drive depending on the VSUPPLY bits. When V
to VDD externally, VSUPPLY = 11, FCDEN = 1, and RVEN = 0; the pins operate as full complementary
drive. For all other VSUPPLY modes, the GPIO shared with LCD operates as open drain.
is connected
LL3
6.3 Port Data and Data Direction
Reading and writing of parallel I/Os are performed through the port data registers (PTxDn). The direction,
either input or output, is controlled through the port data direction registers (PTxDDn). The parallel I/O
port function for an individual pin is illustrated in the block diagram shown in Figure 6-1.
The data direction control bit (PTxDDn) determines whether the output buffer or the input buffer for the
associated pin is enabled. When a shared digital function is enabled for a pin, the output buffer is controlled
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Chapter 6 Parallel Input/Output Control
QD
QD
1
0
Port Read
PTxDDn
PTx Dn
Output Enable
Output Data
Input Data
Synchronizer
Data
BUSCLK
Input Enable
by the shared function. However, the data direction register bit continues to control the source for reads of
the port data register.
When a shared analog function is enabled for a pin, both the input and output buffers are disabled. A value
of 0 is read for any port data bit where the bit is an input (PTxDDn = 0) and the input buffer is disabled. In
general, whenever a pin is shared with both an alternate digital function and an analog function, the analog
function has priority such that if both the digital and analog functions are enabled, the analog function
controls the pin.
It is good programming practice to write to the port data register before changing the direction of a port
pin so it becomes an output. This ensures that the pin is not driven momentarily with an old data value that
happen to be in the port data register.
Figure 6-1. Parallel I/O Block Diagram
6.4 Pullup, Slew Rate, and Drive Strength
Associated with the parallel I/O ports is a set of registers located in the high-page register space that
operates independently of the parallel I/O registers. These registers are used to control pullups, slew rate,
and drive strength for the pins and can be used in conjunction with the peripheral functions on these pins.
6.4.1 Port Internal Pullup Enable
For all GPIOs, set the corresponding bit in the pullup enable register (PTxPEn) to enable an internal pullup
resistor for each port pin. Typically, GPIO internal pullups are disabled when in output mode. However,
for GPIO that are muxed with LCD pins, the internal pullup is not disabled when in open drain, output
mode. Similarly the internal pullup for GPIO muxed with open drain RESET pin is not disabled in the
output mode.
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Chapter 6 Parallel Input/Output Control
The pullup device is disabled if the pin is controlled by an analog function regardless of the state of the
corresponding pullup enable register bit.
6.4.2 Port Slew Rate Enable
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PTxSEn). When enabled, slew control limits the rate at which an output can transition to reduce
EMC emissions. Slew rate control has no effect on pins that are configured as inputs.
6.4.3 Port Drive Strength Select
An output pin can be configured for high-output drive strength by setting the corresponding bit in the drive
strength select register (PTxDSn). When high drive is selected, a pin is capable of sourcing and sinking
greater current. Even though every I/O pin can be selected as high drive, you must ensure that the total
current source and sink limits for the MCU are not exceeded. Drive strength selection is intended to affect
the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin to drive
a greater load with the same switching speed as a low drive enabled pin into a smaller load. Because of
this, the EMC emissions may be affected by enabling pins as high drive.
6.5 Open Drain Operation
For most cases, port pins that share functions with the LCD operate as open drain outputs. As an open drain
output, the output high of the pin is dependent upon the pullup resistor. The pullup resistor can be an
internal resistor enabled by the PTxPEx bit or an external resistor.
• The value of the internal resistor can be in the range of 17.5 to 52.5 kΩ
• The value of an external resistor must be carefully selected to ensure it supports the output loads
that are being driven.
6.6 Pin Behavior in Stop Modes
Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An
explanation of pin behavior for the various stop modes follows:
• Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their pre-STOP
instruction state. CPU register status and the state of I/O registers must be saved in RAM before
the STOP instruction is executed to place the MCU in stop2 mode. Upon recovery from stop2
mode, before accessing any I/O, you must examine the state of the PPDF bit in the SPMSC2
register. If the PPDF bit is 0, I/O must be initialized as if a power-on reset had occurred. If the PPDF
bit is 1, I/O register states must be restored from the values saved in RAM before the STOP
instruction was executed. Peripherals may require initialization or restoration to their pre-stop
condition. You must then write a 1 to the PPDACK bit in the SPMSC2 register. Access to I/O is
again permitted in the user application program.
• If the LCD module is configured to operate in Stop modes, the drive mode of the GPIO shared with
LCD is retained upon stop recovery.
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Chapter 6 Parallel Input/Output Control
• In stop3 mode, all I/O is maintained because internal logic circuitry stays powered up. Upon
recovery, normal I/O function is available to the user.
6.7 Parallel I/O and Pin Control Registers
This section provides information about the registers associated with the parallel I/O ports. The data and
data direction registers are located in page zero of the memory map. The pullup, slew rate, and drive
strength control registers are located in the high-page section of the memory map.
Refer to tables in Chapter 4, “Memory,” for the absolute address assignments for all parallel I/O and their
pin control registers. This section refers to registers and control bits only by their names. A Freescale
Semiconductor-provided equate or header file is normally to translate these names into the appropriate
absolute addresses.
6.7.1 Port A Registers
Port A is controlled by the registers listed below. All the pins of port A are shared with LCD. These pins
have special behavior as explained in Section 6.2.
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