How it Works
NXP Semiconductors
Loading...
MC92602
User Manual
48 pgs1.12 Mb0

NXP Semiconductors MC92602 User Manual

MC92602
Reduced Interface SerDes
Design Verification Board
User’s Guide
MC92602DVBUG
Rev. 3, 06/2005
Contents
Paragraph Page Number Title Number
Chapter 1
General Information
1.1 Introduction...................................................................................................................... 1-1
1.2 Design Verification Board Features ................................................................................. 1-1
1.3 Specifications................................................................................................................... 1-2
1.4 Abbreviation List ............................................................................................................. 1-2
1.5 Related Documentation.................................................................................................... 1-3
1.6 Block Diagram................................................................................................................. 1-3
1.7 Board Components .......................................................................................................... 1-3
1.8 Contact Information......................................................................................................... 1-3
Chapter 2
Hardware Preparation and Installation
2.1 Unpacking Instructions .................................................................................................... 2-1
2.2 MC92602DVB Package Contents ................................................................................... 2-1
2.3 Hardware Preparation ...................................................................................................... 2-1
2.3.1 Setting the Power Supply and Voltage Regulators ...................................................... 2-1
2.3.2 Setting the Voltage Regulators..................................................................................... 2-2
2.3.3 HSTL Voltage Reference Regulator ............................................................................ 2-3
2.4 Reference Clock Source................................................................................................... 2-3
2.4.1 Using the Onboard Oscillator ...................................................................................... 2-4
2.4.2 External Reference Clock Source................................................................................ 2-4
2.4.3 Supplying a Clock to the MC92602 ............................................................................ 2-4
2.4.4 3.3V_CLK_OUTn SMA Connectors .......................................................................... 2-5
2.4.5 Clock Frequency Selection .......................................................................................... 2-5
2.5 Interface Components ...................................................................................................... 2-6
2.5.1 Parallel Inputs and Outputs.......................................................................................... 2-6
2.5.1.1 Parallel Inputs .......................................................................................................... 2-6
2.5.1.2 Parallel Outputs ....................................................................................................... 2-7
2.5.2 +V
2.5.3 Serial Inputs and Outputs............................................................................................. 2-7
2.6 Special Test Connection................................................................................................... 2-7
2.7 Test Traces ....................................................................................................................... 2-8
and Ground (GND) Access Connections........................................................ 2-7
DDQ
Freescale Semiconductor iii
Paragraph Page Number Title Number
Chapter 3
Laboratory Equipment and Quick Setup Evaluation
3.1 Recommended Laboratory Equipment ............................................................................ 3-1
3.2 Quick Setup Data-Eye Diagram ...................................................................................... 3-2
3.2.1 Quick Setup Data-Eye Generation and Observation ................................................... 3-3
3.2.1.1 Equipment Setup...................................................................................................... 3-3
3.2.1.2 Parallel Input Connections....................................................................................... 3-4
3.2.2 Basic Eye Observation—Test Procedure..................................................................... 3-5
3.2.3 Quick Setup Bit Error Rate Checking.......................................................................... 3-6
3.2.3.1 Equipment Setup...................................................................................................... 3-6
3.2.3.2 Parallel I/O Connections.......................................................................................... 3-7
3.2.3.3 Quick Setup BERC Test Procedure ......................................................................... 3-7
Chapter 4
Test Setups
4.1 Serial Link Verification Using a Serial Bit Error Rate Tester (BERT) ............................ 4-1
4.1.1 Test Setup for Full-Speed Mode .................................................................................. 4-2
4.1.2 Test Setup for Half-Speed Mode ................................................................................. 4-2
4.2 Jitter Testing..................................................................................................................... 4-3
4.2.1 Jitter Test System Calibration ...................................................................................... 4-3
4.2.2 Reference Clock Jitter Transfer Test............................................................................ 4-4
4.2.3 Reference Clock Jitter Tolerance Test ......................................................................... 4-5
4.2.4 Data Jitter Tolerance Test............................................................................................. 4-6
Appendix A
Connector Signals
A.1 Input: 2 × 10 (0.100") Connectors.................................................................................... A-1
A.1.1 Control Signal Input Connectors ................................................................................ A-1
A.1.2 Transmitter Parallel Data Input Connectors ............................................................... A-3
A.2 Output: 2 × 20 (0.100") Connectors................................................................................. A-4
A.3 TEST_0 Connector ......................................................................................................... A-5
Appendix B
Parts List
B.1 Design Verification Board Parts List ...............................................................................B-1
iv Freescale Semiconductor
Paragraph Page Number Title Number
Appendix C
Prescaler for Jitter Measurement
C.1 Divide-by-xx Prescaler Description.................................................................................C-1
C.2 Prescaler Components......................................................................................................C-2
Appendix D
Revision History
Freescale Semiconductor v
vi Freescale Semiconductor
Chapter 1 General Information
1.1 Introduction
This user’s guide describes the MC92602 design verification board, Rev. B and higher. The design verification board (DVB) facilitates the full evaluation of the MC92602 Quad Reduced Interface SerDes. It should be read in conjunction with the MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Guide. This design verification board is intended for evaluation and testing purposes only. Freescale does not guarantee its performance in a production environment.
This board was designed to be used with laboratory equipment (pattern generators, data analyzers, BERT, scopes, etc.) or connected to other evaluation boards. Access to the MC92602 device (verification chip) is through connectors to each pin, to allow complete in-depth ‘design verification’ testing of the chip design. This allows the user to check any or all features/functions of the MC92602 device.
The four parallel data input ports and all configuration/control signal pins, are accessed through common 2 × 10, 0.100" male connectors (headers). The parallel data output ports are accessed through 2 × 20, 0.100" connectors. Device JTAG port signals are also accessed with a separate connector.
The MC92602 high-speed serial receivers and transmitters are accessed via SMA coaxial connectors for signal integrity measurements.
A single 5.0-V power source is required for the DVB operation. All necessary voltages are generated by regulators onboard. The reference clock for the MC92602 chip may be provided using either an external clock or the onboard crystal oscillator. Clock drivers on the DVB provide additional clock signals for triggering analyzer instrumentation and scopes.
1.2 Design Verification Board Features
The functional, physical, and performance features of the MC92602DVB are as follows:
• A single external 5.0-V to onboard regulators supply power to all onboard circuitry.
• Reference clock source is a 250-MHz crystal oscillator or an external clock source.
• Parallel data and control interfaces accessible through standard 0.100", 2 row connectors for data generators and analyzers.
• The full-duplex differential data links accessible through SMA connectors.
• Two pairs of 50-Ω test traces with SMA connections facilitate TDR measurements of the characteristic impedance of representative board traces.
• Connector provided for JTAG test access port
Freescale Semiconductor 1-1
General Information
1.3 Specifications
The MC92602DVB design verification board specifications are provided in Table 1-1.
Tabl e 1-1. MC92602DVB Design Verification Board Specifications
Characteristics Specifications
Board revision Rev. B and higher
External power supply +5 V DC ± 0.5 V DC < 2.0 A typical
Support circuit regulator 3.3 V ± 0.3 V DC
MC92602 core and link I/O regulator 1.8 V ± 0.15 V DC
Interface I/O (V
MC92602 package 196 MAPBGA
Operating temperature 0°−30°C
Material FR-4
Dimensions Height 14.8", 377 mm
Conducting layers Four ground planes, one split power plane, three signal routing layers, top and
) regulator 2.5 V ± 0.2 or 3.3 V ± 0.3 V DC
DDQ
Width 12.3", 312 mm
Thickness 0.1", 2.4 mm
bottom component layers with some additional signal routing.
1.4 Abbreviation List
Table 1-2 contains abbreviations used in this document.
Tabl e 1-2. Acronyms and Abbreviated Terms
Term Meaning
‘1’ High logic level (nominally 1.5 or 3.3 V)
‘0’ Low logic level (nominally 0.0 V)
BIST Built-in self-test
DVB Design verification board
I/F Interface
N/C No connection
PN Pseudo-noise
PRBS Pseudo random bit sequence
TA P Test access port
TDR Time delay reflectometry
UIp-p Peak-to-peak unit interval
1-2 Freescale Semiconductor
General Information
1.5 Related Documentation
Related documentation includes the following:
• MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Guide (MC92602RM)
• MC92602DVB schematics
• MC100ES6222 data sheet
• MC100ES8111 data sheet
• MPC9456 data sheet
1.6 Block Diagram
Figure 1-1 shows the MC92602 design verification board block diagram.
1.7 Board Components
Table 1-3 is a list of major components of the MC92602 design verification board. A complete parts listing
can be found in Appendix B, “Parts List.”
Tabl e 1-3. Major Board Components
Component Description
MC92602ZT Freescale Quad 1.25 Gbaud Reduced Interface SerDes
2 × 10, 0.100" connectors PG1–PG11, and PG13 provide access to the parallel inputs and control signals
2 × 20, 0.100" connectors LA1–LA4 provide access to the parallel outputs
2 × 8, 0.100" connectors PG12 and PG14 provide access to the SFP connector and +VDD/ground planes,
respectively.
SMA connectors SMA1–SMA16: Serial transmit and receive connections
TST1–TST8: Impedance test trace connections CLK_OUT1–CLK_OUT6: Reference clock outputs CLK_IN: External reference clock input CLK_A_PG - CLK_D_PG: Input clock connectors
LT1587 voltage regulators VR33, VR18, and VR1: +3.3 V, +1.8 V, and +1.5 (V
Potentiometers R12V, R22V, R22V1, and R22V2: Potentiometers for setting +3.3 V, +1.8 V,
V
+1.5
XTAL oscillator Y1, Y2: Onboard 250-MHz crystal oscillator
MC100ES6222 clock buffer U2: Divide-by-1 or divide-by-2 clock buffer
MPC9456 clock buffer U3: +3.3-V LVCMOS clock buffer
MC100ES8111 clock buffer U4: Level shift and clock buffer
, and HSTL reference voltage levels
DDQ
) voltage regulators
DDQ
1.8 Contact Information
For questions concerning the MC92602 design verification kit or to place an order for a kit, contact your local Freescale field applications engineer.
Freescale Semiconductor 1-3
General Information
+1.5 V/GND
0.100" Connector
CLK_IN
X-TAL
Osc
MC100
ES6222
MPC9456
3.3V_CLK_OUT1
3.3V_CLK_OUT2
3.3V_CLK_OUT3
3.3V_CLK_OUT4
R12V
GND
1.5V_CLK_OUT5
1.5V_CLK_OUT6
TST1 TST2
Vertical 50-Ω Te s t Tr a c e s
TST5 TST6
2 × 20, 0.100"
Connectors
LA4
LA3
LA2
MC100 ES8111
SW1
CLK_C_PG
CLK_D_PG
2×10, 0.100" Connectors
PG1
Control
RECV_D
RECV_C
RECV_B
PG7
PG6
XMIT_C XMIT_D
Reduced Interface
+3.3 V
MC92602
SerDes
PG4
+1.5 V
PG5
+3.3-V
Regulator
Regulator
Regulator
+5 V
R22V1
+1.5-V
R22V
+1.8-V
+1.8 V
RLINK_D0
XLINK_D0
RLINK_C0
XLINK_C0
RLINK_B0
XLINK_B0
LA1
HSTL_VREF
R22V2
TST3 TST7 TST4 TST8
Horizontal 50-
Te s t Tr a c e s
Ω
Figure 1-1. MC92602 Design Verification Board Block Diagram
1-4 Freescale Semiconductor
PG8PG8
RECV_A
HSTL_VREF
XMIT_A
PG9
XMIT_B Ctrl/Tst
PG11
PG10
2×10, 0.100" Connectors
RLINK_A0
XLINK_A0
TPA
CLK_A_PG
CLK_B_PG
PG13PG2
PG3
Chapter 2 Hardware Preparation and Installation
This chapter provides unpacking, hardware preparation, configuration-installation instructions, and description of the interface components for the MC92602DVB.
2.1 Unpacking Instructions
Unpack the board from the shipping carton. Refer to the packing list and verify that all items are present. Save the packing material for storing and reshipping of the equipment.
2.2 MC92602DVB Package Contents
Table 2-1 describes the contents of the MC92602DVB kit.
Tabl e 2-1. MC92602DVB Kit Contents
Quantity Item
1 MC92602DVB design verification board
1 MC92602DVB Reduced Interface SerDes Design Verification Board User’s Guide
1 MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Guide
1 Complete set of MC92602DVB design verification board schematics
45 0.100" shunts
10 Square pin receptacle patch cords
2.3 Hardware Preparation
Operation of the MC92602DVB requires proper setup of the power supply and voltage regulators as well as the reference clock. Figure 2-1 depicts the location of the major components on the board. The following sections describe proper setup of the MC92602DVB.
2.3.1 Setting the Power Supply and Voltage Regulators
The MC92602DVB requires a single +5.0-V supply. Fully operational, the board will draw a maximum current less than 2.0 amps from the +5.0-V supply. Actual current consumption depends on the user set voltage levels, clock frequencies, and the MC92602 operating mode. The board contains two +5.0-V connection posts and two ground connection posts. These duplicate connections simplify using a four-wire supply: supply and ground, force and sense.
Freescale Semiconductor 2-1
Hardware Preparation and Installation
2 × 8 Connector
50-Ω Ver ti ca l Te st Tra ce s
2 × 20 Connectors
2 × 8 Connector
+1.5- and +1.8-V Powe r Connectors
2 × 10 Connectors
Crystal Oscillator
DIP Switch
MC92602
+3.3-V Power Connection
Clock Buffers
Vol tag e Regulators
HSTL Reference Test Point
+5-V Power Connectors
Serial Differential SMA Connectors
Horizontal 50-Ω Te st Tra ce s
2 × 10 Connectors
NOTE:
Freescale has begun the transition of marking Printed Circuit Boards (PCBs) with the Freescale Semiconductor signature/logo. PCBs may have either Motorola or Freescale markings during the transition period. These changes will have no impact on form, fit, or function of the current product.
Figure 2-1. Top Side Part Location Diagram
2.3.2 Setting the Voltage Regulators
The +5.0-V supply is used to power 3 onboard voltage regulators, VR33, VR18, and VR15. These regulators generate +3.3, +1.8, and +1.5/1.8 V (V to the oscillator and clock buffer chips. This supply can be varied over the range +3.3 R12V potentiometer.
The +1.8-V supply is used to power the MC92602 core logic, transceivers, and on-chip phase-locked loop (PLL). This regulator can be adjusted over the range +1.8 V
The +1.5-V (HSTL) V
supply powers the MC92602 control signal, parallel input, and output interface
DDQ
circuitry. This voltage level is determined by the desired logic interface. The +1.5-V supply can be adjusted using a R22V1 potentiometer from +1.5 V + 0.45 V/– 0.15 V. If desired, the +1.5-V regulator can be adjusted to match the +1.8-V range for evaluation in those systems that do not contain a separate +1.5-V supply.
), respectively. The +3.3-V supply provides power
DDQ
V ± 0.3 V using the
± 0.15 V using R22V.
2-2 Freescale Semiconductor
Hardware Preparation and Installation
The +3.3-V, +1.8-V, and +V
supplies are accessible via connection posts. Note that these regulators
DDQ
should be set to voltage limits within the operating ranges described in the MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Guide. Failure to operate within these ranges could cause damage to the MC92602. Freescale will not guarantee MC92602 operation beyond the ranges specified. The R12V, R22V, and R22V1 potentiometers will be factory set for +3.3, +1.8, and +1.5
V, respectively.
2.3.3 HSTL Voltage Reference Regulator
The HSTL I/O has a voltage reference that must be adjusted to set the logic high/low switch point. For a nominal +1.5 V on the +1.5-V, V
supply, R22V2 should be set such that the voltage at the
DDQ
HSTL_VREF test point is +0.75 V. For those systems whose HSTL voltage will be +1.8 V, t h i s potentiometer should be set to +0.9 V. The R22V2 potentiometer is typically factory set for +0.8 V.
2.4 Reference Clock Source
Through a combination of clock buffers, a reference clock is supplied to the MC92602 and several SMA output connectors. The input reference clock for the MC92602 can be supplied using either an onboard crystal oscillator, or by directly driving an external reference clock into the board’s clock buffer circuit via SMA connector, CLK_IN. The clock circuitry for the MC92602DVB is shown in Figure 2-2.
Y1
250-MHz
CLK_IN
Oscillator
Y2
EN
+
U2
CLK_0
CLK_1
CSEL
MC100ES6222
DIV 1/2
DIV by 1
EN
U4 MC100ES8111
PECL
to HSTL Buffer
U3
MPC9456
REF_CLK_P REF_CLK_N
1.5V_CLK_OUT5
1.5V_CLK_OUT6
3.3V_CLK_OUT1
3.3V_CLK_OUT2
3.3V_CLK_OUT3
3.3V_CLK_OUT4
SW1
1 2 3 4 5 6 7
+
CLK
CLK
DIV 1/2
DIV 1/2
EN
Figure 2-2. MC92602DVB Clock Circuitry
Freescale Semiconductor 2-3
Hardware Preparation and Installation
2.4.1 Using the Onboard Oscillator
There are two available positions for using onboard oscillators. A standard 14-pin DIP socket is available on the board to allow the user to easily change frequencies by swapping in crystal oscillators with other values. The onboard oscillators must be two times (2×) the desired MVC92602 reference clock frequency. The default reference clock frequency oscillator supplied with the board is 250 MHz.
Crystal oscillators used with this board should have +3.3-V complementary PECL outputs capable of driving a line terminated with 50 Ω . Oscillators conforming to these specifications are also available in J-lead SMT packages and can be soldered onto the underside of the MC92602DVB at location Y2. This oscillator, Y2, can then be enabled by placing SW1 switch 1 in the ‘off’ position. Both types of crystal oscillators are available from external vendors in a variety of frequencies. Once either type of oscillator is installed, SW1 switch 2 must be placed in the ‘on’ position to select the onboard oscillator.
2.4.2 External Reference Clock Source
The input reference clock can also be supplied by using an external reference clock into the clock buffer circuit on the board via the CLK_IN SMA connector. To supply an external reference clock, switch number 2 on SW1 must be set to the ‘off’ position. The user must then supply a 1.0-Vp-p input clock via the SMA connector. The CLK_IN input is AC coupled on the board and, therefore, does not require any DC biasing of the input signal. This external clock input is also terminated with a 50-Ω impedance.
2.4.3 Supplying a Clock to the MC92602
The input reference clock, from either the onboard oscillator or an external source, is applied to a MC100ES6222 clock buffer. This buffer has an input clock select multiplexer, and a programmable divide-by-one/divide-by-two function. The buffer also contains a master reset (Enable). It is recommended that this reset, found on SW1 switch 4, be activated, then deactivated after changing the divide-by-xx switch. This will ensure proper frequency generation.
Between the MC100ES6222 output and the MC92602 reference clock inputs, REF_CLK_P and REF_CLK_N, is an MC100ES8111 which performs a PECL to HSTL level shift. It also drives two SMA connectors, 1.5V_CLK_OUT5 and 1.5V_CLK_OUT6, with HSTL level clock signals.
NOTE
The outputs of the MCP100ES8111 expect to see a DC 50-Ω path to ground. Therefore, if a DC blocker is being used with the 1.5V_CLK_OUT5 or
1.5V_CLK_OUT6 outputs as a trigger or signal to an oscilloscope, a 50-Ω feed through termination must be placed in line before the DC blocker and before the attachment to the oscilloscope. A 3dB attenuator may be used in place of the 50-Ω feed through termination.
2-4 Freescale Semiconductor
Hardware Preparation and Installation
2.4.4 3.3V_CLK_OUTn SMA Connectors
Four single-ended, 3.3-V level, clock signals are available on SMA connectors to drive other instruments. Between the MC100ES8111 output and the 4 SMAs, is an MPC9456 which performs a differential PECL to single-ended +3.3-V LVTTL/CMOS level shift. These CMOS outputs are series terminated on the board, then connect to the SMA connectors labeled 3.3V_CLK_OUT1, 3.3V_CLK_OUT2,
3.3V_CLK_OUT3, and 3.3V_CLK_OUT4. All of the outputs of the MPC9456 can be disabled by setting the DIP switch SW1, switch 7 to the ‘off’ position.
2.4.5 Clock Frequency Selection
To accommodate the fact that the MC92602 can receive data on both edges of the reference clock (DDR), of which many pieces of test equipment are single-edge triggered (SDR), the MC92602DVB clock outputs can be programmed to be either the same as the supplied frequency or half the supplied frequency by setting SW1, switches 3, 5, and 6 to either ‘on’ (divide-by-one) or to ‘off’ (divide-by-2). This allows the interface between the board and the bench to be either single data rate (SDR) with a double speed clock, or double data rate (DDR) with a single speed clock.
The 1.5V_CLK_OUTn SMA outputs will always follow the clock supplied to the MC92602 and the frequency is programmed via SW1, switch 3. SMA outputs 3.3V_CLK_OUT1 and 3.3V_CLK_OUT2 can be programmed by setting SW1, switch 5 and 3.3V_CLK_OUT3 and 3.3V_CLK_OUT4 can be programmed by setting SW1, switch 6. Table 2-2 lists the switch positions and output frequencies. The input frequency, CLK_IN refers to either the onboard oscillator frequency or the externally applied clock source frequency.
NOTE
Only those frequencies listed in the MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Guide are considered valid. Freescale does not
guarantee operation of the MC92602 at frequencies other than those listed in the reference Guide.
Tabl e 2-2. SW1 Settings and Output Frequencies
MC92602
SW1
Switch
3 On CLK_IN N/A N/A
5 On N/A CLK_IN N/A
6 On N/A N/A CLK_IN
Switch
Position
Off CLK_IN/2 N/A N/A
Off N/A CLK_IN/2 N/A
Off N/A N/A CLK_IN/2
REF_CLK_P, REF_CLK_N,
and 1.5V_CLK_OUTn
3.3V_CLK_OUT1,
3.3V_CLK_OUT2
3.3V_CLK_OUT,
3.3V_CLK_OUT4
Freescale Semiconductor 2-5
Loading...
+ 33 hidden pages
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use