NXP Semiconductors M5253EVBE User Manual

M5253 Evaluation Board

Users Manual

Document Number: M5253EVBUM

Rev. 1

03/2007

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Contents

Chapter 1
M5253 Evaluation Board

1.1 General Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

1.2 System Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.3 Serial Communication Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.4 Parallel I/O Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.5 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.6 Installation and Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.6.1 Unpacking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.6.2 Preparing the Board for Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.6.3 Providing Power to the Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.6.4 Selecting Terminal Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.6.5 Terminal Character Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.6.6 Connecting the Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.6.7 Using a Personal Computer as a Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.7 System Power-up and Initial Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.8 M5253EVBE Jumper Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.9 Using the BDM Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11

Chapter 2
Using the Monitor/Debug Firmware

2.1 What Is dBUG?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

2.2 Operational Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2.1 System Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

2.2.2 System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.2.2.1 Hard RESET Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.2.2.2 ABORT Button. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.2.2.3 Software Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.3 Command Line Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.4 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.4.1 ASM (Assembler). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.4.2 BC (Block Compare) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.4.3 BF (Block Fill) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.4.4 BM (Block Move). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.4.5 BR (Breakpoints) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

2.4.6 BS (Block Search) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

2.4.7 DC (Data Conversion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.4.8 DI (Disassemble) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.4.9 DL (Download Console). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.4.10 DN (Download Network) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

2.4.11 GO (Execute) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.4.12 GT (Execute To). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

2.4.13 IRD (Internal Register Display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

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2.4.14 IRM (Internal Register Modify) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.4.15 HELP (Help). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

2.4.16 LR (Loop Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.4.17 LW (Loop Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.4.18 MD (Memory Display). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14

2.4.19 MM (Memory Modify). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.4.20 MMAP (Memory Map Display). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15

2.4.21 RD (Register Display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.4.22 RM (Register Modify) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.4.23 RESET (Reset the Board and dBUG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.4.24 SET (Set Configurations) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.4.25 SHOW (Show Configurations). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.4.26 STEP (Step Over) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.4.27 SYMBOL (Symbol Name Management) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.4.28 TRACE (Trace Into). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

2.4.29 UPDBUG (Update dBUG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.4.30 UPUSER (Update User Flash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.4.31 VERSION (Display dBUG Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.5 TRAP #15 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.5.1 OUT_CHAR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.5.2 IN_CHAR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.5.3 CHAR_PRESENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

2.5.4 EXIT_TO_dBUG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22

Chapter 3
Hardware Description and Reconfiguration

3.1 Processor and Support Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.1 Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.2 Reset Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1.3 HIZ Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.1.4 Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.1.5 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.1.6 Interrupt Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.1.7 Internal SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.1.8 MCF5253 Registers and Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.1.9 Reset Vector Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.1.10 TA Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.1.11 Wait State Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.1.12 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.1.13 Flash ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.2 Serial Communication Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.2.1 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.2.2 QSPI Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.2.3 I2C Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

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3.2.4 FlexCAN Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

3.2.5 USB 2.0 OTG Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

3.3 General Purpose I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.4 Audio Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.5 Analog to Digital Converter (ADC) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.6 Flash Memory Card/IDE Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

3.7 ATA Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

3.8 Real-Time Clock (RTC) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

3.9 Debug Connector J12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Appendix A
Evaluation Board BOM

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M5253EVBE Users Guide, Rev. 1

Chapter 1
M5253 Evaluation Board

The M5253EVBE is a versatile single-board computer based on the MCF5253 ColdFire® processor. It
may be used as a powerful microprocessor-based controller in a variety of applications. It serves as a
complete microcomputer system for reference design, development/evaluation, training, and educational
use. The user need only connect an RS-232 compatible terminal (or a personal computer with terminal
emulation software) and a power supply to have a fully functional system.

CAUTION

This board generates, uses, and can radiate radio frequency energy and, if
not installed properly, may cause interference to radio communications.
Operation of this product in a residential area is likely to cause interference,
in which case, the user, at his/her own expense, will be required to correct
the interference.

This device complies with part 15 of the FCC Rules. Operation is subject to
the following two conditions: (1) This device may not cause harmful
interference, and (2) this device must accept any interference received,
including interference that may cause undesired operation.

1.1 General Hardware Description

The M5253EVBE board provides SDRAM, Flash ROM, and RS-232 in addition to the built-in I/O
functions of the MCF5253 device for programming and evaluating the attributes of the microprocessor . In
addition, there is an IDE and ATA interface for connection to things like an external HDD. There is also
an SD card interface, CAN interface, and both analog and digital audio I/O connections. The board is
driven by the MCF5253 device, which is a member of the ColdFire® family of processors. It is a 32-bit
processor with a 24-bit address bus and 16 lines of data. The processor has eight 32-bit data registers, eight
32-bit address registers, a 32-bit program counter, and a 16-bit status register.

The MCF5253 processor has a System Integration Module referred to as the SIM. This module
incorporates many of the functions needed for system design. These include programmable chip-select
logic, system protection logic, general purpose I/O and interrupt controller logic. The chip-select logic can
select up to five memory banks and peripherals in addition to one bank of DRAM. The chip-select logic
also allows the insertion of a programmable number of wait states to allow slower memory or
memory-mapped peripherals to be used. (Refer to the MCF5253 Reference Manual for detailed
information about the chip selects.) One of the chip selects (CS0) is used to access the on-board Flash
ROM; the other chip selects are user-programmable. The DRAM controller is used to control one SDRAM
device providing 8 MB of SDRAM memory configured as 4 MB x 16 words. All other functions of the
SIM are available to the user.

M5253EVBE Users Manual, Rev. 1

Freescale Semiconductor 1-1

Figure 1-1 shows the M5253EVBE block diagram.

DB-9

Connector

DB-9

Connector

GPIO

Connectors

Headphone

Socket

RCA

Phono plugs

Optical EBU

Transmitter

Optical EBU

Receiver

RS232

Transceiver

CAN

Transceiver

Audio DAC

(I2S2)

Audio ADC

(I2S3)

Audio Out

(EBUOUT1)

Audio In

(EBUIN1)

Addr
[24:1]

Debug

Module

MCF5253

Data
[31:16]

26-pin debug connector

Oscillators: 32.768 KHz

11.2896 MHz
24 MHz

Flash (CS0)
16 bit,3.3v
2MB

SDRAM
16bit 3.3V
8MB

Buffered
IDE I/F
(CS2

/BUFENB2)

Dedicated
ATA I/F
Supports DMA

.

SD Card
Interface

Keypad

1-2 Freescale Semiconductor

(ATD)

TFT Display

Interface

M5253EVBE Users Manual, Rev. 1

B&W Display

I/F (QSPI)

USB

2.0 OTG

DB-9

Connector

RS232

Transceiver

Debug

Module

26-pin debug connector

DB-9

Connector

GPIO

Connectors

CAN

Transceiver

Addr
[24:1]

MCF5253

Data
[31:16]

Oscillators: 32.768 KHz

11.2896 MHz
24 MHz

Flash (CS0)
16 bit,3.3v
2MB

SDRAM
16bit 3.3V
8MB

Buffered
IDE I/F
(CS2

/BUFENB2)

Dedicated
ATA I/F
Supports DMA

.

SD Card
Interface

Keypad

(ATD)

TFT Display

Interface

B&W Display

I/F (QSPI)

USB

2.0 OTG

Figure 1-1 M5253EVBE Block Diagram

1.2 System Memory

One on-board Flash ROM (U11) is used in the system. The Am29LV160DB-XX device contains 16 Mbits
of non-volatile storage (1 Mbyte x 16), giving a total of 2 Mbytes of Flash memory. The lower 256 Kbytes
are used to store the M5253EVBE dBUG debugger/monitor firmware that is pre-programmed into the
Flash during factory testing.

The MCF5253 processor has 128 Kbytes of internal SRAM organized as 2 banks of 64 Kbytes. The
SRAM can be used for either data or instruction space.

M5253EVBE Users Manual, Rev. 1

Freescale Semiconductor 1-3

There is one SDRAM (U12) device on the PCB. The system ships with 1x4Mbytesx16 of SDRAM
totalling 8 Mbytes of volatile memory.

The internal cache of the MCF5253 is non-blocking. The instruction cache is 8 Kbytes with a 16-byte line
size. The ROM monitor currently does not utilize the cache, but programs downloaded with the ROM
monitor can initialize and use the cache.

1.3 Serial Communication Channels

The MCF5253 processor has 3 built-in UARTs with independent baud rate generators. The signals of all
channels can be passed through the external transceiver to make the channels RS-232 compatible (P4). An
RS-232 serial cable with DB9 connectors is included with the board. UART0 cha nnel is the “TERMINAL”
channel used by dBUG for communication with an external terminal/PC. The “TERMINAL” baud rate
defaults to 115200.

1.4 Parallel I/O Ports

The MCF5253 offers up to 60 lines of general-purpose I/O, of which six are dedicated inputs and three are
dedicated outputs. Seven of the GPIO lines are also available as edge-sensitive interrupt inputs. In
addition, there is one dedicated input for wake-up from low-power mode.

1.5 System Configuration

The M5253EVBE board requires the following items for minimum system configuration:

• The M5253EVBE board (provided)

• Power supply, +7 V to 14 V DC with minimum of 1.0 amp

• RS232C-compatible terminal or a PC with terminal emulation software

• RS232 communication cable (provided)

Refer to Section 2.2.2, “System Initialization” for initial system setup.

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M5253EVBE Users Manual, Rev. 1

Figure 1-2 displays the minimum system configuration.

dBUG>

RS-232 Terminal or PC

Figure 1-2 Minimum System Configuration

Freescale Semiconductor 1-5

+7.0 to +14 VDC

Input Power

M5253EVBE Users Manual, Rev. 1

1.6 Installation and Setup

This section discusses all the steps needed to prepare the board for operation. Read all the sections
carefully before using the board. When you are preparing the board for the first time, be sure to check that
all jumpers are in the default locations.

1.6.1 Unpacking

Unpack the computer board from its shipping box. Save the box for storing or reshipping. Refer to the
following list and verify that all the items are present. You should have received:

• M5253EVBE development system (CE certified)

• Sceptre 9.0 Volt, 2.7 A power supply with WS-047 and WS-048 adapters

• P&E Micro ColdFire USB interface cable

• USB 2.0 cable

• EVB Quickstart Guide (hardcopy)

• Warranty card—920-75133

• Technical Information Center Worldwide Contact List

• Freescale Documentation (http://www.freescale.com/coldfire)
— M5253 Evaluation Board Users Manual (this document)

CAUTION

Avoid touching the MOS devices. Static discharge can and will damage
these devices.

Once you have verified that all the items are present, remove the board from its protective jacket and
anti-static bag. Check the board for any visible damage. Ensure that there are no broken, damaged, or
missing parts. If you have not received all the items listed above or they are damaged, contact Rapid
Design immediately. For contact details, see the front of this manual.

1.6.2 Preparing the Board for Use

The board, as shipped, is ready to be connected to a terminal and power supply without any need for
modification. Figure 1-4 shows the position of the jumpers and connectors.

1.6.3 Providing Power to the Board

The board accepts three means of power supply connection—P1, P2, or J4. Connector P1 is a 2.1 mm
power jack, P2 is a lever-actuated connector, and J4 is a PC disk drive-type power connector. The board
accepts +7 V to +14 V DC at 1.0 amp via either of the connectors. Table 1-2 lists power supply
connections on P2.

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Table 1-1 Power Supply Connections on P2

Contact Number Voltage

1 +7V to +14V DC

2 Ground

1.6.4 Selecting Terminal Baud Rate

The serial channel UAR T0 of the MCF5253 is used for serial communication and has a built in timer . This
timer is used by the dBUG ROM monitor to generate the baud rate used to communicate with a serial
terminal. A number of baud rates can be programmed. On power-up or manual RESET, the dBUG ROM
monitor firmware configures the channel for 115200 baud. Once the dBUG ROM monitor is running, a
SET command may be issued to select any baud rate supported by the ROM monitor. See Section 2.1,

“What Is dBUG?” for the discussion of this command.

1.6.5 Terminal Character Format

The character format of the communication channel is fixed at power-up or RESET. The default character
format is 8 bits per character, no parity and one stop bit with no flow control. It is necessary to ensure that
the terminal or PC is set to this format.

1.6.6 Connecting the Terminal

The board is now ready to be connected to a PC/terminal. Use the RS232 serial cable to connect the
PC/terminal to the M5253EVBE PCB. The cable has a 9-pin female D-sub terminal connector at one end
and a 9-pin male D-sub connector at the other end. Connect the 9-pin male connector to connector P4 on
the M5253EVBE board. Connect the 9-pin female connector to one of the available serial communication
channels normally referred to as COM1 (COM2, etc.) on the PC running terminal emulation software. The
connector on the PC/terminal may be either male 25-pin or 9-pin. It may be necessary to obtain a
25pin-to-9pin adapter to make this connection. If an adapter is required, refer to Figure 1-3, which shows
the pin assignment for the 9-pin connector on the board.

5

Figure 1-3 Pin Assignment for Female (Terminal) Connector

1

69

1.6.7 Using a Personal Computer as a Terminal

A personal computer may be used as a terminal provided a terminal emulation software package is
available. Examples of this software are PROCOMM, KERMIT, QMODEM, Windows 95/98/2000/XP
Hyper Terminal or similar packages. The board should then be connected as described in Section 1.6.6,

“Connecting the Terminal.”

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M5253EVBE Users Manual, Rev. 1

Once the connection to the PC is made, power may be applied to the PC and the terminal emulation
software can be run. In terminal mode, it is necessary to select the baud rate and character format for the
channel. Most terminal emulation software packages provide a command known as “Alt-p” (press the p
key while pressing the Alt key) to choose the baud rate and character format. The character format should
be 8 bits, no parity, one stop bit. (See Section 1.6.5, “Terminal Character Format.”) The baud rate should
be set to 115200. Power can now be applied to the board.

Pin assignments are as follows:

1. Data Carrier Detect—Output (shorted to pins 4 and 6)

2. Receive Data—Output from board (Receive refers to terminal side.)

3. Transmit Data—Input to board (Transmit refers to terminal side.)

4. Data Terminal Ready—Input (shorted to pin 1 and 6)

5. Signal Ground

6. Data Set Ready—Output (shorted to pins 1 and 4)

7. Request to Send—Input

8. Clear to Send—Output

9. Not connected

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Figure 1-4 shows the default jumper locations for the board.

Freescale Semiconductor 1-9

Figure 1-4 Default Jumper Locations

M5253EVBE Users Manual, Rev. 1

1.7 System Power-up and Initial Operation

When all of the cables are connected to the board, power may be applied. The dBUG ROM Monitor
initializes the board and then displays a power-up message on the terminal, which includes the amount of
memory present on the board.

Hard Reset
DRAM Size: 8M

ColdFire MCF5253 on the M5253EVB
Firmware v4c.1b.1a (Built on Feb 1 2007 11:45:04)
Copyright 2006 Freescale Semiconductor, Inc.

Enter 'help' for help.

dBUG>

The board is now ready for operation under the control of the debugger as described in Section 2.2,

“Operational Procedure.” If you do not get the above response, perform the following checks:

1. Make sure that the power supply is properly configured for polarity, voltage level and current
capability (~1A) and is connected to the board.

2. Check that the terminal and board are set for the same character format and baud.

3. Press the RESET button to insure that the board has been initialized properly.

If you still are not receiving the proper response, your board may have been damaged. Contact Rapid PCB
for further instructions. For contact details, see the front of this manual.

1.8 M5253EVBE Jumper Setup

Jumper settings are as follows:

*: Indicates the default setting.

**: Indicates mandatory setting for proper operation.

Table 1-2 Jumper Settings

Jumper Setting Function

JP6 * 1-2 Audio DAC AK4366VT U4 audio format I2S

2-3 Audio DAC AK4366VT U4 audio format 24-bit MSB justified

JP7 1-2 Audio DAC AK4366VT U4 de-emphasis ON

* 2-3 Audio DAC AK4366VT U4 de-emphasis OFF

JP8 Not fitted Enable external audio clock source

JP9 Not fitted Enable XTRIM hardware feature

JP10 Not fitted External 1.2V (core) supply current measurement

JP11,JP13 Not fitted I2S0 5V pull-up (SDA0 and SCL0)

JP12 ** Fitted External 3.3V (pad) supply current measurement

NOTE

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Table 1-2 Jumper Settings (Continued)

Jumper Setting Function

JP14 ** 1-2 1.2V (core) supply from internal regulator

2-3 1.2V (core) supply from external regulator

JP15 * 1-2 Audio clock source taken from CRIN

2-3 Audio clock source taken from external pin (LRCK3)

JP16,JP19 Not fitted I2S1 5V pull-up (SDA1 and SCL1)

JP17 Not fitted SPI EEPROM M25P40 U14 CS enable (QSPICS0)

JP18 ** 1-2 Select BDM debug mode

2-3 Select JTAG debug mode

JP20 1-2 Boot mode select, from internal ROM

* 2-3 Boot mode select, from external memory (CS0)

JP21,JP23,JP27,JP28 Not fitted DDATA signal isolation from BDM interface

JP22,JP26,JP30 Not fitted Internal boot ROM mode select

JP24 * 1-2 (UART0) RS232 transceiver RX select

JP25 1-2 SPI EEPROM M25P40 U14 write protected (WP)

2-3 SPI EEPROM M25P40 U14 write enabled

JP29 * 1-2 (UART0) RS232 transceiver TX select

JP31 Not fitted RS232 transceiver RTS select

JP32 1-2 Wireless module M1 WAIT signal connected to IDEIORDY

2-3 Wireless module M1 WAIT signal connected to TA

JP33 Not fitted RS232 transceiver CTS select

JP34 1-2 Push button S2 connected to interrupt capable GPIO1

2-3 Push button S2 connected to WAKEUP pin

JP36 * Fitted Real Time Clock (RTC) supply isolation / current

measurement

JP37 Not fitted RS232 transceiver INVALID signal connected to GPIO34

JP38 Not fitted CAN transceiver TX select

JP39 Not fitted CAN transceiver RX select

JP40 Not fitted Connect CAN bus termination resistor (120R)

JP41 Not fitted RS232 transceiver READY signal connected to GPIO8

1.9 Using the BDM Port

The MCF5253 microprocessor has a built in debug module referred to as BDM (background debug
module). In order to use the BDM, simply connect the 26-pin debug connector on the board (J12) to the

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